SPI question
Posted: Mon Feb 22, 2021 10:14 am
Hi Team,
On the ADS1118 16Bit ADC according to the SPI protocol it is necessary to check the MISO line after the CS line is pulled low If the MISO line is is High the new data(sample) is not ready if the MISO Line is low the data is ready and the SPI can clock the Configuration bit out and read the Conversion register new data in .
I am confused in how to check the Logic level of the MISO line ,perhaps switching to IO mode and SPI mode Back and forward but this seems not to be the way Any suggestions much appreciated
Thanks as always it is highly appreciated
On the ADS1118 16Bit ADC according to the SPI protocol it is necessary to check the MISO line after the CS line is pulled low If the MISO line is is High the new data(sample) is not ready if the MISO Line is low the data is ready and the SPI can clock the Configuration bit out and read the Conversion register new data in .
I am confused in how to check the Logic level of the MISO line ,perhaps switching to IO mode and SPI mode Back and forward but this seems not to be the way Any suggestions much appreciated
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