// *************************************** // BoostC Header file for PIC18F4455 // Author(s): David Hobday // // Copyright (C) 2003-2009 Pavel Baranov // Copyright (C) 2003-2009 David Hobday // All Rights Reserved // *************************************** #DEVICE pic18f4455 #ifndef _PIC18F4455_H_ #define _PIC18F4455_H_ // *************************************** // W and F definitions // *************************************** #define W 0x0000 #define F 0x0001 //////////////////////////////////////////////////////////////////////////// // // Register Definitions // //////////////////////////////////////////////////////////////////////////// //----- Register Files ----------------------------------------------------- #define SPPDATA 0x00000F62 #define SPPCFG 0x00000F63 #define SPPEPS 0x00000F64 #define SPPCON 0x00000F65 #define UFRM 0x00000F66 #define UFRML 0x00000F66 #define UFRMH 0x00000F67 #define UIR 0x00000F68 #define UIE 0x00000F69 #define UEIR 0x00000F6A #define UEIE 0x00000F6B #define USTAT 0x00000F6C #define UCON 0x00000F6D #define UADDR 0x00000F6E #define UCFG 0x00000F6F #define UEP0 0x00000F70 #define UEP1 0x00000F71 #define UEP2 0x00000F72 #define UEP3 0x00000F73 #define UEP4 0x00000F74 #define UEP5 0x00000F75 #define UEP6 0x00000F76 #define UEP7 0x00000F77 #define UEP8 0x00000F78 #define UEP9 0x00000F79 #define UEP10 0x00000F7A #define UEP11 0x00000F7B #define UEP12 0x00000F7C #define UEP13 0x00000F7D #define UEP14 0x00000F7E #define UEP15 0x00000F7F #define porta 0x00000F80 #define portb 0x00000F81 #define portc 0x00000F82 #define portd 0x00000F83 #define porte 0x00000F84 #define LATA 0x00000F89 #define LATB 0x00000F8A #define LATC 0x00000F8B #define LATD 0x00000F8C #define LATE 0x00000F8D #define ddra 0x00000F92 #define trisa 0x00000F92 #define ddrb 0x00000F93 #define trisb 0x00000F93 #define ddrc 0x00000F94 #define trisc 0x00000F94 #define ddrd 0x00000F95 #define trisd 0x00000F95 #define ddre 0x00000F96 #define trise 0x00000F96 #define OSCTUNE 0x00000F9B #define PIE1 0x00000F9D #define PIR1 0x00000F9E #define IPR1 0x00000F9F #define PIE2 0x00000FA0 #define PIR2 0x00000FA1 #define IPR2 0x00000FA2 #define EECON1 0x00000FA6 #define EECON2 0x00000FA7 #define EEDATA 0x00000FA8 #define EEADR 0x00000FA9 #define RCSTA 0x00000FAB #define TXSTA 0x00000FAC #define TXREG 0x00000FAD #define RCREG 0x00000FAE #define SPBRG 0x00000FAF #define SPBRGH 0x00000FB0 #define T3CON 0x00000FB1 #define TMR3L 0x00000FB2 #define TMR3H 0x00000FB3 #define CMCON 0x00000FB4 #define CVRCON 0x00000FB5 #define CCP1AS 0x00000FB6 #define ECCP1AS 0x00000FB6 #define CCP1DEL 0x00000FB7 #define ECCP1DEL 0x00000FB7 #define BAUDCON 0x00000FB8 #define CCP2CON 0x00000FBA #define CCPR2 0x00000FBB #define CCPR2L 0x00000FBB #define CCPR2H 0x00000FBC #define CCP1CON 0x00000FBD #define ECCP1CON 0x00000FBD #define CCPR1 0x00000FBE #define CCPR1L 0x00000FBE #define CCPR1H 0x00000FBF #define ADCON2 0x00000FC0 #define ADCON1 0x00000FC1 #define ADCON0 0x00000FC2 #define ADRES 0x00000FC3 #define ADRESL 0x00000FC3 #define ADRESH 0x00000FC4 #define SSPCON2 0x00000FC5 #define SSPCON1 0x00000FC6 #define SSPSTAT 0x00000FC7 #define SSPADD 0x00000FC8 #define SSPBUF 0x00000FC9 #define T2CON 0x00000FCA #define PR2 0x00000FCB #define TMR2 0x00000FCC #define T1CON 0x00000FCD #define TMR1L 0x00000FCE #define TMR1H 0x00000FCF #define RCON 0x00000FD0 #define WDTCON 0x00000FD1 #define HLVDCON 0x00000FD2 #define LVDCON 0x00000FD2 #define OSCCON 0x00000FD3 #define T0CON 0x00000FD5 #define TMR0L 0x00000FD6 #define TMR0H 0x00000FD7 #define STATUS 0x00000FD8 #define FSR2L 0x00000FD9 #define FSR2H 0x00000FDA #define PLUSW2 0x00000FDB #define PREINC2 0x00000FDC #define POSTDEC2 0x00000FDD #define POSTINC2 0x00000FDE #define INDF2 0x00000FDF #define BSR 0x00000FE0 #define FSR1L 0x00000FE1 #define FSR1H 0x00000FE2 #define PLUSW1 0x00000FE3 #define PREINC1 0x00000FE4 #define POSTDEC1 0x00000FE5 #define POSTINC1 0x00000FE6 #define INDF1 0x00000FE7 #define WREG 0x00000FE8 #define FSR0L 0x00000FE9 #define FSR0H 0x00000FEA #define PLUSW0 0x00000FEB #define PREINC0 0x00000FEC #define POSTDEC0 0x00000FED #define POSTINC0 0x00000FEE #define INDF0 0x00000FEF #define INTCON3 0x00000FF0 #define INTCON2 0x00000FF1 #define INTCON 0x00000FF2 #define PROD 0x00000FF3 #define PRODL 0x00000FF3 #define PRODH 0x00000FF4 #define TABLAT 0x00000FF5 #define TBLPTR 0x00000FF6 #define TBLPTRL 0x00000FF6 #define TBLPTRH 0x00000FF7 #define TBLPTRU 0x00000FF8 #define PC 0x00000FF9 #define PCL 0x00000FF9 #define PCLATH 0x00000FFA #define PCLATU 0x00000FFB #define STKPTR 0x00000FFC #define TOS 0x00000FFD #define TOSL 0x00000FFD #define TOSH 0x00000FFE #define TOSU 0x00000FFF /////// SPPCFG Bits ///////////////////////////////////////////////////// #define WS0 0x00000000 #define WS1 0x00000001 #define WS2 0x00000002 #define WS3 0x00000003 #define CLK1EN 0x00000004 #define CSEN 0x00000005 #define CLKCFG0 0x00000006 #define CLKCFG1 0x00000007 /////// SPPEPS Bits ///////////////////////////////////////////////////// #define ADDR0 0x00000000 #define ADDR1 0x00000001 #define ADDR2 0x00000002 #define ADDR3 0x00000003 #define SPPBUSY 0x00000004 #define WRSPP 0x00000006 #define RDSPP 0x00000007 /////// SPPCON Bits ///////////////////////////////////////////////////// #define SPPEN 0x00000000 #define SPPOWN 0x00000001 /////// UFRML Bits ///////////////////////////////////////////////////// #define FRM0 0x00000000 #define FRM1 0x00000001 #define FRM2 0x00000002 #define FRM3 0x00000003 #define FRM4 0x00000004 #define FRM5 0x00000005 #define FRM6 0x00000006 #define FRM7 0x00000007 /////// UFRMH Bits ///////////////////////////////////////////////////// #define FRM8 0x00000000 #define FRM9 0x00000001 #define FRM10 0x00000002 /////// UIR Bits ///////////////////////////////////////////////////// #define URSTIF 0x00000000 #define UERRIF 0x00000001 #define ACTVIF 0x00000002 #define TRNIF 0x00000003 #define IDLEIF 0x00000004 #define STALLIF 0x00000005 #define SOFIF 0x00000006 /////// UIE Bits ///////////////////////////////////////////////////// #define URSTIE 0x00000000 #define UERRIE 0x00000001 #define ACTVIE 0x00000002 #define TRNIE 0x00000003 #define IDLEIE 0x00000004 #define STALLIE 0x00000005 #define SOFIE 0x00000006 /////// UEIR Bits ///////////////////////////////////////////////////// #define PIDEF 0x00000000 #define CRC5EF 0x00000001 #define CRC16EF 0x00000002 #define DFN8EF 0x00000003 #define BTOEF 0x00000004 #define BTSEF 0x00000007 /////// UEIE Bits ///////////////////////////////////////////////////// #define PIDEE 0x00000000 #define CRC5EE 0x00000001 #define CRC16EE 0x00000002 #define DFN8EE 0x00000003 #define BTOEE 0x00000004 #define BTSEE 0x00000007 /////// USTAT Bits ///////////////////////////////////////////////////// #define PPBI 0x00000001 #define DIR 0x00000002 #define ENDP0 0x00000003 #define ENDP1 0x00000004 #define ENDP2 0x00000005 #define ENDP3 0x00000006 /////// UCON Bits ///////////////////////////////////////////////////// #define SUSPND 0x00000001 #define RESUME 0x00000002 #define USBEN 0x00000003 #define PKTDIS 0x00000004 #define SE0 0x00000005 #define PPBRST 0x00000006 /////// UADDR Bits ///////////////////////////////////////////////////// #define ADDR0 0x00000000 #define ADDR1 0x00000001 #define ADDR2 0x00000002 #define ADDR3 0x00000003 #define ADDR4 0x00000004 #define ADDR5 0x00000005 #define ADDR6 0x00000006 /////// UCFG Bits ///////////////////////////////////////////////////// #define PPB0 0x00000000 #define PPB1 0x00000001 #define FSEN 0x00000002 #define UTRDIS 0x00000003 #define UPUEN 0x00000004 #define UOEMON 0x00000006 #define UTEYE 0x00000007 /////// UEP0 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP1 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP2 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP3 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP4 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP5 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP6 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP7 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP8 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP9 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP10 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP11 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP12 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP13 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP14 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// UEP15 Bits ///////////////////////////////////////////////////// #define EPSTALL 0x00000000 #define EPINEN 0x00000001 #define EPOUTEN 0x00000002 #define EPCONDIS 0x00000003 #define EPHSHK 0x00000004 /////// PORTA Bits ///////////////////////////////////////////////////// #define RA0 0x00000000 #define RA1 0x00000001 #define RA2 0x00000002 #define RA3 0x00000003 #define RA4 0x00000004 #define RA5 0x00000005 #define RA6 0x00000006 #define AN0 0x00000000 #define AN1 0x00000001 #define AN2 0x00000002 #define AN3 0x00000003 #define T0CKI 0x00000004 #define AN4 0x00000005 #define OSC2 0x00000006 #define VREFM 0x00000002 #define VREFP 0x00000003 #define LVDIN 0x00000005 #define HLVDIN 0x00000005 // added by dh #define SS 0x00000005 #define NOT_SS 0x00000005 /////// PORTB Bits ///////////////////////////////////////////////////// #define RB0 0x00000000 #define RB1 0x00000001 #define RB2 0x00000002 #define RB3 0x00000003 #define RB4 0x00000004 #define RB5 0x00000005 #define RB6 0x00000006 #define RB7 0x00000007 #define INT0 0x00000000 #define INT1 0x00000001 #define INT2 0x00000002 #define PGM 0x00000005 #define PGC 0x00000006 #define PGD 0x00000007 // added by dh #define SDI 0x00000000 #define SCK 0x00000001 /////// PORTC Bits ///////////////////////////////////////////////////// #define RC0 0x00000000 #define RC1 0x00000001 #define RC2 0x00000002 #define RC4 0x00000004 #define RC5 0x00000005 #define RC6 0x00000006 #define RC7 0x00000007 #define T1OSO 0x00000000 #define T1OSI 0x00000001 #define CCP1 0x00000002 #define TX 0x00000006 #define RX 0x00000007 #define T13CKI 0x00000000 #define P1A 0x00000002 #define CK 0x00000006 // DT is a reserved word // added by dh #define SDO 0x00000007 /////// PORTD Bits ///////////////////////////////////////////////////// #define RD0 0x00000000 #define RD1 0x00000001 #define RD2 0x00000002 #define RD3 0x00000003 #define RD4 0x00000004 #define RD5 0x00000005 #define RD6 0x00000006 #define RD7 0x00000007 #define SPP0 0x00000000 #define SPP1 0x00000001 #define SPP2 0x00000002 #define SPP3 0x00000003 #define SPP4 0x00000004 #define SPP5 0x00000005 #define SPP6 0x00000006 #define SPP7 0x00000007 /////// PORTE Bits ///////////////////////////////////////////////////// #define RE0 0x00000000 #define RE1 0x00000001 #define RE2 0x00000002 #define RE3 0x00000003 #define RDPU 0x00000007 #define CK1SPP 0x00000000 #define CK2SPP 0x00000001 #define OESPP 0x00000002 /////// LATA Bits ///////////////////////////////////////////////////// #define LATA0 0x00000000 #define LATA1 0x00000001 #define LATA2 0x00000002 #define LATA3 0x00000003 #define LATA4 0x00000004 #define LATA5 0x00000005 #define LATA6 0x00000006 /////// LATB Bits ///////////////////////////////////////////////////// #define LATB0 0x00000000 #define LATB1 0x00000001 #define LATB2 0x00000002 #define LATB3 0x00000003 #define LATB4 0x00000004 #define LATB5 0x00000005 #define LATB6 0x00000006 #define LATB7 0x00000007 /////// LATC Bits ///////////////////////////////////////////////////// #define LATC0 0x00000000 #define LATC1 0x00000001 #define LATC2 0x00000002 #define LATC6 0x00000006 #define LATC7 0x00000007 /////// LATD Bits ///////////////////////////////////////////////////// #define LATD0 0x00000000 #define LATD1 0x00000001 #define LATD2 0x00000002 #define LATD3 0x00000003 #define LATD4 0x00000004 #define LATD5 0x00000005 #define LATD6 0x00000006 #define LATD7 0x00000007 /////// LATE Bits ///////////////////////////////////////////////////// #define LATE0 0x00000000 #define LATE1 0x00000001 #define LATE2 0x00000002 /////// DDRA Bits ///////////////////////////////////////////////////// #define RA0 0x00000000 #define RA1 0x00000001 #define RA2 0x00000002 #define RA3 0x00000003 #define RA4 0x00000004 #define RA5 0x00000005 #define RA6 0x00000006 /////// TRISA Bits ///////////////////////////////////////////////////// #define TRISA0 0x00000000 #define TRISA1 0x00000001 #define TRISA2 0x00000002 #define TRISA3 0x00000003 #define TRISA4 0x00000004 #define TRISA5 0x00000005 #define TRISA6 0x00000006 /////// DDRB Bits ///////////////////////////////////////////////////// #define RB0 0x00000000 #define RB1 0x00000001 #define RB2 0x00000002 #define RB3 0x00000003 #define RB4 0x00000004 #define RB5 0x00000005 #define RB6 0x00000006 #define RB7 0x00000007 /////// TRISB Bits ///////////////////////////////////////////////////// #define TRISB0 0x00000000 #define TRISB1 0x00000001 #define TRISB2 0x00000002 #define TRISB3 0x00000003 #define TRISB4 0x00000004 #define TRISB5 0x00000005 #define TRISB6 0x00000006 #define TRISB7 0x00000007 /////// DDRC Bits ///////////////////////////////////////////////////// #define RC0 0x00000000 #define RC1 0x00000001 #define RC2 0x00000002 #define RC6 0x00000006 #define RC7 0x00000007 /////// TRISC Bits ///////////////////////////////////////////////////// #define TRISC0 0x00000000 #define TRISC1 0x00000001 #define TRISC2 0x00000002 #define TRISC6 0x00000006 #define TRISC7 0x00000007 /////// DDRD Bits ///////////////////////////////////////////////////// #define RD0 0x00000000 #define RD1 0x00000001 #define RD2 0x00000002 #define RD3 0x00000003 #define RD4 0x00000004 #define RD5 0x00000005 #define RD6 0x00000006 #define RD7 0x00000007 /////// TRISD Bits ///////////////////////////////////////////////////// #define TRISD0 0x00000000 #define TRISD1 0x00000001 #define TRISD2 0x00000002 #define TRISD3 0x00000003 #define TRISD4 0x00000004 #define TRISD5 0x00000005 #define TRISD6 0x00000006 #define TRISD7 0x00000007 /////// DDRE Bits ///////////////////////////////////////////////////// #define RE0 0x00000000 #define RE1 0x00000001 #define RE2 0x00000002 /////// TRISE Bits ///////////////////////////////////////////////////// #define TRISE0 0x00000000 #define TRISE1 0x00000001 #define TRISE2 0x00000002 /////// OSCTUNE Bits ///////////////////////////////////////////////////// #define TUN0 0x00000000 #define TUN1 0x00000001 #define TUN2 0x00000002 #define TUN3 0x00000003 #define TUN4 0x00000004 #define INTSRC 0x00000007 /////// PIE1 Bits ///////////////////////////////////////////////////// #define TMR1IE 0x00000000 #define TMR2IE 0x00000001 #define CCP1IE 0x00000002 #define SSPIE 0x00000003 #define TXIE 0x00000004 #define RCIE 0x00000005 #define ADIE 0x00000006 #define SPPIE 0x00000007 /////// PIR1 Bits ///////////////////////////////////////////////////// #define TMR1IF 0x00000000 #define TMR2IF 0x00000001 #define CCP1IF 0x00000002 #define SSPIF 0x00000003 #define TXIF 0x00000004 #define RCIF 0x00000005 #define ADIF 0x00000006 #define SPPIF 0x00000007 /////// IPR1 Bits ///////////////////////////////////////////////////// #define TMR1IP 0x00000000 #define TMR2IP 0x00000001 #define CCP1IP 0x00000002 #define SSPIP 0x00000003 #define TXIP 0x00000004 #define RCIP 0x00000005 #define ADIP 0x00000006 #define SPPIP 0x00000007 /////// PIE2 Bits ///////////////////////////////////////////////////// #define CCP2IE 0x00000000 #define TMR3IE 0x00000001 #define LVDIE 0x00000002 #define BCLIE 0x00000003 #define EEIE 0x00000004 #define USBIE 0x00000005 #define CMIE 0x00000006 #define OSCFIE 0x00000007 #define HLVDIE 0x00000002 /////// PIR2 Bits ///////////////////////////////////////////////////// #define CCP2IF 0x00000000 #define TMR3IF 0x00000001 #define LVDIF 0x00000002 #define BCLIF 0x00000003 #define EEIF 0x00000004 #define USBIF 0x00000005 #define CMIF 0x00000006 #define OSCFIF 0x00000007 #define HLVDIF 0x00000002 /////// IPR2 Bits ///////////////////////////////////////////////////// #define CCP2IP 0x00000000 #define TMR3IP 0x00000001 #define LVDIP 0x00000002 #define BCLIP 0x00000003 #define EEIP 0x00000004 #define USBIP 0x00000005 #define CMIP 0x00000006 #define OSCFIP 0x00000007 #define HLVDIP 0x00000002 /////// EECON1 Bits ///////////////////////////////////////////////////// #define RD 0x00000000 #define WR 0x00000001 #define WREN 0x00000002 #define WRERR 0x00000003 #define FREE 0x00000004 #define CFGS 0x00000006 #define EEPGD 0x00000007 /////// RCSTA Bits ///////////////////////////////////////////////////// #define RX9D 0x00000000 #define OERR 0x00000001 #define FERR 0x00000002 #define ADDEN 0x00000003 #define CREN 0x00000004 #define SREN 0x00000005 #define RX9 0x00000006 #define SPEN 0x00000007 #define ADEN 0x00000003 /////// TXSTA Bits ///////////////////////////////////////////////////// #define TX9D 0x00000000 #define TRMT 0x00000001 #define BRGH 0x00000002 #define SENDB 0x00000003 #define SYNC 0x00000004 #define TXEN 0x00000005 #define TX9 0x00000006 #define CSRC 0x00000007 /////// T3CON Bits ///////////////////////////////////////////////////// #define TMR3ON 0x00000000 #define TMR3CS 0x00000001 #define T3SYNC 0x00000002 #define T3CCP1 0x00000003 #define T3CKPS0 0x00000004 #define T3CKPS1 0x00000005 #define T3CCP2 0x00000006 #define RD16 0x00000007 #define T3NSYNC 0x00000002 #define NOT_T3SYNC 0x00000002 /////// CMCON Bits ///////////////////////////////////////////////////// #define CM0 0x00000000 #define CM1 0x00000001 #define CM2 0x00000002 #define CIS 0x00000003 #define C1INV 0x00000004 #define C2INV 0x00000005 #define C1OUT 0x00000006 #define C2OUT 0x00000007 /////// CVRCON Bits ///////////////////////////////////////////////////// #define CVR0 0x00000000 #define CVR1 0x00000001 #define CVR2 0x00000002 #define CVR3 0x00000003 #define CVREF 0x00000004 #define CVRR 0x00000005 #define CVROE 0x00000006 #define CVREN 0x00000007 #define CVRSS 0x00000004 /////// CCP1AS Bits ///////////////////////////////////////////////////// #define PSSBD0 0x00000000 #define PSSBD1 0x00000001 #define PSSAC0 0x00000002 #define PSSAC1 0x00000003 #define ECCPAS0 0x00000004 #define ECCPAS1 0x00000005 #define ECCPAS2 0x00000006 #define ECCPASE 0x00000007 /////// ECCP1AS Bits ///////////////////////////////////////////////////// #define PSSBD0 0x00000000 #define PSSBD1 0x00000001 #define PSSAC0 0x00000002 #define PSSAC1 0x00000003 #define ECCPAS0 0x00000004 #define ECCPAS1 0x00000005 #define ECCPAS2 0x00000006 #define ECCPASE 0x00000007 /////// CCP1DEL Bits ///////////////////////////////////////////////////// #define PDC0 0x00000000 #define PDC1 0x00000001 #define PDC2 0x00000002 #define PDC3 0x00000003 #define PDC4 0x00000004 #define PDC5 0x00000005 #define PDC6 0x00000006 #define PRSEN 0x00000007 /////// ECCP1DEL Bits ///////////////////////////////////////////////////// #define PDC0 0x00000000 #define PDC1 0x00000001 #define PDC2 0x00000002 #define PDC3 0x00000003 #define PDC4 0x00000004 #define PDC5 0x00000005 #define PDC6 0x00000006 #define PRSEN 0x00000007 /////// BAUDCON Bits ///////////////////////////////////////////////////// #define ABDEN 0x00000000 #define WUE 0x00000001 #define BRG16 0x00000003 #define SCKP 0x00000004 #define RCIDL 0x00000006 #define ABDOVF 0x00000007 #define TXCKP 0x00000004 #define RXDTP 0x00000005 #define RCMT 0x00000006 /////// CCP2CON Bits ///////////////////////////////////////////////////// #define CCP2M0 0x00000000 #define CCP2M1 0x00000001 #define CCP2M2 0x00000002 #define CCP2M3 0x00000003 #define DC2B0 0x00000004 #define DC2B1 0x00000005 /////// CCP1CON Bits ///////////////////////////////////////////////////// #define CCP1M0 0x00000000 #define CCP1M1 0x00000001 #define CCP1M2 0x00000002 #define CCP1M3 0x00000003 #define DC1B0 0x00000004 #define DC1B1 0x00000005 #define P1M0 0x00000006 #define P1M1 0x00000007 /////// ECCP1CON Bits ///////////////////////////////////////////////////// #define CCP1M0 0x00000000 #define CCP1M1 0x00000001 #define CCP1M2 0x00000002 #define CCP1M3 0x00000003 #define DC1B0 0x00000004 #define DC1B1 0x00000005 #define P1M0 0x00000006 #define P1M1 0x00000007 /////// ADCON2 Bits ///////////////////////////////////////////////////// #define ADCS0 0x00000000 #define ADCS1 0x00000001 #define ADCS2 0x00000002 #define ACQT0 0x00000003 #define ACQT1 0x00000004 #define ACQT2 0x00000005 #define ADFM 0x00000007 /////// ADCON1 Bits ///////////////////////////////////////////////////// #define PCFG0 0x00000000 #define PCFG1 0x00000001 #define PCFG2 0x00000002 #define PCFG3 0x00000003 #define VCFG0 0x00000004 #define VCFG1 0x00000005 /////// ADCON0 Bits ///////////////////////////////////////////////////// #define ADON 0x00000000 #define GO_DONE 0x00000001 #define CHS0 0x00000002 #define CHS1 0x00000003 #define CHS2 0x00000004 #define CHS3 0x00000005 #define DONE 0x00000001 #define GO 0x00000001 #define NOT_DONE 0x00000001 /////// SSPCON2 Bits ///////////////////////////////////////////////////// #define SEN 0x00000000 #define RSEN 0x00000001 #define PEN 0x00000002 #define RCEN 0x00000003 #define ACKEN 0x00000004 #define ACKDT 0x00000005 #define ACKSTAT 0x00000006 #define GCEN 0x00000007 /////// SSPCON1 Bits ///////////////////////////////////////////////////// #define SSPM0 0x00000000 #define SSPM1 0x00000001 #define SSPM2 0x00000002 #define SSPM3 0x00000003 #define CKP 0x00000004 #define SSPEN 0x00000005 #define SSPOV 0x00000006 #define WCOL 0x00000007 /////// SSPSTAT Bits ///////////////////////////////////////////////////// #define BF 0x00000000 #define UA 0x00000001 #define R_W 0x00000002 #define S 0x00000003 #define P 0x00000004 #define D_A 0x00000005 #define CKE 0x00000006 #define SMP 0x00000007 #define I2C_READ 0x00000002 #define I2C_START 0x00000003 #define I2C_STOP 0x00000004 #define I2C_DAT 0x00000005 #define NOT_W 0x00000002 #define NOT_A 0x00000005 #define NOT_WRITE 0x00000002 #define NOT_ADDRESS 0x00000005 #define READ_WRITE 0x00000002 #define DATA_ADDRESS 0x00000005 #define R 0x00000002 #define D 0x00000005 /////// T2CON Bits ///////////////////////////////////////////////////// #define T2CKPS0 0x00000000 #define T2CKPS1 0x00000001 #define TMR2ON 0x00000002 #define T2OUTPS0 0x00000003 #define T2OUTPS1 0x00000004 #define T2OUTPS2 0x00000005 #define T2OUTPS3 0x00000006 /////// T1CON Bits ///////////////////////////////////////////////////// #define TMR1ON 0x00000000 #define TMR1CS 0x00000001 #define T1SYNC 0x00000002 #define T1OSCEN 0x00000003 #define T1CKPS0 0x00000004 #define T1CKPS1 0x00000005 #define T1RUN 0x00000006 #define RD16 0x00000007 #define NOT_T1SYNC 0x00000002 /////// RCON Bits ///////////////////////////////////////////////////// #define NOT_BOR 0x00000000 #define NOT_POR 0x00000001 #define NOT_PD 0x00000002 #define NOT_TO 0x00000003 #define NOT_RI 0x00000004 #define SBOREN 0x00000006 #define NOT_IPEN 0x00000007 #define BOR 0x00000000 #define POR 0x00000001 #define PD 0x00000002 #define TO 0x00000003 #define RI 0x00000004 #define IPEN 0x00000007 /////// WDTCON Bits ///////////////////////////////////////////////////// #define SWDTEN 0x00000000 #define SWDTE 0x00000000 /////// HLVDCON Bits ///////////////////////////////////////////////////// #define LVDL0 0x00000000 #define LVDL1 0x00000001 #define LVDL2 0x00000002 #define LVDL3 0x00000003 #define LVDEN 0x00000004 #define IRVST 0x00000005 #define LVV0 0x00000000 #define LVV1 0x00000001 #define LVV2 0x00000002 #define LVV3 0x00000003 #define BGST 0x00000005 #define HLVDL0 0x00000000 #define HLVDL1 0x00000001 #define HLVDL2 0x00000002 #define HLVDL3 0x00000003 #define HLVDEN 0x00000004 #define VDIRMAG 0x00000007 #define IVRST 0x00000005 /////// LVDCON Bits ///////////////////////////////////////////////////// #define LVDL0 0x00000000 #define LVDL1 0x00000001 #define LVDL2 0x00000002 #define LVDL3 0x00000003 #define LVDEN 0x00000004 #define IRVST 0x00000005 #define LVV0 0x00000000 #define LVV1 0x00000001 #define LVV2 0x00000002 #define LVV3 0x00000003 #define BGST 0x00000005 #define HLVDL0 0x00000000 #define HLVDL1 0x00000001 #define HLVDL2 0x00000002 #define HLVDL3 0x00000003 #define HLVDEN 0x00000004 #define VDIRMAG 0x00000007 #define IVRST 0x00000005 /////// OSCCON Bits ///////////////////////////////////////////////////// #define SCS0 0x00000000 #define SCS1 0x00000001 #define IOFS 0x00000002 #define OSTS 0x00000003 #define IRCF0 0x00000004 #define IRCF1 0x00000005 #define IRCF2 0x00000006 #define IDLEN 0x00000007 #define FLTS 0x00000002 /////// T0CON Bits ///////////////////////////////////////////////////// #define T0PS0 0x00000000 #define T0PS1 0x00000001 #define T0PS2 0x00000002 #define PSA 0x00000003 #define T0SE 0x00000004 #define T0CS 0x00000005 #define T08BIT 0x00000006 #define TMR0ON 0x00000007 /////// STATUS Bits ///////////////////////////////////////////////////// #define C 0x00000000 #define DC 0x00000001 #define Z 0x00000002 #define OV 0x00000003 #define N 0x00000004 /////// INTCON3 Bits ///////////////////////////////////////////////////// #define INT1IF 0x00000000 #define INT2IF 0x00000001 #define INT1IE 0x00000003 #define INT2IE 0x00000004 #define INT1IP 0x00000006 #define INT2IP 0x00000007 #define INT1F 0x00000000 #define INT2F 0x00000001 #define INT1E 0x00000003 #define INT2E 0x00000004 #define INT1P 0x00000006 #define INT2P 0x00000007 /////// INTCON2 Bits ///////////////////////////////////////////////////// #define RBIP 0x00000000 #define TMR0IP 0x00000002 #define INTEDG2 0x00000004 #define INTEDG1 0x00000005 #define INTEDG0 0x00000006 #define NOT_RBPU 0x00000007 #define T0IP 0x00000002 #define RBPU 0x00000007 /////// INTCON Bits ///////////////////////////////////////////////////// #define RBIF 0x00000000 #define INT0IF 0x00000001 #define TMR0IF 0x00000002 #define RBIE 0x00000003 #define INT0IE 0x00000004 #define TMR0IE 0x00000005 #define PEIE 0x00000006 #define GIE 0x00000007 #define INT0F 0x00000001 #define T0IF 0x00000002 #define INT0E 0x00000004 #define T0IE 0x00000005 #define GIEL 0x00000006 #define GIEH 0x00000007 /////// STKPTR Bits ///////////////////////////////////////////////////// #define STKPTR0 0x00000000 #define STKPTR1 0x00000001 #define STKPTR2 0x00000002 #define STKPTR3 0x00000003 #define STKPTR4 0x00000004 #define STKUNF 0x00000006 #define STKFUL 0x00000007 //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// // // Configuration Bits // // NAME Address // CONFIG1L 300000h // CONFIG1H 300001h // CONFIG2L 300002h // CONFIG2H 300003h // CONFIG3H 300005h // CONFIG4L 300006h // CONFIG5L 300008h // CONFIG5H 300009h // CONFIG6L 30000Ah // CONFIG6H 30000Bh // CONFIG7L 30000Ch // CONFIG7H 30000Dh // //////////////////////////////////////////////////////////////////////////// // The following is an assignment of address values for all of the // configuration registers for the purpose of table reads #define _CONFIG1L 0x00300000 #define _CONFIG1H 0x00300001 #define _CONFIG2L 0x00300002 #define _CONFIG2H 0x00300003 #define _CONFIG3H 0x00300005 #define _CONFIG4L 0x00300006 #define _CONFIG5L 0x00300008 #define _CONFIG5H 0x00300009 #define _CONFIG6L 0x0030000A #define _CONFIG6H 0x0030000B #define _CONFIG7L 0x0030000C #define _CONFIG7H 0x0030000D /////// CONFIG1L Options ////////////////////////////////////////////////// #define _PLLDIV_1_1L 0x000000F8 // No prescale (4 MHz oscillator input drives PLL directly) #define _PLLDIV_2_1L 0x000000F9 // Divide by 2 (8 MHz oscillator input) #define _PLLDIV_3_1L 0x000000FA // Divide by 3 (12 MHz oscillator input) #define _PLLDIV_4_1L 0x000000FB // Divide by 4 (16 MHz oscillator input) #define _PLLDIV_5_1L 0x000000FC // Divide by 5 (20 MHz oscillator input) #define _PLLDIV_6_1L 0x000000FD // Divide by 6 (24 MHz oscillator input) #define _PLLDIV_10_1L 0x000000FE // Divide by 10 (40 MHz oscillator input) #define _PLLDIV_12_1L 0x000000FF // Divide by 12 (48 MHz oscillator input) #define _CPUDIV_OSC1_PLL2_1L 0x000000E7 // [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] #define _CPUDIV_OSC2_PLL3_1L 0x000000EF // [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] #define _CPUDIV_OSC3_PLL4_1L 0x000000F7 // [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] #define _CPUDIV_OSC4_PLL6_1L 0x000000FF // [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] #define _USBDIV_1_1L 0x000000DF // USB clock source comes directly from the primary oscillator block with no postscale #define _USBDIV_2_1L 0x000000FF // USB clock source comes from the 96 MHz PLL divided by 2 /////// CONFIG1H Options ////////////////////////////////////////////////// #define _FOSC_XT_XT_1H 0x000000F0 // XT oscillator, XT used by USB #define _FOSC_XTPLL_XT_1H 0x000000F2 // XT oscillator, PLL enabled, XT used by USB #define _FOSC_ECIO_EC_1H 0x000000F4 // External clock, port function on RA6, EC used by USB #define _FOSC_EC_EC_1H 0x000000F5 // External clock, CLKOUT on RA6, EC used by USB #define _FOSC_ECPLLIO_EC_1H 0x000000F6 // External clock, PLL enabled, port function on RA6, EC used by USB #define _FOSC_ECPLL_EC_1H 0x000000F7 // External clock, PLL enabled, CLKOUT on RA6, EC used by USB #define _FOSC_INTOSCIO_EC_1H 0x000000F8 // Internal oscillator, port function on RA6, EC used by USB #define _FOSC_INTOSC_EC_1H 0x000000F9 // Internal oscillator, CLKOUT on RA6, EC used by USB #define _FOSC_INTOSC_XT_1H 0x000000FA // Internal oscillator, XT used by USB #define _FOSC_INTOSC_HS_1H 0x000000FB // Internal oscillator, HS used by USB #define _FOSC_HS_1H 0x000000FC // HS oscillator, HS used by USB #define _FOSC_HSPLL_HS_1H 0x000000FE // HS oscillator, PLL enabled, HS used by USB #define _FCMEN_OFF_1H 0x000000BF // Fail-Safe Clock Monitor disabled #define _FCMEN_ON_1H 0x000000FF // Fail-Safe Clock Monitor enabled #define _IESO_OFF_1H 0x0000007F // Oscillator Switchover mode disabled #define _IESO_ON_1H 0x000000FF // Oscillator Switchover mode enabled /////// CONFIG2L Options ////////////////////////////////////////////////// #define _PWRT_ON_2L 0x000000FE // PWRT enabled #define _PWRT_OFF_2L 0x000000FF // PWRT disabled #define _BOR_OFF_2L 0x000000F9 // Brown-out Reset disabled in hardware and software #define _BOR_SOFT_2L 0x000000FB // Brown-out Reset enabled and controlled by software (SBOREN is enabled) #define _BOR_ON_ACTIVE_2L 0x000000FD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) #define _BOR_ON_2L 0x000000FF // Brown-out Reset enabled in hardware only (SBOREN is disabled) #define _BORV_0_2L 0x000000E7 // Maximum setting #define _BORV_1_2L 0x000000EF // #define _BORV_2_2L 0x000000F7 // #define _BORV_3_2L 0x000000FF // Minimum setting #define _VREGEN_OFF_2L 0x000000DF // USB voltage regulator disabled #define _VREGEN_ON_2L 0x000000FF // USB voltage regulator enabled /////// CONFIG2H Options ////////////////////////////////////////////////// #define _WDT_OFF_2H 0x000000FE // HW Disabled - SW Controlled #define _WDT_ON_2H 0x000000FF // HW Enabled - SW Disabled #define _WDTPS_1_2H 0x000000E1 // 1:1 #define _WDTPS_2_2H 0x000000E3 // 1:2 #define _WDTPS_4_2H 0x000000E5 // 1:4 #define _WDTPS_8_2H 0x000000E7 // 1:8 #define _WDTPS_16_2H 0x000000E9 // 1:16 #define _WDTPS_32_2H 0x000000EB // 1:32 #define _WDTPS_64_2H 0x000000ED // 1:64 #define _WDTPS_128_2H 0x000000EF // 1:128 #define _WDTPS_256_2H 0x000000F1 // 1:256 #define _WDTPS_512_2H 0x000000F3 // 1:512 #define _WDTPS_1024_2H 0x000000F5 // 1:1024 #define _WDTPS_2048_2H 0x000000F7 // 1:2048 #define _WDTPS_4096_2H 0x000000F9 // 1:4096 #define _WDTPS_8192_2H 0x000000FB // 1:8192 #define _WDTPS_16384_2H 0x000000FD // 1:16384 #define _WDTPS_32768_2H 0x000000FF // 1:32768 /////// CONFIG3H Options ////////////////////////////////////////////////// #define _MCLRE_OFF_3H 0x0000007F // RE3 input pin enabled// MCLR disabled #define _MCLRE_ON_3H 0x000000FF // MCLR pin enabled// RE3 input pin disabled #define _LPT1OSC_OFF_3H 0x000000FB // Timer1 configured for higher power operation #define _LPT1OSC_ON_3H 0x000000FF // Timer1 configured for low-power operation #define _PBADEN_OFF_3H 0x000000FD // PORTB<4:0> pins are configured as digital I/O on Reset #define _PBADEN_ON_3H 0x000000FF // PORTB<4:0> pins are configured as analog input channels on Reset #define _CCP2MX_OFF_3H 0x000000FE // CCP2 input/output is multiplexed with RB3 #define _CCP2MX_ON_3H 0x000000FF // CCP2 input/output is multiplexed with RC1 /////// CONFIG4L Options ////////////////////////////////////////////////// #define _STVREN_OFF_4L 0x000000FE // Stack full/underflow will not cause Reset #define _STVREN_ON_4L 0x000000FF // Stack full/underflow will cause Reset #define _LVP_OFF_4L 0x000000FB // Single-Supply ICSP disabled #define _LVP_ON_4L 0x000000FF // Single-Supply ICSP enabled #define _ICPRT_OFF_4L 0x000000DF // ICPORT disabled #define _ICPRT_ON_4L 0x000000FF // ICPORT enabled #define _XINST_OFF_4L 0x000000BF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode) #define _XINST_ON_4L 0x000000FF // Instruction set extension and Indexed Addressing mode enabled #define _DEBUG_ON_4L 0x0000007F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug #define _DEBUG_OFF_4L 0x000000FF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins /////// CONFIG5L Options ////////////////////////////////////////////////// #define _CP0_ON_5L 0x000000FE // Block 0 (000800-001FFFh) code-protected #define _CP0_OFF_5L 0x000000FF // Block 0 (000800-001FFFh) not code-protected #define _CP1_ON_5L 0x000000FD // Block 1 (002000-003FFFh) code-protected #define _CP1_OFF_5L 0x000000FF // Block 1 (002000-003FFFh) not code-protected #define _CP2_ON_5L 0x000000FB // Block 2 (004000-005FFFh) code-protected #define _CP2_OFF_5L 0x000000FF // Block 2 (004000-005FFFh) not code-protected /////// CONFIG5H Options ////////////////////////////////////////////////// #define _CPB_ON_5H 0x000000BF // Boot block (000000-0007FFh) code-protected #define _CPB_OFF_5H 0x000000FF // Boot block (000000-0007FFh) not code-protected #define _CPD_ON_5H 0x0000007F // Data EEPROM code-protected #define _CPD_OFF_5H 0x000000FF // Data EEPROM not code-protected /////// CONFIG6L Options ////////////////////////////////////////////////// #define _WRT0_ON_6L 0x000000FE // Block 0 (000800-001FFFh) write-protected #define _WRT0_OFF_6L 0x000000FF // Block 0 (000800-001FFFh) not write-protected #define _WRT1_ON_6L 0x000000FD // Block 1 (002000-003FFFh) write-protected #define _WRT1_OFF_6L 0x000000FF // Block 1 (002000-003FFFh) not write-protected #define _WRT2_ON_6L 0x000000FB // Block 2 (004000-005FFFh) write-protected #define _WRT2_OFF_6L 0x000000FF // Block 2 (004000-005FFFh) not write-protected /////// CONFIG6H Options ////////////////////////////////////////////////// #define _WRTB_ON_6H 0x000000BF // Boot block (000000-0007FFh) write-protected #define _WRTB_OFF_6H 0x000000FF // Boot block (000000-0007FFh) not write-protected #define _WRTC_ON_6H 0x000000DF // Configuration registers (300000-3000FFh) write-protected #define _WRTC_OFF_6H 0x000000FF // Configuration registers (300000-3000FFh) not write-protected #define _WRTD_ON_6H 0x0000007F // Data EEPROM write-protected #define _WRTD_OFF_6H 0x000000FF // Data EEPROM not write-protected /////// CONFIG7L Options ////////////////////////////////////////////////// #define _EBTR0_ON_7L 0x000000FE // Block 0 (000800-001FFFh) protected from table reads executed in other blocks #define _EBTR0_OFF_7L 0x000000FF // Block 0 (000800-001FFFh) not protected from table reads executed in other blocks #define _EBTR1_ON_7L 0x000000FD // Block 1 (002000-003FFFh) protected from table reads executed in other blocks #define _EBTR1_OFF_7L 0x000000FF // Block 1 (002000-003FFFh) not protected from table reads executed in other blocks #define _EBTR2_ON_7L 0x000000FB // Block 2 (004000-005FFFh) protected from table reads executed in other blocks #define _EBTR2_OFF_7L 0x000000FF // Block 2 (004000-005FFFh) not protected from table reads executed in other blocks /////// CONFIG7H Options ////////////////////////////////////////////////// #define _EBTRB_ON_7H 0x000000BF // Boot block (000000-0007FFh) protected from table reads executed in other blocks #define _EBTRB_OFF_7H 0x000000FF // Boot block (000000-0007FFh) not protected from table reads executed in other blocks #define _DEVID1 0x003FFFFE #define _DEVID2 0x003FFFFF #define _IDLOC0 0x00200000 #define _IDLOC1 0x00200001 #define _IDLOC2 0x00200002 #define _IDLOC3 0x00200003 #define _IDLOC4 0x00200004 #define _IDLOC5 0x00200005 #define _IDLOC6 0x00200006 #define _IDLOC7 0x00200007 ///////////////////////////////////////////////// // EEPROM Base Address when programing ///////////////////////////////////////////////// // To initialise EEPROM when a device is programmed // use #pragma DATA _EEPROM, 12, 34, 56 #define _EEPROM 0xF00000 /* //////////////////////////////////////////////// // registers define with @ for direct access //////////////////////////////////////////////// volatile char sppdata @SPPDATA; volatile char sppcfg @SPPCFG; volatile char sppeps @SPPEPS; volatile char sppcon @SPPCON; volatile char ufrm @UFRM; volatile char ufrml @UFRML; volatile char ufrmh @UFRMH; volatile char uir @UIR; volatile char uie @UIE; volatile char ueir @UEIR; volatile char ueie @UEIE; volatile char ustat @USTAT; volatile char ucon @UCON; volatile char uaddr @UADDR; volatile char ucfg @UCFG; volatile char uep0 @UEP0; volatile char uep1 @UEP1; volatile char uep2 @UEP2; volatile char uep3 @UEP3; volatile char uep4 @UEP4; volatile char uep5 @UEP5; volatile char uep6 @UEP6; volatile char uep7 @UEP7; volatile char uep8 @UEP8; volatile char uep9 @UEP9; volatile char uep10 @UEP10; volatile char uep11 @UEP11; volatile char uep12 @UEP12; volatile char uep13 @UEP13; volatile char uep14 @UEP14; volatile char uep15 @UEP15; volatile char PORTA @porta; // @PORTA; volatile char portb @PORTB; volatile char portc @PORTC; volatile char portd @PORTD; volatile char porte @PORTE; volatile char lata @LATA; volatile char latb @LATB; volatile char latc @LATC; volatile char latd @LATD; volatile char late @LATE; volatile char ddra @DDRA; volatile char trisa @TRISA; volatile char ddrb @DDRB; volatile char trisb @TRISB; volatile char ddrc @DDRC; volatile char trisc @TRISC; volatile char ddrd @DDRD; volatile char trisd @TRISD; volatile char ddre @DDRE; volatile char trise @TRISE; volatile char osctune @OSCTUNE; volatile char pie1 @PIE1; volatile char pir1 @PIR1; volatile char ipr1 @IPR1; volatile char pie2 @PIE2; volatile char pir2 @PIR2; volatile char ipr2 @IPR2; volatile char eecon1 @EECON1; volatile char eecon2 @EECON2; volatile char eedata @EEDATA; volatile char eeadr @EEADR; volatile char rcsta @RCSTA; volatile char txsta @TXSTA; volatile char txreg @TXREG; volatile char rcreg @RCREG; volatile char spbrg @SPBRG; volatile char spbrgh @SPBRGH; volatile char t3con @T3CON; volatile char tmr3l @TMR3L; volatile char tmr3h @TMR3H; volatile char cmcon @CMCON; volatile char cvrcon @CVRCON; volatile char ccp1as @CCP1AS; volatile char eccp1as @ECCP1AS; volatile char ccp1del @CCP1DEL; volatile char eccp1del @ECCP1DEL; volatile char baudcon @BAUDCON; volatile char ccp2con @CCP2CON; volatile char ccpr2 @CCPR2; volatile char ccpr2l @CCPR2L; volatile char ccpr2h @CCPR2H; volatile char ccp1con @CCP1CON; volatile char eccp1con @ECCP1CON; volatile char ccpr1 @CCPR1; volatile char ccpr1l @CCPR1L; volatile char ccpr1h @CCPR1H; volatile char adcon2 @ADCON2; volatile char adcon1 @ADCON1; volatile char adcon0 @ADCON0; volatile char adres @ADRES; volatile char adresl @ADRESL; volatile char adresh @ADRESH; volatile char sspcon2 @SSPCON2; volatile char sspcon1 @SSPCON1; volatile char sspstat @SSPSTAT; volatile char sspadd @SSPADD; volatile char sspbuf @SSPBUF; volatile char t2con @T2CON; volatile char pr2 @PR2; volatile char tmr2 @TMR2; volatile char t1con @T1CON; volatile char tmr1l @TMR1L; volatile char tmr1h @TMR1H; volatile char rcon @RCON; volatile char wdtcon @WDTCON; volatile char hlvdcon @HLVDCON; volatile char lvdcon @LVDCON; volatile char osccon @OSCCON; volatile char t0con @T0CON; volatile char tmr0l @TMR0L; volatile char tmr0h @TMR0H; volatile char status @STATUS; volatile char fsr2l @FSR2L; volatile char fsr2h @FSR2H; volatile char plusw2 @PLUSW2; volatile char preinc2 @PREINC2; volatile char postdec2 @POSTDEC2; volatile char postinc2 @POSTINC2; volatile char indf2 @INDF2; volatile char bsr @BSR; volatile char fsr1l @FSR1L; volatile char fsr1h @FSR1H; volatile char plusw1 @PLUSW1; volatile char preinc1 @PREINC1; volatile char postdec1 @POSTDEC1; volatile char postinc1 @POSTINC1; volatile char indf1 @INDF1; volatile char wreg @WREG; volatile char fsr0l @FSR0L; volatile char fsr0h @FSR0H; volatile char plusw0 @PLUSW0; volatile char preinc0 @PREINC0; volatile char postdec0 @POSTDEC0; volatile char postinc0 @POSTINC0; volatile char indf0 @INDF0; volatile char intcon3 @INTCON3; volatile char intcon2 @INTCON2; volatile char intcon @INTCON; volatile char prod @PROD; volatile char prodl @PRODL; volatile char prodh @PRODH; volatile char tablat @TABLAT; volatile char tblptr @TBLPTR; volatile char tblptrl @TBLPTRL; volatile char tblptrh @TBLPTRH; volatile char tblptru @TBLPTRU; volatile char pc @PC; volatile char pcl @PCL; volatile char pclath @PCLATH; volatile char pclatu @PCLATU; volatile char stkptr @STKPTR; volatile char tos @TOS; volatile char tosl @TOSL; volatile char tosh @TOSH; volatile char tosu @TOSU; */ #endif // _PIC18F4455_H_