|clock_block
icl => inst1.ACLR
icl => inst2.ACLR
icl => inst.ACLR
icl => inst3.ACLR
icl => inst4.ACLR
icl => inst14.ACLR
icl => inst15.ACLR
icl => inst16.ACLR
icl => inst21.ACLR
icl => inst22.ACLR
icl => inst23.ACLR
icl => inst24.ACLR
input_clock => inst1.CLK
test_output <= inst3
output_clock <= inst24

