// *************************************** // BoostC Header file for PIC18F2685 // Author(s): David Hobday // // Copyright (C) 2003-2010 Pavel Baranov // Copyright (C) 2003-2010 David Hobday // All Rights Reserved // *************************************** #ifndef _PIC18F2685_H_ #define _PIC18F2685_H_ // *************************************** // W and F definitions // *************************************** #define W 0x0000 #define F 0x0001 //////////////////////////////////////////////////////////////////////////// // // Register Definitions // //////////////////////////////////////////////////////////////////////////// //----- Register Files ----------------------------------------------------- #define RXF6SIDH 0x00000D60 #define RXF6SIDL 0x00000D61 #define RXF6EIDH 0x00000D62 #define RXF6EIDL 0x00000D63 #define RXF7SIDH 0x00000D64 #define RXF7SIDL 0x00000D65 #define RXF7EIDH 0x00000D66 #define RXF7EIDL 0x00000D67 #define RXF8SIDH 0x00000D68 #define RXF8SIDL 0x00000D69 #define RXF8EIDH 0x00000D6A #define RXF8EIDL 0x00000D6B #define RXF9SIDH 0x00000D70 #define RXF9SIDL 0x00000D71 #define RXF9EIDH 0x00000D72 #define RXF9EIDL 0x00000D73 #define RXF10SIDH 0x00000D74 #define RXF10SIDL 0x00000D75 #define RXF10EIDH 0x00000D76 #define RXF10EIDL 0x00000D77 #define RXF11SIDH 0x00000D78 #define RXF11SIDL 0x00000D79 #define RXF11EIDH 0x00000D7A #define RXF11EIDL 0x00000D7B #define RXF12SIDH 0x00000D80 #define RXF12SIDL 0x00000D81 #define RXF12EIDH 0x00000D82 #define RXF12EIDL 0x00000D83 #define RXF13SIDH 0x00000D84 #define RXF13SIDL 0x00000D85 #define RXF13EIDH 0x00000D86 #define RXF13EIDL 0x00000D87 #define RXF14SIDH 0x00000D88 #define RXF14SIDL 0x00000D89 #define RXF14EIDH 0x00000D8A #define RXF14EIDL 0x00000D8B #define RXF15SIDH 0x00000D90 #define RXF15SIDL 0x00000D91 #define RXF15EIDH 0x00000D92 #define RXF15EIDL 0x00000D93 #define RXFCON0 0x00000DD4 #define RXFCON1 0x00000DD5 #define SDFLC 0x00000DD8 #define RXFBCON0 0x00000DE0 #define RXFBCON1 0x00000DE1 #define RXFBCON2 0x00000DE2 #define RXFBCON3 0x00000DE3 #define RXFBCON4 0x00000DE4 #define RXFBCON5 0x00000DE5 #define RXFBCON6 0x00000DE6 #define RXFBCON7 0x00000DE7 #define MSEL0 0x00000DF0 #define MSEL1 0x00000DF1 #define MSEL2 0x00000DF2 #define MSEL3 0x00000DF3 #define BSEL0 0x00000DF8 #define BIE0 0x00000DFA #define TXBIE 0x00000DFC #define B0CON 0x00000E20 #define B0SIDH 0x00000E21 #define B0SIDL 0x00000E22 #define B0EIDH 0x00000E23 #define B0EIDL 0x00000E24 #define B0DLC 0x00000E25 #define B0D0 0x00000E26 #define B0D1 0x00000E27 #define B0D2 0x00000E28 #define B0D3 0x00000E29 #define B0D4 0x00000E2A #define B0D5 0x00000E2B #define B0D6 0x00000E2C #define B0D7 0x00000E2D #define CANSTAT_RO9 0x00000E2E #define CANCON_RO9 0x00000E2F #define B1CON 0x00000E30 #define B1SIDH 0x00000E31 #define B1SIDL 0x00000E32 #define B1EIDH 0x00000E33 #define B1EIDL 0x00000E34 #define B1DLC 0x00000E35 #define B1D0 0x00000E36 #define B1D1 0x00000E37 #define B1D2 0x00000E38 #define B1D3 0x00000E39 #define B1D4 0x00000E3A #define B1D5 0x00000E3B #define B1D6 0x00000E3C #define B1D7 0x00000E3D #define CANSTAT_RO8 0x00000E3E #define CANCON_RO8 0x00000E3F #define B2CON 0x00000E40 #define B2SIDH 0x00000E41 #define B2SIDL 0x00000E42 #define B2EIDH 0x00000E43 #define B2EIDL 0x00000E44 #define B2DLC 0x00000E45 #define B2D0 0x00000E46 #define B2D1 0x00000E47 #define B2D2 0x00000E48 #define B2D3 0x00000E49 #define B2D4 0x00000E4A #define B2D5 0x00000E4B #define B2D6 0x00000E4C #define B2D7 0x00000E4D #define CANSTAT_RO7 0x00000E4E #define CANCON_RO7 0x00000E4F #define B3CON 0x00000E50 #define B3SIDH 0x00000E51 #define B3SIDL 0x00000E52 #define B3EIDH 0x00000E53 #define B3EIDL 0x00000E54 #define B3DLC 0x00000E55 #define B3D0 0x00000E56 #define B3D1 0x00000E57 #define B3D2 0x00000E58 #define B3D3 0x00000E59 #define B3D4 0x00000E5A #define B3D5 0x00000E5B #define B3D6 0x00000E5C #define B3D7 0x00000E5D #define CANSTAT_RO6 0x00000E5E #define CANCON_RO6 0x00000E5F #define B4CON 0x00000E60 #define B4SIDH 0x00000E61 #define B4SIDL 0x00000E62 #define B4EIDH 0x00000E63 #define B4EIDL 0x00000E64 #define B4DLC 0x00000E65 #define B4D0 0x00000E66 #define B4D1 0x00000E67 #define B4D2 0x00000E68 #define B4D3 0x00000E69 #define B4D4 0x00000E6A #define B4D5 0x00000E6B #define B4D6 0x00000E6C #define B4D7 0x00000E6D #define CANSTAT_RO5 0x00000E6E #define CANCON_RO5 0x00000E6F #define B5CON 0x00000E70 #define B5SIDH 0x00000E71 #define B5SIDL 0x00000E72 #define B5EIDH 0x00000E73 #define B5EIDL 0x00000E74 #define B5DLC 0x00000E75 #define B5D0 0x00000E76 #define B5D1 0x00000E77 #define B5D2 0x00000E78 #define B5D3 0x00000E79 #define B5D4 0x00000E7A #define B5D5 0x00000E7B #define B5D6 0x00000E7C #define B5D7 0x00000E7D #define CANSTAT_RO4 0x00000E7E #define CANCON_RO4 0x00000E7F #define RXF0SIDH 0x00000F00 #define RXF0SIDL 0x00000F01 #define RXF0EIDH 0x00000F02 #define RXF0EIDL 0x00000F03 #define RXF1SIDH 0x00000F04 #define RXF1SIDL 0x00000F05 #define RXF1EIDH 0x00000F06 #define RXF1EIDL 0x00000F07 #define RXF2SIDH 0x00000F08 #define RXF2SIDL 0x00000F09 #define RXF2EIDH 0x00000F0A #define RXF2EIDL 0x00000F0B #define RXF3SIDH 0x00000F0C #define RXF3SIDL 0x00000F0D #define RXF3EIDH 0x00000F0E #define RXF3EIDL 0x00000F0F #define RXF4SIDH 0x00000F10 #define RXF4SIDL 0x00000F11 #define RXF4EIDH 0x00000F12 #define RXF4EIDL 0x00000F13 #define RXF5SIDH 0x00000F14 #define RXF5SIDL 0x00000F15 #define RXF5EIDH 0x00000F16 #define RXF5EIDL 0x00000F17 #define RXM0SIDH 0x00000F18 #define RXM0SIDL 0x00000F19 #define RXM0EIDH 0x00000F1A #define RXM0EIDL 0x00000F1B #define RXM1SIDH 0x00000F1C #define RXM1SIDL 0x00000F1D #define RXM1EIDH 0x00000F1E #define RXM1EIDL 0x00000F1F #define TXB2CON 0x00000F20 #define TXB2SIDH 0x00000F21 #define TXB2SIDL 0x00000F22 #define TXB2EIDH 0x00000F23 #define TXB2EIDL 0x00000F24 #define TXB2DLC 0x00000F25 #define TXB2D0 0x00000F26 #define TXB2D1 0x00000F27 #define TXB2D2 0x00000F28 #define TXB2D3 0x00000F29 #define TXB2D4 0x00000F2A #define TXB2D5 0x00000F2B #define TXB2D6 0x00000F2C #define TXB2D7 0x00000F2D #define CANSTAT_RO3 0x00000F2E #define CANCON_RO3 0x00000F2F #define TXB1CON 0x00000F30 #define TXB1SIDH 0x00000F31 #define TXB1SIDL 0x00000F32 #define TXB1EIDH 0x00000F33 #define TXB1EIDL 0x00000F34 #define TXB1DLC 0x00000F35 #define TXB1D0 0x00000F36 #define TXB1D1 0x00000F37 #define TXB1D2 0x00000F38 #define TXB1D3 0x00000F39 #define TXB1D4 0x00000F3A #define TXB1D5 0x00000F3B #define TXB1D6 0x00000F3C #define TXB1D7 0x00000F3D #define CANSTAT_RO2 0x00000F3E #define CANCON_RO2 0x00000F3F #define TXB0CON 0x00000F40 #define TXB0SIDH 0x00000F41 #define TXB0SIDL 0x00000F42 #define TXB0EIDH 0x00000F43 #define TXB0EIDL 0x00000F44 #define TXB0DLC 0x00000F45 #define TXB0D0 0x00000F46 #define TXB0D1 0x00000F47 #define TXB0D2 0x00000F48 #define TXB0D3 0x00000F49 #define TXB0D4 0x00000F4A #define TXB0D5 0x00000F4B #define TXB0D6 0x00000F4C #define TXB0D7 0x00000F4D #define CANSTAT_RO1 0x00000F4E #define CANCON_RO1 0x00000F4F #define RXB1CON 0x00000F50 #define RXB1SIDH 0x00000F51 #define RXB1SIDL 0x00000F52 #define RXB1EIDH 0x00000F53 #define RXB1EIDL 0x00000F54 #define RXB1DLC 0x00000F55 #define RXB1D0 0x00000F56 #define RXB1D1 0x00000F57 #define RXB1D2 0x00000F58 #define RXB1D3 0x00000F59 #define RXB1D4 0x00000F5A #define RXB1D5 0x00000F5B #define RXB1D6 0x00000F5C #define RXB1D7 0x00000F5D #define CANSTAT_RO0 0x00000F5E #define CANCON_RO0 0x00000F5F #define RXB0CON 0x00000F60 #define RXB0SIDH 0x00000F61 #define RXB0SIDL 0x00000F62 #define RXB0EIDH 0x00000F63 #define RXB0EIDL 0x00000F64 #define RXB0DLC 0x00000F65 #define RXB0D0 0x00000F66 #define RXB0D1 0x00000F67 #define RXB0D2 0x00000F68 #define RXB0D3 0x00000F69 #define RXB0D4 0x00000F6A #define RXB0D5 0x00000F6B #define RXB0D6 0x00000F6C #define RXB0D7 0x00000F6D #define CANSTAT 0x00000F6E #define CANCON 0x00000F6F #define BRGCON1 0x00000F70 #define BRGCON2 0x00000F71 #define BRGCON3 0x00000F72 #define CIOCON 0x00000F73 #define COMSTAT 0x00000F74 #define RXERRCNT 0x00000F75 #define TXERRCNT 0x00000F76 #define ECANCON 0x00000F77 #define PORTA 0x00000F80 #define PORTB 0x00000F81 #define PORTC 0x00000F82 //#define PORTE 0x00000F84 #define LATA 0x00000F89 #define LATB 0x00000F8A #define LATC 0x00000F8B #define DDRA 0x00000F92 #define TRISA 0x00000F92 #define DDRB 0x00000F93 #define TRISB 0x00000F93 #define DDRC 0x00000F94 #define TRISC 0x00000F94 #define OSCTUNE 0x00000F9B #define PIE1 0x00000F9D #define PIR1 0x00000F9E #define IPR1 0x00000F9F #define PIE2 0x00000FA0 #define PIR2 0x00000FA1 #define IPR2 0x00000FA2 #define PIE3 0x00000FA3 #define PIR3 0x00000FA4 #define IPR3 0x00000FA5 #define EECON1 0x00000FA6 #define EECON2 0x00000FA7 #define EEDATA 0x00000FA8 #define EEADR 0x00000FA9 #define EEADRH 0x00000FAA #define RCSTA 0x00000FAB #define TXSTA 0x00000FAC #define TXREG 0x00000FAD #define RCREG 0x00000FAE #define SPBRG 0x00000FAF #define SPBRGH 0x00000FB0 #define T3CON 0x00000FB1 #define TMR3L 0x00000FB2 #define TMR3H 0x00000FB3 #define BAUDCON 0x00000FB8 #define CCP1CON 0x00000FBD #define CCPR1 0x00000FBE #define CCPR1L 0x00000FBE #define CCPR1H 0x00000FBF #define ADCON2 0x00000FC0 #define ADCON1 0x00000FC1 #define ADCON0 0x00000FC2 #define ADRES 0x00000FC3 #define ADRESL 0x00000FC3 #define ADRESH 0x00000FC4 #define SSPCON2 0x00000FC5 #define SSPCON1 0x00000FC6 #define SSPSTAT 0x00000FC7 #define SSPADD 0x00000FC8 #define SSPBUF 0x00000FC9 #define T2CON 0x00000FCA #define PR2 0x00000FCB #define TMR2 0x00000FCC #define T1CON 0x00000FCD #define TMR1L 0x00000FCE #define TMR1H 0x00000FCF #define RCON 0x00000FD0 #define WDTCON 0x00000FD1 #define HLVDCON 0x00000FD2 #define LVDCON 0x00000FD2 #define OSCCON 0x00000FD3 #define T0CON 0x00000FD5 #define TMR0L 0x00000FD6 #define TMR0H 0x00000FD7 #define STATUS 0x00000FD8 #define FSR2L 0x00000FD9 #define FSR2H 0x00000FDA #define PLUSW2 0x00000FDB #define PREINC2 0x00000FDC #define POSTDEC2 0x00000FDD #define POSTINC2 0x00000FDE #define INDF2 0x00000FDF #define BSR 0x00000FE0 #define FSR1L 0x00000FE1 #define FSR1H 0x00000FE2 #define PLUSW1 0x00000FE3 #define PREINC1 0x00000FE4 #define POSTDEC1 0x00000FE5 #define POSTINC1 0x00000FE6 #define INDF1 0x00000FE7 #define WREG 0x00000FE8 #define FSR0L 0x00000FE9 #define FSR0H 0x00000FEA #define PLUSW0 0x00000FEB #define PREINC0 0x00000FEC #define POSTDEC0 0x00000FED #define POSTINC0 0x00000FEE #define INDF0 0x00000FEF #define INTCON3 0x00000FF0 #define INTCON2 0x00000FF1 #define INTCON 0x00000FF2 #define PROD 0x00000FF3 #define PRODL 0x00000FF3 #define PRODH 0x00000FF4 #define TABLAT 0x00000FF5 #define TBLPTR 0x00000FF6 #define TBLPTRL 0x00000FF6 #define TBLPTRH 0x00000FF7 #define TBLPTRU 0x00000FF8 #define PC 0x00000FF9 #define PCL 0x00000FF9 #define PCLATH 0x00000FFA #define PCLATU 0x00000FFB #define STKPTR 0x00000FFC #define TOS 0x00000FFD #define TOSL 0x00000FFD #define TOSH 0x00000FFE #define TOSU 0x00000FFF /////// RXF6SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF6SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF6EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF6EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF7SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF7SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF7EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF7EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF8SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF8SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF8EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF8EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF9SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF9SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF9EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF9EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF10SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF10SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF10EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF10EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF11SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF11SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF11EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF11EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF12SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF12SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF12EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF12EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF13SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF13SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF13EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF13EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF14SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF14SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF14EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF14EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF15SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF15SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF15EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF15EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXFCON0 Bits ///////////////////////////////////////////////////// #define RXF0EN 0x00000000 #define RXF1EN 0x00000001 #define RXF2EN 0x00000002 #define RXF3EN 0x00000003 #define RXF4EN 0x00000004 #define RXF5EN 0x00000005 #define RXF6EN 0x00000006 #define RXF7EN 0x00000007 /////// RXFCON1 Bits ///////////////////////////////////////////////////// #define RXF8EN 0x00000000 #define RXF9EN 0x00000001 #define RXF10EN 0x00000002 #define RXF11EN 0x00000003 #define RXF12EN 0x00000004 #define RXF13EN 0x00000005 #define RXF14EN 0x00000006 #define RXF15EN 0x00000007 /////// SDFLC Bits ///////////////////////////////////////////////////// #define DFLC0 0x00000000 #define DFLC1 0x00000001 #define DFLC2 0x00000002 #define DFLC3 0x00000003 #define DFLC4 0x00000004 #define FLC0 0x00000000 #define FLC1 0x00000001 #define FLC2 0x00000002 #define FLC3 0x00000003 #define FLC4 0x00000004 /////// RXFBCON0 Bits ///////////////////////////////////////////////////// #define F0BP_0 0x00000000 #define F0BP_1 0x00000001 #define F0BP_2 0x00000002 #define F0BP_3 0x00000003 #define F1BP_0 0x00000004 #define F1BP_1 0x00000005 #define F1BP_2 0x00000006 #define F1BP_3 0x00000007 /////// RXFBCON1 Bits ///////////////////////////////////////////////////// #define F2BP_0 0x00000000 #define F2BP_1 0x00000001 #define F2BP_2 0x00000002 #define F2BP_3 0x00000003 #define F3BP_0 0x00000004 #define F3BP_1 0x00000005 #define F3BP_2 0x00000006 #define F3BP_3 0x00000007 /////// RXFBCON2 Bits ///////////////////////////////////////////////////// #define F4BP_0 0x00000000 #define F4BP_1 0x00000001 #define F4BP_2 0x00000002 #define F4BP_3 0x00000003 #define F5BP_0 0x00000004 #define F5BP_1 0x00000005 #define F5BP_2 0x00000006 #define F5BP_3 0x00000007 /////// RXFBCON3 Bits ///////////////////////////////////////////////////// #define F6BP_0 0x00000000 #define F6BP_1 0x00000001 #define F6BP_2 0x00000002 #define F6BP_3 0x00000003 #define F7BP_0 0x00000004 #define F7BP_1 0x00000005 #define F7BP_2 0x00000006 #define F7BP_3 0x00000007 /////// RXFBCON4 Bits ///////////////////////////////////////////////////// #define F8BP_0 0x00000000 #define F8BP_1 0x00000001 #define F8BP_2 0x00000002 #define F8BP_3 0x00000003 #define F9BP_0 0x00000004 #define F9BP_1 0x00000005 #define F9BP_2 0x00000006 #define F9BP_3 0x00000007 /////// RXFBCON5 Bits ///////////////////////////////////////////////////// #define F10BP_0 0x00000000 #define F10BP_1 0x00000001 #define F10BP_2 0x00000002 #define F10BP_3 0x00000003 #define F11BP_0 0x00000004 #define F11BP_1 0x00000005 #define F11BP_2 0x00000006 #define F11BP_3 0x00000007 /////// RXFBCON6 Bits ///////////////////////////////////////////////////// #define F12BP_0 0x00000000 #define F12BP_1 0x00000001 #define F12BP_2 0x00000002 #define F12BP_3 0x00000003 #define F13BP_0 0x00000004 #define F13BP_1 0x00000005 #define F13BP_2 0x00000006 #define F13BP_3 0x00000007 /////// RXFBCON7 Bits ///////////////////////////////////////////////////// #define F14BP_0 0x00000000 #define F14BP_1 0x00000001 #define F14BP_2 0x00000002 #define F14BP_3 0x00000003 #define F15BP_0 0x00000004 #define F15BP_1 0x00000005 #define F15BP_2 0x00000006 #define F15BP_3 0x00000007 /////// MSEL0 Bits ///////////////////////////////////////////////////// #define FIL0_0 0x00000000 #define FIL0_1 0x00000001 #define FIL1_0 0x00000002 #define FIL1_1 0x00000003 #define FIL2_0 0x00000004 #define FIL2_1 0x00000005 #define FIL3_0 0x00000006 #define FIL3_1 0x00000007 /////// MSEL1 Bits ///////////////////////////////////////////////////// #define FIL4_0 0x00000000 #define FIL4_1 0x00000001 #define FIL5_0 0x00000002 #define FIL5_1 0x00000003 #define FIL6_0 0x00000004 #define FIL6_1 0x00000005 #define FIL7_0 0x00000006 #define FIL7_1 0x00000007 /////// MSEL2 Bits ///////////////////////////////////////////////////// #define FIL8_0 0x00000000 #define FIL8_1 0x00000001 #define FIL9_0 0x00000002 #define FIL9_1 0x00000003 #define FIL10_0 0x00000004 #define FIL10_1 0x00000005 #define FIL11_0 0x00000006 #define FIL11_1 0x00000007 /////// MSEL3 Bits ///////////////////////////////////////////////////// #define FIL12_0 0x00000000 #define FIL12_1 0x00000001 #define FIL13_0 0x00000002 #define FIL13_1 0x00000003 #define FIL14_0 0x00000004 #define FIL14_1 0x00000005 #define FIL15_0 0x00000006 #define FIL15_1 0x00000007 /////// BSEL0 Bits ///////////////////////////////////////////////////// #define B0TXEN 0x00000002 #define B1TXEN 0x00000003 #define B2TXEN 0x00000004 #define B3TXEN 0x00000005 #define B4TXEN 0x00000006 #define B5TXEN 0x00000007 /////// BIE0 Bits ///////////////////////////////////////////////////// #define RXB0IE 0x00000000 #define RXB1IE 0x00000001 #define B0IE 0x00000002 #define B1IE 0x00000003 #define B2IE 0x00000004 #define B3IE 0x00000005 #define B4IE 0x00000006 #define B5IE 0x00000007 /////// TXBIE Bits ///////////////////////////////////////////////////// #define TXB0IE 0x00000002 #define TXB1IE 0x00000003 #define TXB2IE 0x00000004 /////// B0CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B0CON 0x00000005 /////// B0SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B0SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDE 0x00000003 /////// B0EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B0EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B0DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define TXRTR 0x00000006 #define RB0_B0DLC 0x00000004 #define RB1_B0DLC 0x00000005 /////// B0D0 Bits ///////////////////////////////////////////////////// #define B0D00 0x00000000 #define B0D01 0x00000001 #define B0D02 0x00000002 #define B0D03 0x00000003 #define B0D04 0x00000004 #define B0D05 0x00000005 #define B0D06 0x00000006 #define B0D07 0x00000007 /////// B0D1 Bits ///////////////////////////////////////////////////// #define B0D10 0x00000000 #define B0D11 0x00000001 #define B0D12 0x00000002 #define B0D13 0x00000003 #define B0D14 0x00000004 #define B0D15 0x00000005 #define B0D16 0x00000006 #define B0D17 0x00000007 /////// B0D2 Bits ///////////////////////////////////////////////////// #define B0D20 0x00000000 #define B0D21 0x00000001 #define B0D22 0x00000002 #define B0D23 0x00000003 #define B0D24 0x00000004 #define B0D25 0x00000005 #define B0D26 0x00000006 #define B0D27 0x00000007 /////// B0D3 Bits ///////////////////////////////////////////////////// #define B0D30 0x00000000 #define B0D31 0x00000001 #define B0D32 0x00000002 #define B0D33 0x00000003 #define B0D34 0x00000004 #define B0D35 0x00000005 #define B0D36 0x00000006 #define B0D37 0x00000007 /////// B0D4 Bits ///////////////////////////////////////////////////// #define B0D40 0x00000000 #define B0D41 0x00000001 #define B0D42 0x00000002 #define B0D43 0x00000003 #define B0D44 0x00000004 #define B0D45 0x00000005 #define B0D46 0x00000006 #define B0D47 0x00000007 /////// B0D5 Bits ///////////////////////////////////////////////////// #define B0D50 0x00000000 #define B0D51 0x00000001 #define B0D52 0x00000002 #define B0D53 0x00000003 #define B0D54 0x00000004 #define B0D55 0x00000005 #define B0D56 0x00000006 #define B0D57 0x00000007 /////// B0D6 Bits ///////////////////////////////////////////////////// #define B0D60 0x00000000 #define B0D61 0x00000001 #define B0D62 0x00000002 #define B0D63 0x00000003 #define B0D64 0x00000004 #define B0D65 0x00000005 #define B0D66 0x00000006 #define B0D67 0x00000007 /////// B0D7 Bits ///////////////////////////////////////////////////// #define B0D70 0x00000000 #define B0D71 0x00000001 #define B0D72 0x00000002 #define B0D73 0x00000003 #define B0D74 0x00000004 #define B0D75 0x00000005 #define B0D76 0x00000006 #define B0D77 0x00000007 /////// CANSTAT_RO9 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO9 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// B1CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B1CON 0x00000005 /////// B1SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B1SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDE 0x00000003 /////// B1EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B1EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B1DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define RB0_B1DLC 0x00000004 #define RB1_B1DLC 0x00000005 #define TXRTR 0x00000006 /////// B1D0 Bits ///////////////////////////////////////////////////// #define B1D00 0x00000000 #define B1D01 0x00000001 #define B1D02 0x00000002 #define B1D03 0x00000003 #define B1D04 0x00000004 #define B1D05 0x00000005 #define B1D06 0x00000006 #define B1D07 0x00000007 /////// B1D1 Bits ///////////////////////////////////////////////////// #define B1D10 0x00000000 #define B1D11 0x00000001 #define B1D12 0x00000002 #define B1D13 0x00000003 #define B1D14 0x00000004 #define B1D15 0x00000005 #define B1D16 0x00000006 #define B1D17 0x00000007 /////// B1D2 Bits ///////////////////////////////////////////////////// #define B1D20 0x00000000 #define B1D21 0x00000001 #define B1D22 0x00000002 #define B1D23 0x00000003 #define B1D24 0x00000004 #define B1D25 0x00000005 #define B1D26 0x00000006 #define B1D27 0x00000007 /////// B1D3 Bits ///////////////////////////////////////////////////// #define B1D30 0x00000000 #define B1D31 0x00000001 #define B1D32 0x00000002 #define B1D33 0x00000003 #define B1D34 0x00000004 #define B1D35 0x00000005 #define B1D36 0x00000006 #define B1D37 0x00000007 /////// B1D4 Bits ///////////////////////////////////////////////////// #define B1D40 0x00000000 #define B1D41 0x00000001 #define B1D42 0x00000002 #define B1D43 0x00000003 #define B1D44 0x00000004 #define B1D45 0x00000005 #define B1D46 0x00000006 #define B1D47 0x00000007 /////// B1D5 Bits ///////////////////////////////////////////////////// #define B1D50 0x00000000 #define B1D51 0x00000001 #define B1D52 0x00000002 #define B1D53 0x00000003 #define B1D54 0x00000004 #define B1D55 0x00000005 #define B1D56 0x00000006 #define B1D57 0x00000007 /////// B1D6 Bits ///////////////////////////////////////////////////// #define B1D60 0x00000000 #define B1D61 0x00000001 #define B1D62 0x00000002 #define B1D63 0x00000003 #define B1D64 0x00000004 #define B1D65 0x00000005 #define B1D66 0x00000006 #define B1D67 0x00000007 /////// B1D7 Bits ///////////////////////////////////////////////////// #define B1D70 0x00000000 #define B1D71 0x00000001 #define B1D72 0x00000002 #define B1D73 0x00000003 #define B1D74 0x00000004 #define B1D75 0x00000005 #define B1D76 0x00000006 #define B1D77 0x00000007 /////// CANSTAT_RO8 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO8 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// B2CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B2CON 0x00000005 /////// B2SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B2SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDE 0x00000003 /////// B2EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B2EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B2DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define TXRTR 0x00000006 #define RB0_B2DLC 0x00000004 #define RB1_B2DLC 0x00000005 /////// B2D0 Bits ///////////////////////////////////////////////////// #define B2D00 0x00000000 #define B2D01 0x00000001 #define B2D02 0x00000002 #define B2D03 0x00000003 #define B2D04 0x00000004 #define B2D05 0x00000005 #define B2D06 0x00000006 #define B2D07 0x00000007 /////// B2D1 Bits ///////////////////////////////////////////////////// #define B2D10 0x00000000 #define B2D11 0x00000001 #define B2D12 0x00000002 #define B2D13 0x00000003 #define B2D14 0x00000004 #define B2D15 0x00000005 #define B2D16 0x00000006 #define B2D17 0x00000007 /////// B2D2 Bits ///////////////////////////////////////////////////// #define B2D20 0x00000000 #define B2D21 0x00000001 #define B2D22 0x00000002 #define B2D23 0x00000003 #define B2D24 0x00000004 #define B2D25 0x00000005 #define B2D26 0x00000006 #define B2D27 0x00000007 /////// B2D3 Bits ///////////////////////////////////////////////////// #define B2D30 0x00000000 #define B2D31 0x00000001 #define B2D32 0x00000002 #define B2D33 0x00000003 #define B2D34 0x00000004 #define B2D35 0x00000005 #define B2D36 0x00000006 #define B2D37 0x00000007 /////// B2D4 Bits ///////////////////////////////////////////////////// #define B2D40 0x00000000 #define B2D41 0x00000001 #define B2D42 0x00000002 #define B2D43 0x00000003 #define B2D44 0x00000004 #define B2D45 0x00000005 #define B2D46 0x00000006 #define B2D47 0x00000007 /////// B2D5 Bits ///////////////////////////////////////////////////// #define B2D50 0x00000000 #define B2D51 0x00000001 #define B2D52 0x00000002 #define B2D53 0x00000003 #define B2D54 0x00000004 #define B2D55 0x00000005 #define B2D56 0x00000006 #define B2D57 0x00000007 /////// B2D6 Bits ///////////////////////////////////////////////////// #define B2D60 0x00000000 #define B2D61 0x00000001 #define B2D62 0x00000002 #define B2D63 0x00000003 #define B2D64 0x00000004 #define B2D65 0x00000005 #define B2D66 0x00000006 #define B2D67 0x00000007 /////// B2D7 Bits ///////////////////////////////////////////////////// #define B2D70 0x00000000 #define B2D71 0x00000001 #define B2D72 0x00000002 #define B2D73 0x00000003 #define B2D74 0x00000004 #define B2D75 0x00000005 #define B2D76 0x00000006 #define B2D77 0x00000007 /////// CANSTAT_RO7 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO7 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// B3CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B3CON 0x00000005 /////// B3SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B3SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDE 0x00000003 /////// B3EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B3EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B3DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define TXRTR 0x00000006 #define RB0_B3DLC 0x00000004 #define RB1_B3DLC 0x00000005 /////// B3D0 Bits ///////////////////////////////////////////////////// #define B3D00 0x00000000 #define B3D01 0x00000001 #define B3D02 0x00000002 #define B3D03 0x00000003 #define B3D04 0x00000004 #define B3D05 0x00000005 #define B3D06 0x00000006 #define B3D07 0x00000007 /////// B3D1 Bits ///////////////////////////////////////////////////// #define B3D10 0x00000000 #define B3D11 0x00000001 #define B3D12 0x00000002 #define B3D13 0x00000003 #define B3D14 0x00000004 #define B3D15 0x00000005 #define B3D16 0x00000006 #define B3D17 0x00000007 /////// B3D2 Bits ///////////////////////////////////////////////////// #define B3D20 0x00000000 #define B3D21 0x00000001 #define B3D22 0x00000002 #define B3D23 0x00000003 #define B3D24 0x00000004 #define B3D25 0x00000005 #define B3D26 0x00000006 #define B3D27 0x00000007 /////// B3D3 Bits ///////////////////////////////////////////////////// #define B3D30 0x00000000 #define B3D31 0x00000001 #define B3D32 0x00000002 #define B3D33 0x00000003 #define B3D34 0x00000004 #define B3D35 0x00000005 #define B3D36 0x00000006 #define B3D37 0x00000007 /////// B3D4 Bits ///////////////////////////////////////////////////// #define B3D40 0x00000000 #define B3D41 0x00000001 #define B3D42 0x00000002 #define B3D43 0x00000003 #define B3D44 0x00000004 #define B3D45 0x00000005 #define B3D46 0x00000006 #define B3D47 0x00000007 /////// B3D5 Bits ///////////////////////////////////////////////////// #define B3D50 0x00000000 #define B3D51 0x00000001 #define B3D52 0x00000002 #define B3D53 0x00000003 #define B3D54 0x00000004 #define B3D55 0x00000005 #define B3D56 0x00000006 #define B3D57 0x00000007 /////// B3D6 Bits ///////////////////////////////////////////////////// #define B3D60 0x00000000 #define B3D61 0x00000001 #define B3D62 0x00000002 #define B3D63 0x00000003 #define B3D64 0x00000004 #define B3D65 0x00000005 #define B3D66 0x00000006 #define B3D67 0x00000007 /////// B3D7 Bits ///////////////////////////////////////////////////// #define B3D70 0x00000000 #define B3D71 0x00000001 #define B3D72 0x00000002 #define B3D73 0x00000003 #define B3D74 0x00000004 #define B3D75 0x00000005 #define B3D76 0x00000006 #define B3D77 0x00000007 /////// CANSTAT_RO6 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO6 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// B4CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B4CON 0x00000005 /////// B4SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B4SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDE 0x00000003 /////// B4EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B4EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B4DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define TXRTR 0x00000006 #define RB0_B4DLC 0x00000004 #define RB1_B4DLC 0x00000005 /////// B4D0 Bits ///////////////////////////////////////////////////// #define B4D00 0x00000000 #define B4D01 0x00000001 #define B4D02 0x00000002 #define B4D03 0x00000003 #define B4D04 0x00000004 #define B4D05 0x00000005 #define B4D06 0x00000006 #define B4D07 0x00000007 /////// B4D1 Bits ///////////////////////////////////////////////////// #define B4D10 0x00000000 #define B4D11 0x00000001 #define B4D12 0x00000002 #define B4D13 0x00000003 #define B4D14 0x00000004 #define B4D15 0x00000005 #define B4D16 0x00000006 #define B4D17 0x00000007 /////// B4D2 Bits ///////////////////////////////////////////////////// #define B4D20 0x00000000 #define B4D21 0x00000001 #define B4D22 0x00000002 #define B4D23 0x00000003 #define B4D24 0x00000004 #define B4D25 0x00000005 #define B4D26 0x00000006 #define B4D27 0x00000007 /////// B4D3 Bits ///////////////////////////////////////////////////// #define B4D30 0x00000000 #define B4D31 0x00000001 #define B4D32 0x00000002 #define B4D33 0x00000003 #define B4D34 0x00000004 #define B4D35 0x00000005 #define B4D36 0x00000006 #define B4D37 0x00000007 /////// B4D4 Bits ///////////////////////////////////////////////////// #define B4D40 0x00000000 #define B4D41 0x00000001 #define B4D42 0x00000002 #define B4D43 0x00000003 #define B4D44 0x00000004 #define B4D45 0x00000005 #define B4D46 0x00000006 #define B4D47 0x00000007 /////// B4D5 Bits ///////////////////////////////////////////////////// #define B4D50 0x00000000 #define B4D51 0x00000001 #define B4D52 0x00000002 #define B4D53 0x00000003 #define B4D54 0x00000004 #define B4D55 0x00000005 #define B4D56 0x00000006 #define B4D57 0x00000007 /////// B4D6 Bits ///////////////////////////////////////////////////// #define B4D60 0x00000000 #define B4D61 0x00000001 #define B4D62 0x00000002 #define B4D63 0x00000003 #define B4D64 0x00000004 #define B4D65 0x00000005 #define B4D66 0x00000006 #define B4D67 0x00000007 /////// B4D7 Bits ///////////////////////////////////////////////////// #define B4D70 0x00000000 #define B4D71 0x00000001 #define B4D72 0x00000002 #define B4D73 0x00000003 #define B4D74 0x00000004 #define B4D75 0x00000005 #define B4D76 0x00000006 #define B46D77 0x00000007 #define B4D77 0x00000007 /////// CANSTAT_RO5 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO5 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// B5CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define RTREN 0x00000002 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 #define RXRTRRO_B5CON 0x00000005 /////// B5SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// B5SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// B5EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// B5EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// B5DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define RB0_B5DLC 0x00000004 #define RB1_B5DLC 0x00000005 /////// B5D0 Bits ///////////////////////////////////////////////////// #define B5D00 0x00000000 #define B5D01 0x00000001 #define B5D02 0x00000002 #define B5D03 0x00000003 #define B5D04 0x00000004 #define B5D05 0x00000005 #define B5D06 0x00000006 #define B57D07 0x00000007 #define B5D07 0x00000007 /////// B5D1 Bits ///////////////////////////////////////////////////// #define B5D10 0x00000000 #define B5D11 0x00000001 #define B5D12 0x00000002 #define B5D13 0x00000003 #define B5D14 0x00000004 #define B5D15 0x00000005 #define B5D16 0x00000006 #define B5D17 0x00000007 /////// B5D2 Bits ///////////////////////////////////////////////////// #define B5D20 0x00000000 #define B5D21 0x00000001 #define B5D22 0x00000002 #define B57D23 0x00000003 #define B5D24 0x00000004 #define B5D25 0x00000005 #define B5D26 0x00000006 #define B5D27 0x00000007 #define B5D23 0x00000003 /////// B5D3 Bits ///////////////////////////////////////////////////// #define B5D30 0x00000000 #define B5D31 0x00000001 #define B5D32 0x00000002 #define B5D33 0x00000003 #define B5D34 0x00000004 #define B5D35 0x00000005 #define B5D36 0x00000006 #define B5D37 0x00000007 /////// B5D4 Bits ///////////////////////////////////////////////////// #define B5D40 0x00000000 #define B5D41 0x00000001 #define B5D42 0x00000002 #define B5D43 0x00000003 #define B5D44 0x00000004 #define B5D45 0x00000005 #define B5D46 0x00000006 #define B5D47 0x00000007 /////// B5D5 Bits ///////////////////////////////////////////////////// #define B5D50 0x00000000 #define B5D51 0x00000001 #define B5D52 0x00000002 #define B5D53 0x00000003 #define B5D54 0x00000004 #define B5D55 0x00000005 #define B5D56 0x00000006 #define B5D57 0x00000007 /////// B5D6 Bits ///////////////////////////////////////////////////// #define B5D60 0x00000000 #define B5D61 0x00000001 #define B5D62 0x00000002 #define B5D63 0x00000003 #define B5D64 0x00000004 #define B5D65 0x00000005 #define B5D66 0x00000006 #define B5D67 0x00000007 /////// B5D7 Bits ///////////////////////////////////////////////////// #define B5D70 0x00000000 #define B5D71 0x00000001 #define B5D72 0x00000002 #define B5D73 0x00000003 #define B5D74 0x00000004 #define B5D75 0x00000005 #define B5D76 0x00000006 #define B5D77 0x00000007 /////// CANSTAT_RO4 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO4 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// RXF0SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF0SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF0EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF0EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF1SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF1SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF1EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF1EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF2SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF2SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF2EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF2EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF3SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF3SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF3EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF3EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF4SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF4SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF4EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF4EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXF5SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXF5SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 #define EXIDEN 0x00000003 /////// RXF5EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXF5EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXM0SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXM0SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDEN 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// RXM0EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXM0EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXM1SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXM1SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDEN 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// RXM1EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXM1EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// TXB2CON Bits ///////////////////////////////////////////////////// #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIFBXB2CON 0x00000007 #define TXBIF 0x00000007 /////// TXB2SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// TXB2SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// TXB2EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// TXB2EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// TXB2DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define TXRTR 0x00000006 /////// TXB2D0 Bits ///////////////////////////////////////////////////// #define TXB2D00 0x00000000 #define TXB2D01 0x00000001 #define TXB2D02 0x00000002 #define TXB2D03 0x00000003 #define TXB2D04 0x00000004 #define TXB2D05 0x00000005 #define TXB2D06 0x00000006 #define TXB2D07 0x00000007 /////// TXB2D1 Bits ///////////////////////////////////////////////////// #define TXB2D10 0x00000000 #define TXB2D11 0x00000001 #define TXB2D12 0x00000002 #define TXB2D13 0x00000003 #define TXB2D14 0x00000004 #define TXB2D15 0x00000005 #define TXB2D16 0x00000006 #define TXB2D17 0x00000007 /////// TXB2D2 Bits ///////////////////////////////////////////////////// #define TXB2D20 0x00000000 #define TXB2D21 0x00000001 #define TXB2D22 0x00000002 #define TXB2D23 0x00000003 #define TXB2D24 0x00000004 #define TXB2D25 0x00000005 #define TXB2D26 0x00000006 #define TXB2D27 0x00000007 /////// TXB2D3 Bits ///////////////////////////////////////////////////// #define TXB2D30 0x00000000 #define TXB2D31 0x00000001 #define TXB2D32 0x00000002 #define TXB2D33 0x00000003 #define TXB2D34 0x00000004 #define TXB2D35 0x00000005 #define TXB2D36 0x00000006 #define TXB2D37 0x00000007 /////// TXB2D4 Bits ///////////////////////////////////////////////////// #define TXB2D40 0x00000000 #define TXB2D41 0x00000001 #define TXB2D42 0x00000002 #define TXB2D43 0x00000003 #define TXB2D44 0x00000004 #define TXB2D45 0x00000005 #define TXB2D46 0x00000006 #define TXB2D47 0x00000007 /////// TXB2D5 Bits ///////////////////////////////////////////////////// #define TXB2D50 0x00000000 #define TXB2D51 0x00000001 #define TXB2D52 0x00000002 #define TXB2D53 0x00000003 #define TXB2D54 0x00000004 #define TXB2D55 0x00000005 #define TXB2D56 0x00000006 #define TXB2D57 0x00000007 /////// TXB2D6 Bits ///////////////////////////////////////////////////// #define TXB2D60 0x00000000 #define TXB2D61 0x00000001 #define TXB2D62 0x00000002 #define TXB2D63 0x00000003 #define TXB2D64 0x00000004 #define TXB2D65 0x00000005 #define TXB2D66 0x00000006 #define TXB2D67 0x00000007 /////// TXB2D7 Bits ///////////////////////////////////////////////////// #define TXB2D70 0x00000000 #define TXB2D71 0x00000001 #define TXB2D72 0x00000002 #define TXB2D73 0x00000003 #define TXB2D74 0x00000004 #define TXB2D75 0x00000005 #define TXB2D76 0x00000006 #define TXB2D77 0x00000007 /////// CANSTAT_RO3 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO3 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// TXB1CON Bits ///////////////////////////////////////////////////// #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIFTXB1CON 0x00000007 #define TXBIF 0x00000007 /////// TXB1SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// TXB1SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// TXB1EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// TXB1EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// TXB1DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define TXRTR 0x00000006 /////// TXB1D0 Bits ///////////////////////////////////////////////////// #define TXB1D00 0x00000000 #define TXB1D01 0x00000001 #define TXB1D02 0x00000002 #define TXB1D03 0x00000003 #define TXB1D04 0x00000004 #define TXB1D05 0x00000005 #define TXB1D06 0x00000006 #define TXB1D07 0x00000007 /////// TXB1D1 Bits ///////////////////////////////////////////////////// #define TXB1D10 0x00000000 #define TXB1D11 0x00000001 #define TXB1D12 0x00000002 #define TXB1D13 0x00000003 #define TXB1D14 0x00000004 #define TXB1D15 0x00000005 #define TXB1D16 0x00000006 #define TXB1D17 0x00000007 /////// TXB1D2 Bits ///////////////////////////////////////////////////// #define TXB1D20 0x00000000 #define TXB1D21 0x00000001 #define TXB1D22 0x00000002 #define TXB1D23 0x00000003 #define TXB1D24 0x00000004 #define TXB1D25 0x00000005 #define TXB1D26 0x00000006 #define TXB1D27 0x00000007 /////// TXB1D3 Bits ///////////////////////////////////////////////////// #define TXB1D30 0x00000000 #define TXB1D31 0x00000001 #define TXB1D32 0x00000002 #define TXB1D33 0x00000003 #define TXB1D34 0x00000004 #define TXB1D35 0x00000005 #define TXB1D36 0x00000006 #define TXB1D37 0x00000007 /////// TXB1D4 Bits ///////////////////////////////////////////////////// #define TXB1D40 0x00000000 #define TXB1D41 0x00000001 #define TXB1D42 0x00000002 #define TXB1D43 0x00000003 #define TXB1D44 0x00000004 #define TXB1D45 0x00000005 #define TXB1D46 0x00000006 #define TXB1D47 0x00000007 /////// TXB1D5 Bits ///////////////////////////////////////////////////// #define TXB1D50 0x00000000 #define TXB1D51 0x00000001 #define TXB1D52 0x00000002 #define TXB1D53 0x00000003 #define TXB1D54 0x00000004 #define TXB1D55 0x00000005 #define TXB1D56 0x00000006 #define TXB1D57 0x00000007 /////// TXB1D6 Bits ///////////////////////////////////////////////////// #define TXB1D60 0x00000000 #define TXB1D61 0x00000001 #define TXB1D62 0x00000002 #define TXB1D63 0x00000003 #define TXB1D64 0x00000004 #define TXB1D65 0x00000005 #define TXB1D66 0x00000006 #define TXB1D67 0x00000007 /////// TXB1D7 Bits ///////////////////////////////////////////////////// #define TXB1D70 0x00000000 #define TXB1D71 0x00000001 #define TXB1D72 0x00000002 #define TXB1D73 0x00000003 #define TXB1D74 0x00000004 #define TXB1D75 0x00000005 #define TXB1D76 0x00000006 #define TXB1D77 0x00000007 /////// CANSTAT_RO2 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO2 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// TXB0CON Bits ///////////////////////////////////////////////////// #define TXPRI0 0x00000000 #define TXPRI1 0x00000001 #define TXREQ 0x00000003 #define TXERR 0x00000004 #define TXLARB 0x00000005 #define TXABT 0x00000006 #define TXBIF 0x00000007 /////// TXB0SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// TXB0SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXIDE 0x00000003 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// TXB0EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// TXB0EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// TXB0DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define TXRTR 0x00000006 /////// TXB0D0 Bits ///////////////////////////////////////////////////// #define TXB0D00 0x00000000 #define TXB0D01 0x00000001 #define TXB0D02 0x00000002 #define TXB0D03 0x00000003 #define TXB0D04 0x00000004 #define TXB0D05 0x00000005 #define TXB0D06 0x00000006 #define TXB0D07 0x00000007 /////// TXB0D1 Bits ///////////////////////////////////////////////////// #define TXB0D10 0x00000000 #define TXB0D11 0x00000001 #define TXB0D12 0x00000002 #define TXB0D13 0x00000003 #define TXB0D14 0x00000004 #define TXB0D15 0x00000005 #define TXB0D16 0x00000006 #define TXB0D17 0x00000007 /////// TXB0D2 Bits ///////////////////////////////////////////////////// #define TXB0D20 0x00000000 #define TXB0D21 0x00000001 #define TXB0D22 0x00000002 #define TXB0D23 0x00000003 #define TXB0D24 0x00000004 #define TXB0D25 0x00000005 #define TXB0D26 0x00000006 #define TXB0D27 0x00000007 /////// TXB0D3 Bits ///////////////////////////////////////////////////// #define TXB0D30 0x00000000 #define TXB0D31 0x00000001 #define TXB0D32 0x00000002 #define TXB0D33 0x00000003 #define TXB0D34 0x00000004 #define TXB0D35 0x00000005 #define TXB0D36 0x00000006 #define TXB0D37 0x00000007 /////// TXB0D4 Bits ///////////////////////////////////////////////////// #define TXB0D40 0x00000000 #define TXB0D41 0x00000001 #define TXB0D42 0x00000002 #define TXB0D43 0x00000003 #define TXB0D44 0x00000004 #define TXB0D45 0x00000005 #define TXB0D46 0x00000006 #define TXB0D47 0x00000007 /////// TXB0D5 Bits ///////////////////////////////////////////////////// #define TXB0D50 0x00000000 #define TXB0D51 0x00000001 #define TXB0D52 0x00000002 #define TXB0D53 0x00000003 #define TXB0D54 0x00000004 #define TXB0D55 0x00000005 #define TXB0D56 0x00000006 #define TXB0D57 0x00000007 /////// TXB0D6 Bits ///////////////////////////////////////////////////// #define TXB0D60 0x00000000 #define TXB0D61 0x00000001 #define TXB0D62 0x00000002 #define TXB0D63 0x00000003 #define TXB0D64 0x00000004 #define TXB0D65 0x00000005 #define TXB0D66 0x00000006 #define TXB0D67 0x00000007 /////// TXB0D7 Bits ///////////////////////////////////////////////////// #define TXB0D70 0x00000000 #define TXB0D71 0x00000001 #define TXB0D72 0x00000002 #define TXB0D73 0x00000003 #define TXB0D74 0x00000004 #define TXB0D75 0x00000005 #define TXB0D76 0x00000006 #define TXB0D77 0x00000007 /////// CANSTAT_RO1 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO1 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// RXB1CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define RXRTRRO_RXB1CON 0x00000003 #define RXM0 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 /////// RXB1SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXB1SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// RXB1EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXB1EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXB1DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define RB0_RXB1DLC 0x00000004 #define RB1_RXB1DLC 0x00000005 /////// RXB1D0 Bits ///////////////////////////////////////////////////// #define RXB1D00 0x00000000 #define RXB1D01 0x00000001 #define RXB1D02 0x00000002 #define RXB1D03 0x00000003 #define RXB1D04 0x00000004 #define RXB1D05 0x00000005 #define RXB1D06 0x00000006 #define RXB1D07 0x00000007 /////// RXB1D1 Bits ///////////////////////////////////////////////////// #define RXB1D10 0x00000000 #define RXB1D11 0x00000001 #define RXB1D12 0x00000002 #define RXB1D13 0x00000003 #define RXB1D14 0x00000004 #define RXB1D15 0x00000005 #define RXB1D16 0x00000006 #define RXB1D17 0x00000007 /////// RXB1D2 Bits ///////////////////////////////////////////////////// #define RXB1D20 0x00000000 #define RXB1D21 0x00000001 #define RXB1D22 0x00000002 #define RXB1D23 0x00000003 #define RXB1D24 0x00000004 #define RXB1D25 0x00000005 #define RXB1D26 0x00000006 #define RXB1D27 0x00000007 /////// RXB1D3 Bits ///////////////////////////////////////////////////// #define RXB1D30 0x00000000 #define RXB1D31 0x00000001 #define RXB1D32 0x00000002 #define RXB1D33 0x00000003 #define RXB1D34 0x00000004 #define RXB1D35 0x00000005 #define RXB1D36 0x00000006 #define RXB1D37 0x00000007 /////// RXB1D4 Bits ///////////////////////////////////////////////////// #define RXB1D40 0x00000000 #define RXB1D41 0x00000001 #define RXB1D42 0x00000002 #define RXB1D43 0x00000003 #define RXB1D44 0x00000004 #define RXB1D45 0x00000005 #define RXB1D46 0x00000006 #define RXB1D47 0x00000007 /////// RXB1D5 Bits ///////////////////////////////////////////////////// #define RXB1D50 0x00000000 #define RXB1D51 0x00000001 #define RXB1D52 0x00000002 #define RXB1D53 0x00000003 #define RXB1D54 0x00000004 #define RXB1D55 0x00000005 #define RXB1D56 0x00000006 #define RXB1D57 0x00000007 /////// RXB1D6 Bits ///////////////////////////////////////////////////// #define RXB1D60 0x00000000 #define RXB1D61 0x00000001 #define RXB1D62 0x00000002 #define RXB1D63 0x00000003 #define RXB1D64 0x00000004 #define RXB1D65 0x00000005 #define RXB1D66 0x00000006 #define RXB1D67 0x00000007 /////// RXB1D7 Bits ///////////////////////////////////////////////////// #define RXB1D70 0x00000000 #define RXB1D71 0x00000001 #define RXB1D72 0x00000002 #define RXB1D73 0x00000003 #define RXB1D74 0x00000004 #define RXB1D75 0x00000005 #define RXB1D76 0x00000006 #define RXB1D77 0x00000007 /////// CANSTAT_RO0 Bits ///////////////////////////////////////////////////// #define ICODE0 0x00000000 #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define ICODE4 0x00000004 #define OPMODE 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// CANCON_RO0 Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 /////// RXB0CON Bits ///////////////////////////////////////////////////// #define FILHIT0 0x00000000 #define JTOFF 0x00000001 #define RXB0DBEN 0x00000002 #define RXRTRRO_RXB0CON 0x00000003 #define RXM0 0x00000005 #define RXM1 0x00000006 #define RXFUL 0x00000007 #define FILHIT1 0x00000001 #define FILHIT2 0x00000002 #define FILHIT3 0x00000003 #define FILHIT4 0x00000004 #define RTRRO 0x00000005 #define RXBODBEN 0x00000002 /////// RXB0SIDH Bits ///////////////////////////////////////////////////// #define SID3 0x00000000 #define SID4 0x00000001 #define SID5 0x00000002 #define SID6 0x00000003 #define SID7 0x00000004 #define SID8 0x00000005 #define SID9 0x00000006 #define SID10 0x00000007 /////// RXB0SIDL Bits ///////////////////////////////////////////////////// #define EID16 0x00000000 #define EID17 0x00000001 #define EXID 0x00000003 #define SRR 0x00000004 #define SID0 0x00000005 #define SID1 0x00000006 #define SID2 0x00000007 /////// RXB0EIDH Bits ///////////////////////////////////////////////////// #define EID8 0x00000000 #define EID9 0x00000001 #define EID10 0x00000002 #define EID11 0x00000003 #define EID12 0x00000004 #define EID13 0x00000005 #define EID14 0x00000006 #define EID15 0x00000007 /////// RXB0EIDL Bits ///////////////////////////////////////////////////// #define EID0 0x00000000 #define EID1 0x00000001 #define EID2 0x00000002 #define EID3 0x00000003 #define EID4 0x00000004 #define EID5 0x00000005 #define EID6 0x00000006 #define EID7 0x00000007 /////// RXB0DLC Bits ///////////////////////////////////////////////////// #define DLC0 0x00000000 #define DLC1 0x00000001 #define DLC2 0x00000002 #define DLC3 0x00000003 #define RESRB0 0x00000004 #define RESRB1 0x00000005 #define RXRTR 0x00000006 #define RB0_RXB0DLC 0x00000004 #define RB1_RXB0DLC 0x00000005 /////// RXB0D0 Bits ///////////////////////////////////////////////////// #define RXB0D00 0x00000000 #define RXB0D01 0x00000001 #define RXB0D02 0x00000002 #define RXB0D03 0x00000003 #define RXB0D04 0x00000004 #define RXB0D05 0x00000005 #define RXB0D06 0x00000006 #define RXB0D07 0x00000007 /////// RXB0D1 Bits ///////////////////////////////////////////////////// #define RXB0D10 0x00000000 #define RXB0D11 0x00000001 #define RXB0D12 0x00000002 #define RXB0D13 0x00000003 #define RXB0D14 0x00000004 #define RXB0D15 0x00000005 #define RXB0D16 0x00000006 #define RXB0D17 0x00000007 /////// RXB0D2 Bits ///////////////////////////////////////////////////// #define RXB0D20 0x00000000 #define RXB0D21 0x00000001 #define RXB0D22 0x00000002 #define RXB0D23 0x00000003 #define RXB0D24 0x00000004 #define RXB0D25 0x00000005 #define RXB0D26 0x00000006 #define RXB0D27 0x00000007 /////// RXB0D3 Bits ///////////////////////////////////////////////////// #define RXB0D30 0x00000000 #define RXB0D31 0x00000001 #define RXB0D32 0x00000002 #define RXB0D33 0x00000003 #define RXB0D34 0x00000004 #define RXB0D35 0x00000005 #define RXB0D36 0x00000006 #define RXB0D37 0x00000007 /////// RXB0D4 Bits ///////////////////////////////////////////////////// #define RXB0D40 0x00000000 #define RXB0D41 0x00000001 #define RXB0D42 0x00000002 #define RXB0D43 0x00000003 #define RXB0D44 0x00000004 #define RXB0D45 0x00000005 #define RXB0D46 0x00000006 #define RXB0D47 0x00000007 /////// RXB0D5 Bits ///////////////////////////////////////////////////// #define RXB0D50 0x00000000 #define RXB0D51 0x00000001 #define RXB0D52 0x00000002 #define RXB0D53 0x00000003 #define RXB0D54 0x00000004 #define RXB0D55 0x00000005 #define RXB0D56 0x00000006 #define RXB0D57 0x00000007 /////// RXB0D6 Bits ///////////////////////////////////////////////////// #define RXB0D60 0x00000000 #define RXB0D61 0x00000001 #define RXB0D62 0x00000002 #define RXB0D63 0x00000003 #define RXB0D64 0x00000004 #define RXB0D65 0x00000005 #define RXB0D66 0x00000006 #define RXB0D67 0x00000007 /////// RXB0D7 Bits ///////////////////////////////////////////////////// #define RXB0D70 0x00000000 #define RXB0D71 0x00000001 #define RXB0D72 0x00000002 #define RXB0D73 0x00000003 #define RXB0D74 0x00000004 #define RXB0D75 0x00000005 #define RXB0D76 0x00000006 #define RXB0D77 0x00000007 /////// CANSTAT Bits ///////////////////////////////////////////////////// #define ICODE1 0x00000001 #define ICODE2 0x00000002 #define ICODE3 0x00000003 #define OPMODE0 0x00000005 #define OPMODE1 0x00000006 #define OPMODE2 0x00000007 #define EICODE0 0x00000000 #define EICODE1 0x00000001 #define EICODE2 0x00000002 #define EICODE3 0x00000003 #define EICODE4 0x00000004 /////// CANCON Bits ///////////////////////////////////////////////////// #define WIN0 0x00000001 #define WIN1 0x00000002 #define WIN2 0x00000003 #define ABAT 0x00000004 #define REQOP0 0x00000005 #define REQOP1 0x00000006 #define REQOP2 0x00000007 #define FP0 0x00000000 #define FP1 0x00000001 #define FP2 0x00000002 #define FP3 0x00000003 /////// BRGCON1 Bits ///////////////////////////////////////////////////// #define BRP0 0x00000000 #define BRP1 0x00000001 #define BRP2 0x00000002 #define BRP3 0x00000003 #define BRP4 0x00000004 #define BRP5 0x00000005 #define SJW0 0x00000006 #define SJW1 0x00000007 /////// BRGCON2 Bits ///////////////////////////////////////////////////// #define PRSEG0 0x00000000 #define PRSEG1 0x00000001 #define PRSEG2 0x00000002 #define SEG1PH0 0x00000003 #define SEG1PH1 0x00000004 #define SEG1PH2 0x00000005 #define SAM 0x00000006 #define SEG2PHTS 0x00000007 #define SEG2PHT 0x00000007 /////// BRGCON3 Bits ///////////////////////////////////////////////////// #define SEG2PH0 0x00000000 #define SEG2PH1 0x00000001 #define SEG2PH2 0x00000002 #define WAKFIL 0x00000006 #define WAKDIS 0x00000007 /////// CIOCON Bits ///////////////////////////////////////////////////// #define CANCAP 0x00000004 #define ENDRHI 0x00000005 /////// COMSTAT Bits ///////////////////////////////////////////////////// #define EWARN 0x00000000 #define RXWARN 0x00000001 #define TXWARN 0x00000002 #define RXBP 0x00000003 #define TXBP 0x00000004 #define TXBO 0x00000005 #define RXB1OVFL 0x00000006 #define RXB0OVFL 0x00000007 #define RXBnOVFL 0x00000006 #define FIFOEMPTY 0x00000007 /////// RXERRCNT Bits ///////////////////////////////////////////////////// #define REC0 0x00000000 #define REC1 0x00000001 #define REC2 0x00000002 #define REC3 0x00000003 #define REC4 0x00000004 #define REC5 0x00000005 #define REC6 0x00000006 #define REC7 0x00000007 /////// TXERRCNT Bits ///////////////////////////////////////////////////// #define TEC0 0x00000000 #define TEC1 0x00000001 #define TEC2 0x00000002 #define TEC3 0x00000003 #define TEC4 0x00000004 #define TEC5 0x00000005 #define TEC6 0x00000006 #define TEC7 0x00000007 /////// ECANCON Bits ///////////////////////////////////////////////////// #define EWIN0 0x00000000 #define EWIN1 0x00000001 #define EWIN2 0x00000002 #define EWIN3 0x00000003 #define EWIN4 0x00000004 #define FIFOWM 0x00000005 #define MDSEL0 0x00000006 #define MDSEL1 0x00000007 /////// PORTA Bits ///////////////////////////////////////////////////// #define RA0 0x00000000 #define RA1 0x00000001 #define RA2 0x00000002 #define RA3 0x00000003 #define RA4 0x00000004 #define RA5 0x00000005 #define RA6 0x00000006 #define RA7 0x00000007 #define AN0 0x00000000 #define AN1 0x00000001 #define AN2 0x00000002 #define AN3 0x00000003 #define T0CKI 0x00000004 #define AN4 0x00000005 #define OSC2 0x00000006 #define OSC1 0x00000007 #define CVREF 0x00000000 #define VREFM 0x00000002 #define VREFP 0x00000003 #define LVDIN 0x00000005 #define CLKO 0x00000006 #define CLKI 0x00000007 #define SS 0x00000005 #define NOT_SS 0x00000005 #define HLVDIN 0x00000005 /////// PORTB Bits ///////////////////////////////////////////////////// #define RB0_PORTB 0x00000000 #define RB1_PORTB 0x00000001 #define RB2 0x00000002 #define RB3 0x00000003 #define RB4 0x00000004 #define RB5 0x00000005 #define RB6 0x00000006 #define RB7 0x00000007 #define INT0 0x00000000 #define INT1 0x00000001 #define INT2 0x00000002 #define CANRX 0x00000003 #define KBI0 0x00000004 #define KBI1 0x00000005 #define KBI2 0x00000006 #define KBI3 0x00000007 #define AN10 0x00000000 #define FLT0 0x00000000 #define AN8 0x00000001 #define CANTX 0x00000002 #define AN9 0x00000004 #define PGM 0x00000005 #define PGC 0x00000006 #define PGD 0x00000007 /////// PORTC Bits ///////////////////////////////////////////////////// #define RC0 0x00000000 #define RC1 0x00000001 #define RC2 0x00000002 #define RC3 0x00000003 #define RC4 0x00000004 #define RC5 0x00000005 #define RC6 0x00000006 #define RC7 0x00000007 #define T1OSO 0x00000000 #define T1OSI 0x00000001 #define CCP1 0x00000002 #define SCK 0x00000003 #define SDI 0x00000004 #define SDO 0x00000005 #define TX 0x00000006 #define RX 0x00000007 #define T13CKI 0x00000000 #define SCL 0x00000003 #define SDA 0x00000004 #define CK 0x00000006 // DT is a reserved word /////// PORTE Bits ///////////////////////////////////////////////////// #define RE3 0x00000003 /////// LATA Bits ///////////////////////////////////////////////////// #define LATA0 0x00000000 #define LATA1 0x00000001 #define LATA2 0x00000002 #define LATA3 0x00000003 #define LATA4 0x00000004 #define LATA5 0x00000005 #define LATA6 0x00000006 #define LATA7 0x00000007 /////// LATB Bits ///////////////////////////////////////////////////// #define LATB0 0x00000000 #define LATB1 0x00000001 #define LATB2 0x00000002 #define LATB3 0x00000003 #define LATB4 0x00000004 #define LATB5 0x00000005 #define LATB6 0x00000006 #define LATB7 0x00000007 /////// LATC Bits ///////////////////////////////////////////////////// #define LATC0 0x00000000 #define LATC1 0x00000001 #define LATC2 0x00000002 #define LATC3 0x00000003 #define LATC4 0x00000004 #define LATC5 0x00000005 #define LATC6 0x00000006 #define LATC7 0x00000007 /////// DDRA Bits ///////////////////////////////////////////////////// #define RA0 0x00000000 #define RA1 0x00000001 #define RA2 0x00000002 #define RA3 0x00000003 #define RA4 0x00000004 #define RA5 0x00000005 #define RA6 0x00000006 /////// TRISA Bits ///////////////////////////////////////////////////// #define TRISA0 0x00000000 #define TRISA1 0x00000001 #define TRISA2 0x00000002 #define TRISA3 0x00000003 #define TRISA4 0x00000004 #define TRISA5 0x00000005 #define TRISA6 0x00000006 #define TRISA7 0x00000007 /////// DDRB Bits ///////////////////////////////////////////////////// #define RB0_DDRB 0x00000000 #define RB1_DDRB 0x00000001 #define RB2 0x00000002 #define RB3 0x00000003 #define RB4 0x00000004 #define RB5 0x00000005 #define RB6 0x00000006 #define RB7 0x00000007 /////// TRISB Bits ///////////////////////////////////////////////////// #define TRISB0 0x00000000 #define TRISB1 0x00000001 #define TRISB2 0x00000002 #define TRISB3 0x00000003 #define TRISB4 0x00000004 #define TRISB5 0x00000005 #define TRISB6 0x00000006 #define TRISB7 0x00000007 /////// DDRC Bits ///////////////////////////////////////////////////// #define RC0 0x00000000 #define RC1 0x00000001 #define RC2 0x00000002 #define RC3 0x00000003 #define RC4 0x00000004 #define RC5 0x00000005 #define RC6 0x00000006 #define RC7 0x00000007 /////// TRISC Bits ///////////////////////////////////////////////////// #define TRISC0 0x00000000 #define TRISC1 0x00000001 #define TRISC2 0x00000002 #define TRISC3 0x00000003 #define TRISC4 0x00000004 #define TRISC5 0x00000005 #define TRISC6 0x00000006 #define TRISC7 0x00000007 /////// OSCTUNE Bits ///////////////////////////////////////////////////// #define TUN0 0x00000000 #define TUN1 0x00000001 #define TUN2 0x00000002 #define TUN3 0x00000003 #define TUN4 0x00000004 #define PLLEN 0x00000006 #define INTSCR 0x00000007 #define INTSRC 0x00000007 /////// PIE1 Bits ///////////////////////////////////////////////////// #define TMR1IE 0x00000000 #define TMR2IE 0x00000001 #define CCP1IE 0x00000002 #define SSPIE 0x00000003 #define TXIE 0x00000004 #define RCIE 0x00000005 #define ADIE 0x00000006 /////// PIR1 Bits ///////////////////////////////////////////////////// #define TMR1IF 0x00000000 #define TMR2IF 0x00000001 #define CCP1IF 0x00000002 #define SSPIF 0x00000003 #define TXIF 0x00000004 #define RCIF 0x00000005 #define ADIF 0x00000006 /////// IPR1 Bits ///////////////////////////////////////////////////// #define TMR1IP 0x00000000 #define TMR2IP 0x00000001 #define CCP1IP 0x00000002 #define SSPIP 0x00000003 #define TXBIP 0x00000004 #define RCIP 0x00000005 #define ADIP 0x00000006 #define TXIP 0x00000004 /////// PIE2 Bits ///////////////////////////////////////////////////// #define TMR3IE 0x00000001 #define LVDIE 0x00000002 #define BCLIE 0x00000003 #define EEIE 0x00000004 #define OSCFIE 0x00000007 #define HLVDIE 0x00000002 /////// PIR2 Bits ///////////////////////////////////////////////////// #define TMR3IF 0x00000001 #define LVDIF 0x00000002 #define BCLIF 0x00000003 #define EEIF 0x00000004 #define OSCFIF 0x00000007 #define HLVDIF 0x00000002 /////// IPR2 Bits ///////////////////////////////////////////////////// #define TMR3IP 0x00000001 #define LVDIP 0x00000002 #define BCLIP 0x00000003 #define EEIP 0x00000004 #define OSCFIP 0x00000007 #define HLVDIP 0x00000002 /////// PIE3 Bits ///////////////////////////////////////////////////// #define RXB0IE 0x00000000 #define RXB1IE 0x00000001 #define TXB0IE 0x00000002 #define TXB1IE 0x00000003 #define TXB2IE 0x00000004 #define ERRIE 0x00000005 #define WAKIE 0x00000006 #define IRXIE 0x00000007 #define FIFOWMIE 0x00000000 #define RXBnIE 0x00000001 #define TXBnIE 0x00000004 #define FIFOMWIE 0x00000000 /////// PIR3 Bits ///////////////////////////////////////////////////// #define RXB0IF 0x00000000 #define RXB1IF 0x00000001 #define TXB0IF 0x00000002 #define TXB1IF 0x00000003 #define TXB2IF 0x00000004 #define ERRIF 0x00000005 #define WAKIF 0x00000006 #define IRXIF 0x00000007 #define FIFOWMIF 0x00000000 #define RXBnIF 0x00000001 #define TXBnIF 0x00000004 /////// IPR3 Bits ///////////////////////////////////////////////////// #define RXB0IP 0x00000000 #define RXB1IP 0x00000001 #define TXB0IP 0x00000002 #define TXB1IP 0x00000003 #define TXB2IP 0x00000004 #define ERRIP 0x00000005 #define WAKIP 0x00000006 #define IRXIP 0x00000007 #define FIFOWMIP 0x00000000 #define RXBnIP 0x00000001 #define TXBnIP 0x00000004 /////// EECON1 Bits ///////////////////////////////////////////////////// #define RD 0x00000000 #define WR 0x00000001 #define WREN 0x00000002 #define WRERR 0x00000003 #define FREE 0x00000004 #define CFGS 0x00000006 #define EEPGD 0x00000007 /////// RCSTA Bits ///////////////////////////////////////////////////// #define RX9D 0x00000000 #define OERR 0x00000001 #define FERR 0x00000002 #define ADEN 0x00000003 #define CREN 0x00000004 #define SREN 0x00000005 #define RX9 0x00000006 #define SPEN 0x00000007 #define ADDEN 0x00000003 /////// TXSTA Bits ///////////////////////////////////////////////////// #define TX9D 0x00000000 #define TRMT 0x00000001 #define BRGH 0x00000002 #define SENDB 0x00000003 #define SYNC 0x00000004 #define TXEN 0x00000005 #define TX9 0x00000006 #define CSRC 0x00000007 /////// T3CON Bits ///////////////////////////////////////////////////// #define TMR3ON 0x00000000 #define TMR3CS 0x00000001 #define T3SYNC 0x00000002 #define T3CCP1 0x00000003 #define T3CKPS0 0x00000004 #define T3CKPS1 0x00000005 #define T3CCP2 0x00000006 #define RD16 0x00000007 #define T3NSYNC 0x00000002 #define T3ECCP1 0x00000006 #define NOT_T3SYNC 0x00000002 /////// BAUDCON Bits ///////////////////////////////////////////////////// #define ABDEN 0x00000000 #define WUE 0x00000001 #define BRG16 0x00000003 #define SCKP 0x00000004 #define RCIDL 0x00000006 #define ABDOVF 0x00000007 /////// CCP1CON Bits ///////////////////////////////////////////////////// #define CCP1M0 0x00000000 #define CCP1M1 0x00000001 #define CCP1M2 0x00000002 #define CCP1M3 0x00000003 #define DC1B0 0x00000004 #define DC1B1 0x00000005 /////// ADCON2 Bits ///////////////////////////////////////////////////// #define ADCS0 0x00000000 #define ADCS1 0x00000001 #define ADCS2 0x00000002 #define ACQT0 0x00000003 #define ACQT1 0x00000004 #define ACQT2 0x00000005 #define ADFM 0x00000007 /////// ADCON1 Bits ///////////////////////////////////////////////////// #define PCFG0 0x00000000 #define PCFG1 0x00000001 #define PCFG2 0x00000002 #define PCFG3 0x00000003 #define VCFG0 0x00000004 #define VCFG1 0x00000005 /////// ADCON0 Bits ///////////////////////////////////////////////////// #define ADON 0x00000000 #define GO_DONE 0x00000001 #define CHS0 0x00000002 #define CHS1 0x00000003 #define CHS2 0x00000004 #define CHS3 0x00000005 #define DONE 0x00000001 #define GO 0x00000001 #define NOT_DONE 0x00000001 /////// SSPCON2 Bits ///////////////////////////////////////////////////// #define SEN 0x00000000 #define RSEN 0x00000001 #define PEN 0x00000002 #define RCEN 0x00000003 #define ACKEN 0x00000004 #define ACKDT 0x00000005 #define ACKSTAT 0x00000006 #define GCEN 0x00000007 /////// SSPCON1 Bits ///////////////////////////////////////////////////// #define SSPM0 0x00000000 #define SSPM1 0x00000001 #define SSPM2 0x00000002 #define SSPM3 0x00000003 #define CKP 0x00000004 #define SSPEN 0x00000005 #define SSPOV 0x00000006 #define WCOL 0x00000007 /////// SSPSTAT Bits ///////////////////////////////////////////////////// #define BF 0x00000000 #define UA 0x00000001 #define R_W 0x00000002 #define S 0x00000003 #define P 0x00000004 #define D_A 0x00000005 #define CKE 0x00000006 #define SMP 0x00000007 #define I2C_READ 0x00000002 #define I2C_START 0x00000003 #define I2C_STOP 0x00000004 #define I2C_DAT 0x00000005 #define NOT_W 0x00000002 #define NOT_A 0x00000005 #define NOT_WRITE 0x00000002 #define NOT_ADDRESS 0x00000005 #define READ_WRITE 0x00000002 #define DATA_ADDRESS 0x00000005 #define R 0x00000002 #define D 0x00000005 /////// T2CON Bits ///////////////////////////////////////////////////// #define T2CKPS0 0x00000000 #define T2CKPS1 0x00000001 #define TMR2ON 0x00000002 #define T2OUTPS0 0x00000003 #define T2OUTPS1 0x00000004 #define T2OUTPS2 0x00000005 #define T2OUTPS3 0x00000006 /////// T1CON Bits ///////////////////////////////////////////////////// #define TMR1ON 0x00000000 #define TMR1CS 0x00000001 #define T1SYNC 0x00000002 #define T1OSCEN 0x00000003 #define T1CKPS0 0x00000004 #define T1CKPS1 0x00000005 #define T1RUN 0x00000006 #define RD16 0x00000007 #define T1INSYNC 0x00000002 #define NOT_T1SYNC 0x00000002 /////// RCON Bits ///////////////////////////////////////////////////// #define NOT_BOR 0x00000000 #define NOT_POR 0x00000001 #define NOT_PD 0x00000002 #define NOT_TO 0x00000003 #define NOT_RI 0x00000004 #define SBOREN 0x00000006 #define IPEN 0x00000007 #define BOR 0x00000000 #define POR 0x00000001 #define PD 0x00000002 #define TO 0x00000003 #define RI 0x00000004 /////// WDTCON Bits ///////////////////////////////////////////////////// #define SWDTEN 0x00000000 #define SWDTE 0x00000000 /////// HLVDCON Bits ///////////////////////////////////////////////////// #define LVDL0 0x00000000 #define LVDL1 0x00000001 #define LVDL2 0x00000002 #define LVDL3 0x00000003 #define LVDEN 0x00000004 #define IRVST 0x00000005 #define LVV0 0x00000000 #define LVV1 0x00000001 #define LVV2 0x00000002 #define LVV3 0x00000003 #define BGST 0x00000005 #define HLVDL0 0x00000000 #define HLVDL1 0x00000001 #define HLVDL2 0x00000002 #define HLVDL3 0x00000003 #define HLVDEN 0x00000004 #define VDIRMAG 0x00000007 #define IVRST 0x00000005 /////// LVDCON Bits ///////////////////////////////////////////////////// #define LVDL0 0x00000000 #define LVDL1 0x00000001 #define LVDL2 0x00000002 #define LVDL3 0x00000003 #define LVDEN 0x00000004 #define IRVST 0x00000005 #define LVV0 0x00000000 #define LVV1 0x00000001 #define LVV2 0x00000002 #define LVV3 0x00000003 #define BGST 0x00000005 #define HLVDL0 0x00000000 #define HLVDL1 0x00000001 #define HLVDL2 0x00000002 #define HLVDL3 0x00000003 #define HLVDEN 0x00000004 #define VDIRMAG 0x00000007 #define IVRST 0x00000005 /////// OSCCON Bits ///////////////////////////////////////////////////// #define SCS0 0x00000000 #define SCS1 0x00000001 #define IOFS 0x00000002 #define OSTS 0x00000003 #define IRCF0 0x00000004 #define IRCF1 0x00000005 #define IRCF2 0x00000006 #define IDLEN 0x00000007 /////// T0CON Bits ///////////////////////////////////////////////////// #define T0PS0 0x00000000 #define T0PS1 0x00000001 #define T0PS2 0x00000002 #define PSA 0x00000003 #define T0SE 0x00000004 #define T0CS 0x00000005 #define T08BIT 0x00000006 #define TMR0ON 0x00000007 #define T0PS3 0x00000003 /////// STATUS Bits ///////////////////////////////////////////////////// #define C 0x00000000 #define DC 0x00000001 #define Z 0x00000002 #define OV 0x00000003 #define N 0x00000004 /////// INTCON3 Bits ///////////////////////////////////////////////////// #define INT1IF 0x00000000 #define INT2IF 0x00000001 #define INT1IE 0x00000003 #define INT2IE 0x00000004 #define INT1IP 0x00000006 #define INT2IP 0x00000007 #define INT1F 0x00000000 #define INT2F 0x00000001 #define INT1E 0x00000003 #define INT2E 0x00000004 #define INT1P 0x00000006 #define INT2P 0x00000007 /////// INTCON2 Bits ///////////////////////////////////////////////////// #define RBIP 0x00000000 #define TMR0IP 0x00000002 #define INTEDG2 0x00000004 #define INTEDG1 0x00000005 #define INTEDG0 0x00000006 #define NOT_RBPU 0x00000007 #define T0IP 0x00000002 #define RBPU 0x00000007 /////// INTCON Bits ///////////////////////////////////////////////////// #define RBIF 0x00000000 #define INT0IF 0x00000001 #define TMR0IF 0x00000002 #define RBIE 0x00000003 #define INT0IE 0x00000004 #define TMR0IE 0x00000005 #define PEIE 0x00000006 #define GIE 0x00000007 #define INT0F 0x00000001 #define T0IF 0x00000002 #define INT0E 0x00000004 #define T0IE 0x00000005 #define GIEL 0x00000006 #define GIEH 0x00000007 /////// STKPTR Bits ///////////////////////////////////////////////////// #define STKPTR0 0x00000000 #define STKPTR1 0x00000001 #define STKPTR2 0x00000002 #define STKPTR3 0x00000003 #define STKPTR4 0x00000004 #define STKUNF 0x00000006 #define STKOVF 0x00000007 #define SP0 0x00000000 #define SP1 0x00000001 #define SP2 0x00000002 #define SP3 0x00000003 #define SP4 0x00000004 #define STKFUL 0x00000007 //////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// // // Configuration Bits // // NAME Address // CONFIG1H 300001h // CONFIG2L 300002h // CONFIG2H 300003h // CONFIG3H 300005h // CONFIG4L 300006h // CONFIG5L 300008h // CONFIG5H 300009h // CONFIG6L 30000Ah // CONFIG6H 30000Bh // CONFIG7L 30000Ch // CONFIG7H 30000Dh // //////////////////////////////////////////////////////////////////////////// // The following is an assignment of address values for all of the // configuration registers for the purpose of table reads #define _CONFIG1H 0x00300001 #define _CONFIG2L 0x00300002 #define _CONFIG2H 0x00300003 #define _CONFIG3H 0x00300005 #define _CONFIG4L 0x00300006 #define _CONFIG5L 0x00300008 #define _CONFIG5H 0x00300009 #define _CONFIG6L 0x0030000A #define _CONFIG6H 0x0030000B #define _CONFIG7L 0x0030000C #define _CONFIG7H 0x0030000D /////// CONFIG1H Options ////////////////////////////////////////////////// #define _OSC_LP_1H 0x000000F0 // LP oscillator #define _OSC_XT_1H 0x000000F1 // XT oscillator #define _OSC_HS_1H 0x000000F2 // HS oscillator #define _OSC_RC_1H 0x000000F3 // External RC oscillator, CLKO function on RA6 #define _OSC_EC_1H 0x000000F4 // EC oscillator, CLKO function on RA6 #define _OSC_ECIO_1H 0x000000F5 // EC oscillator, port function on RA6 #define _OSC_HSPLL_1H 0x000000F6 // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) #define _OSC_RCIO_1H 0x000000F7 // External RC oscillator, port function on RA6 #define _OSC_IRCIO67_1H 0x000000F8 // Internal oscillator block, port function on RA6 and RA7 #define _OSC_IRCIO7_1H 0x000000F9 // Internal oscillator block, CLKO function on RA6, port function on RA7 #define _FCMEN_OFF_1H 0x000000BF // Fail-Safe Clock Monitor disabled #define _FCMEN_ON_1H 0x000000FF // Fail-Safe Clock Monitor enabled #define _IESO_OFF_1H 0x0000007F // Oscillator Switchover mode disabled #define _IESO_ON_1H 0x000000FF // Oscillator Switchover mode enabled /////// CONFIG2L Options ////////////////////////////////////////////////// #define _PWRT_ON_2L 0x000000FE // PWRT enabled #define _PWRT_OFF_2L 0x000000FF // PWRT disabled #define _BOREN_OFF_2L 0x000000F9 // Brown-out Reset disabled in hardware and software #define _BOREN_SBORENCTRL_2L 0x000000FB // Brown-out Reset enabled and controlled by software (SBOREN is enabled) #define _BOREN_BOACTIVE_2L 0x000000FD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) #define _BOREN_BOHW_2L 0x000000FF // Brown-out Reset enabled in hardware only (SBOREN is disabled) #define _BORV_0_2L 0x000000E7 // Maximum setting #define _BORV_1_2L 0x000000EF // #define _BORV_2_2L 0x000000F7 // #define _BORV_3_2L 0x000000FF // Minimum setting /////// CONFIG2H Options ////////////////////////////////////////////////// #define _WDT_OFF_2H 0x000000FE // WDT disabled (control is placed on the SWDTEN bit) #define _WDT_ON_2H 0x000000FF // WDT enabled #define _WDTPS_1_2H 0x000000E1 // 1:1 #define _WDTPS_2_2H 0x000000E3 // 1:2 #define _WDTPS_4_2H 0x000000E5 // 1:4 #define _WDTPS_8_2H 0x000000E7 // 1:8 #define _WDTPS_16_2H 0x000000E9 // 1:16 #define _WDTPS_32_2H 0x000000EB // 1:32 #define _WDTPS_64_2H 0x000000ED // 1:64 #define _WDTPS_128_2H 0x000000EF // 1:128 #define _WDTPS_256_2H 0x000000F1 // 1:256 #define _WDTPS_512_2H 0x000000F3 // 1:512 #define _WDTPS_1024_2H 0x000000F5 // 1:1024 #define _WDTPS_2048_2H 0x000000F7 // 1:2048 #define _WDTPS_4096_2H 0x000000F9 // 1:4096 #define _WDTPS_8192_2H 0x000000FB // 1:8192 #define _WDTPS_16384_2H 0x000000FD // 1:16384 #define _WDTPS_32768_2H 0x000000FF // 1:32768 /////// CONFIG3H Options ////////////////////////////////////////////////// #define _MCLRE_OFF_3H 0x0000007F // RE3 input pin enabled// MCLR disabled #define _MCLRE_ON_3H 0x000000FF // MCLR pin enabled// RE3 input pin disabled #define _LPT1OSC_OFF_3H 0x000000FB // Timer1 configured for higher power operation #define _LPT1OSC_ON_3H 0x000000FF // Timer1 configured for low-power operation #define _PBADEN_OFF_3H 0x000000FD // PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset #define _PBADEN_ON_3H 0x000000FF // PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset /////// CONFIG4L Options ////////////////////////////////////////////////// #define _DEBUG_ON_4L 0x0000007F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug #define _DEBUG_OFF_4L 0x000000FF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins #define _XINST_OFF_4L 0x000000BF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode) #define _XINST_ON_4L 0x000000FF // Instruction set extension and Indexed Addressing mode enabled #define _BBSIZ_1024_4L 0x000000CF // 1K words (2K bytes) Boot Block #define _BBSIZ_2048_4L 0x000000DF // 2K words (4K bytes) Boot Block #define _BBSIZ_4096_4L 0x000000EF // 4K words (8K bytes) Boot Block #define _LVP_OFF_4L 0x000000FB // Disabled #define _LVP_ON_4L 0x000000FF // Enabled #define _STVREN_OFF_4L 0x000000FE // Stack full/underflow will not cause Reset #define _STVREN_ON_4L 0x000000FF // Stack full/underflow will cause Reset /////// CONFIG5L Options ////////////////////////////////////////////////// #define _CP0_ON_5L 0x000000FE // Block 0 (000800-003FFFh) code-protected #define _CP0_OFF_5L 0x000000FF // Block 0 (000800-003FFFh) not code-protected #define _CP1_ON_5L 0x000000FD // Block 1 (004000-007FFFh) code-protected #define _CP1_OFF_5L 0x000000FF // Block 1 (004000-007FFFh) not code-protected #define _CP2_ON_5L 0x000000FB // Block 2 (008000-00BFFFh) code-protected #define _CP2_OFF_5L 0x000000FF // Block 2 (008000-00BFFFh) not code-protected #define _CP3_ON_5L 0x000000F7 // Block 3 (00C000-00FFFFh) code-protected #define _CP3_OFF_5L 0x000000FF // Block 3 (00C000-00FFFFh) not code-protected #define _CP4_ON_5L 0x000000EF // Block 4 (010000-013FFFh) code-protected #define _CP4_OFF_5L 0x000000FF // Block 4 (010000-013FFFh) not code-protected #define _CP5_ON_5L 0x000000DF // Block 5 (014000-017FFFh) code-protected #define _CP5_OFF_5L 0x000000FF // Block 5 (014000-017FFFh) not code-protected /////// CONFIG5H Options ////////////////////////////////////////////////// #define _CPB_ON_5H 0x000000BF // Boot Block (000000-0007FFh) code-protected #define _CPB_OFF_5H 0x000000FF // Boot Block (000000-0007FFh) not code-protected #define _CPD_ON_5H 0x0000007F // Data EEPROM code-protected #define _CPD_OFF_5H 0x000000FF // Data EEPROM not code-protected /////// CONFIG6L Options ////////////////////////////////////////////////// #define _WRT0_ON_6L 0x000000FE // Block 0 (000800-003FFFh) write-protected #define _WRT0_OFF_6L 0x000000FF // Block 0 (000800-003FFFh) not write-protected #define _WRT1_ON_6L 0x000000FD // Block 1 (004000-007FFFh) write-protected #define _WRT1_OFF_6L 0x000000FF // Block 1 (004000-007FFFh) not write-protected #define _WRT2_ON_6L 0x000000FB // Block 2 (008000-00BFFFh) write-protected #define _WRT2_OFF_6L 0x000000FF // Block 2 (008000-00BFFFh) not write-protected #define _WRT3_ON_6L 0x000000F7 // Block 3 (00C000-00FFFFh) write-protected #define _WRT3_OFF_6L 0x000000FF // Block 3 (00C000-00FFFFh) not write-protected #define _WRT4_ON_6L 0x000000EF // Block 4 (010000-013FFFh) write-protected #define _WRT4_OFF_6L 0x000000FF // Block 4 (010000-013FFFh) not write-protected #define _WRT5_ON_6L 0x000000DF // Block 5 (014000-017FFFh) write-protected #define _WRT5_OFF_6L 0x000000FF // Block 5 (014000-017FFFh) not write-protected /////// CONFIG6H Options ////////////////////////////////////////////////// #define _WRTB_ON_6H 0x000000BF // Boot Block (000000-0007FFh) write-protected #define _WRTB_OFF_6H 0x000000FF // Boot Block (000000-0007FFh) not write-protected #define _WRTC_ON_6H 0x000000DF // Configuration registers (300000-3000FFh) write-protected #define _WRTC_OFF_6H 0x000000FF // Configuration registers (300000-3000FFh) not write-protected #define _WRTD_ON_6H 0x0000007F // Data EEPROM write-protected #define _WRTD_OFF_6H 0x000000FF // Data EEPROM not write-protected /////// CONFIG7L Options ////////////////////////////////////////////////// #define _EBTR0_ON_7L 0x000000FE // Block 0 (000800-003FFFh) protected from table reads executed in other blocks #define _EBTR0_OFF_7L 0x000000FF // Block 0 (000800-003FFFh) not protected from table reads executed in other blocks #define _EBTR1_ON_7L 0x000000FD // Block 1 (004000-007FFFh) protected from table reads executed in other blocks #define _EBTR1_OFF_7L 0x000000FF // Block 1 (004000-007FFFh) not protected from table reads executed in other blocks #define _EBTR2_ON_7L 0x000000FB // Block 2 (008000-00BFFFh) protected from table reads executed in other blocks #define _EBTR2_OFF_7L 0x000000FF // Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks #define _EBTR3_ON_7L 0x000000F7 // Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks #define _EBTR3_OFF_7L 0x000000FF // Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks #define _EBTR4_ON_7L 0x000000EF // Block 4 (010000-013FFFh) protected from table reads executed in other blocks #define _EBTR4_OFF_7L 0x000000FF // Block 4 (010000-013FFFh) not protected from table reads executed in other blocks #define _EBTR5_ON_7L 0x000000DF // Block 5 (014000-017FFFh) protected from table reads executed in other blocks #define _EBTR5_OFF_7L 0x000000FF // Block 5 (014000-017FFFh) not protected from table reads executed in other blocks /////// CONFIG7H Options ////////////////////////////////////////////////// #define _EBTRB_ON_7H 0x000000BF // Boot Block (000000-0007FFh) protected from table reads executed in other blocks #define _EBTRB_OFF_7H 0x000000FF // Boot Block (000000-0007FFh) not protected from table reads executed in other blocks #define _DEVID1 0x003FFFFE #define _DEVID2 0x003FFFFF #define _IDLOC0 0x00200000 #define _IDLOC1 0x00200001 #define _IDLOC2 0x00200002 #define _IDLOC3 0x00200003 #define _IDLOC4 0x00200004 #define _IDLOC5 0x00200005 #define _IDLOC6 0x00200006 #define _IDLOC7 0x00200007 ///////////////////////////////////////////////// // EEPROM Base Address when programing ///////////////////////////////////////////////// // To initialise EEPROM when a device is programmed // use #pragma DATA _EEPROM, 12, 34, 56 #define _EEPROM 0xF00000 //////////////////////////////////////////////// // registers define with @ for direct access //////////////////////////////////////////////// volatile char rxf6sidh @RXF6SIDH; volatile char rxf6sidl @RXF6SIDL; volatile char rxf6eidh @RXF6EIDH; volatile char rxf6eidl @RXF6EIDL; volatile char rxf7sidh @RXF7SIDH; volatile char rxf7sidl @RXF7SIDL; volatile char rxf7eidh @RXF7EIDH; volatile char rxf7eidl @RXF7EIDL; volatile char rxf8sidh @RXF8SIDH; volatile char rxf8sidl @RXF8SIDL; volatile char rxf8eidh @RXF8EIDH; volatile char rxf8eidl @RXF8EIDL; volatile char rxf9sidh @RXF9SIDH; volatile char rxf9sidl @RXF9SIDL; volatile char rxf9eidh @RXF9EIDH; volatile char rxf9eidl @RXF9EIDL; volatile char rxf10sidh @RXF10SIDH; volatile char rxf10sidl @RXF10SIDL; volatile char rxf10eidh @RXF10EIDH; volatile char rxf10eidl @RXF10EIDL; volatile char rxf11sidh @RXF11SIDH; volatile char rxf11sidl @RXF11SIDL; volatile char rxf11eidh @RXF11EIDH; volatile char rxf11eidl @RXF11EIDL; volatile char rxf12sidh @RXF12SIDH; volatile char rxf12sidl @RXF12SIDL; volatile char rxf12eidh @RXF12EIDH; volatile char rxf12eidl @RXF12EIDL; volatile char rxf13sidh @RXF13SIDH; volatile char rxf13sidl @RXF13SIDL; volatile char rxf13eidh @RXF13EIDH; volatile char rxf13eidl @RXF13EIDL; volatile char rxf14sidh @RXF14SIDH; volatile char rxf14sidl @RXF14SIDL; volatile char rxf14eidh @RXF14EIDH; volatile char rxf14eidl @RXF14EIDL; volatile char rxf15sidh @RXF15SIDH; volatile char rxf15sidl @RXF15SIDL; volatile char rxf15eidh @RXF15EIDH; volatile char rxf15eidl @RXF15EIDL; volatile char rxfcon0 @RXFCON0; volatile char rxfcon1 @RXFCON1; volatile char sdflc @SDFLC; volatile char rxfbcon0 @RXFBCON0; volatile char rxfbcon1 @RXFBCON1; volatile char rxfbcon2 @RXFBCON2; volatile char rxfbcon3 @RXFBCON3; volatile char rxfbcon4 @RXFBCON4; volatile char rxfbcon5 @RXFBCON5; volatile char rxfbcon6 @RXFBCON6; volatile char rxfbcon7 @RXFBCON7; volatile char msel0 @MSEL0; volatile char msel1 @MSEL1; volatile char msel2 @MSEL2; volatile char msel3 @MSEL3; volatile char bsel0 @BSEL0; volatile char bie0 @BIE0; volatile char txbie @TXBIE; volatile char b0con @B0CON; volatile char b0sidh @B0SIDH; volatile char b0sidl @B0SIDL; volatile char b0eidh @B0EIDH; volatile char b0eidl @B0EIDL; volatile char b0dlc @B0DLC; volatile char b0d0 @B0D0; volatile char b0d1 @B0D1; volatile char b0d2 @B0D2; volatile char b0d3 @B0D3; volatile char b0d4 @B0D4; volatile char b0d5 @B0D5; volatile char b0d6 @B0D6; volatile char b0d7 @B0D7; volatile char canstat_ro9 @CANSTAT_RO9; volatile char cancon_ro9 @CANCON_RO9; volatile char b1con @B1CON; volatile char b1sidh @B1SIDH; volatile char b1sidl @B1SIDL; volatile char b1eidh @B1EIDH; volatile char b1eidl @B1EIDL; volatile char b1dlc @B1DLC; volatile char b1d0 @B1D0; volatile char b1d1 @B1D1; volatile char b1d2 @B1D2; volatile char b1d3 @B1D3; volatile char b1d4 @B1D4; volatile char b1d5 @B1D5; volatile char b1d6 @B1D6; volatile char b1d7 @B1D7; volatile char canstat_ro8 @CANSTAT_RO8; volatile char cancon_ro8 @CANCON_RO8; volatile char b2con @B2CON; volatile char b2sidh @B2SIDH; volatile char b2sidl @B2SIDL; volatile char b2eidh @B2EIDH; volatile char b2eidl @B2EIDL; volatile char b2dlc @B2DLC; volatile char b2d0 @B2D0; volatile char b2d1 @B2D1; volatile char b2d2 @B2D2; volatile char b2d3 @B2D3; volatile char b2d4 @B2D4; volatile char b2d5 @B2D5; volatile char b2d6 @B2D6; volatile char b2d7 @B2D7; volatile char canstat_ro7 @CANSTAT_RO7; volatile char cancon_ro7 @CANCON_RO7; volatile char b3con @B3CON; volatile char b3sidh @B3SIDH; volatile char b3sidl @B3SIDL; volatile char b3eidh @B3EIDH; volatile char b3eidl @B3EIDL; volatile char b3dlc @B3DLC; volatile char b3d0 @B3D0; volatile char b3d1 @B3D1; volatile char b3d2 @B3D2; volatile char b3d3 @B3D3; volatile char b3d4 @B3D4; volatile char b3d5 @B3D5; volatile char b3d6 @B3D6; volatile char b3d7 @B3D7; volatile char canstat_ro6 @CANSTAT_RO6; volatile char cancon_ro6 @CANCON_RO6; volatile char b4con @B4CON; volatile char b4sidh @B4SIDH; volatile char b4sidl @B4SIDL; volatile char b4eidh @B4EIDH; volatile char b4eidl @B4EIDL; volatile char b4dlc @B4DLC; volatile char b4d0 @B4D0; volatile char b4d1 @B4D1; volatile char b4d2 @B4D2; volatile char b4d3 @B4D3; volatile char b4d4 @B4D4; volatile char b4d5 @B4D5; volatile char b4d6 @B4D6; volatile char b4d7 @B4D7; volatile char canstat_ro5 @CANSTAT_RO5; volatile char cancon_ro5 @CANCON_RO5; volatile char b5con @B5CON; volatile char b5sidh @B5SIDH; volatile char b5sidl @B5SIDL; volatile char b5eidh @B5EIDH; volatile char b5eidl @B5EIDL; volatile char b5dlc @B5DLC; volatile char b5d0 @B5D0; volatile char b5d1 @B5D1; volatile char b5d2 @B5D2; volatile char b5d3 @B5D3; volatile char b5d4 @B5D4; volatile char b5d5 @B5D5; volatile char b5d6 @B5D6; volatile char b5d7 @B5D7; volatile char canstat_ro4 @CANSTAT_RO4; volatile char cancon_ro4 @CANCON_RO4; volatile char rxf0sidh @RXF0SIDH; volatile char rxf0sidl @RXF0SIDL; volatile char rxf0eidh @RXF0EIDH; volatile char rxf0eidl @RXF0EIDL; volatile char rxf1sidh @RXF1SIDH; volatile char rxf1sidl @RXF1SIDL; volatile char rxf1eidh @RXF1EIDH; volatile char rxf1eidl @RXF1EIDL; volatile char rxf2sidh @RXF2SIDH; volatile char rxf2sidl @RXF2SIDL; volatile char rxf2eidh @RXF2EIDH; volatile char rxf2eidl @RXF2EIDL; volatile char rxf3sidh @RXF3SIDH; volatile char rxf3sidl @RXF3SIDL; volatile char rxf3eidh @RXF3EIDH; volatile char rxf3eidl @RXF3EIDL; volatile char rxf4sidh @RXF4SIDH; volatile char rxf4sidl @RXF4SIDL; volatile char rxf4eidh @RXF4EIDH; volatile char rxf4eidl @RXF4EIDL; volatile char rxf5sidh @RXF5SIDH; volatile char rxf5sidl @RXF5SIDL; volatile char rxf5eidh @RXF5EIDH; volatile char rxf5eidl @RXF5EIDL; volatile char rxm0sidh @RXM0SIDH; volatile char rxm0sidl @RXM0SIDL; volatile char rxm0eidh @RXM0EIDH; volatile char rxm0eidl @RXM0EIDL; volatile char rxm1sidh @RXM1SIDH; volatile char rxm1sidl @RXM1SIDL; volatile char rxm1eidh @RXM1EIDH; volatile char rxm1eidl @RXM1EIDL; volatile char txb2con @TXB2CON; volatile char txb2sidh @TXB2SIDH; volatile char txb2sidl @TXB2SIDL; volatile char txb2eidh @TXB2EIDH; volatile char txb2eidl @TXB2EIDL; volatile char txb2dlc @TXB2DLC; volatile char txb2d0 @TXB2D0; volatile char txb2d1 @TXB2D1; volatile char txb2d2 @TXB2D2; volatile char txb2d3 @TXB2D3; volatile char txb2d4 @TXB2D4; volatile char txb2d5 @TXB2D5; volatile char txb2d6 @TXB2D6; volatile char txb2d7 @TXB2D7; volatile char canstat_ro3 @CANSTAT_RO3; volatile char cancon_ro3 @CANCON_RO3; volatile char txb1con @TXB1CON; volatile char txb1sidh @TXB1SIDH; volatile char txb1sidl @TXB1SIDL; volatile char txb1eidh @TXB1EIDH; volatile char txb1eidl @TXB1EIDL; volatile char txb1dlc @TXB1DLC; volatile char txb1d0 @TXB1D0; volatile char txb1d1 @TXB1D1; volatile char txb1d2 @TXB1D2; volatile char txb1d3 @TXB1D3; volatile char txb1d4 @TXB1D4; volatile char txb1d5 @TXB1D5; volatile char txb1d6 @TXB1D6; volatile char txb1d7 @TXB1D7; volatile char canstat_ro2 @CANSTAT_RO2; volatile char cancon_ro2 @CANCON_RO2; volatile char txb0con @TXB0CON; volatile char txb0sidh @TXB0SIDH; volatile char txb0sidl @TXB0SIDL; volatile char txb0eidh @TXB0EIDH; volatile char txb0eidl @TXB0EIDL; volatile char txb0dlc @TXB0DLC; volatile char txb0d0 @TXB0D0; volatile char txb0d1 @TXB0D1; volatile char txb0d2 @TXB0D2; volatile char txb0d3 @TXB0D3; volatile char txb0d4 @TXB0D4; volatile char txb0d5 @TXB0D5; volatile char txb0d6 @TXB0D6; volatile char txb0d7 @TXB0D7; volatile char canstat_ro1 @CANSTAT_RO1; volatile char cancon_ro1 @CANCON_RO1; volatile char rxb1con @RXB1CON; volatile char rxb1sidh @RXB1SIDH; volatile char rxb1sidl @RXB1SIDL; volatile char rxb1eidh @RXB1EIDH; volatile char rxb1eidl @RXB1EIDL; volatile char rxb1dlc @RXB1DLC; volatile char rxb1d0 @RXB1D0; volatile char rxb1d1 @RXB1D1; volatile char rxb1d2 @RXB1D2; volatile char rxb1d3 @RXB1D3; volatile char rxb1d4 @RXB1D4; volatile char rxb1d5 @RXB1D5; volatile char rxb1d6 @RXB1D6; volatile char rxb1d7 @RXB1D7; volatile char canstat_ro0 @CANSTAT_RO0; volatile char cancon_ro0 @CANCON_RO0; volatile char rxb0con @RXB0CON; volatile char rxb0sidh @RXB0SIDH; volatile char rxb0sidl @RXB0SIDL; volatile char rxb0eidh @RXB0EIDH; volatile char rxb0eidl @RXB0EIDL; volatile char rxb0dlc @RXB0DLC; volatile char rxb0d0 @RXB0D0; volatile char rxb0d1 @RXB0D1; volatile char rxb0d2 @RXB0D2; volatile char rxb0d3 @RXB0D3; volatile char rxb0d4 @RXB0D4; volatile char rxb0d5 @RXB0D5; volatile char rxb0d6 @RXB0D6; volatile char rxb0d7 @RXB0D7; volatile char canstat @CANSTAT; volatile char cancon @CANCON; volatile char brgcon1 @BRGCON1; volatile char brgcon2 @BRGCON2; volatile char brgcon3 @BRGCON3; volatile char ciocon @CIOCON; volatile char comstat @COMSTAT; volatile char rxerrcnt @RXERRCNT; volatile char txerrcnt @TXERRCNT; volatile char ecancon @ECANCON; volatile char porta @PORTA; volatile char portb @PORTB; volatile char portc @PORTC; //volatile char porte @PORTE; volatile char lata @LATA; volatile char latb @LATB; volatile char latc @LATC; volatile char ddra @DDRA; volatile char trisa @TRISA; volatile char ddrb @DDRB; volatile char trisb @TRISB; volatile char ddrc @DDRC; volatile char trisc @TRISC; volatile char osctune @OSCTUNE; volatile char pie1 @PIE1; volatile char pir1 @PIR1; volatile char ipr1 @IPR1; volatile char pie2 @PIE2; volatile char pir2 @PIR2; volatile char ipr2 @IPR2; volatile char pie3 @PIE3; volatile char pir3 @PIR3; volatile char ipr3 @IPR3; volatile char eecon1 @EECON1; volatile char eecon2 @EECON2; volatile char eedata @EEDATA; volatile char eeadr @EEADR; volatile char eeadrh @EEADRH; volatile char rcsta @RCSTA; volatile char txsta @TXSTA; volatile char txreg @TXREG; volatile char rcreg @RCREG; volatile char spbrg @SPBRG; volatile char spbrgh @SPBRGH; volatile char t3con @T3CON; volatile char tmr3l @TMR3L; volatile char tmr3h @TMR3H; volatile char baudcon @BAUDCON; volatile char ccp1con @CCP1CON; volatile char ccpr1 @CCPR1; volatile char ccpr1l @CCPR1L; volatile char ccpr1h @CCPR1H; volatile char adcon2 @ADCON2; volatile char adcon1 @ADCON1; volatile char adcon0 @ADCON0; volatile char adres @ADRES; volatile char adresl @ADRESL; volatile char adresh @ADRESH; volatile char sspcon2 @SSPCON2; volatile char sspcon1 @SSPCON1; volatile char sspstat @SSPSTAT; volatile char sspadd @SSPADD; volatile char sspbuf @SSPBUF; volatile char t2con @T2CON; volatile char pr2 @PR2; volatile char tmr2 @TMR2; volatile char t1con @T1CON; volatile char tmr1l @TMR1L; volatile char tmr1h @TMR1H; volatile char rcon @RCON; volatile char wdtcon @WDTCON; volatile char hlvdcon @HLVDCON; volatile char lvdcon @LVDCON; volatile char osccon @OSCCON; volatile char t0con @T0CON; volatile char tmr0l @TMR0L; volatile char tmr0h @TMR0H; volatile char status @STATUS; volatile char fsr2l @FSR2L; volatile char fsr2h @FSR2H; volatile char plusw2 @PLUSW2; volatile char preinc2 @PREINC2; volatile char postdec2 @POSTDEC2; volatile char postinc2 @POSTINC2; volatile char indf2 @INDF2; volatile char bsr @BSR; volatile char fsr1l @FSR1L; volatile char fsr1h @FSR1H; volatile char plusw1 @PLUSW1; volatile char preinc1 @PREINC1; volatile char postdec1 @POSTDEC1; volatile char postinc1 @POSTINC1; volatile char indf1 @INDF1; volatile char wreg @WREG; volatile char fsr0l @FSR0L; volatile char fsr0h @FSR0H; volatile char plusw0 @PLUSW0; volatile char preinc0 @PREINC0; volatile char postdec0 @POSTDEC0; volatile char postinc0 @POSTINC0; volatile char indf0 @INDF0; volatile char intcon3 @INTCON3; volatile char intcon2 @INTCON2; volatile char intcon @INTCON; volatile char prod @PROD; volatile char prodl @PRODL; volatile char prodh @PRODH; volatile char tablat @TABLAT; volatile char tblptr @TBLPTR; volatile char tblptrl @TBLPTRL; volatile char tblptrh @TBLPTRH; volatile char tblptru @TBLPTRU; volatile char pc @PC; volatile char pcl @PCL; volatile char pclath @PCLATH; volatile char pclatu @PCLATU; volatile char stkptr @STKPTR; volatile char tos @TOS; volatile char tosl @TOSL; volatile char tosh @TOSH; volatile char tosu @TOSU; #endif // _PIC18F2685_H_ ////////////////////////////////////////////////////////////////// // Target Configuration Options for: PIC18F2685 ////////////////////////////////////////////////////////////////// #define _TARGET_CONFIG_OPTIONS_TYPE_2 ////////////////////////////////////////////////////////////////// // Oscillator Selection bits: // #pragma config OSC = LP // LP oscillator // #pragma config OSC = XT // XT oscillator // #pragma config OSC = HS // HS oscillator // #pragma config OSC = RC // External RC oscillator, CLKO function on RA6 // #pragma config OSC = EC // EC oscillator, CLKO function on RA6 // #pragma config OSC = ECIO // EC oscillator, port function on RA6 // #pragma config OSC = HSPLL // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) // #pragma config OSC = RCIO // External RC oscillator, port function on RA6 // #pragma config OSC = IRCIO67 // Internal oscillator block, port function on RA6 and RA7 // #pragma config OSC = IRCIO7 // Internal oscillator block, CLKO function on RA6, port function on RA7 ////////////////////////////////////////////////////////////////// // Fail-Safe Clock Monitor Enable bit: // #pragma config FCMEN = OFF // Fail-Safe Clock Monitor disabled // #pragma config FCMEN = ON // Fail-Safe Clock Monitor enabled ////////////////////////////////////////////////////////////////// // Internal/External Oscillator Switchover bit: // #pragma config IESO = OFF // Oscillator Switchover mode disabled // #pragma config IESO = ON // Oscillator Switchover mode enabled ////////////////////////////////////////////////////////////////// // Power-up Timer Enable bit: // #pragma config PWRT = ON // PWRT enabled // #pragma config PWRT = OFF // PWRT disabled ////////////////////////////////////////////////////////////////// // Brown-out Reset Enable bits: // #pragma config BOREN = OFF // Brown-out Reset disabled in hardware and software // #pragma config BOREN = SBORENCTRL // Brown-out Reset enabled and controlled by software (SBOREN is enabled) // #pragma config BOREN = BOACTIVE // Brown-out Reset enabled in hardware only and disabledin Sleep mode (SBOREN is disabled) // #pragma config BOREN = BOHW // Brown-out Reset enabled in hardware only (SBOREN is disabled) ////////////////////////////////////////////////////////////////// // Brown-out Reset Voltage bits: // #pragma config BORV = 0 // Maximum setting // #pragma config BORV = 1 //   // #pragma config BORV = 2 //   // #pragma config BORV = 3 // Minimum setting ////////////////////////////////////////////////////////////////// // Watchdog Timer Enable bit: // #pragma config WDT = OFF // WDT disabled (control is placed on the SWDTEN bit) // #pragma config WDT = ON // WDT enabled ////////////////////////////////////////////////////////////////// // Watchdog Timer Postscale Select bits: // #pragma config WDTPS = 1 // 1:1 // #pragma config WDTPS = 2 // 1:2 // #pragma config WDTPS = 4 // 1:4 // #pragma config WDTPS = 8 // 1:8 // #pragma config WDTPS = 16 // 1:16 // #pragma config WDTPS = 32 // 1:32 // #pragma config WDTPS = 64 // 1:64 // #pragma config WDTPS = 128 // 1:128 // #pragma config WDTPS = 256 // 1:256 // #pragma config WDTPS = 512 // 1:512 // #pragma config WDTPS = 1024 // 1:1024 // #pragma config WDTPS = 2048 // 1:2048 // #pragma config WDTPS = 4096 // 1:4096 // #pragma config WDTPS = 8192 // 1:8192 // #pragma config WDTPS = 16384 // 1:16384 // #pragma config WDTPS = 32768 // 1:32768 ////////////////////////////////////////////////////////////////// // MCLR Pin Enable bit: // #pragma config MCLRE = OFF // RE3 input pin enabled; MCLR disabled // #pragma config MCLRE = ON // MCLR pin enabled; RE3 input pin disabled ////////////////////////////////////////////////////////////////// // Low Power Timer1 Oscillator Enable bit: // #pragma config LPT1OSC = OFF // Timer1 configured for higher power operation // #pragma config LPT1OSC = ON // Timer1 configured for low-power operation ////////////////////////////////////////////////////////////////// // PORTB Pins Configured for A/D: // #pragma config PBADEN = OFF // PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset // #pragma config PBADEN = ON // PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ////////////////////////////////////////////////////////////////// // BackGround Debugger Enable bit: // #pragma config DEBUG = ON // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug // #pragma config DEBUG = OFF // Background debugger disabled, RB6 and RB7 configuredas general purpose I/O pins ////////////////////////////////////////////////////////////////// // Extended Instruction Set Enable bit: // #pragma config XINST = OFF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode) // #pragma config XINST = ON // Instruction set extension and Indexed Addressing mode enabled ////////////////////////////////////////////////////////////////// // Boot Block Size Select Bits: // #pragma config BBSIZ = 1024 // 1K words (2K bytes) Boot Block // #pragma config BBSIZ = 2048 // 2K words (4K bytes) Boot Block // #pragma config BBSIZ = 4096 // 4K words (8K bytes) Boot Block ////////////////////////////////////////////////////////////////// // Low Voltage Programming: // #pragma config LVP = OFF // Disabled // #pragma config LVP = ON // Enabled ////////////////////////////////////////////////////////////////// // Stack Full/Underflow Reset Enable bit: // #pragma config STVREN = OFF // Stack full/underflow will not cause Reset // #pragma config STVREN = ON // Stack full/underflow will cause Reset ////////////////////////////////////////////////////////////////// // Code Protection Block 0: // #pragma config CP0 = ON // Block 0 (000800-003FFFh) code-protected // #pragma config CP0 = OFF // Block 0 (000800-003FFFh) not code-protected ////////////////////////////////////////////////////////////////// // Code Protection Block 1: // #pragma config CP1 = ON // Block 1 (004000-007FFFh) code-protected // #pragma config CP1 = OFF // Block 1 (004000-007FFFh) not code-protected ////////////////////////////////////////////////////////////////// // Code Protection Block 2: // #pragma config CP2 = ON // Block 2 (008000-00BFFFh) code-protected // #pragma config CP2 = OFF // Block 2 (008000-00BFFFh) not code-protected ////////////////////////////////////////////////////////////////// // Code Protection Block 3: // #pragma config CP3 = ON // Block 3 (00C000-00FFFFh) code-protected // #pragma config CP3 = OFF // Block 3 (00C000-00FFFFh) not code-protected ////////////////////////////////////////////////////////////////// // Code Protection Block 4: // #pragma config CP4 = ON // Block 4 (010000-013FFFh) code-protected // #pragma config CP4 = OFF // Block 4 (010000-013FFFh) not code-protected ////////////////////////////////////////////////////////////////// // Code Protection Block 5: // #pragma config CP5 = ON // Block 5 (014000-017FFFh) code-protected // #pragma config CP5 = OFF // Block 5 (014000-017FFFh) not code-protected ////////////////////////////////////////////////////////////////// // Boot Block Code Protection: // #pragma config CPB = ON // Boot Block (000000-0007FFh) code-protected // #pragma config CPB = OFF // Boot Block (000000-0007FFh) not code-protected ////////////////////////////////////////////////////////////////// // Data EEPROM Code Protection: // #pragma config CPD = ON // Data EEPROM code-protected // #pragma config CPD = OFF // Data EEPROM not code-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 0: // #pragma config WRT0 = ON // Block 0 (000800-003FFFh) write-protected // #pragma config WRT0 = OFF // Block 0 (000800-003FFFh) not write-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 1: // #pragma config WRT1 = ON // Block 1 (004000-007FFFh) write-protected // #pragma config WRT1 = OFF // Block 1 (004000-007FFFh) not write-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 2: // #pragma config WRT2 = ON // Block 2 (008000-00BFFFh) write-protected // #pragma config WRT2 = OFF // Block 2 (008000-00BFFFh) not write-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 3: // #pragma config WRT3 = ON // Block 3 (00C000-00FFFFh) write-protected // #pragma config WRT3 = OFF // Block 3 (00C000-00FFFFh) not write-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 4: // #pragma config WRT4 = ON // Block 4 (010000-013FFFh) write-protected // #pragma config WRT4 = OFF // Block 4 (010000-013FFFh) not write-protected ////////////////////////////////////////////////////////////////// // Write Protection Block 5: // #pragma config WRT5 = ON // Block 5 (014000-017FFFh) write-protected // #pragma config WRT5 = OFF // Block 5 (014000-017FFFh) not write-protected ////////////////////////////////////////////////////////////////// // Boot Block Write Protection: // #pragma config WRTB = ON // Boot Block (000000-0007FFh) write-protected // #pragma config WRTB = OFF // Boot Block (000000-0007FFh) not write-protected ////////////////////////////////////////////////////////////////// // Configuration Register Write Protection: // #pragma config WRTC = ON // Configuration registers (300000-3000FFh) write-protected // #pragma config WRTC = OFF // Configuration registers (300000-3000FFh) not write-protected ////////////////////////////////////////////////////////////////// // Data EEPROM Write Protection: // #pragma config WRTD = ON // Data EEPROM write-protected // #pragma config WRTD = OFF // Data EEPROM not write-protected ////////////////////////////////////////////////////////////////// // Table Read Protection Block 0: // #pragma config EBTR0 = ON // Block 0 (000800-003FFFh) protected from table reads executed in other blocks // #pragma config EBTR0 = OFF // Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Table Read Protection Block 1: // #pragma config EBTR1 = ON // Block 1 (004000-007FFFh) protected from table reads executed in other blocks // #pragma config EBTR1 = OFF // Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Table Read Protection Block 2: // #pragma config EBTR2 = ON // Block 2 (008000-00BFFFh) protected from table reads executed in other blocks // #pragma config EBTR2 = OFF // Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Table Read Protection Block 3: // #pragma config EBTR3 = ON // Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks // #pragma config EBTR3 = OFF // Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Table Read Protection Block 4: // #pragma config EBTR4 = ON // Block 4 (010000-013FFFh) protected from table reads executed in other blocks // #pragma config EBTR4 = OFF // Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Table Read Protection Block 5: // #pragma config EBTR5 = ON // Block 5 (014000-017FFFh) protected from table reads executed in other blocks // #pragma config EBTR5 = OFF // Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Boot Block Table Read Protection: // #pragma config EBTRB = ON // Boot Block (000000-0007FFh) protected from table reads executed in other blocks // #pragma config EBTRB = OFF // Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ////////////////////////////////////////////////////////////////// // Watchdog Timer: // #pragma config WDTEN = OFF // Disabled - Controlled by SWDTEN bit // #pragma config WDTEN = ON // Enabled