// *************************************** // BoostC Header file for PIC16F1508 // Author(s): David Hobday // // Copyright (C) 2003-2010 Pavel Baranov // Copyright (C) 2003-2010 David Hobday // All Rights Reserved // *************************************** #ifndef _PIC16F1508_H_ #define _PIC16F1508_H_ //////////////////////////////////////////////////////////////////////////// // // Register Definitions // //////////////////////////////////////////////////////////////////////////// #define W 0x0000 #define F 0x0001 /////// Register Files ///////////////////////////////////////////////////// ///////Bank0////////////////// #define INDF0 0x0000 #define INDF1 0x0001 #define PCL 0x0002 #define STATUS 0x0003 #define FSR0 0x0004 #define FSR0L 0x0004 #define FSR0H 0x0005 #define FSR1 0x0006 #define FSR1L 0x0006 #define FSR1H 0x0007 #define BSR 0x0008 #define WREG 0x0009 #define PCLATH 0x000A #define INTCON 0x000B #define PORTA 0x000C #define PORTB 0x000D #define PORTC 0x000E #define PIR1 0x0011 #define PIR2 0x0012 #define PIR3 0x0013 #define TMR0 0x0015 #define TMR1 0x0016 #define TMR1L 0x0016 #define TMR1H 0x0017 #define T1CON 0x0018 #define T1GCON 0x0019 #define TMR2 0x001A #define PR2 0x001B #define T2CON 0x001C ///////Bank1////////////////// #define TRISA 0x008C #define TRISB 0x008D #define TRISC 0x008E #define PIE1 0x0091 #define PIE2 0x0092 #define PIE3 0x0093 #define OPTION_REG 0x0095 #define PCON 0x0096 #define WDTCON 0x0097 #define OSCCON 0x0099 #define OSCSTAT 0x009A #define ADRES 0x009B #define ADRESL 0x009B #define ADRESH 0x009C #define ADCON0 0x009D #define ADCON1 0x009E #define ADCON2 0x009F ///////Bank2////////////////// #define LATA 0x010C #define LATB 0x010D #define LATC 0x010E #define CM1CON0 0x0111 #define CM1CON1 0x0112 #define CM2CON0 0x0113 #define CM2CON1 0x0114 #define CMOUT 0x0115 #define BORCON 0x0116 #define FVRCON 0x0117 #define DACCON0 0x0118 #define DACCON1 0x0119 #define APFCON 0x011D ///////Bank3////////////////// #define ANSELA 0x018C #define ANSELB 0x018D #define ANSELC 0x018E #define PMADR 0x0191 #define PMADRL 0x0191 #define PMADRH 0x0192 #define PMDAT 0x0193 #define PMDATL 0x0193 #define PMDATH 0x0194 #define PMCON1 0x0195 #define PMCON2 0x0196 #define VREGCON 0x0197 #define RCREG 0x0199 #define TXREG 0x019A #define SPBRGL 0x019B #define SPBRGH 0x019C #define RCSTA 0x019D #define TXSTA 0x019E #define BAUDCON 0x019F ///////Bank4////////////////// #define WPUA 0x020C #define WPUB 0x020D #define SSP1BUF 0x0211 #define SSPBUF 0x0211 #define SSP1ADD 0x0212 #define SSPADD 0x0212 #define SSP1MSK 0x0213 #define SSPMSK 0x0213 #define SSP1STAT 0x0214 #define SSPSTAT 0x0214 #define SSP1CON1 0x0215 #define SSPCON 0x0215 #define SSPCON1 0x0215 #define SSP1CON2 0x0216 #define SSPCON2 0x0216 #define SSP1CON3 0x0217 #define SSPCON3 0x0217 ///////Bank7////////////////// #define IOCAP 0x0391 #define IOCAN 0x0392 #define IOCAF 0x0393 #define IOCBP 0x0394 #define IOCBN 0x0395 #define IOCBF 0x0396 ///////Bank9////////////////// #define NCO1ACC 0x0498 #define NCO1ACCL 0x0498 #define NCO1ACCH 0x0499 #define NCO1ACCU 0x049A #define NCO1INC 0x049B #define NCO1INCL 0x049B #define NCO1INCH 0x049C #define NCO1INCU 0x049D #define NCO1CON 0x049E #define NCO1CLK 0x049F ///////Bank12////////////////// #define PWM1DCL 0x0611 #define PWM1DCH 0x0612 #define PWM1CON 0x0613 #define PWM1CON0 0x0613 #define PWM2DCL 0x0614 #define PWM2DCH 0x0615 #define PWM2CON 0x0616 #define PWM2CON0 0x0616 #define PWM3DCL 0x0617 #define PWM3DCH 0x0618 #define PWM3CON 0x0619 #define PWM3CON0 0x0619 #define PWM4DCL 0x061A #define PWM4DCH 0x061B #define PWM4CON 0x061C #define PWM4CON0 0x061C ///////Bank13////////////////// #define CWG1DBR 0x0691 #define CWG1DBF 0x0692 #define CWG1CON0 0x0693 #define CWG1CON1 0x0694 #define CWG1CON2 0x0695 ///////Bank30////////////////// #define CLCDATA 0x0F0F #define CLC1CON 0x0F10 #define CLC1POL 0x0F11 #define CLC1SEL0 0x0F12 #define CLC1SEL1 0x0F13 #define CLC1GLS0 0x0F14 #define CLC1GLS1 0x0F15 #define CLC1GLS2 0x0F16 #define CLC1GLS3 0x0F17 #define CLC2CON 0x0F18 #define CLC2POL 0x0F19 #define CLC2SEL0 0x0F1A #define CLC2SEL1 0x0F1B #define CLC2GLS0 0x0F1C #define CLC2GLS1 0x0F1D #define CLC2GLS2 0x0F1E #define CLC2GLS3 0x0F1F #define CLC3CON 0x0F20 #define CLC3POL 0x0F21 #define CLC3SEL0 0x0F22 #define CLC3SEL1 0x0F23 #define CLC3GLS0 0x0F24 #define CLC3GLS1 0x0F25 #define CLC3GLS2 0x0F26 #define CLC3GLS3 0x0F27 #define CLC4CON 0x0F28 #define CLC4POL 0x0F29 #define CLC4SEL0 0x0F2A #define CLC4SEL1 0x0F2B #define CLC4GLS0 0x0F2C #define CLC4GLS1 0x0F2D #define CLC4GLS2 0x0F2E #define CLC4GLS3 0x0F2F ///////Bank31////////////////// #define ICDIO 0x0F8C #define ICDCON0 0x0F8D #define ICDSTAT 0x0F91 #define DEVSEL 0x0F95 #define ICDINSTL 0x0F96 #define ICDINSTH 0x0F97 #define ICDBK0CON 0x0F9C #define ICDBK0L 0x0F9D #define ICDBK0H 0x0F9E #define BSRICDSHAD 0x0FE3 #define STATUS_SHAD 0x0FE4 #define WREG_SHAD 0x0FE5 #define BSR_SHAD 0x0FE6 #define PCLATH_SHAD 0x0FE7 #define FSR0L_SHAD 0x0FE8 #define FSR0H_SHAD 0x0FE9 #define FSR1L_SHAD 0x0FEA #define FSR1H_SHAD 0x0FEB #define STKPTR 0x0FED #define TOSL 0x0FEE #define TOSH 0x0FEF /////// STATUS Bits ///////////////////////////////////////////////////// #define C 0x0000 #define DC 0x0001 #define Z 0x0002 #define NOT_PD 0x0003 #define NOT_TO 0x0004 /////// BSR Bits ///////////////////////////////////////////////////// #define BSR0 0x0000 #define BSR1 0x0001 #define BSR2 0x0002 #define BSR3 0x0003 #define BSR4 0x0004 /////// INTCON Bits ///////////////////////////////////////////////////// #define IOCIF 0x0000 #define INTF 0x0001 #define TMR0IF 0x0002 #define IOCIE 0x0003 #define INTE 0x0004 #define TMR0IE 0x0005 #define PEIE 0x0006 #define GIE 0x0007 #define T0IF 0x0002 #define T0IE 0x0005 /////// PORTA Bits ///////////////////////////////////////////////////// #define RA0 0x0000 #define RA1 0x0001 #define RA2 0x0002 #define RA3 0x0003 #define RA4 0x0004 #define RA5 0x0005 /////// PORTB Bits ///////////////////////////////////////////////////// #define RB4 0x0004 #define RB5 0x0005 #define RB6 0x0006 #define RB7 0x0007 /////// PORTC Bits ///////////////////////////////////////////////////// #define RC0 0x0000 #define RC1 0x0001 #define RC2 0x0002 #define RC3 0x0003 #define RC4 0x0004 #define RC5 0x0005 #define RC6 0x0006 #define RC7 0x0007 /////// PIR1 Bits ///////////////////////////////////////////////////// #define TMR1IF 0x0000 #define TMR2IF 0x0001 #define SSP1IF 0x0003 #define TXIF 0x0004 #define RCIF 0x0005 #define ADIF 0x0006 #define TMR1GIF 0x0007 /////// PIR2 Bits ///////////////////////////////////////////////////// #define NCO1IF 0x0002 #define BCL1IF 0x0003 #define C1IF 0x0005 #define C2IF 0x0006 #define OSFIF 0x0007 /////// PIR3 Bits ///////////////////////////////////////////////////// #define CLC1IF 0x0000 #define CLC2IF 0x0001 #define CLC3IF 0x0002 #define CLC4IF 0x0003 /////// T1CON Bits ///////////////////////////////////////////////////// #define TMR1ON 0x0000 #define NOT_T1SYNC 0x0002 #define T1OSCEN 0x0003 #define T1CKPS0 0x0004 #define T1CKPS1 0x0005 #define TMR1CS0 0x0006 #define TMR1CS1 0x0007 /////// T1GCON Bits ///////////////////////////////////////////////////// #define T1GVAL 0x0002 #define T1GGO_NOT_DONE 0x0003 #define T1GSPM 0x0004 #define T1GTM 0x0005 #define T1GPOL 0x0006 #define TMR1GE 0x0007 #define T1GSS0 0x0000 #define T1GSS1 0x0001 /////// T2CON Bits ///////////////////////////////////////////////////// #define TMR2ON 0x0002 #define T2CKPS0 0x0000 #define T2CKPS1 0x0001 #define TOUTPS0 0x0003 #define TOUTPS1 0x0004 #define TOUTPS2 0x0005 #define TOUTPS3 0x0006 /////// TRISA Bits ///////////////////////////////////////////////////// #define TRISA0 0x0000 #define TRISA1 0x0001 #define TRISA2 0x0002 #define TRISA3 0x0003 #define TRISA4 0x0004 #define TRISA5 0x0005 /////// TRISB Bits ///////////////////////////////////////////////////// #define TRISB4 0x0004 #define TRISB5 0x0005 #define TRISB6 0x0006 #define TRISB7 0x0007 /////// TRISC Bits ///////////////////////////////////////////////////// #define TRISC0 0x0000 #define TRISC1 0x0001 #define TRISC2 0x0002 #define TRISC3 0x0003 #define TRISC4 0x0004 #define TRISC5 0x0005 #define TRISC6 0x0006 #define TRISC7 0x0007 /////// PIE1 Bits ///////////////////////////////////////////////////// #define TMR1IE 0x0000 #define TMR2IE 0x0001 #define SSP1IE 0x0003 #define TXIE 0x0004 #define RCIE 0x0005 #define ADIE 0x0006 #define TMR1GIE 0x0007 /////// PIE2 Bits ///////////////////////////////////////////////////// #define NCO1IE 0x0002 #define BCL1IE 0x0003 #define C1IE 0x0005 #define C2IE 0x0006 #define OSFIE 0x0007 /////// PIE3 Bits ///////////////////////////////////////////////////// #define CLC1E 0x0000 #define CLC2IE 0x0001 #define CLC3IE 0x0002 #define CLC4IE 0x0003 /////// OPTION_REG Bits ///////////////////////////////////////////////////// #define PSA 0x0003 #define TMR0SE 0x0004 #define TMR0CS 0x0005 #define INTEDG 0x0006 #define NOT_WPUEN 0x0007 #define PS0 0x0000 #define PS1 0x0001 #define PS2 0x0002 #define T0SE 0x0004 #define T0CS 0x0005 /////// PCON Bits ///////////////////////////////////////////////////// #define NOT_BOR 0x0000 #define NOT_POR 0x0001 #define NOT_RI 0x0002 #define NOT_RMCLR 0x0003 #define NOT_RWDT 0x0004 #define STKUNF 0x0006 #define STKOVF 0x0007 /////// WDTCON Bits ///////////////////////////////////////////////////// #define SWDTEN 0x0000 #define WDTPS0 0x0001 #define WDTPS1 0x0002 #define WDTPS2 0x0003 #define WDTPS3 0x0004 #define WDTPS4 0x0005 /////// OSCCON Bits ///////////////////////////////////////////////////// #define SCS0 0x0000 #define SCS1 0x0001 #define IRCF0 0x0003 #define IRCF1 0x0004 #define IRCF2 0x0005 #define IRCF3 0x0006 /////// OSCSTAT Bits ///////////////////////////////////////////////////// #define HFIOFS 0x0000 #define LFIOFR 0x0001 #define HFIOFR 0x0004 #define OSTS 0x0005 #define SOSCR 0x0007 /////// ADCON0 Bits ///////////////////////////////////////////////////// #define ADON 0x0000 #define GO_NOT_DONE 0x0001 #define ADGO 0x0001 #define CHS0 0x0002 #define CHS1 0x0003 #define CHS2 0x0004 #define CHS3 0x0005 #define CHS4 0x0006 #define GO 0x0001 /////// ADCON1 Bits ///////////////////////////////////////////////////// #define ADFM 0x0007 #define ADPREF0 0x0000 #define ADPREF1 0x0001 /////// ADCON2 Bits ///////////////////////////////////////////////////// #define TRIGSEL0 0x0004 #define TRIGSEL1 0x0005 #define TRIGSEL2 0x0006 #define TRIGSEL3 0x0007 /////// LATA Bits ///////////////////////////////////////////////////// #define LATA0 0x0000 #define LATA1 0x0001 #define LATA2 0x0002 #define LATA4 0x0004 #define LATA5 0x0005 /////// LATB Bits ///////////////////////////////////////////////////// #define LATB4 0x0004 #define LATB5 0x0005 #define LATB6 0x0006 #define LATB7 0x0007 /////// LATC Bits ///////////////////////////////////////////////////// #define LATC0 0x0000 #define LATC1 0x0001 #define LATC2 0x0002 #define LATC3 0x0003 #define LATC4 0x0004 #define LATC5 0x0005 #define LATC6 0x0006 #define LATC7 0x0007 /////// CM1CON0 Bits ///////////////////////////////////////////////////// #define C1SYNC 0x0000 #define C1HYS 0x0001 #define C1SP 0x0002 #define C1POL 0x0004 #define C1OE 0x0005 #define C1OUT 0x0006 #define C1ON 0x0007 /////// CM1CON1 Bits ///////////////////////////////////////////////////// #define C1NCH0 0x0000 #define C1NCH1 0x0001 #define C1PCH0 0x0004 #define C1PCH1 0x0005 #define C1INTN 0x0006 #define C1INTP 0x0007 /////// CM2CON0 Bits ///////////////////////////////////////////////////// #define C2SYNC 0x0000 #define C2HYS 0x0001 #define C2SP 0x0002 #define C2POL 0x0004 #define C2OE 0x0005 #define C2OUT 0x0006 #define C2ON 0x0007 /////// CM2CON1 Bits ///////////////////////////////////////////////////// #define C2NCH0 0x0000 #define C2NCH1 0x0001 #define C2PCH0 0x0004 #define C2PCH1 0x0005 #define C2INTN 0x0006 #define C2INTP 0x0007 /////// CMOUT Bits ///////////////////////////////////////////////////// #define MC1OUT 0x0000 #define MC2OUT 0x0001 /////// BORCON Bits ///////////////////////////////////////////////////// #define BORRDY 0x0000 #define BORFS 0x0006 #define SBOREN 0x0007 /////// FVRCON Bits ///////////////////////////////////////////////////// #define FVRRDY 0x0006 #define FVREN 0x0007 #define ADFVR0 0x0000 #define ADFVR1 0x0001 #define CDAFVR0 0x0002 #define CDAFVR1 0x0003 /////// DACCON0 Bits ///////////////////////////////////////////////////// #define DACPSS 0x0002 #define DACOE2 0x0004 #define DACOE1 0x0005 #define DACEN 0x0007 /////// DACCON1 Bits ///////////////////////////////////////////////////// #define DACR0 0x0000 #define DACR1 0x0001 #define DACR2 0x0002 #define DACR3 0x0003 #define DACR4 0x0004 /////// APFCON Bits ///////////////////////////////////////////////////// #define NCOSEL 0x0000 #define CLC1SEL 0x0001 #define T1GSEL 0x0003 #define SSSEL 0x0004 /////// ANSELA Bits ///////////////////////////////////////////////////// #define ANSA0 0x0000 #define ANSA1 0x0001 #define ANSA2 0x0002 #define ANSA4 0x0004 /////// ANSELB Bits ///////////////////////////////////////////////////// #define ANSB4 0x0004 #define ANSB5 0x0005 /////// ANSELC Bits ///////////////////////////////////////////////////// #define ANSC0 0x0000 #define ANSC1 0x0001 #define ANSC2 0x0002 #define ANSC3 0x0003 #define ANSC6 0x0006 #define ANSC7 0x0007 /////// PMCON1 Bits ///////////////////////////////////////////////////// #define RD 0x0000 #define WR 0x0001 #define WREN 0x0002 #define WRERR 0x0003 #define FREE 0x0004 #define LWLO 0x0005 #define CFGS 0x0006 #define EEPGD 0x0007 /////// VREGCON Bits ///////////////////////////////////////////////////// #define VREGPM0 0x0000 #define VREGPM1 0x0001 /////// RCSTA Bits ///////////////////////////////////////////////////// #define RX9D 0x0000 #define OERR 0x0001 #define FERR 0x0002 #define ADDEN 0x0003 #define CREN 0x0004 #define SREN 0x0005 #define RX9 0x0006 #define SPEN 0x0007 /////// TXSTA Bits ///////////////////////////////////////////////////// #define TX9D 0x0000 #define TRMT 0x0001 #define BRGH 0x0002 #define SENDB 0x0003 #define SYNC 0x0004 #define TXEN 0x0005 #define TX9 0x0006 #define CSRC 0x0007 /////// BAUDCON Bits ///////////////////////////////////////////////////// #define ABDEN 0x0000 #define WUE 0x0001 #define BRG16 0x0003 #define SCKP 0x0004 #define RCIDL 0x0006 #define ABDOVF 0x0007 /////// WPUA Bits ///////////////////////////////////////////////////// #define WPUA0 0x0000 #define WPUA1 0x0001 #define WPUA2 0x0002 #define WPUA3 0x0003 #define WPUA4 0x0004 #define WPUA5 0x0005 /////// WPUB Bits ///////////////////////////////////////////////////// #define WPUB4 0x0004 #define WPUB5 0x0005 #define WPUB6 0x0006 #define WPUB7 0x0007 /////// SSP1STAT Bits ///////////////////////////////////////////////////// #define BF 0x0000 #define UA 0x0001 #define R_NOT_W 0x0002 #define S 0x0003 #define P 0x0004 #define D_NOT_A 0x0005 #define CKE 0x0006 #define SMP 0x0007 /////// SSPSTAT Bits ///////////////////////////////////////////////////// #define BF 0x0000 #define UA 0x0001 #define R_NOT_W 0x0002 #define S 0x0003 #define P 0x0004 #define D_NOT_A 0x0005 #define CKE 0x0006 #define SMP 0x0007 /////// SSP1CON1 Bits ///////////////////////////////////////////////////// #define SSP1M0 0x0000 #define SSP1M1 0x0001 #define SSP1M2 0x0002 #define SSP1M3 0x0003 #define CKP 0x0004 #define SSPEN 0x0005 #define SSPOV 0x0006 #define WCOL 0x0007 /////// SSPCON Bits ///////////////////////////////////////////////////// #define SSP1M0 0x0000 #define SSP1M1 0x0001 #define SSP1M2 0x0002 #define SSP1M3 0x0003 #define CKP 0x0004 #define SSP1EN 0x0005 #define SSP1OV 0x0006 #define WCOL 0x0007 /////// SSPCON1 Bits ///////////////////////////////////////////////////// #define SSP1M0 0x0000 #define SSP1M1 0x0001 #define SSP1M2 0x0002 #define SSP1M3 0x0003 #define CKP 0x0004 #define SSP1EN 0x0005 #define SSP1OV 0x0006 #define WCOL 0x0007 /////// SSP1CON2 Bits ///////////////////////////////////////////////////// #define SEN 0x0000 #define RSEN 0x0001 #define PEN 0x0002 #define RCEN 0x0003 #define ACKEN 0x0004 #define ACKDT 0x0005 #define ACKSTAT 0x0006 #define GCEN 0x0007 /////// SSPCON2 Bits ///////////////////////////////////////////////////// #define SEN 0x0000 #define RSEN 0x0001 #define PEN 0x0002 #define RCEN 0x0003 #define ACKEN 0x0004 #define ACKDT 0x0005 #define ACKSTAT 0x0006 #define GCEN 0x0007 /////// SSP1CON3 Bits ///////////////////////////////////////////////////// #define DHEN 0x0000 #define AHEN 0x0001 #define SBCDE 0x0002 #define SDAHT 0x0003 #define BOEN 0x0004 #define SCIE 0x0005 #define PCIE 0x0006 #define ACKTIM 0x0007 /////// SSPCON3 Bits ///////////////////////////////////////////////////// #define DHEN 0x0000 #define AHEN 0x0001 #define SBCDE 0x0002 #define SDAHT 0x0003 #define BOEN 0x0004 #define SCIE 0x0005 #define PCIE 0x0006 #define ACKTIM 0x0007 /////// IOCAP Bits ///////////////////////////////////////////////////// #define IOCAP0 0x0000 #define IOCAP1 0x0001 #define IOCAP2 0x0002 #define IOCAP3 0x0003 #define IOCAP4 0x0004 #define IOCAP5 0x0005 /////// IOCAN Bits ///////////////////////////////////////////////////// #define IOCAN0 0x0000 #define IOCAN1 0x0001 #define IOCAN2 0x0002 #define IOCAN3 0x0003 #define IOCAN4 0x0004 #define IOCAN5 0x0005 /////// IOCAF Bits ///////////////////////////////////////////////////// #define IOCAF0 0x0000 #define IOCAF1 0x0001 #define IOCAF2 0x0002 #define IOCAF3 0x0003 #define IOCAF4 0x0004 #define IOCAF5 0x0005 /////// IOCBP Bits ///////////////////////////////////////////////////// #define IOCBP4 0x0004 #define IOCBP5 0x0005 #define IOCBP6 0x0006 #define IOCBP7 0x0007 /////// IOCBN Bits ///////////////////////////////////////////////////// #define IOCBN4 0x0004 #define IOCBN5 0x0005 #define IOCBN6 0x0006 #define IOCBN7 0x0007 /////// IOCBF Bits ///////////////////////////////////////////////////// #define IOCBF4 0x0004 #define IOCBF5 0x0005 #define IOCBF6 0x0006 #define IOCBF7 0x0007 /////// NCO1ACCL Bits ///////////////////////////////////////////////////// #define NCO1ACC0 0x0000 #define NCO1ACC1 0x0001 #define NCO1ACC2 0x0002 #define NCO1ACC3 0x0003 #define NCO1ACC4 0x0004 #define NCO1ACC5 0x0005 #define NCO1ACC6 0x0006 #define NCO1ACC7 0x0007 /////// NCO1ACCH Bits ///////////////////////////////////////////////////// #define NCO1ACC8 0x0000 #define NCO1ACC9 0x0001 #define NCO1ACC10 0x0002 #define NCO1ACC11 0x0003 #define NCO1ACC12 0x0004 #define NCO1ACC13 0x0005 #define NCO1ACC14 0x0006 #define NCO1ACC15 0x0007 /////// NCO1ACCU Bits ///////////////////////////////////////////////////// #define NCO1ACC16 0x0000 #define NCO1ACC17 0x0001 #define NCO1ACC18 0x0002 #define NCO1ACC19 0x0003 /////// NCO1INCL Bits ///////////////////////////////////////////////////// #define NCO1INC0 0x0000 #define NCO1INC1 0x0001 #define NCO1INC2 0x0002 #define NCO1INC3 0x0003 #define NCO1INC4 0x0004 #define NCO1INC5 0x0005 #define NCO1INC6 0x0006 #define NCO1INC7 0x0007 /////// NCO1INCH Bits ///////////////////////////////////////////////////// #define NCO1INC8 0x0000 #define NCO1INC9 0x0001 #define NCO1INC10 0x0002 #define NCO1INC11 0x0003 #define NCO1INC12 0x0004 #define NCO1INC13 0x0005 #define NCO1INC14 0x0006 #define NCO1INC15 0x0007 /////// NCO1CON Bits ///////////////////////////////////////////////////// #define N1PFM 0x0000 #define N1POL 0x0004 #define N1OUT 0x0005 #define N1OE 0x0006 #define N1EN 0x0007 /////// NCO1CLK Bits ///////////////////////////////////////////////////// #define N1CKS0 0x0000 #define N1CKS1 0x0001 #define N1PWS0 0x0005 #define N1PWS1 0x0006 #define N1PWS2 0x0007 /////// PWM1DCL Bits ///////////////////////////////////////////////////// #define PWM1DCL0 0x0006 #define PWM1DCL1 0x0007 /////// PWM1DCH Bits ///////////////////////////////////////////////////// #define PWM1DCH0 0x0000 #define PWM1DCH1 0x0001 #define PWM1DCH2 0x0002 #define PWM1DCH3 0x0003 #define PWM1DCH4 0x0004 #define PWM1DCH5 0x0005 #define PWM1DCH6 0x0006 #define PWM1DCH7 0x0007 /////// PWM1CON Bits ///////////////////////////////////////////////////// #define PWM1POL 0x0004 #define PWM1OUT 0x0005 #define PWM1OE 0x0006 #define PWM1EN 0x0007 /////// PWM1CON0 Bits ///////////////////////////////////////////////////// #define PWM1POL 0x0004 #define PWM1OUT 0x0005 #define PWM1OE 0x0006 #define PWM1EN 0x0007 /////// PWM2DCL Bits ///////////////////////////////////////////////////// #define PWM2DCL0 0x0006 #define PWM2DCL1 0x0007 /////// PWM2DCH Bits ///////////////////////////////////////////////////// #define PWM2DCH0 0x0000 #define PWM2DCH1 0x0001 #define PWM2DCH2 0x0002 #define PWM2DCH3 0x0003 #define PWM2DCH4 0x0004 #define PWM2DCH5 0x0005 #define PWM2DCH6 0x0006 #define PWM2DCH7 0x0007 /////// PWM2CON Bits ///////////////////////////////////////////////////// #define PWM2POL 0x0004 #define PWM2OUT 0x0005 #define PWM2OE 0x0006 #define PWM2EN 0x0007 /////// PWM2CON0 Bits ///////////////////////////////////////////////////// #define PWM2POL 0x0004 #define PWM2OUT 0x0005 #define PWM2OE 0x0006 #define PWM2EN 0x0007 /////// PWM3DCL Bits ///////////////////////////////////////////////////// #define PWM3DCL0 0x0006 #define PWM3DCL1 0x0007 /////// PWM3DCH Bits ///////////////////////////////////////////////////// #define PWM3DCH0 0x0000 #define PWM3DCH1 0x0001 #define PWM3DCH2 0x0002 #define PWM3DCH3 0x0003 #define PWM3DCH4 0x0004 #define PWM3DCH5 0x0005 #define PWM3DCH6 0x0006 #define PWM3DCH7 0x0007 /////// PWM3CON Bits ///////////////////////////////////////////////////// #define PWM3POL 0x0004 #define PWM3OUT 0x0005 #define PWM3OE 0x0006 #define PWM3EN 0x0007 /////// PWM3CON0 Bits ///////////////////////////////////////////////////// #define PWM3POL 0x0004 #define PWM3OUT 0x0005 #define PWM3OE 0x0006 #define PWM3EN 0x0007 /////// PWM4DCL Bits ///////////////////////////////////////////////////// #define PWM4DCL0 0x0006 #define PWM4DCL1 0x0007 /////// PWM4DCH Bits ///////////////////////////////////////////////////// #define PWM4DCH0 0x0000 #define PWM4DCH1 0x0001 #define PWM4DCH2 0x0002 #define PWM4DCH3 0x0003 #define PWM4DCH4 0x0004 #define PWM4DCH5 0x0005 #define PWM4DCH6 0x0006 #define PWM4DCH7 0x0007 /////// PWM4CON Bits ///////////////////////////////////////////////////// #define PWM4POL 0x0004 #define PWM4OUT 0x0005 #define PWM4OE 0x0006 #define PWM4EN 0x0007 /////// PWM4CON0 Bits ///////////////////////////////////////////////////// #define PWM4POL 0x0004 #define PWM4OUT 0x0005 #define PWM4OE 0x0006 #define PWM4EN 0x0007 /////// CWG1DBR Bits ///////////////////////////////////////////////////// #define CWG1DBR0 0x0000 #define CWG1DBR1 0x0001 #define CWG1DBR2 0x0002 #define CWG1DBR3 0x0003 #define CWG1DBR4 0x0004 #define CWG1DBR5 0x0005 /////// CWG1DBF Bits ///////////////////////////////////////////////////// #define CWG1DBF0 0x0000 #define CWG1DBF1 0x0001 #define CWG1DBF2 0x0002 #define CWG1DBF3 0x0003 #define CWG1DBF4 0x0004 #define CWG1DBF5 0x0005 /////// CWG1CON0 Bits ///////////////////////////////////////////////////// #define G1CS0 0x0000 #define G1POLA 0x0003 #define G1POLB 0x0004 #define G1OEA 0x0005 #define G1OEB 0x0006 #define G1EN 0x0007 /////// CWG1CON1 Bits ///////////////////////////////////////////////////// #define G1IS0 0x0000 #define G1IS1 0x0001 #define G1IS2 0x0002 #define G1ASDLA0 0x0004 #define G1ASDLA1 0x0005 #define G1ASDLB0 0x0006 #define G1ASDLB1 0x0007 /////// CWG1CON2 Bits ///////////////////////////////////////////////////// #define G1ASDSCLC2 0x0000 #define G1ASDSFLT 0x0001 #define G1ASDSC1 0x0002 #define G1ASDSC2 0x0003 #define G1ARSEN 0x0006 #define G1ASE 0x0007 /////// CLCDATA Bits ///////////////////////////////////////////////////// #define MCLC1OUT 0x0000 #define MCLC2OUT 0x0001 #define MCLC3OUT 0x0002 #define MCLC4OUT 0x0003 /////// CLC1CON Bits ///////////////////////////////////////////////////// #define LC1MODE0 0x0000 #define LC1MODE1 0x0001 #define LC1MODE2 0x0002 #define LC1INTN 0x0003 #define LC1INTP 0x0004 #define LC1OUT 0x0005 #define LC1OE 0x0006 #define LC1EN 0x0007 #define LCMODE0 0x0000 #define LCMODE1 0x0001 #define LCMODE2 0x0002 #define LCINTN 0x0003 #define LCINTP 0x0004 #define LCOUT 0x0005 #define LCOE 0x0006 #define LCEN 0x0007 /////// CLC1POL Bits ///////////////////////////////////////////////////// #define LC1G1POL 0x0000 #define LC1G2POL 0x0001 #define LC1G3POL 0x0002 #define LC1G4POL 0x0003 #define LC1POL 0x0007 #define G1POL 0x0000 #define G2POL 0x0001 #define G3POL 0x0002 #define G4POL 0x0003 #define POL 0x0007 /////// CLC1SEL0 Bits ///////////////////////////////////////////////////// #define LC1D1S0 0x0000 #define LC1D1S1 0x0001 #define LC1D1S2 0x0002 #define LC1D2S0 0x0004 #define LC1D2S1 0x0005 #define LC1D2S2 0x0006 #define D1S0 0x0000 #define D1S1 0x0001 #define D1S2 0x0002 #define D2S0 0x0004 #define D2S1 0x0005 #define D2S2 0x0006 /////// CLC1SEL1 Bits ///////////////////////////////////////////////////// #define LC1D3S0 0x0000 #define LC1D3S1 0x0001 #define LC1D3S2 0x0002 #define LC1D4S0 0x0004 #define LC1D4S1 0x0005 #define LC1D4S2 0x0006 #define D3S0 0x0000 #define D3S1 0x0001 #define D3S2 0x0002 #define D4S0 0x0004 #define D4S1 0x0005 #define D4S2 0x0006 /////// CLC1GLS0 Bits ///////////////////////////////////////////////////// #define LC1G1D1N 0x0000 #define LC1G1D1T 0x0001 #define LC1G1D2N 0x0002 #define LC1G1D2T 0x0003 #define LC1G1D3N 0x0004 #define LC1G1D3T 0x0005 #define LC1G1D4N 0x0006 #define LC1G1D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC1GLS1 Bits ///////////////////////////////////////////////////// #define LC1G2D1N 0x0000 #define LC1G2D1T 0x0001 #define LC1G2D2N 0x0002 #define LC1G2D2T 0x0003 #define LC1G2D3N 0x0004 #define LC1G2D3T 0x0005 #define LC1G2D4N 0x0006 #define LC1G2D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC1GLS2 Bits ///////////////////////////////////////////////////// #define LC1G3D1N 0x0000 #define LC1G3D1T 0x0001 #define LC1G3D2N 0x0002 #define LC1G3D2T 0x0003 #define LC1G3D3N 0x0004 #define LC1G3D3T 0x0005 #define LC1G3D4N 0x0006 #define LC1G3D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC1GLS3 Bits ///////////////////////////////////////////////////// #define LC1G4D1N 0x0000 #define LC1G4D1T 0x0001 #define LC1G4D2N 0x0002 #define LC1G4D2T 0x0003 #define LC1G4D3N 0x0004 #define LC1G4D3T 0x0005 #define LC1G4D4N 0x0006 #define LC1G4D4T 0x0007 #define G4D1N 0x0000 #define G4D1T 0x0001 #define G4D2N 0x0002 #define G4D2T 0x0003 #define G4D3N 0x0004 #define G4D3T 0x0005 #define G4D4N 0x0006 #define G4D4T 0x0007 /////// CLC2CON Bits ///////////////////////////////////////////////////// #define LC2MODE0 0x0000 #define LC2MODE1 0x0001 #define LC2MODE2 0x0002 #define LC2INTN 0x0003 #define LC2INTP 0x0004 #define LC2OUT 0x0005 #define LC2OE 0x0006 #define LC2EN 0x0007 #define LCMODE0 0x0000 #define LCMODE1 0x0001 #define LCMODE2 0x0002 #define LCINTN 0x0003 #define LCINTP 0x0004 #define LCOUT 0x0005 #define LCOE 0x0006 #define LCEN 0x0007 /////// CLC2POL Bits ///////////////////////////////////////////////////// #define LC2G1POL 0x0000 #define LC2G2POL 0x0001 #define LC2G3POL 0x0002 #define LC2G4POL 0x0003 #define LC2POL 0x0007 #define G1POL 0x0000 #define G2POL 0x0001 #define G3POL 0x0002 #define G4POL 0x0003 #define POL 0x0007 /////// CLC2SEL0 Bits ///////////////////////////////////////////////////// #define LC2D1S0 0x0000 #define LC2D1S1 0x0001 #define LC2D1S2 0x0002 #define LC2D2S0 0x0004 #define LC2D2S1 0x0005 #define LC2D2S2 0x0006 #define D1S0 0x0000 #define D1S1 0x0001 #define D1S2 0x0002 #define D2S0 0x0004 #define D2S1 0x0005 #define D2S2 0x0006 /////// CLC2SEL1 Bits ///////////////////////////////////////////////////// #define LC2D3S0 0x0000 #define LC2D3S1 0x0001 #define LC2D3S2 0x0002 #define LC2D4S0 0x0004 #define LC2D4S1 0x0005 #define LC2D4S2 0x0006 #define D3S0 0x0000 #define D3S1 0x0001 #define D3S2 0x0002 #define D4S0 0x0004 #define D4S1 0x0005 #define D4S2 0x0006 /////// CLC2GLS0 Bits ///////////////////////////////////////////////////// #define LC2G1D1N 0x0000 #define LC2G1D1T 0x0001 #define LC2G1D2N 0x0002 #define LC2G1D2T 0x0003 #define LC2G1D3N 0x0004 #define LC2G1D3T 0x0005 #define LC2G1D4N 0x0006 #define LC2G1D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC2GLS1 Bits ///////////////////////////////////////////////////// #define LC2G2D1N 0x0000 #define LC2G2D1T 0x0001 #define LC2G2D2N 0x0002 #define LC2G2D2T 0x0003 #define LC2G2D3N 0x0004 #define LC2G2D3T 0x0005 #define LC2G2D4N 0x0006 #define LC2G2D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC2GLS2 Bits ///////////////////////////////////////////////////// #define LC2G3D1N 0x0000 #define LC2G3D1T 0x0001 #define LC2G3D2N 0x0002 #define LC2G3D2T 0x0003 #define LC2G3D3N 0x0004 #define LC2G3D3T 0x0005 #define LC2G3D4N 0x0006 #define LC2G3D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC2GLS3 Bits ///////////////////////////////////////////////////// #define LC2G4D1N 0x0000 #define LC2G4D1T 0x0001 #define LC2G4D2N 0x0002 #define LC2G4D2T 0x0003 #define LC2G4D3N 0x0004 #define LC2G4D3T 0x0005 #define LC2G4D4N 0x0006 #define LC2G4D4T 0x0007 #define G4D1N 0x0000 #define G4D1T 0x0001 #define G4D2N 0x0002 #define G4D2T 0x0003 #define G4D3N 0x0004 #define G4D3T 0x0005 #define G4D4N 0x0006 #define G4D4T 0x0007 /////// CLC3CON Bits ///////////////////////////////////////////////////// #define LC3MODE0 0x0000 #define LC3MODE1 0x0001 #define LC3MODE2 0x0002 #define LC3INTN 0x0003 #define LC3INTP 0x0004 #define LC3OUT 0x0005 #define LC3OE 0x0006 #define LC3EN 0x0007 #define LCMODE0 0x0000 #define LCMODE1 0x0001 #define LCMODE2 0x0002 #define LCINTN 0x0003 #define LCINTP 0x0004 #define LCOUT 0x0005 #define LCOE 0x0006 #define LCEN 0x0007 /////// CLC3POL Bits ///////////////////////////////////////////////////// #define LC3G1POL 0x0000 #define LC3G2POL 0x0001 #define LC3G3POL 0x0002 #define LC3G4POL 0x0003 #define LC3POL 0x0007 #define G1POL 0x0000 #define G2POL 0x0001 #define G3POL 0x0002 #define G4POL 0x0003 #define POL 0x0007 /////// CLC3SEL0 Bits ///////////////////////////////////////////////////// #define LC3D1S0 0x0000 #define LC3D1S1 0x0001 #define LC3D1S2 0x0002 #define LC3D2S0 0x0004 #define LC3D2S1 0x0005 #define LC3D2S2 0x0006 #define D1S0 0x0000 #define D1S1 0x0001 #define D1S2 0x0002 #define D2S0 0x0004 #define D2S1 0x0005 #define D2S2 0x0006 /////// CLC3SEL1 Bits ///////////////////////////////////////////////////// #define LC3D3S0 0x0000 #define LC3D3S1 0x0001 #define LC3D3S2 0x0002 #define LC3D4S0 0x0004 #define LC3D4S1 0x0005 #define LC3D4S2 0x0006 #define D3S0 0x0000 #define D3S1 0x0001 #define D3S2 0x0002 #define D4S0 0x0004 #define D4S1 0x0005 #define D4S2 0x0006 /////// CLC3GLS0 Bits ///////////////////////////////////////////////////// #define LC3G1D1N 0x0000 #define LC3G1D1T 0x0001 #define LC3G1D2N 0x0002 #define LC3G1D2T 0x0003 #define LC3G1D3N 0x0004 #define LC3G1D3T 0x0005 #define LC3G1D4N 0x0006 #define LC3G1D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC3GLS1 Bits ///////////////////////////////////////////////////// #define LC3G2D1N 0x0000 #define LC3G2D1T 0x0001 #define LC3G2D2N 0x0002 #define LC3G2D2T 0x0003 #define LC3G2D3N 0x0004 #define LC3G2D3T 0x0005 #define LC3G2D4N 0x0006 #define LC3G2D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC3GLS2 Bits ///////////////////////////////////////////////////// #define LC3G3D1N 0x0000 #define LC3G3D1T 0x0001 #define LC3G3D2N 0x0002 #define LC3G3D2T 0x0003 #define LC3G3D3N 0x0004 #define LC3G3D3T 0x0005 #define LC3G3D4N 0x0006 #define LC3G3D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC3GLS3 Bits ///////////////////////////////////////////////////// #define LC3G4D1N 0x0000 #define LC3G4D1T 0x0001 #define LC3G4D2N 0x0002 #define LC3G4D2T 0x0003 #define LC3G4D3N 0x0004 #define LC3G4D3T 0x0005 #define LC3G4D4N 0x0006 #define LC3G4D4T 0x0007 #define G4D1N 0x0000 #define G4D1T 0x0001 #define G4D2N 0x0002 #define G4D2T 0x0003 #define G4D3N 0x0004 #define G4D3T 0x0005 #define G4D4N 0x0006 #define G4D4T 0x0007 /////// CLC4CON Bits ///////////////////////////////////////////////////// #define LC4MODE0 0x0000 #define LC4MODE1 0x0001 #define LC4MODE2 0x0002 #define LC4INTN 0x0003 #define LC4INTP 0x0004 #define LC4OUT 0x0005 #define LC4OE 0x0006 #define LC4EN 0x0007 #define LCMODE0 0x0000 #define LCMODE1 0x0001 #define LCMODE2 0x0002 #define LCINTN 0x0003 #define LCINTP 0x0004 #define LCOUT 0x0005 #define LCOE 0x0006 #define LCEN 0x0007 /////// CLC4POL Bits ///////////////////////////////////////////////////// #define LC4G1POL 0x0000 #define LC4G2POL 0x0001 #define LC4G3POL 0x0002 #define LC4G4POL 0x0003 #define LC4POL 0x0007 #define G1POL 0x0000 #define G2POL 0x0001 #define G3POL 0x0002 #define G4POL 0x0003 #define POL 0x0007 /////// CLC4SEL0 Bits ///////////////////////////////////////////////////// #define LC4D1S0 0x0000 #define LC4D1S1 0x0001 #define LC4D1S2 0x0002 #define LC4D2S0 0x0004 #define LC4D2S1 0x0005 #define LC4D2S2 0x0006 #define D1S0 0x0000 #define D1S1 0x0001 #define D1S2 0x0002 #define D2S0 0x0004 #define D2S1 0x0005 #define D2S2 0x0006 /////// CLC4SEL1 Bits ///////////////////////////////////////////////////// #define LC4D3S0 0x0000 #define LC4D3S1 0x0001 #define LC4D3S2 0x0002 #define LC4D4S0 0x0004 #define LC4D4S1 0x0005 #define LC4D4S2 0x0006 #define D3S0 0x0000 #define D3S1 0x0001 #define D3S2 0x0002 #define D4S0 0x0004 #define D4S1 0x0005 #define D4S2 0x0006 /////// CLC4GLS0 Bits ///////////////////////////////////////////////////// #define LC4G1D1N 0x0000 #define LC4G1D1T 0x0001 #define LC4G1D2N 0x0002 #define LC4G1D2T 0x0003 #define LC4G1D3N 0x0004 #define LC4G1D3T 0x0005 #define LC4G1D4N 0x0006 #define LC4G1D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC4GLS1 Bits ///////////////////////////////////////////////////// #define LC4G2D1N 0x0000 #define LC4G2D1T 0x0001 #define LC4G2D2N 0x0002 #define LC4G2D2T 0x0003 #define LC4G2D3N 0x0004 #define LC4G2D3T 0x0005 #define LC4G2D4N 0x0006 #define LC4G2D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC4GLS2 Bits ///////////////////////////////////////////////////// #define LC4G3D1N 0x0000 #define LC4G3D1T 0x0001 #define LC4G3D2N 0x0002 #define LC4G3D2T 0x0003 #define LC4G3D3N 0x0004 #define LC4G3D3T 0x0005 #define LC4G3D4N 0x0006 #define LC4G3D4T 0x0007 #define D1N 0x0000 #define D1T 0x0001 #define D2N 0x0002 #define D2T 0x0003 #define D3N 0x0004 #define D3T 0x0005 #define D4N 0x0006 #define D4T 0x0007 /////// CLC4GLS3 Bits ///////////////////////////////////////////////////// #define LC4G4D1N 0x0000 #define LC4G4D1T 0x0001 #define LC4G4D2N 0x0002 #define LC4G4D2T 0x0003 #define LC4G4D3N 0x0004 #define LC4G4D3T 0x0005 #define LC4G4D4N 0x0006 #define LC4G4D4T 0x0007 #define G4D1N 0x0000 #define G4D1T 0x0001 #define G4D2N 0x0002 #define G4D2T 0x0003 #define G4D3N 0x0004 #define G4D3T 0x0005 #define G4D4N 0x0006 #define G4D4T 0x0007 /////// ICDIO Bits ///////////////////////////////////////////////////// #define TRIS_ICDCLK 0x0002 #define TRIS_ICDDAT 0x0003 #define LAT_ICDCLK 0x0004 #define LAT_ICDDAT 0x0005 #define PORT_ICDCLK 0x0006 #define PORT_ICDDAT 0x0007 /////// ICDCON0 Bits ///////////////////////////////////////////////////// #define RSTVEC 0x0000 #define DBGINEX 0x0003 #define SSTEP 0x0005 #define FREEZ 0x0006 #define INBUG 0x0007 /////// ICDSTAT Bits ///////////////////////////////////////////////////// #define USRHLTF 0x0001 #define TRP0HLTF 0x0006 #define TRP1HLTF 0x0007 /////// DEVSEL Bits ///////////////////////////////////////////////////// #define DEVSEL0 0x0000 #define DEVSEL1 0x0001 #define DEVSEL2 0x0002 /////// ICDINSTL Bits ///////////////////////////////////////////////////// #define DBGIN0 0x0000 #define DBGIN1 0x0001 #define DBGIN2 0x0002 #define DBGIN3 0x0003 #define DBGIN4 0x0004 #define DBGIN5 0x0005 #define DBGIN6 0x0006 #define DBGIN7 0x0007 /////// ICDINSTH Bits ///////////////////////////////////////////////////// #define DBGIN8 0x0000 #define DBGIN9 0x0001 #define DBGIN10 0x0002 #define DBGIN11 0x0003 #define DBGIN12 0x0004 #define DBGIN13 0x0005 /////// ICDBK0CON Bits ///////////////////////////////////////////////////// #define BKHLT 0x0000 #define BKEN 0x0007 /////// ICDBK0L Bits ///////////////////////////////////////////////////// #define BKA0 0x0000 #define BKA1 0x0001 #define BKA2 0x0002 #define BKA3 0x0003 #define BKA4 0x0004 #define BKA5 0x0005 #define BKA6 0x0006 #define BKA7 0x0007 /////// ICDBK0H Bits ///////////////////////////////////////////////////// #define BKA8 0x0000 #define BKA9 0x0001 #define BKA10 0x0002 #define BKA11 0x0003 #define BKA12 0x0004 #define BKA13 0x0005 #define BKA14 0x0006 /////// STATUS_SHAD Bits ///////////////////////////////////////////////////// #define C 0x0000 #define DC 0x0001 #define Z 0x0002 // The following is an assignment of address values for all of the // configuration registers for the purpose of table reads //////////////////////////////////////////////////////////////////////////// // // Configuration Bits // // NAME Address // CONFIG1 8007h // CONFIG2 8008h // //////////////////////////////////////////////////////////////////////////// #define _CONFIG1 0x8007 #define _CONFIG2 0x8008 /////// CONFIG1 Options ////////////////////////////////////////////////// #define _FOSC_LP 0xFFF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins #define _FOSC_XT 0xFFF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins #define _FOSC_HS 0xFFFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins #define _FOSC_EXTRC 0xFFFB // EXTRC oscillator: External RC circuit connected to CLKIN pin #define _FOSC_INTOSC 0xFFFC // INTOSC oscillator: I/O function on CLKIN pin #define _FOSC_ECL 0xFFFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins #define _FOSC_ECM 0xFFFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins #define _FOSC_ECH 0xFFFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins #define _WDTE_OFF 0xFFE7 // WDT disabled #define _WDTE_SWDTEN 0xFFEF // WDT controlled by the SWDTEN bit in the WDTCON register #define _WDTE_NSLEEP 0xFFF7 // WDT enabled while running and disabled in Sleep #define _WDTE_ON 0xFFFF // WDT enabled #define _PWRTE_ON 0xFFDF // PWRT enabled #define _PWRTE_OFF 0xFFFF // PWRT disabled #define _MCLRE_OFF 0xFFBF // MCLR/VPP pin function is digital input #define _MCLRE_ON 0xFFFF // MCLR/VPP pin function is MCLR #define _CP_ON 0xFF7F // Program memory code protection is enabled #define _CP_OFF 0xFFFF // Program memory code protection is disabled #define _BOREN_OFF 0xF9FF // Brown-out Reset disabled #define _BOREN_SBODEN 0xFBFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register #define _BOREN_NSLEEP 0xFDFF // Brown-out Reset enabled while running and disabled in Sleep #define _BOREN_ON 0xFFFF // Brown-out Reset enabled #define _CLKOUTEN_ON 0xF7FF // CLKOUT function is enabled on the CLKOUT pin #define _CLKOUTEN_OFF 0xFFFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin #define _IESO_OFF 0xEFFF // Internal/External Switchover Mode is disabled #define _IESO_ON 0xFFFF // Internal/External Switchover Mode is enabled #define _FCMEN_OFF 0xDFFF // Fail-Safe Clock Monitor is disabled #define _FCMEN_ON 0xFFFF // Fail-Safe Clock Monitor is enabled /////// CONFIG2 Options ////////////////////////////////////////////////// #define _WRT_ALL 0xFFFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control #define _WRT_HALF 0xFFFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control #define _WRT_BOOT 0xFFFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control #define _WRT_OFF 0xFFFF // Write protection off #define _STVREN_OFF 0xFDFF // Stack Overflow or Underflow will not cause a Reset #define _STVREN_ON 0xFFFF // Stack Overflow or Underflow will cause a Reset #define _BORV_HI 0xFBFF // Brown-out Reset Voltage (VBOR) set to 2.7V #define _BORV_LO 0xFFFF // Brown-out Reset Voltage (VBOR) set to 2.4V #define _LPBOR_ON 0xF7FF // Low-Power BOR is enabled #define _LPBOR_OFF 0xFFFF // Low-Power BOR is disabled #define _LVP_OFF 0xDFFF // High-voltage on MCLR/VPP must be used for programming #define _LVP_ON 0xFFFF // Low-voltage programming enabled /////// DEVID Equates ////////////////////////////////////////////////// #define _DEVID1 0x8006 /////// IDLOC Equates ////////////////////////////////////////////////// #define _IDLOC0 0x8000 #define _IDLOC1 0x8001 #define _IDLOC2 0x8002 #define _IDLOC3 0x8003 volatile char indf0 @INDF0; volatile char indf1 @INDF1; volatile char pcl @PCL; volatile char status @STATUS; volatile char fsr0 @FSR0; volatile char fsr0l @FSR0L; volatile char fsr0h @FSR0H; volatile char fsr1 @FSR1; volatile char fsr1l @FSR1L; volatile char fsr1h @FSR1H; volatile char bsr @BSR; volatile char wreg @WREG; volatile char pclath @PCLATH; volatile char intcon @INTCON; volatile char porta @PORTA; volatile char portb @PORTB; volatile char portc @PORTC; volatile char pir1 @PIR1; volatile char pir2 @PIR2; volatile char pir3 @PIR3; volatile char tmr0 @TMR0; volatile char tmr1 @TMR1; volatile char tmr1l @TMR1L; volatile char tmr1h @TMR1H; volatile char t1con @T1CON; volatile char t1gcon @T1GCON; volatile char tmr2 @TMR2; volatile char pr2 @PR2; volatile char t2con @T2CON; volatile char trisa @TRISA; volatile char trisb @TRISB; volatile char trisc @TRISC; volatile char pie1 @PIE1; volatile char pie2 @PIE2; volatile char pie3 @PIE3; volatile char option_reg @OPTION_REG; volatile char pcon @PCON; volatile char wdtcon @WDTCON; volatile char osccon @OSCCON; volatile char oscstat @OSCSTAT; volatile char adres @ADRES; volatile char adresl @ADRESL; volatile char adresh @ADRESH; volatile char adcon0 @ADCON0; volatile char adcon1 @ADCON1; volatile char adcon2 @ADCON2; volatile char lata @LATA; volatile char latb @LATB; volatile char latc @LATC; volatile char cm1con0 @CM1CON0; volatile char cm1con1 @CM1CON1; volatile char cm2con0 @CM2CON0; volatile char cm2con1 @CM2CON1; volatile char cmout @CMOUT; volatile char borcon @BORCON; volatile char fvrcon @FVRCON; volatile char daccon0 @DACCON0; volatile char daccon1 @DACCON1; volatile char apfcon @APFCON; volatile char ansela @ANSELA; volatile char anselb @ANSELB; volatile char anselc @ANSELC; volatile char pmadr @PMADR; volatile char pmadrl @PMADRL; volatile char pmadrh @PMADRH; volatile char pmdat @PMDAT; volatile char pmdatl @PMDATL; volatile char pmdath @PMDATH; volatile char pmcon1 @PMCON1; volatile char pmcon2 @PMCON2; volatile char vregcon @VREGCON; volatile char rcreg @RCREG; volatile char txreg @TXREG; volatile char spbrgl @SPBRGL; volatile char spbrgh @SPBRGH; volatile char rcsta @RCSTA; volatile char txsta @TXSTA; volatile char baudcon @BAUDCON; volatile char wpua @WPUA; volatile char wpub @WPUB; volatile char ssp1buf @SSP1BUF; volatile char sspbuf @SSPBUF; volatile char ssp1add @SSP1ADD; volatile char sspadd @SSPADD; volatile char ssp1msk @SSP1MSK; volatile char sspmsk @SSPMSK; volatile char ssp1stat @SSP1STAT; volatile char sspstat @SSPSTAT; volatile char ssp1con1 @SSP1CON1; volatile char sspcon @SSPCON; volatile char sspcon1 @SSPCON1; volatile char ssp1con2 @SSP1CON2; volatile char sspcon2 @SSPCON2; volatile char ssp1con3 @SSP1CON3; volatile char sspcon3 @SSPCON3; volatile char iocap @IOCAP; volatile char iocan @IOCAN; volatile char iocaf @IOCAF; volatile char iocbp @IOCBP; volatile char iocbn @IOCBN; volatile char iocbf @IOCBF; volatile char nco1acc @NCO1ACC; volatile char nco1accl @NCO1ACCL; volatile char nco1acch @NCO1ACCH; volatile char nco1accu @NCO1ACCU; volatile char nco1inc @NCO1INC; volatile char nco1incl @NCO1INCL; volatile char nco1inch @NCO1INCH; volatile char nco1incu @NCO1INCU; volatile char nco1con @NCO1CON; volatile char nco1clk @NCO1CLK; volatile char pwm1dcl @PWM1DCL; volatile char pwm1dch @PWM1DCH; volatile char pwm1con @PWM1CON; volatile char pwm1con0 @PWM1CON0; volatile char pwm2dcl @PWM2DCL; volatile char pwm2dch @PWM2DCH; volatile char pwm2con @PWM2CON; volatile char pwm2con0 @PWM2CON0; volatile char pwm3dcl @PWM3DCL; volatile char pwm3dch @PWM3DCH; volatile char pwm3con @PWM3CON; volatile char pwm3con0 @PWM3CON0; volatile char pwm4dcl @PWM4DCL; volatile char pwm4dch @PWM4DCH; volatile char pwm4con @PWM4CON; volatile char pwm4con0 @PWM4CON0; volatile char cwg1dbr @CWG1DBR; volatile char cwg1dbf @CWG1DBF; volatile char cwg1con0 @CWG1CON0; volatile char cwg1con1 @CWG1CON1; volatile char cwg1con2 @CWG1CON2; volatile char clcdata @CLCDATA; volatile char clc1con @CLC1CON; volatile char clc1pol @CLC1POL; volatile char clc1sel0 @CLC1SEL0; volatile char clc1sel1 @CLC1SEL1; volatile char clc1gls0 @CLC1GLS0; volatile char clc1gls1 @CLC1GLS1; volatile char clc1gls2 @CLC1GLS2; volatile char clc1gls3 @CLC1GLS3; volatile char clc2con @CLC2CON; volatile char clc2pol @CLC2POL; volatile char clc2sel0 @CLC2SEL0; volatile char clc2sel1 @CLC2SEL1; volatile char clc2gls0 @CLC2GLS0; volatile char clc2gls1 @CLC2GLS1; volatile char clc2gls2 @CLC2GLS2; volatile char clc2gls3 @CLC2GLS3; volatile char clc3con @CLC3CON; volatile char clc3pol @CLC3POL; volatile char clc3sel0 @CLC3SEL0; volatile char clc3sel1 @CLC3SEL1; volatile char clc3gls0 @CLC3GLS0; volatile char clc3gls1 @CLC3GLS1; volatile char clc3gls2 @CLC3GLS2; volatile char clc3gls3 @CLC3GLS3; volatile char clc4con @CLC4CON; volatile char clc4pol @CLC4POL; volatile char clc4sel0 @CLC4SEL0; volatile char clc4sel1 @CLC4SEL1; volatile char clc4gls0 @CLC4GLS0; volatile char clc4gls1 @CLC4GLS1; volatile char clc4gls2 @CLC4GLS2; volatile char clc4gls3 @CLC4GLS3; volatile char icdio @ICDIO; volatile char icdcon0 @ICDCON0; volatile char icdstat @ICDSTAT; volatile char devsel @DEVSEL; volatile char icdinstl @ICDINSTL; volatile char icdinsth @ICDINSTH; volatile char icdbk0con @ICDBK0CON; volatile char icdbk0l @ICDBK0L; volatile char icdbk0h @ICDBK0H; volatile char bsricdshad @BSRICDSHAD; volatile char status_shad @STATUS_SHAD; volatile char wreg_shad @WREG_SHAD; volatile char bsr_shad @BSR_SHAD; volatile char pclath_shad @PCLATH_SHAD; volatile char fsr0l_shad @FSR0L_SHAD; volatile char fsr0h_shad @FSR0H_SHAD; volatile char fsr1l_shad @FSR1L_SHAD; volatile char fsr1h_shad @FSR1H_SHAD; volatile char stkptr @STKPTR; volatile char tosl @TOSL; volatile char tosh @TOSH; #endif // _PIC16F1508_H_