/********************************************************************* * Flowcode CAL SPI File * * File: PIC_CAL_SPI.c * * (c) 2011 Matrix Multimedia Ltd. * http://www.matrixmultimedia.com * * Software License Agreement * * The software supplied herewith by Matrix Multimedia Ltd (the * “Company”) for its Flowcode graphical programming language is * intended and supplied to you, the Company’s customer, for use * solely and exclusively on the Company's products. The software * is owned by the Company, and is protected under applicable * copyright laws. All rights are reserved. Any use in violation * of the foregoing restrictions may subject the user to criminal * sanctions under applicable laws, as well as to civil liability * for the breach of the terms and conditions of this licence. * * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * * Changelog: * * date | by | description * -------+----+----------------------------------------------------- * 010911 | BR | Created * 150911 | BR | Updated variables with typedef alternatives * 011211 | BR | Converted to new dynamic defines mechanism * 200712 | BR | Added new macro to configure prescaler on the fly * 080812 | ST | Fixed undefines typo * 090812 | ST | Fixed initial clock polarity setting * 090812 | ST | Added comments to explain the BMODE settings and Master_Byte function * 140912 | BR | Chaned prescaler function to tie in with the FAT component * 171212 | BR | Bug fix - added undefine to allow more then 1 instance of the SPI CAL * 090413 | LM | Port definitions from SPI CAL component * 210613 | BR | Bug fix defines mod for HW SPI Prescaler - also related mods to init * 030713 | LM | Standard API calls * 250713 | LM | Upper case register name typo fix * 260416 | LM | Updates for XC8 */ //When using hardware SPI channels override port and pin conns with FCD conn definitions //Only overwrite CS pin defines when using SPI in slave mode on a hardware channel //Also sort out postscale and prescale options for hardware channels //Channel Abstraction #define MX_SPI_REF_X CAL_APPEND(MX_SPI_REF, MX_SPI_NUM) #define MX_SPI_CHANNEL_X CAL_APPEND(MX_SPI_CHANNEL_, MX_SPI_NUM) #define MX_SPI_MOSI_PIN_X CAL_APPEND(MX_SPI_MOSI_PIN_, MX_SPI_NUM) #define MX_SPI_MOSI_PORT_X CAL_APPEND(MX_SPI_MOSI_PORT_, MX_SPI_NUM) #define MX_SPI_MOSI_TRIS_X CAL_APPEND(MX_SPI_MOSI_TRIS_, MX_SPI_NUM) #define MX_SPI_MISO_PIN_X CAL_APPEND(MX_SPI_MISO_PIN_, MX_SPI_NUM) #define MX_SPI_MISO_PORT_X CAL_APPEND(MX_SPI_MISO_PORT_, MX_SPI_NUM) #define MX_SPI_MISO_TRIS_X CAL_APPEND(MX_SPI_MISO_TRIS_, MX_SPI_NUM) #define MX_SPI_SCK_PIN_X CAL_APPEND(MX_SPI_SCK_PIN_, MX_SPI_NUM) #define MX_SPI_SCK_PORT_X CAL_APPEND(MX_SPI_SCK_PORT_, MX_SPI_NUM) #define MX_SPI_SCK_TRIS_X CAL_APPEND(MX_SPI_SCK_TRIS_, MX_SPI_NUM) #define MX_SPI_CS_PIN_X CAL_APPEND(MX_SPI_CS_PIN_, MX_SPI_NUM) #define MX_SPI_CS_PORT_X CAL_APPEND(MX_SPI_CS_PORT_, MX_SPI_NUM) #define MX_SPI_CS_TRIS_X CAL_APPEND(MX_SPI_CS_TRIS_, MX_SPI_NUM) #define MX_SPI_BMODE_X CAL_APPEND(MX_SPI_BMODE_, MX_SPI_NUM) #define MX_SPI_PR_SCALE_X CAL_APPEND(MX_SPI_PR_SCALE_, MX_SPI_NUM) #define MX_SPI_PO_SCALE_X CAL_APPEND(MX_SPI_PO_SCALE_, MX_SPI_NUM) #define MX_SPI_INT_X CAL_APPEND(MX_SPI_INT_, MX_SPI_NUM) #define MX_SPI_REMAPPABLE_X CAL_APPEND(MX_SPI_REMAPPABLE_, MX_SPI_NUM) #define MX_SPI_MISO_RPINR_X CAL_APPEND(MX_SPI_MISO_RPINR_, MX_SPI_NUM) #define MX_SPI_MISO_RP_X CAL_APPEND(MX_SPI_MISO_RP_, MX_SPI_NUM) #define MX_SPI_MOSI_RPOR_X CAL_APPEND(MX_SPI_MOSI_RPOR_, MX_SPI_NUM) #define MX_SPI_MOSI_SDO_X CAL_APPEND(MX_SPI_MOSI_SDO_, MX_SPI_NUM) #define MX_SPI_CLK_RPOR_X CAL_APPEND(MX_SPI_CLK_RPOR_, MX_SPI_NUM) #define MX_SPI_CLK_SCK_X CAL_APPEND(MX_SPI_CLK_SCK_, MX_SPI_NUM) #define MX_PRESCALE_VAR_X CAL_APPEND(prescale_, MX_SPI_NUM) MX_UINT8 MX_PRESCALE_VAR_X = (MX_SPI_PR_SCALE_X / 4) - 1; //Function Prototypes CALFUNCTION(void, FC_CAL_SPI_Master_Init_, (void)); CALFUNCTION(void, FC_CAL_SPI_Master_Uninit_, (void)); CALFUNCTION(MX_UINT8, FC_CAL_SPI_Master_Byte_, (MX_UINT8 DataOut)); CALFUNCTION(void, FC_CAL_SPI_SetPrescaler_, (MX_UINT8 Prescaler)); CALFUNCTION(void, FC_CAL_SPI_Slave_Init_, (void)); CALFUNCTION(void, FC_CAL_SPI_Slave_Uninit_, (void)); CALFUNCTION(void, FC_CAL_SPI_Slave_SetTxData_, (MX_UINT8 Data)); CALFUNCTION(MX_UINT8, FC_CAL_SPI_Slave_GetRxData_, (void)); #if (MX_SPI_CHANNEL_X > 0) #if (MX_SPI_PR_SCALE_X == 4) #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0 #endif #if (MX_SPI_PR_SCALE_X == 16) #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 1 #endif #if (MX_SPI_PR_SCALE_X == 64) #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 2 #endif #endif //Bus Mode - Bit0=CKP=CPOL, Bit1=CKE=!CPHA, Bit2=CSMP //CKP=CPOL - Clock Polarity - Idle State of the clock 0=0, 1=1 //CKE=CPHA - Clock Phase - Clock Edge 0=leading edge, 1=trailing edge //CSMP - Input Data Bit Sample Phase //CRAT - SPI Clock Rate 0=1/4, 1=1/16, 2=1/64 // There are 4 SPI clock modes as follows: // // SPI Mode | CKP (CPOL) | CKE (CPHA) | BMODE | Explanation //----------+------------+--------------------+------------------------------------------------ // 1 (0,1) | 0 (0) | 0 (1) | xx00 | idle low; data out on falling/trailing edge // 3 (1,1) | 1 (1) | 0 (1) | xx01 | idle high; data out on rising/trailing edge // 0 (0,0) | 0 (0) | 1 (0) | xx10 | idle low; data out on rising/leading edge // 2 (1,0) | 1 (1) | 1 (0) | xx11 | idle high; data out on falling/leading edge //----------+------------+--------------------------------------------------------------------- // // So: // BMODE & 0x01 = CKP = CPOL // BMODE & 0x02 = CKE = !CPHA //Ensure registers are defined correctly #ifndef SSPCON_SSPM0_POSN #ifdef _SSPCON1_SSPM0_POSN #define SSPCON SSPCON1 #define SSPCONbits SSPCON1bits #else #ifdef _SSP1CON1_SSPM0_POSN #define SSPCON SSP1CON1 #define SSPCONbits SSP1CON1bits #endif #endif #endif #ifndef _SSP2CON_CKP_POSN #ifdef _SSP2CON1_CKP_POSN #define SSP2CON SSP2CON1 #endif #endif #ifndef _SSPBUF_SSPBUF_POSN #ifdef _SSP1BUF_SSPBUF_POSN #define SSPBUF SSP1BUF #endif #endif #ifndef _SSPSTAT_BF_POSN #ifdef _SSP1STAT_BF_POSN #define SSPSTAT SSP1STAT #endif #endif CALFUNCTION(void, FC_CAL_SPI_Master_Init_, (void)) { FC_CAL_Bit_High_DDR (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_TRIS_X, MX_SPI_MOSI_PIN_X); // MOSI pin is default high FC_CAL_Bit_In_DDR (MX_SPI_MISO_PORT_X, MX_SPI_MISO_TRIS_X, MX_SPI_MISO_PIN_X); // MISO pin is a input #if (MX_SPI_BMODE_X & 0x01) FC_CAL_Bit_High_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); // Clock pin is default high #else FC_CAL_Bit_Low_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); // Clock pin is default low #endif #if (MX_SPI_REMAPPABLE_X == 1) MX_SPI_MISO_RPINR_X = MX_SPI_MISO_RP_X; MX_SPI_MOSI_RPOR_X = MX_SPI_MOSI_SDO_X; MX_SPI_CLK_RPOR_X = MX_SPI_CLK_SCK_X; //For some reason the SPI clock is not included in the remap on PIC32 #endif #if (MX_SPI_CHANNEL_X == 1) SSPCON = MX_SPI_PR_SCALE_X & 0x03; //Assign Clock Prescaler ld_bit(SSPCON, CKP, (MX_SPI_BMODE_X & 0x01)); //Assign Clock Polarity ld_bit(SSPSTAT, CKE, (MX_SPI_BMODE_X & 0x02)); //Assign Clock Phase ld_bit(SSPSTAT, SMP, (MX_SPI_BMODE_X & 0x04)); //Assign Input Data Phase st_bit(SSPCON, SSPEN); //Activate SPI Peripheral #endif #if (MX_SPI_CHANNEL_X == 2) SSP2CON = MX_SPI_PR_SCALE_X & 0x03; //Assign Clock Prescaler ld_bit(SSP2CON, CKP, (MX_SPI_BMODE_X & 0x01)); //Assign Clock Polarity ld_bit(SSP2STAT, CKE, (MX_SPI_BMODE_X & 0x02)); //Assign Clock Phase ld_bit(SSP2STAT, SMP, (MX_SPI_BMODE_X & 0x04)); //Assign Input Data Phase st_bit(SSP2CON, SSPEN); //Activate SPI Peripheral #endif } CALFUNCTION(void, FC_CAL_SPI_Master_Uninit_, (void)) { #if (MX_SPI_CHANNEL_X == 1) SSPCON = 0; #endif #if (MX_SPI_CHANNEL_X == 2) SSP2CON = 0; #endif //Reset Pins to Inputs FC_CAL_Bit_In_DDR (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_TRIS_X, MX_SPI_MOSI_PIN_X); FC_CAL_Bit_In_DDR (MX_SPI_MISO_PORT_X, MX_SPI_MISO_TRIS_X, MX_SPI_MISO_PIN_X); FC_CAL_Bit_In_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); } CALFUNCTION(MX_UINT8, FC_CAL_SPI_Master_Byte_, (MX_UINT8 DataOut)) { MX_UINT8 retVal = 0; #if (MX_SPI_CHANNEL_X == 0) MX_UINT8 idx, i; for (idx = 0; idx < 8; idx++) { retVal = retVal << 1; //If mode 1 or 3, switch the clock #if ((MX_SPI_BMODE_X & 0x02) == 0x00) //CKE = 0; (mode 1 or 3) Set SCK active before data #if ((MX_SPI_BMODE_X & 0x01) == 0x00) FC_CAL_Bit_High(MX_SPI_SCK_PORT_X, MX_SPI_SCK_PIN_X); //CKP = 0; (mode 1) #else FC_CAL_Bit_Low(MX_SPI_SCK_PORT_X, MX_SPI_SCK_PIN_X); //CKP = 1; (mode 3) #endif #endif //Data setup if (DataOut & 0x80) //Test Data bit FC_CAL_Bit_High(MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_PIN_X); //Set SDO bit else FC_CAL_Bit_Low (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_PIN_X); //Clear SDO bit //Clock delay for (i=0; i