// Version 1.45 // Generated 16/11/2017 GMT /* * Copyright © 2017, Microchip Technology Inc. and its subsidiaries ("Microchip") * All rights reserved. * * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). * * Redistribution and use in source and binary forms, with or without modification, are * permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this list of * conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, this list * of conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * * 3. Microchip's name may not be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _PIC18F26K80_H_ #define _PIC18F26K80_H_ /* * C Header file for the Microchip PIC Microcontroller * PIC18F26K80 */ #ifndef __XC8 #warning Header file pic18f26k80.h included directly. Use #include instead. #endif /* * Register Definitions */ // Register: RXERRCNT #define RXERRCNT RXERRCNT extern volatile unsigned char RXERRCNT @ 0xE41; #ifndef _LIB_BUILD asm("RXERRCNT equ 0E41h"); #endif // bitfield definitions typedef union { struct { unsigned REC :8; }; struct { unsigned REC0 :1; unsigned REC1 :1; unsigned REC2 :1; unsigned REC3 :1; unsigned REC4 :1; unsigned REC5 :1; unsigned REC6 :1; unsigned REC7 :1; }; } RXERRCNTbits_t; extern volatile RXERRCNTbits_t RXERRCNTbits @ 0xE41; // bitfield macros #define _RXERRCNT_REC_POSN 0x0 #define _RXERRCNT_REC_POSITION 0x0 #define _RXERRCNT_REC_SIZE 0x8 #define _RXERRCNT_REC_LENGTH 0x8 #define _RXERRCNT_REC_MASK 0xFF #define _RXERRCNT_REC0_POSN 0x0 #define _RXERRCNT_REC0_POSITION 0x0 #define _RXERRCNT_REC0_SIZE 0x1 #define _RXERRCNT_REC0_LENGTH 0x1 #define _RXERRCNT_REC0_MASK 0x1 #define _RXERRCNT_REC1_POSN 0x1 #define _RXERRCNT_REC1_POSITION 0x1 #define _RXERRCNT_REC1_SIZE 0x1 #define _RXERRCNT_REC1_LENGTH 0x1 #define _RXERRCNT_REC1_MASK 0x2 #define _RXERRCNT_REC2_POSN 0x2 #define _RXERRCNT_REC2_POSITION 0x2 #define _RXERRCNT_REC2_SIZE 0x1 #define _RXERRCNT_REC2_LENGTH 0x1 #define _RXERRCNT_REC2_MASK 0x4 #define _RXERRCNT_REC3_POSN 0x3 #define _RXERRCNT_REC3_POSITION 0x3 #define _RXERRCNT_REC3_SIZE 0x1 #define _RXERRCNT_REC3_LENGTH 0x1 #define _RXERRCNT_REC3_MASK 0x8 #define _RXERRCNT_REC4_POSN 0x4 #define _RXERRCNT_REC4_POSITION 0x4 #define _RXERRCNT_REC4_SIZE 0x1 #define _RXERRCNT_REC4_LENGTH 0x1 #define _RXERRCNT_REC4_MASK 0x10 #define _RXERRCNT_REC5_POSN 0x5 #define _RXERRCNT_REC5_POSITION 0x5 #define _RXERRCNT_REC5_SIZE 0x1 #define _RXERRCNT_REC5_LENGTH 0x1 #define _RXERRCNT_REC5_MASK 0x20 #define _RXERRCNT_REC6_POSN 0x6 #define _RXERRCNT_REC6_POSITION 0x6 #define _RXERRCNT_REC6_SIZE 0x1 #define _RXERRCNT_REC6_LENGTH 0x1 #define _RXERRCNT_REC6_MASK 0x40 #define _RXERRCNT_REC7_POSN 0x7 #define _RXERRCNT_REC7_POSITION 0x7 #define _RXERRCNT_REC7_SIZE 0x1 #define _RXERRCNT_REC7_LENGTH 0x1 #define _RXERRCNT_REC7_MASK 0x80 // Register: TXERRCNT #define TXERRCNT TXERRCNT extern volatile unsigned char TXERRCNT @ 0xE42; #ifndef _LIB_BUILD asm("TXERRCNT equ 0E42h"); #endif // bitfield definitions typedef union { struct { unsigned TEC :8; }; struct { unsigned TEC0 :1; unsigned TEC1 :1; unsigned TEC2 :1; unsigned TEC3 :1; unsigned TEC4 :1; unsigned TEC5 :1; unsigned TEC6 :1; unsigned TEC7 :1; }; } TXERRCNTbits_t; extern volatile TXERRCNTbits_t TXERRCNTbits @ 0xE42; // bitfield macros #define _TXERRCNT_TEC_POSN 0x0 #define _TXERRCNT_TEC_POSITION 0x0 #define _TXERRCNT_TEC_SIZE 0x8 #define _TXERRCNT_TEC_LENGTH 0x8 #define _TXERRCNT_TEC_MASK 0xFF #define _TXERRCNT_TEC0_POSN 0x0 #define _TXERRCNT_TEC0_POSITION 0x0 #define _TXERRCNT_TEC0_SIZE 0x1 #define _TXERRCNT_TEC0_LENGTH 0x1 #define _TXERRCNT_TEC0_MASK 0x1 #define _TXERRCNT_TEC1_POSN 0x1 #define _TXERRCNT_TEC1_POSITION 0x1 #define _TXERRCNT_TEC1_SIZE 0x1 #define _TXERRCNT_TEC1_LENGTH 0x1 #define _TXERRCNT_TEC1_MASK 0x2 #define _TXERRCNT_TEC2_POSN 0x2 #define _TXERRCNT_TEC2_POSITION 0x2 #define _TXERRCNT_TEC2_SIZE 0x1 #define _TXERRCNT_TEC2_LENGTH 0x1 #define _TXERRCNT_TEC2_MASK 0x4 #define _TXERRCNT_TEC3_POSN 0x3 #define _TXERRCNT_TEC3_POSITION 0x3 #define _TXERRCNT_TEC3_SIZE 0x1 #define _TXERRCNT_TEC3_LENGTH 0x1 #define _TXERRCNT_TEC3_MASK 0x8 #define _TXERRCNT_TEC4_POSN 0x4 #define _TXERRCNT_TEC4_POSITION 0x4 #define _TXERRCNT_TEC4_SIZE 0x1 #define _TXERRCNT_TEC4_LENGTH 0x1 #define _TXERRCNT_TEC4_MASK 0x10 #define _TXERRCNT_TEC5_POSN 0x5 #define _TXERRCNT_TEC5_POSITION 0x5 #define _TXERRCNT_TEC5_SIZE 0x1 #define _TXERRCNT_TEC5_LENGTH 0x1 #define _TXERRCNT_TEC5_MASK 0x20 #define _TXERRCNT_TEC6_POSN 0x6 #define _TXERRCNT_TEC6_POSITION 0x6 #define _TXERRCNT_TEC6_SIZE 0x1 #define _TXERRCNT_TEC6_LENGTH 0x1 #define _TXERRCNT_TEC6_MASK 0x40 #define _TXERRCNT_TEC7_POSN 0x7 #define _TXERRCNT_TEC7_POSITION 0x7 #define _TXERRCNT_TEC7_SIZE 0x1 #define _TXERRCNT_TEC7_LENGTH 0x1 #define _TXERRCNT_TEC7_MASK 0x80 // Register: BRGCON1 #define BRGCON1 BRGCON1 extern volatile unsigned char BRGCON1 @ 0xE43; #ifndef _LIB_BUILD asm("BRGCON1 equ 0E43h"); #endif // bitfield definitions typedef union { struct { unsigned BRP :6; unsigned SJW :2; }; struct { unsigned BRP0 :1; unsigned BRP1 :1; unsigned BRP2 :1; unsigned BRP3 :1; unsigned BRP4 :1; unsigned BRP5 :1; unsigned SJW0 :1; unsigned SJW1 :1; }; } BRGCON1bits_t; extern volatile BRGCON1bits_t BRGCON1bits @ 0xE43; // bitfield macros #define _BRGCON1_BRP_POSN 0x0 #define _BRGCON1_BRP_POSITION 0x0 #define _BRGCON1_BRP_SIZE 0x6 #define _BRGCON1_BRP_LENGTH 0x6 #define _BRGCON1_BRP_MASK 0x3F #define _BRGCON1_SJW_POSN 0x6 #define _BRGCON1_SJW_POSITION 0x6 #define _BRGCON1_SJW_SIZE 0x2 #define _BRGCON1_SJW_LENGTH 0x2 #define _BRGCON1_SJW_MASK 0xC0 #define _BRGCON1_BRP0_POSN 0x0 #define _BRGCON1_BRP0_POSITION 0x0 #define _BRGCON1_BRP0_SIZE 0x1 #define _BRGCON1_BRP0_LENGTH 0x1 #define _BRGCON1_BRP0_MASK 0x1 #define _BRGCON1_BRP1_POSN 0x1 #define _BRGCON1_BRP1_POSITION 0x1 #define _BRGCON1_BRP1_SIZE 0x1 #define _BRGCON1_BRP1_LENGTH 0x1 #define _BRGCON1_BRP1_MASK 0x2 #define _BRGCON1_BRP2_POSN 0x2 #define _BRGCON1_BRP2_POSITION 0x2 #define _BRGCON1_BRP2_SIZE 0x1 #define _BRGCON1_BRP2_LENGTH 0x1 #define _BRGCON1_BRP2_MASK 0x4 #define _BRGCON1_BRP3_POSN 0x3 #define _BRGCON1_BRP3_POSITION 0x3 #define _BRGCON1_BRP3_SIZE 0x1 #define _BRGCON1_BRP3_LENGTH 0x1 #define _BRGCON1_BRP3_MASK 0x8 #define _BRGCON1_BRP4_POSN 0x4 #define _BRGCON1_BRP4_POSITION 0x4 #define _BRGCON1_BRP4_SIZE 0x1 #define _BRGCON1_BRP4_LENGTH 0x1 #define _BRGCON1_BRP4_MASK 0x10 #define _BRGCON1_BRP5_POSN 0x5 #define _BRGCON1_BRP5_POSITION 0x5 #define _BRGCON1_BRP5_SIZE 0x1 #define _BRGCON1_BRP5_LENGTH 0x1 #define _BRGCON1_BRP5_MASK 0x20 #define _BRGCON1_SJW0_POSN 0x6 #define _BRGCON1_SJW0_POSITION 0x6 #define _BRGCON1_SJW0_SIZE 0x1 #define _BRGCON1_SJW0_LENGTH 0x1 #define _BRGCON1_SJW0_MASK 0x40 #define _BRGCON1_SJW1_POSN 0x7 #define _BRGCON1_SJW1_POSITION 0x7 #define _BRGCON1_SJW1_SIZE 0x1 #define _BRGCON1_SJW1_LENGTH 0x1 #define _BRGCON1_SJW1_MASK 0x80 // Register: BRGCON2 #define BRGCON2 BRGCON2 extern volatile unsigned char BRGCON2 @ 0xE44; #ifndef _LIB_BUILD asm("BRGCON2 equ 0E44h"); #endif // bitfield definitions typedef union { struct { unsigned PRSEG :3; unsigned SEG1PH :3; unsigned SAM :1; unsigned SEG2PHTS :1; }; struct { unsigned PRSEG0 :1; unsigned PRSEG1 :1; unsigned PRSEG2 :1; unsigned SEG1PH0 :1; unsigned SEG1PH1 :1; unsigned SEG1PH2 :1; }; struct { unsigned :7; unsigned SEG2PHT :1; }; } BRGCON2bits_t; extern volatile BRGCON2bits_t BRGCON2bits @ 0xE44; // bitfield macros #define _BRGCON2_PRSEG_POSN 0x0 #define _BRGCON2_PRSEG_POSITION 0x0 #define _BRGCON2_PRSEG_SIZE 0x3 #define _BRGCON2_PRSEG_LENGTH 0x3 #define _BRGCON2_PRSEG_MASK 0x7 #define _BRGCON2_SEG1PH_POSN 0x3 #define _BRGCON2_SEG1PH_POSITION 0x3 #define _BRGCON2_SEG1PH_SIZE 0x3 #define _BRGCON2_SEG1PH_LENGTH 0x3 #define _BRGCON2_SEG1PH_MASK 0x38 #define _BRGCON2_SAM_POSN 0x6 #define _BRGCON2_SAM_POSITION 0x6 #define _BRGCON2_SAM_SIZE 0x1 #define _BRGCON2_SAM_LENGTH 0x1 #define _BRGCON2_SAM_MASK 0x40 #define _BRGCON2_SEG2PHTS_POSN 0x7 #define _BRGCON2_SEG2PHTS_POSITION 0x7 #define _BRGCON2_SEG2PHTS_SIZE 0x1 #define _BRGCON2_SEG2PHTS_LENGTH 0x1 #define _BRGCON2_SEG2PHTS_MASK 0x80 #define _BRGCON2_PRSEG0_POSN 0x0 #define _BRGCON2_PRSEG0_POSITION 0x0 #define _BRGCON2_PRSEG0_SIZE 0x1 #define _BRGCON2_PRSEG0_LENGTH 0x1 #define _BRGCON2_PRSEG0_MASK 0x1 #define _BRGCON2_PRSEG1_POSN 0x1 #define _BRGCON2_PRSEG1_POSITION 0x1 #define _BRGCON2_PRSEG1_SIZE 0x1 #define _BRGCON2_PRSEG1_LENGTH 0x1 #define _BRGCON2_PRSEG1_MASK 0x2 #define _BRGCON2_PRSEG2_POSN 0x2 #define _BRGCON2_PRSEG2_POSITION 0x2 #define _BRGCON2_PRSEG2_SIZE 0x1 #define _BRGCON2_PRSEG2_LENGTH 0x1 #define _BRGCON2_PRSEG2_MASK 0x4 #define _BRGCON2_SEG1PH0_POSN 0x3 #define _BRGCON2_SEG1PH0_POSITION 0x3 #define _BRGCON2_SEG1PH0_SIZE 0x1 #define _BRGCON2_SEG1PH0_LENGTH 0x1 #define _BRGCON2_SEG1PH0_MASK 0x8 #define _BRGCON2_SEG1PH1_POSN 0x4 #define _BRGCON2_SEG1PH1_POSITION 0x4 #define _BRGCON2_SEG1PH1_SIZE 0x1 #define _BRGCON2_SEG1PH1_LENGTH 0x1 #define _BRGCON2_SEG1PH1_MASK 0x10 #define _BRGCON2_SEG1PH2_POSN 0x5 #define _BRGCON2_SEG1PH2_POSITION 0x5 #define _BRGCON2_SEG1PH2_SIZE 0x1 #define _BRGCON2_SEG1PH2_LENGTH 0x1 #define _BRGCON2_SEG1PH2_MASK 0x20 #define _BRGCON2_SEG2PHT_POSN 0x7 #define _BRGCON2_SEG2PHT_POSITION 0x7 #define _BRGCON2_SEG2PHT_SIZE 0x1 #define _BRGCON2_SEG2PHT_LENGTH 0x1 #define _BRGCON2_SEG2PHT_MASK 0x80 // Register: BRGCON3 #define BRGCON3 BRGCON3 extern volatile unsigned char BRGCON3 @ 0xE45; #ifndef _LIB_BUILD asm("BRGCON3 equ 0E45h"); #endif // bitfield definitions typedef union { struct { unsigned SEG2PH :3; unsigned :3; unsigned WAKFIL :1; unsigned WAKDIS :1; }; struct { unsigned SEG2PH0 :1; unsigned SEG2PH1 :1; unsigned SEG2PH2 :1; }; } BRGCON3bits_t; extern volatile BRGCON3bits_t BRGCON3bits @ 0xE45; // bitfield macros #define _BRGCON3_SEG2PH_POSN 0x0 #define _BRGCON3_SEG2PH_POSITION 0x0 #define _BRGCON3_SEG2PH_SIZE 0x3 #define _BRGCON3_SEG2PH_LENGTH 0x3 #define _BRGCON3_SEG2PH_MASK 0x7 #define _BRGCON3_WAKFIL_POSN 0x6 #define _BRGCON3_WAKFIL_POSITION 0x6 #define _BRGCON3_WAKFIL_SIZE 0x1 #define _BRGCON3_WAKFIL_LENGTH 0x1 #define _BRGCON3_WAKFIL_MASK 0x40 #define _BRGCON3_WAKDIS_POSN 0x7 #define _BRGCON3_WAKDIS_POSITION 0x7 #define _BRGCON3_WAKDIS_SIZE 0x1 #define _BRGCON3_WAKDIS_LENGTH 0x1 #define _BRGCON3_WAKDIS_MASK 0x80 #define _BRGCON3_SEG2PH0_POSN 0x0 #define _BRGCON3_SEG2PH0_POSITION 0x0 #define _BRGCON3_SEG2PH0_SIZE 0x1 #define _BRGCON3_SEG2PH0_LENGTH 0x1 #define _BRGCON3_SEG2PH0_MASK 0x1 #define _BRGCON3_SEG2PH1_POSN 0x1 #define _BRGCON3_SEG2PH1_POSITION 0x1 #define _BRGCON3_SEG2PH1_SIZE 0x1 #define _BRGCON3_SEG2PH1_LENGTH 0x1 #define _BRGCON3_SEG2PH1_MASK 0x2 #define _BRGCON3_SEG2PH2_POSN 0x2 #define _BRGCON3_SEG2PH2_POSITION 0x2 #define _BRGCON3_SEG2PH2_SIZE 0x1 #define _BRGCON3_SEG2PH2_LENGTH 0x1 #define _BRGCON3_SEG2PH2_MASK 0x4 // Register: RXFCON0 #define RXFCON0 RXFCON0 extern volatile unsigned char RXFCON0 @ 0xE46; #ifndef _LIB_BUILD asm("RXFCON0 equ 0E46h"); #endif // bitfield definitions typedef union { struct { unsigned RXF0EN :1; unsigned RXF1EN :1; unsigned RXF2EN :1; unsigned RXF3EN :1; unsigned RXF4EN :1; unsigned RXF5EN :1; unsigned RXF6EN :1; unsigned RXF7EN :1; }; } RXFCON0bits_t; extern volatile RXFCON0bits_t RXFCON0bits @ 0xE46; // bitfield macros #define _RXFCON0_RXF0EN_POSN 0x0 #define _RXFCON0_RXF0EN_POSITION 0x0 #define _RXFCON0_RXF0EN_SIZE 0x1 #define _RXFCON0_RXF0EN_LENGTH 0x1 #define _RXFCON0_RXF0EN_MASK 0x1 #define _RXFCON0_RXF1EN_POSN 0x1 #define _RXFCON0_RXF1EN_POSITION 0x1 #define _RXFCON0_RXF1EN_SIZE 0x1 #define _RXFCON0_RXF1EN_LENGTH 0x1 #define _RXFCON0_RXF1EN_MASK 0x2 #define _RXFCON0_RXF2EN_POSN 0x2 #define _RXFCON0_RXF2EN_POSITION 0x2 #define _RXFCON0_RXF2EN_SIZE 0x1 #define _RXFCON0_RXF2EN_LENGTH 0x1 #define _RXFCON0_RXF2EN_MASK 0x4 #define _RXFCON0_RXF3EN_POSN 0x3 #define _RXFCON0_RXF3EN_POSITION 0x3 #define _RXFCON0_RXF3EN_SIZE 0x1 #define _RXFCON0_RXF3EN_LENGTH 0x1 #define _RXFCON0_RXF3EN_MASK 0x8 #define _RXFCON0_RXF4EN_POSN 0x4 #define _RXFCON0_RXF4EN_POSITION 0x4 #define _RXFCON0_RXF4EN_SIZE 0x1 #define _RXFCON0_RXF4EN_LENGTH 0x1 #define _RXFCON0_RXF4EN_MASK 0x10 #define _RXFCON0_RXF5EN_POSN 0x5 #define _RXFCON0_RXF5EN_POSITION 0x5 #define _RXFCON0_RXF5EN_SIZE 0x1 #define _RXFCON0_RXF5EN_LENGTH 0x1 #define _RXFCON0_RXF5EN_MASK 0x20 #define _RXFCON0_RXF6EN_POSN 0x6 #define _RXFCON0_RXF6EN_POSITION 0x6 #define _RXFCON0_RXF6EN_SIZE 0x1 #define _RXFCON0_RXF6EN_LENGTH 0x1 #define _RXFCON0_RXF6EN_MASK 0x40 #define _RXFCON0_RXF7EN_POSN 0x7 #define _RXFCON0_RXF7EN_POSITION 0x7 #define _RXFCON0_RXF7EN_SIZE 0x1 #define _RXFCON0_RXF7EN_LENGTH 0x1 #define _RXFCON0_RXF7EN_MASK 0x80 // Register: RXFCON1 #define RXFCON1 RXFCON1 extern volatile unsigned char RXFCON1 @ 0xE47; #ifndef _LIB_BUILD asm("RXFCON1 equ 0E47h"); #endif // bitfield definitions typedef union { struct { unsigned RXF8EN :1; unsigned RXF9EN :1; unsigned RXF10EN :1; unsigned RXF11EN :1; unsigned RXF12EN :1; unsigned RXF13EN :1; unsigned RXF14EN :1; unsigned RXF15EN :1; }; } RXFCON1bits_t; extern volatile RXFCON1bits_t RXFCON1bits @ 0xE47; // bitfield macros #define _RXFCON1_RXF8EN_POSN 0x0 #define _RXFCON1_RXF8EN_POSITION 0x0 #define _RXFCON1_RXF8EN_SIZE 0x1 #define _RXFCON1_RXF8EN_LENGTH 0x1 #define _RXFCON1_RXF8EN_MASK 0x1 #define _RXFCON1_RXF9EN_POSN 0x1 #define _RXFCON1_RXF9EN_POSITION 0x1 #define _RXFCON1_RXF9EN_SIZE 0x1 #define _RXFCON1_RXF9EN_LENGTH 0x1 #define _RXFCON1_RXF9EN_MASK 0x2 #define _RXFCON1_RXF10EN_POSN 0x2 #define _RXFCON1_RXF10EN_POSITION 0x2 #define _RXFCON1_RXF10EN_SIZE 0x1 #define _RXFCON1_RXF10EN_LENGTH 0x1 #define _RXFCON1_RXF10EN_MASK 0x4 #define _RXFCON1_RXF11EN_POSN 0x3 #define _RXFCON1_RXF11EN_POSITION 0x3 #define _RXFCON1_RXF11EN_SIZE 0x1 #define _RXFCON1_RXF11EN_LENGTH 0x1 #define _RXFCON1_RXF11EN_MASK 0x8 #define _RXFCON1_RXF12EN_POSN 0x4 #define _RXFCON1_RXF12EN_POSITION 0x4 #define _RXFCON1_RXF12EN_SIZE 0x1 #define _RXFCON1_RXF12EN_LENGTH 0x1 #define _RXFCON1_RXF12EN_MASK 0x10 #define _RXFCON1_RXF13EN_POSN 0x5 #define _RXFCON1_RXF13EN_POSITION 0x5 #define _RXFCON1_RXF13EN_SIZE 0x1 #define _RXFCON1_RXF13EN_LENGTH 0x1 #define _RXFCON1_RXF13EN_MASK 0x20 #define _RXFCON1_RXF14EN_POSN 0x6 #define _RXFCON1_RXF14EN_POSITION 0x6 #define _RXFCON1_RXF14EN_SIZE 0x1 #define _RXFCON1_RXF14EN_LENGTH 0x1 #define _RXFCON1_RXF14EN_MASK 0x40 #define _RXFCON1_RXF15EN_POSN 0x7 #define _RXFCON1_RXF15EN_POSITION 0x7 #define _RXFCON1_RXF15EN_SIZE 0x1 #define _RXFCON1_RXF15EN_LENGTH 0x1 #define _RXFCON1_RXF15EN_MASK 0x80 // Register: RXF6SIDH #define RXF6SIDH RXF6SIDH extern volatile unsigned char RXF6SIDH @ 0xE48; #ifndef _LIB_BUILD asm("RXF6SIDH equ 0E48h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF6SID3 :1; unsigned RXF6SID4 :1; unsigned RXF6SID5 :1; unsigned RXF6SID6 :1; unsigned RXF6SID7 :1; unsigned RXF6SID8 :1; unsigned RXF6SID9 :1; unsigned RXF6SID10 :1; }; } RXF6SIDHbits_t; extern volatile RXF6SIDHbits_t RXF6SIDHbits @ 0xE48; // bitfield macros #define _RXF6SIDH_SID_POSN 0x0 #define _RXF6SIDH_SID_POSITION 0x0 #define _RXF6SIDH_SID_SIZE 0x8 #define _RXF6SIDH_SID_LENGTH 0x8 #define _RXF6SIDH_SID_MASK 0xFF #define _RXF6SIDH_SID3_POSN 0x0 #define _RXF6SIDH_SID3_POSITION 0x0 #define _RXF6SIDH_SID3_SIZE 0x1 #define _RXF6SIDH_SID3_LENGTH 0x1 #define _RXF6SIDH_SID3_MASK 0x1 #define _RXF6SIDH_SID4_POSN 0x1 #define _RXF6SIDH_SID4_POSITION 0x1 #define _RXF6SIDH_SID4_SIZE 0x1 #define _RXF6SIDH_SID4_LENGTH 0x1 #define _RXF6SIDH_SID4_MASK 0x2 #define _RXF6SIDH_SID5_POSN 0x2 #define _RXF6SIDH_SID5_POSITION 0x2 #define _RXF6SIDH_SID5_SIZE 0x1 #define _RXF6SIDH_SID5_LENGTH 0x1 #define _RXF6SIDH_SID5_MASK 0x4 #define _RXF6SIDH_SID6_POSN 0x3 #define _RXF6SIDH_SID6_POSITION 0x3 #define _RXF6SIDH_SID6_SIZE 0x1 #define _RXF6SIDH_SID6_LENGTH 0x1 #define _RXF6SIDH_SID6_MASK 0x8 #define _RXF6SIDH_SID7_POSN 0x4 #define _RXF6SIDH_SID7_POSITION 0x4 #define _RXF6SIDH_SID7_SIZE 0x1 #define _RXF6SIDH_SID7_LENGTH 0x1 #define _RXF6SIDH_SID7_MASK 0x10 #define _RXF6SIDH_SID8_POSN 0x5 #define _RXF6SIDH_SID8_POSITION 0x5 #define _RXF6SIDH_SID8_SIZE 0x1 #define _RXF6SIDH_SID8_LENGTH 0x1 #define _RXF6SIDH_SID8_MASK 0x20 #define _RXF6SIDH_SID9_POSN 0x6 #define _RXF6SIDH_SID9_POSITION 0x6 #define _RXF6SIDH_SID9_SIZE 0x1 #define _RXF6SIDH_SID9_LENGTH 0x1 #define _RXF6SIDH_SID9_MASK 0x40 #define _RXF6SIDH_SID10_POSN 0x7 #define _RXF6SIDH_SID10_POSITION 0x7 #define _RXF6SIDH_SID10_SIZE 0x1 #define _RXF6SIDH_SID10_LENGTH 0x1 #define _RXF6SIDH_SID10_MASK 0x80 #define _RXF6SIDH_RXF6SID3_POSN 0x0 #define _RXF6SIDH_RXF6SID3_POSITION 0x0 #define _RXF6SIDH_RXF6SID3_SIZE 0x1 #define _RXF6SIDH_RXF6SID3_LENGTH 0x1 #define _RXF6SIDH_RXF6SID3_MASK 0x1 #define _RXF6SIDH_RXF6SID4_POSN 0x1 #define _RXF6SIDH_RXF6SID4_POSITION 0x1 #define _RXF6SIDH_RXF6SID4_SIZE 0x1 #define _RXF6SIDH_RXF6SID4_LENGTH 0x1 #define _RXF6SIDH_RXF6SID4_MASK 0x2 #define _RXF6SIDH_RXF6SID5_POSN 0x2 #define _RXF6SIDH_RXF6SID5_POSITION 0x2 #define _RXF6SIDH_RXF6SID5_SIZE 0x1 #define _RXF6SIDH_RXF6SID5_LENGTH 0x1 #define _RXF6SIDH_RXF6SID5_MASK 0x4 #define _RXF6SIDH_RXF6SID6_POSN 0x3 #define _RXF6SIDH_RXF6SID6_POSITION 0x3 #define _RXF6SIDH_RXF6SID6_SIZE 0x1 #define _RXF6SIDH_RXF6SID6_LENGTH 0x1 #define _RXF6SIDH_RXF6SID6_MASK 0x8 #define _RXF6SIDH_RXF6SID7_POSN 0x4 #define _RXF6SIDH_RXF6SID7_POSITION 0x4 #define _RXF6SIDH_RXF6SID7_SIZE 0x1 #define _RXF6SIDH_RXF6SID7_LENGTH 0x1 #define _RXF6SIDH_RXF6SID7_MASK 0x10 #define _RXF6SIDH_RXF6SID8_POSN 0x5 #define _RXF6SIDH_RXF6SID8_POSITION 0x5 #define _RXF6SIDH_RXF6SID8_SIZE 0x1 #define _RXF6SIDH_RXF6SID8_LENGTH 0x1 #define _RXF6SIDH_RXF6SID8_MASK 0x20 #define _RXF6SIDH_RXF6SID9_POSN 0x6 #define _RXF6SIDH_RXF6SID9_POSITION 0x6 #define _RXF6SIDH_RXF6SID9_SIZE 0x1 #define _RXF6SIDH_RXF6SID9_LENGTH 0x1 #define _RXF6SIDH_RXF6SID9_MASK 0x40 #define _RXF6SIDH_RXF6SID10_POSN 0x7 #define _RXF6SIDH_RXF6SID10_POSITION 0x7 #define _RXF6SIDH_RXF6SID10_SIZE 0x1 #define _RXF6SIDH_RXF6SID10_LENGTH 0x1 #define _RXF6SIDH_RXF6SID10_MASK 0x80 // Register: RXF6SIDL #define RXF6SIDL RXF6SIDL extern volatile unsigned char RXF6SIDL @ 0xE49; #ifndef _LIB_BUILD asm("RXF6SIDL equ 0E49h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF6EID16 :1; unsigned RXF6EID17 :1; unsigned :1; unsigned RXF6EXIDEN :1; unsigned :1; unsigned RXF6SID0 :1; unsigned RXF6SID1 :1; unsigned RXF6SID2 :1; }; } RXF6SIDLbits_t; extern volatile RXF6SIDLbits_t RXF6SIDLbits @ 0xE49; // bitfield macros #define _RXF6SIDL_EID_POSN 0x0 #define _RXF6SIDL_EID_POSITION 0x0 #define _RXF6SIDL_EID_SIZE 0x2 #define _RXF6SIDL_EID_LENGTH 0x2 #define _RXF6SIDL_EID_MASK 0x3 #define _RXF6SIDL_EXIDEN_POSN 0x3 #define _RXF6SIDL_EXIDEN_POSITION 0x3 #define _RXF6SIDL_EXIDEN_SIZE 0x1 #define _RXF6SIDL_EXIDEN_LENGTH 0x1 #define _RXF6SIDL_EXIDEN_MASK 0x8 #define _RXF6SIDL_SID_POSN 0x5 #define _RXF6SIDL_SID_POSITION 0x5 #define _RXF6SIDL_SID_SIZE 0x3 #define _RXF6SIDL_SID_LENGTH 0x3 #define _RXF6SIDL_SID_MASK 0xE0 #define _RXF6SIDL_EID16_POSN 0x0 #define _RXF6SIDL_EID16_POSITION 0x0 #define _RXF6SIDL_EID16_SIZE 0x1 #define _RXF6SIDL_EID16_LENGTH 0x1 #define _RXF6SIDL_EID16_MASK 0x1 #define _RXF6SIDL_EID17_POSN 0x1 #define _RXF6SIDL_EID17_POSITION 0x1 #define _RXF6SIDL_EID17_SIZE 0x1 #define _RXF6SIDL_EID17_LENGTH 0x1 #define _RXF6SIDL_EID17_MASK 0x2 #define _RXF6SIDL_SID0_POSN 0x5 #define _RXF6SIDL_SID0_POSITION 0x5 #define _RXF6SIDL_SID0_SIZE 0x1 #define _RXF6SIDL_SID0_LENGTH 0x1 #define _RXF6SIDL_SID0_MASK 0x20 #define _RXF6SIDL_SID1_POSN 0x6 #define _RXF6SIDL_SID1_POSITION 0x6 #define _RXF6SIDL_SID1_SIZE 0x1 #define _RXF6SIDL_SID1_LENGTH 0x1 #define _RXF6SIDL_SID1_MASK 0x40 #define _RXF6SIDL_SID2_POSN 0x7 #define _RXF6SIDL_SID2_POSITION 0x7 #define _RXF6SIDL_SID2_SIZE 0x1 #define _RXF6SIDL_SID2_LENGTH 0x1 #define _RXF6SIDL_SID2_MASK 0x80 #define _RXF6SIDL_RXF6EID16_POSN 0x0 #define _RXF6SIDL_RXF6EID16_POSITION 0x0 #define _RXF6SIDL_RXF6EID16_SIZE 0x1 #define _RXF6SIDL_RXF6EID16_LENGTH 0x1 #define _RXF6SIDL_RXF6EID16_MASK 0x1 #define _RXF6SIDL_RXF6EID17_POSN 0x1 #define _RXF6SIDL_RXF6EID17_POSITION 0x1 #define _RXF6SIDL_RXF6EID17_SIZE 0x1 #define _RXF6SIDL_RXF6EID17_LENGTH 0x1 #define _RXF6SIDL_RXF6EID17_MASK 0x2 #define _RXF6SIDL_RXF6EXIDEN_POSN 0x3 #define _RXF6SIDL_RXF6EXIDEN_POSITION 0x3 #define _RXF6SIDL_RXF6EXIDEN_SIZE 0x1 #define _RXF6SIDL_RXF6EXIDEN_LENGTH 0x1 #define _RXF6SIDL_RXF6EXIDEN_MASK 0x8 #define _RXF6SIDL_RXF6SID0_POSN 0x5 #define _RXF6SIDL_RXF6SID0_POSITION 0x5 #define _RXF6SIDL_RXF6SID0_SIZE 0x1 #define _RXF6SIDL_RXF6SID0_LENGTH 0x1 #define _RXF6SIDL_RXF6SID0_MASK 0x20 #define _RXF6SIDL_RXF6SID1_POSN 0x6 #define _RXF6SIDL_RXF6SID1_POSITION 0x6 #define _RXF6SIDL_RXF6SID1_SIZE 0x1 #define _RXF6SIDL_RXF6SID1_LENGTH 0x1 #define _RXF6SIDL_RXF6SID1_MASK 0x40 #define _RXF6SIDL_RXF6SID2_POSN 0x7 #define _RXF6SIDL_RXF6SID2_POSITION 0x7 #define _RXF6SIDL_RXF6SID2_SIZE 0x1 #define _RXF6SIDL_RXF6SID2_LENGTH 0x1 #define _RXF6SIDL_RXF6SID2_MASK 0x80 // Register: RXF6EIDH #define RXF6EIDH RXF6EIDH extern volatile unsigned char RXF6EIDH @ 0xE4A; #ifndef _LIB_BUILD asm("RXF6EIDH equ 0E4Ah"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF6EID8 :1; unsigned RXF6EID9 :1; unsigned RXF6EID10 :1; unsigned RXF6EID11 :1; unsigned RXF6EID12 :1; unsigned RXF6EID13 :1; unsigned RXF6EID14 :1; unsigned RXF6EID15 :1; }; } RXF6EIDHbits_t; extern volatile RXF6EIDHbits_t RXF6EIDHbits @ 0xE4A; // bitfield macros #define _RXF6EIDH_EID_POSN 0x0 #define _RXF6EIDH_EID_POSITION 0x0 #define _RXF6EIDH_EID_SIZE 0x8 #define _RXF6EIDH_EID_LENGTH 0x8 #define _RXF6EIDH_EID_MASK 0xFF #define _RXF6EIDH_EID8_POSN 0x0 #define _RXF6EIDH_EID8_POSITION 0x0 #define _RXF6EIDH_EID8_SIZE 0x1 #define _RXF6EIDH_EID8_LENGTH 0x1 #define _RXF6EIDH_EID8_MASK 0x1 #define _RXF6EIDH_EID9_POSN 0x1 #define _RXF6EIDH_EID9_POSITION 0x1 #define _RXF6EIDH_EID9_SIZE 0x1 #define _RXF6EIDH_EID9_LENGTH 0x1 #define _RXF6EIDH_EID9_MASK 0x2 #define _RXF6EIDH_EID10_POSN 0x2 #define _RXF6EIDH_EID10_POSITION 0x2 #define _RXF6EIDH_EID10_SIZE 0x1 #define _RXF6EIDH_EID10_LENGTH 0x1 #define _RXF6EIDH_EID10_MASK 0x4 #define _RXF6EIDH_EID11_POSN 0x3 #define _RXF6EIDH_EID11_POSITION 0x3 #define _RXF6EIDH_EID11_SIZE 0x1 #define _RXF6EIDH_EID11_LENGTH 0x1 #define _RXF6EIDH_EID11_MASK 0x8 #define _RXF6EIDH_EID12_POSN 0x4 #define _RXF6EIDH_EID12_POSITION 0x4 #define _RXF6EIDH_EID12_SIZE 0x1 #define _RXF6EIDH_EID12_LENGTH 0x1 #define _RXF6EIDH_EID12_MASK 0x10 #define _RXF6EIDH_EID13_POSN 0x5 #define _RXF6EIDH_EID13_POSITION 0x5 #define _RXF6EIDH_EID13_SIZE 0x1 #define _RXF6EIDH_EID13_LENGTH 0x1 #define _RXF6EIDH_EID13_MASK 0x20 #define _RXF6EIDH_EID14_POSN 0x6 #define _RXF6EIDH_EID14_POSITION 0x6 #define _RXF6EIDH_EID14_SIZE 0x1 #define _RXF6EIDH_EID14_LENGTH 0x1 #define _RXF6EIDH_EID14_MASK 0x40 #define _RXF6EIDH_EID15_POSN 0x7 #define _RXF6EIDH_EID15_POSITION 0x7 #define _RXF6EIDH_EID15_SIZE 0x1 #define _RXF6EIDH_EID15_LENGTH 0x1 #define _RXF6EIDH_EID15_MASK 0x80 #define _RXF6EIDH_RXF6EID8_POSN 0x0 #define _RXF6EIDH_RXF6EID8_POSITION 0x0 #define _RXF6EIDH_RXF6EID8_SIZE 0x1 #define _RXF6EIDH_RXF6EID8_LENGTH 0x1 #define _RXF6EIDH_RXF6EID8_MASK 0x1 #define _RXF6EIDH_RXF6EID9_POSN 0x1 #define _RXF6EIDH_RXF6EID9_POSITION 0x1 #define _RXF6EIDH_RXF6EID9_SIZE 0x1 #define _RXF6EIDH_RXF6EID9_LENGTH 0x1 #define _RXF6EIDH_RXF6EID9_MASK 0x2 #define _RXF6EIDH_RXF6EID10_POSN 0x2 #define _RXF6EIDH_RXF6EID10_POSITION 0x2 #define _RXF6EIDH_RXF6EID10_SIZE 0x1 #define _RXF6EIDH_RXF6EID10_LENGTH 0x1 #define _RXF6EIDH_RXF6EID10_MASK 0x4 #define _RXF6EIDH_RXF6EID11_POSN 0x3 #define _RXF6EIDH_RXF6EID11_POSITION 0x3 #define _RXF6EIDH_RXF6EID11_SIZE 0x1 #define _RXF6EIDH_RXF6EID11_LENGTH 0x1 #define _RXF6EIDH_RXF6EID11_MASK 0x8 #define _RXF6EIDH_RXF6EID12_POSN 0x4 #define _RXF6EIDH_RXF6EID12_POSITION 0x4 #define _RXF6EIDH_RXF6EID12_SIZE 0x1 #define _RXF6EIDH_RXF6EID12_LENGTH 0x1 #define _RXF6EIDH_RXF6EID12_MASK 0x10 #define _RXF6EIDH_RXF6EID13_POSN 0x5 #define _RXF6EIDH_RXF6EID13_POSITION 0x5 #define _RXF6EIDH_RXF6EID13_SIZE 0x1 #define _RXF6EIDH_RXF6EID13_LENGTH 0x1 #define _RXF6EIDH_RXF6EID13_MASK 0x20 #define _RXF6EIDH_RXF6EID14_POSN 0x6 #define _RXF6EIDH_RXF6EID14_POSITION 0x6 #define _RXF6EIDH_RXF6EID14_SIZE 0x1 #define _RXF6EIDH_RXF6EID14_LENGTH 0x1 #define _RXF6EIDH_RXF6EID14_MASK 0x40 #define _RXF6EIDH_RXF6EID15_POSN 0x7 #define _RXF6EIDH_RXF6EID15_POSITION 0x7 #define _RXF6EIDH_RXF6EID15_SIZE 0x1 #define _RXF6EIDH_RXF6EID15_LENGTH 0x1 #define _RXF6EIDH_RXF6EID15_MASK 0x80 // Register: RXF6EIDL #define RXF6EIDL RXF6EIDL extern volatile unsigned char RXF6EIDL @ 0xE4B; #ifndef _LIB_BUILD asm("RXF6EIDL equ 0E4Bh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF6EID0 :1; unsigned RXF6EID1 :1; unsigned RXF6EID2 :1; unsigned RXF6EID3 :1; unsigned RXF6EID4 :1; unsigned RXF6EID5 :1; unsigned RXF6EID6 :1; unsigned RXF6EID7 :1; }; } RXF6EIDLbits_t; extern volatile RXF6EIDLbits_t RXF6EIDLbits @ 0xE4B; // bitfield macros #define _RXF6EIDL_EID_POSN 0x0 #define _RXF6EIDL_EID_POSITION 0x0 #define _RXF6EIDL_EID_SIZE 0x8 #define _RXF6EIDL_EID_LENGTH 0x8 #define _RXF6EIDL_EID_MASK 0xFF #define _RXF6EIDL_EID0_POSN 0x0 #define _RXF6EIDL_EID0_POSITION 0x0 #define _RXF6EIDL_EID0_SIZE 0x1 #define _RXF6EIDL_EID0_LENGTH 0x1 #define _RXF6EIDL_EID0_MASK 0x1 #define _RXF6EIDL_EID1_POSN 0x1 #define _RXF6EIDL_EID1_POSITION 0x1 #define _RXF6EIDL_EID1_SIZE 0x1 #define _RXF6EIDL_EID1_LENGTH 0x1 #define _RXF6EIDL_EID1_MASK 0x2 #define _RXF6EIDL_EID2_POSN 0x2 #define _RXF6EIDL_EID2_POSITION 0x2 #define _RXF6EIDL_EID2_SIZE 0x1 #define _RXF6EIDL_EID2_LENGTH 0x1 #define _RXF6EIDL_EID2_MASK 0x4 #define _RXF6EIDL_EID3_POSN 0x3 #define _RXF6EIDL_EID3_POSITION 0x3 #define _RXF6EIDL_EID3_SIZE 0x1 #define _RXF6EIDL_EID3_LENGTH 0x1 #define _RXF6EIDL_EID3_MASK 0x8 #define _RXF6EIDL_EID4_POSN 0x4 #define _RXF6EIDL_EID4_POSITION 0x4 #define _RXF6EIDL_EID4_SIZE 0x1 #define _RXF6EIDL_EID4_LENGTH 0x1 #define _RXF6EIDL_EID4_MASK 0x10 #define _RXF6EIDL_EID5_POSN 0x5 #define _RXF6EIDL_EID5_POSITION 0x5 #define _RXF6EIDL_EID5_SIZE 0x1 #define _RXF6EIDL_EID5_LENGTH 0x1 #define _RXF6EIDL_EID5_MASK 0x20 #define _RXF6EIDL_EID6_POSN 0x6 #define _RXF6EIDL_EID6_POSITION 0x6 #define _RXF6EIDL_EID6_SIZE 0x1 #define _RXF6EIDL_EID6_LENGTH 0x1 #define _RXF6EIDL_EID6_MASK 0x40 #define _RXF6EIDL_EID7_POSN 0x7 #define _RXF6EIDL_EID7_POSITION 0x7 #define _RXF6EIDL_EID7_SIZE 0x1 #define _RXF6EIDL_EID7_LENGTH 0x1 #define _RXF6EIDL_EID7_MASK 0x80 #define _RXF6EIDL_RXF6EID0_POSN 0x0 #define _RXF6EIDL_RXF6EID0_POSITION 0x0 #define _RXF6EIDL_RXF6EID0_SIZE 0x1 #define _RXF6EIDL_RXF6EID0_LENGTH 0x1 #define _RXF6EIDL_RXF6EID0_MASK 0x1 #define _RXF6EIDL_RXF6EID1_POSN 0x1 #define _RXF6EIDL_RXF6EID1_POSITION 0x1 #define _RXF6EIDL_RXF6EID1_SIZE 0x1 #define _RXF6EIDL_RXF6EID1_LENGTH 0x1 #define _RXF6EIDL_RXF6EID1_MASK 0x2 #define _RXF6EIDL_RXF6EID2_POSN 0x2 #define _RXF6EIDL_RXF6EID2_POSITION 0x2 #define _RXF6EIDL_RXF6EID2_SIZE 0x1 #define _RXF6EIDL_RXF6EID2_LENGTH 0x1 #define _RXF6EIDL_RXF6EID2_MASK 0x4 #define _RXF6EIDL_RXF6EID3_POSN 0x3 #define _RXF6EIDL_RXF6EID3_POSITION 0x3 #define _RXF6EIDL_RXF6EID3_SIZE 0x1 #define _RXF6EIDL_RXF6EID3_LENGTH 0x1 #define _RXF6EIDL_RXF6EID3_MASK 0x8 #define _RXF6EIDL_RXF6EID4_POSN 0x4 #define _RXF6EIDL_RXF6EID4_POSITION 0x4 #define _RXF6EIDL_RXF6EID4_SIZE 0x1 #define _RXF6EIDL_RXF6EID4_LENGTH 0x1 #define _RXF6EIDL_RXF6EID4_MASK 0x10 #define _RXF6EIDL_RXF6EID5_POSN 0x5 #define _RXF6EIDL_RXF6EID5_POSITION 0x5 #define _RXF6EIDL_RXF6EID5_SIZE 0x1 #define _RXF6EIDL_RXF6EID5_LENGTH 0x1 #define _RXF6EIDL_RXF6EID5_MASK 0x20 #define _RXF6EIDL_RXF6EID6_POSN 0x6 #define _RXF6EIDL_RXF6EID6_POSITION 0x6 #define _RXF6EIDL_RXF6EID6_SIZE 0x1 #define _RXF6EIDL_RXF6EID6_LENGTH 0x1 #define _RXF6EIDL_RXF6EID6_MASK 0x40 #define _RXF6EIDL_RXF6EID7_POSN 0x7 #define _RXF6EIDL_RXF6EID7_POSITION 0x7 #define _RXF6EIDL_RXF6EID7_SIZE 0x1 #define _RXF6EIDL_RXF6EID7_LENGTH 0x1 #define _RXF6EIDL_RXF6EID7_MASK 0x80 // Register: RXF7SIDH #define RXF7SIDH RXF7SIDH extern volatile unsigned char RXF7SIDH @ 0xE4C; #ifndef _LIB_BUILD asm("RXF7SIDH equ 0E4Ch"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF7SID3 :1; unsigned RXF7SID4 :1; unsigned RXF7SID5 :1; unsigned RXF7SID6 :1; unsigned RXF7SID7 :1; unsigned RXF7SID8 :1; unsigned RXF7SID9 :1; unsigned RXF7SID10 :1; }; } RXF7SIDHbits_t; extern volatile RXF7SIDHbits_t RXF7SIDHbits @ 0xE4C; // bitfield macros #define _RXF7SIDH_SID_POSN 0x0 #define _RXF7SIDH_SID_POSITION 0x0 #define _RXF7SIDH_SID_SIZE 0x8 #define _RXF7SIDH_SID_LENGTH 0x8 #define _RXF7SIDH_SID_MASK 0xFF #define _RXF7SIDH_SID3_POSN 0x0 #define _RXF7SIDH_SID3_POSITION 0x0 #define _RXF7SIDH_SID3_SIZE 0x1 #define _RXF7SIDH_SID3_LENGTH 0x1 #define _RXF7SIDH_SID3_MASK 0x1 #define _RXF7SIDH_SID4_POSN 0x1 #define _RXF7SIDH_SID4_POSITION 0x1 #define _RXF7SIDH_SID4_SIZE 0x1 #define _RXF7SIDH_SID4_LENGTH 0x1 #define _RXF7SIDH_SID4_MASK 0x2 #define _RXF7SIDH_SID5_POSN 0x2 #define _RXF7SIDH_SID5_POSITION 0x2 #define _RXF7SIDH_SID5_SIZE 0x1 #define _RXF7SIDH_SID5_LENGTH 0x1 #define _RXF7SIDH_SID5_MASK 0x4 #define _RXF7SIDH_SID6_POSN 0x3 #define _RXF7SIDH_SID6_POSITION 0x3 #define _RXF7SIDH_SID6_SIZE 0x1 #define _RXF7SIDH_SID6_LENGTH 0x1 #define _RXF7SIDH_SID6_MASK 0x8 #define _RXF7SIDH_SID7_POSN 0x4 #define _RXF7SIDH_SID7_POSITION 0x4 #define _RXF7SIDH_SID7_SIZE 0x1 #define _RXF7SIDH_SID7_LENGTH 0x1 #define _RXF7SIDH_SID7_MASK 0x10 #define _RXF7SIDH_SID8_POSN 0x5 #define _RXF7SIDH_SID8_POSITION 0x5 #define _RXF7SIDH_SID8_SIZE 0x1 #define _RXF7SIDH_SID8_LENGTH 0x1 #define _RXF7SIDH_SID8_MASK 0x20 #define _RXF7SIDH_SID9_POSN 0x6 #define _RXF7SIDH_SID9_POSITION 0x6 #define _RXF7SIDH_SID9_SIZE 0x1 #define _RXF7SIDH_SID9_LENGTH 0x1 #define _RXF7SIDH_SID9_MASK 0x40 #define _RXF7SIDH_SID10_POSN 0x7 #define _RXF7SIDH_SID10_POSITION 0x7 #define _RXF7SIDH_SID10_SIZE 0x1 #define _RXF7SIDH_SID10_LENGTH 0x1 #define _RXF7SIDH_SID10_MASK 0x80 #define _RXF7SIDH_RXF7SID3_POSN 0x0 #define _RXF7SIDH_RXF7SID3_POSITION 0x0 #define _RXF7SIDH_RXF7SID3_SIZE 0x1 #define _RXF7SIDH_RXF7SID3_LENGTH 0x1 #define _RXF7SIDH_RXF7SID3_MASK 0x1 #define _RXF7SIDH_RXF7SID4_POSN 0x1 #define _RXF7SIDH_RXF7SID4_POSITION 0x1 #define _RXF7SIDH_RXF7SID4_SIZE 0x1 #define _RXF7SIDH_RXF7SID4_LENGTH 0x1 #define _RXF7SIDH_RXF7SID4_MASK 0x2 #define _RXF7SIDH_RXF7SID5_POSN 0x2 #define _RXF7SIDH_RXF7SID5_POSITION 0x2 #define _RXF7SIDH_RXF7SID5_SIZE 0x1 #define _RXF7SIDH_RXF7SID5_LENGTH 0x1 #define _RXF7SIDH_RXF7SID5_MASK 0x4 #define _RXF7SIDH_RXF7SID6_POSN 0x3 #define _RXF7SIDH_RXF7SID6_POSITION 0x3 #define _RXF7SIDH_RXF7SID6_SIZE 0x1 #define _RXF7SIDH_RXF7SID6_LENGTH 0x1 #define _RXF7SIDH_RXF7SID6_MASK 0x8 #define _RXF7SIDH_RXF7SID7_POSN 0x4 #define _RXF7SIDH_RXF7SID7_POSITION 0x4 #define _RXF7SIDH_RXF7SID7_SIZE 0x1 #define _RXF7SIDH_RXF7SID7_LENGTH 0x1 #define _RXF7SIDH_RXF7SID7_MASK 0x10 #define _RXF7SIDH_RXF7SID8_POSN 0x5 #define _RXF7SIDH_RXF7SID8_POSITION 0x5 #define _RXF7SIDH_RXF7SID8_SIZE 0x1 #define _RXF7SIDH_RXF7SID8_LENGTH 0x1 #define _RXF7SIDH_RXF7SID8_MASK 0x20 #define _RXF7SIDH_RXF7SID9_POSN 0x6 #define _RXF7SIDH_RXF7SID9_POSITION 0x6 #define _RXF7SIDH_RXF7SID9_SIZE 0x1 #define _RXF7SIDH_RXF7SID9_LENGTH 0x1 #define _RXF7SIDH_RXF7SID9_MASK 0x40 #define _RXF7SIDH_RXF7SID10_POSN 0x7 #define _RXF7SIDH_RXF7SID10_POSITION 0x7 #define _RXF7SIDH_RXF7SID10_SIZE 0x1 #define _RXF7SIDH_RXF7SID10_LENGTH 0x1 #define _RXF7SIDH_RXF7SID10_MASK 0x80 // Register: RXF7SIDL #define RXF7SIDL RXF7SIDL extern volatile unsigned char RXF7SIDL @ 0xE4D; #ifndef _LIB_BUILD asm("RXF7SIDL equ 0E4Dh"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF7EID16 :1; unsigned RXF7EID17 :1; unsigned :1; unsigned RXF7EXIDEN :1; unsigned :1; unsigned RXF7SID0 :1; unsigned RXF7SID1 :1; unsigned RXF7SID2 :1; }; } RXF7SIDLbits_t; extern volatile RXF7SIDLbits_t RXF7SIDLbits @ 0xE4D; // bitfield macros #define _RXF7SIDL_EID_POSN 0x0 #define _RXF7SIDL_EID_POSITION 0x0 #define _RXF7SIDL_EID_SIZE 0x2 #define _RXF7SIDL_EID_LENGTH 0x2 #define _RXF7SIDL_EID_MASK 0x3 #define _RXF7SIDL_EXIDEN_POSN 0x3 #define _RXF7SIDL_EXIDEN_POSITION 0x3 #define _RXF7SIDL_EXIDEN_SIZE 0x1 #define _RXF7SIDL_EXIDEN_LENGTH 0x1 #define _RXF7SIDL_EXIDEN_MASK 0x8 #define _RXF7SIDL_SID_POSN 0x5 #define _RXF7SIDL_SID_POSITION 0x5 #define _RXF7SIDL_SID_SIZE 0x3 #define _RXF7SIDL_SID_LENGTH 0x3 #define _RXF7SIDL_SID_MASK 0xE0 #define _RXF7SIDL_EID16_POSN 0x0 #define _RXF7SIDL_EID16_POSITION 0x0 #define _RXF7SIDL_EID16_SIZE 0x1 #define _RXF7SIDL_EID16_LENGTH 0x1 #define _RXF7SIDL_EID16_MASK 0x1 #define _RXF7SIDL_EID17_POSN 0x1 #define _RXF7SIDL_EID17_POSITION 0x1 #define _RXF7SIDL_EID17_SIZE 0x1 #define _RXF7SIDL_EID17_LENGTH 0x1 #define _RXF7SIDL_EID17_MASK 0x2 #define _RXF7SIDL_SID0_POSN 0x5 #define _RXF7SIDL_SID0_POSITION 0x5 #define _RXF7SIDL_SID0_SIZE 0x1 #define _RXF7SIDL_SID0_LENGTH 0x1 #define _RXF7SIDL_SID0_MASK 0x20 #define _RXF7SIDL_SID1_POSN 0x6 #define _RXF7SIDL_SID1_POSITION 0x6 #define _RXF7SIDL_SID1_SIZE 0x1 #define _RXF7SIDL_SID1_LENGTH 0x1 #define _RXF7SIDL_SID1_MASK 0x40 #define _RXF7SIDL_SID2_POSN 0x7 #define _RXF7SIDL_SID2_POSITION 0x7 #define _RXF7SIDL_SID2_SIZE 0x1 #define _RXF7SIDL_SID2_LENGTH 0x1 #define _RXF7SIDL_SID2_MASK 0x80 #define _RXF7SIDL_RXF7EID16_POSN 0x0 #define _RXF7SIDL_RXF7EID16_POSITION 0x0 #define _RXF7SIDL_RXF7EID16_SIZE 0x1 #define _RXF7SIDL_RXF7EID16_LENGTH 0x1 #define _RXF7SIDL_RXF7EID16_MASK 0x1 #define _RXF7SIDL_RXF7EID17_POSN 0x1 #define _RXF7SIDL_RXF7EID17_POSITION 0x1 #define _RXF7SIDL_RXF7EID17_SIZE 0x1 #define _RXF7SIDL_RXF7EID17_LENGTH 0x1 #define _RXF7SIDL_RXF7EID17_MASK 0x2 #define _RXF7SIDL_RXF7EXIDEN_POSN 0x3 #define _RXF7SIDL_RXF7EXIDEN_POSITION 0x3 #define _RXF7SIDL_RXF7EXIDEN_SIZE 0x1 #define _RXF7SIDL_RXF7EXIDEN_LENGTH 0x1 #define _RXF7SIDL_RXF7EXIDEN_MASK 0x8 #define _RXF7SIDL_RXF7SID0_POSN 0x5 #define _RXF7SIDL_RXF7SID0_POSITION 0x5 #define _RXF7SIDL_RXF7SID0_SIZE 0x1 #define _RXF7SIDL_RXF7SID0_LENGTH 0x1 #define _RXF7SIDL_RXF7SID0_MASK 0x20 #define _RXF7SIDL_RXF7SID1_POSN 0x6 #define _RXF7SIDL_RXF7SID1_POSITION 0x6 #define _RXF7SIDL_RXF7SID1_SIZE 0x1 #define _RXF7SIDL_RXF7SID1_LENGTH 0x1 #define _RXF7SIDL_RXF7SID1_MASK 0x40 #define _RXF7SIDL_RXF7SID2_POSN 0x7 #define _RXF7SIDL_RXF7SID2_POSITION 0x7 #define _RXF7SIDL_RXF7SID2_SIZE 0x1 #define _RXF7SIDL_RXF7SID2_LENGTH 0x1 #define _RXF7SIDL_RXF7SID2_MASK 0x80 // Register: RXF7EIDH #define RXF7EIDH RXF7EIDH extern volatile unsigned char RXF7EIDH @ 0xE4E; #ifndef _LIB_BUILD asm("RXF7EIDH equ 0E4Eh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF7EID8 :1; unsigned RXF7EID9 :1; unsigned RXF7EID10 :1; unsigned RXF7EID11 :1; unsigned RXF7EID12 :1; unsigned RXF7EID13 :1; unsigned RXF7EID14 :1; unsigned RXF7EID15 :1; }; } RXF7EIDHbits_t; extern volatile RXF7EIDHbits_t RXF7EIDHbits @ 0xE4E; // bitfield macros #define _RXF7EIDH_EID_POSN 0x0 #define _RXF7EIDH_EID_POSITION 0x0 #define _RXF7EIDH_EID_SIZE 0x8 #define _RXF7EIDH_EID_LENGTH 0x8 #define _RXF7EIDH_EID_MASK 0xFF #define _RXF7EIDH_EID8_POSN 0x0 #define _RXF7EIDH_EID8_POSITION 0x0 #define _RXF7EIDH_EID8_SIZE 0x1 #define _RXF7EIDH_EID8_LENGTH 0x1 #define _RXF7EIDH_EID8_MASK 0x1 #define _RXF7EIDH_EID9_POSN 0x1 #define _RXF7EIDH_EID9_POSITION 0x1 #define _RXF7EIDH_EID9_SIZE 0x1 #define _RXF7EIDH_EID9_LENGTH 0x1 #define _RXF7EIDH_EID9_MASK 0x2 #define _RXF7EIDH_EID10_POSN 0x2 #define _RXF7EIDH_EID10_POSITION 0x2 #define _RXF7EIDH_EID10_SIZE 0x1 #define _RXF7EIDH_EID10_LENGTH 0x1 #define _RXF7EIDH_EID10_MASK 0x4 #define _RXF7EIDH_EID11_POSN 0x3 #define _RXF7EIDH_EID11_POSITION 0x3 #define _RXF7EIDH_EID11_SIZE 0x1 #define _RXF7EIDH_EID11_LENGTH 0x1 #define _RXF7EIDH_EID11_MASK 0x8 #define _RXF7EIDH_EID12_POSN 0x4 #define _RXF7EIDH_EID12_POSITION 0x4 #define _RXF7EIDH_EID12_SIZE 0x1 #define _RXF7EIDH_EID12_LENGTH 0x1 #define _RXF7EIDH_EID12_MASK 0x10 #define _RXF7EIDH_EID13_POSN 0x5 #define _RXF7EIDH_EID13_POSITION 0x5 #define _RXF7EIDH_EID13_SIZE 0x1 #define _RXF7EIDH_EID13_LENGTH 0x1 #define _RXF7EIDH_EID13_MASK 0x20 #define _RXF7EIDH_EID14_POSN 0x6 #define _RXF7EIDH_EID14_POSITION 0x6 #define _RXF7EIDH_EID14_SIZE 0x1 #define _RXF7EIDH_EID14_LENGTH 0x1 #define _RXF7EIDH_EID14_MASK 0x40 #define _RXF7EIDH_EID15_POSN 0x7 #define _RXF7EIDH_EID15_POSITION 0x7 #define _RXF7EIDH_EID15_SIZE 0x1 #define _RXF7EIDH_EID15_LENGTH 0x1 #define _RXF7EIDH_EID15_MASK 0x80 #define _RXF7EIDH_RXF7EID8_POSN 0x0 #define _RXF7EIDH_RXF7EID8_POSITION 0x0 #define _RXF7EIDH_RXF7EID8_SIZE 0x1 #define _RXF7EIDH_RXF7EID8_LENGTH 0x1 #define _RXF7EIDH_RXF7EID8_MASK 0x1 #define _RXF7EIDH_RXF7EID9_POSN 0x1 #define _RXF7EIDH_RXF7EID9_POSITION 0x1 #define _RXF7EIDH_RXF7EID9_SIZE 0x1 #define _RXF7EIDH_RXF7EID9_LENGTH 0x1 #define _RXF7EIDH_RXF7EID9_MASK 0x2 #define _RXF7EIDH_RXF7EID10_POSN 0x2 #define _RXF7EIDH_RXF7EID10_POSITION 0x2 #define _RXF7EIDH_RXF7EID10_SIZE 0x1 #define _RXF7EIDH_RXF7EID10_LENGTH 0x1 #define _RXF7EIDH_RXF7EID10_MASK 0x4 #define _RXF7EIDH_RXF7EID11_POSN 0x3 #define _RXF7EIDH_RXF7EID11_POSITION 0x3 #define _RXF7EIDH_RXF7EID11_SIZE 0x1 #define _RXF7EIDH_RXF7EID11_LENGTH 0x1 #define _RXF7EIDH_RXF7EID11_MASK 0x8 #define _RXF7EIDH_RXF7EID12_POSN 0x4 #define _RXF7EIDH_RXF7EID12_POSITION 0x4 #define _RXF7EIDH_RXF7EID12_SIZE 0x1 #define _RXF7EIDH_RXF7EID12_LENGTH 0x1 #define _RXF7EIDH_RXF7EID12_MASK 0x10 #define _RXF7EIDH_RXF7EID13_POSN 0x5 #define _RXF7EIDH_RXF7EID13_POSITION 0x5 #define _RXF7EIDH_RXF7EID13_SIZE 0x1 #define _RXF7EIDH_RXF7EID13_LENGTH 0x1 #define _RXF7EIDH_RXF7EID13_MASK 0x20 #define _RXF7EIDH_RXF7EID14_POSN 0x6 #define _RXF7EIDH_RXF7EID14_POSITION 0x6 #define _RXF7EIDH_RXF7EID14_SIZE 0x1 #define _RXF7EIDH_RXF7EID14_LENGTH 0x1 #define _RXF7EIDH_RXF7EID14_MASK 0x40 #define _RXF7EIDH_RXF7EID15_POSN 0x7 #define _RXF7EIDH_RXF7EID15_POSITION 0x7 #define _RXF7EIDH_RXF7EID15_SIZE 0x1 #define _RXF7EIDH_RXF7EID15_LENGTH 0x1 #define _RXF7EIDH_RXF7EID15_MASK 0x80 // Register: RXF7EIDL #define RXF7EIDL RXF7EIDL extern volatile unsigned char RXF7EIDL @ 0xE4F; #ifndef _LIB_BUILD asm("RXF7EIDL equ 0E4Fh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF7EID0 :1; unsigned RXF7EID1 :1; unsigned RXF7EID2 :1; unsigned RXF7EID3 :1; unsigned RXF7EID4 :1; unsigned RXF7EID5 :1; unsigned RXF7EID6 :1; unsigned RXF7EID7 :1; }; } RXF7EIDLbits_t; extern volatile RXF7EIDLbits_t RXF7EIDLbits @ 0xE4F; // bitfield macros #define _RXF7EIDL_EID_POSN 0x0 #define _RXF7EIDL_EID_POSITION 0x0 #define _RXF7EIDL_EID_SIZE 0x8 #define _RXF7EIDL_EID_LENGTH 0x8 #define _RXF7EIDL_EID_MASK 0xFF #define _RXF7EIDL_EID0_POSN 0x0 #define _RXF7EIDL_EID0_POSITION 0x0 #define _RXF7EIDL_EID0_SIZE 0x1 #define _RXF7EIDL_EID0_LENGTH 0x1 #define _RXF7EIDL_EID0_MASK 0x1 #define _RXF7EIDL_EID1_POSN 0x1 #define _RXF7EIDL_EID1_POSITION 0x1 #define _RXF7EIDL_EID1_SIZE 0x1 #define _RXF7EIDL_EID1_LENGTH 0x1 #define _RXF7EIDL_EID1_MASK 0x2 #define _RXF7EIDL_EID2_POSN 0x2 #define _RXF7EIDL_EID2_POSITION 0x2 #define _RXF7EIDL_EID2_SIZE 0x1 #define _RXF7EIDL_EID2_LENGTH 0x1 #define _RXF7EIDL_EID2_MASK 0x4 #define _RXF7EIDL_EID3_POSN 0x3 #define _RXF7EIDL_EID3_POSITION 0x3 #define _RXF7EIDL_EID3_SIZE 0x1 #define _RXF7EIDL_EID3_LENGTH 0x1 #define _RXF7EIDL_EID3_MASK 0x8 #define _RXF7EIDL_EID4_POSN 0x4 #define _RXF7EIDL_EID4_POSITION 0x4 #define _RXF7EIDL_EID4_SIZE 0x1 #define _RXF7EIDL_EID4_LENGTH 0x1 #define _RXF7EIDL_EID4_MASK 0x10 #define _RXF7EIDL_EID5_POSN 0x5 #define _RXF7EIDL_EID5_POSITION 0x5 #define _RXF7EIDL_EID5_SIZE 0x1 #define _RXF7EIDL_EID5_LENGTH 0x1 #define _RXF7EIDL_EID5_MASK 0x20 #define _RXF7EIDL_EID6_POSN 0x6 #define _RXF7EIDL_EID6_POSITION 0x6 #define _RXF7EIDL_EID6_SIZE 0x1 #define _RXF7EIDL_EID6_LENGTH 0x1 #define _RXF7EIDL_EID6_MASK 0x40 #define _RXF7EIDL_EID7_POSN 0x7 #define _RXF7EIDL_EID7_POSITION 0x7 #define _RXF7EIDL_EID7_SIZE 0x1 #define _RXF7EIDL_EID7_LENGTH 0x1 #define _RXF7EIDL_EID7_MASK 0x80 #define _RXF7EIDL_RXF7EID0_POSN 0x0 #define _RXF7EIDL_RXF7EID0_POSITION 0x0 #define _RXF7EIDL_RXF7EID0_SIZE 0x1 #define _RXF7EIDL_RXF7EID0_LENGTH 0x1 #define _RXF7EIDL_RXF7EID0_MASK 0x1 #define _RXF7EIDL_RXF7EID1_POSN 0x1 #define _RXF7EIDL_RXF7EID1_POSITION 0x1 #define _RXF7EIDL_RXF7EID1_SIZE 0x1 #define _RXF7EIDL_RXF7EID1_LENGTH 0x1 #define _RXF7EIDL_RXF7EID1_MASK 0x2 #define _RXF7EIDL_RXF7EID2_POSN 0x2 #define _RXF7EIDL_RXF7EID2_POSITION 0x2 #define _RXF7EIDL_RXF7EID2_SIZE 0x1 #define _RXF7EIDL_RXF7EID2_LENGTH 0x1 #define _RXF7EIDL_RXF7EID2_MASK 0x4 #define _RXF7EIDL_RXF7EID3_POSN 0x3 #define _RXF7EIDL_RXF7EID3_POSITION 0x3 #define _RXF7EIDL_RXF7EID3_SIZE 0x1 #define _RXF7EIDL_RXF7EID3_LENGTH 0x1 #define _RXF7EIDL_RXF7EID3_MASK 0x8 #define _RXF7EIDL_RXF7EID4_POSN 0x4 #define _RXF7EIDL_RXF7EID4_POSITION 0x4 #define _RXF7EIDL_RXF7EID4_SIZE 0x1 #define _RXF7EIDL_RXF7EID4_LENGTH 0x1 #define _RXF7EIDL_RXF7EID4_MASK 0x10 #define _RXF7EIDL_RXF7EID5_POSN 0x5 #define _RXF7EIDL_RXF7EID5_POSITION 0x5 #define _RXF7EIDL_RXF7EID5_SIZE 0x1 #define _RXF7EIDL_RXF7EID5_LENGTH 0x1 #define _RXF7EIDL_RXF7EID5_MASK 0x20 #define _RXF7EIDL_RXF7EID6_POSN 0x6 #define _RXF7EIDL_RXF7EID6_POSITION 0x6 #define _RXF7EIDL_RXF7EID6_SIZE 0x1 #define _RXF7EIDL_RXF7EID6_LENGTH 0x1 #define _RXF7EIDL_RXF7EID6_MASK 0x40 #define _RXF7EIDL_RXF7EID7_POSN 0x7 #define _RXF7EIDL_RXF7EID7_POSITION 0x7 #define _RXF7EIDL_RXF7EID7_SIZE 0x1 #define _RXF7EIDL_RXF7EID7_LENGTH 0x1 #define _RXF7EIDL_RXF7EID7_MASK 0x80 // Register: RXF8SIDH #define RXF8SIDH RXF8SIDH extern volatile unsigned char RXF8SIDH @ 0xE50; #ifndef _LIB_BUILD asm("RXF8SIDH equ 0E50h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF8SID3 :1; unsigned RXF8SID4 :1; unsigned RXF8SID5 :1; unsigned RXF8SID6 :1; unsigned RXF8SID7 :1; unsigned RXF8SID8 :1; unsigned RXF8SID9 :1; unsigned RXF8SID10 :1; }; } RXF8SIDHbits_t; extern volatile RXF8SIDHbits_t RXF8SIDHbits @ 0xE50; // bitfield macros #define _RXF8SIDH_SID_POSN 0x0 #define _RXF8SIDH_SID_POSITION 0x0 #define _RXF8SIDH_SID_SIZE 0x8 #define _RXF8SIDH_SID_LENGTH 0x8 #define _RXF8SIDH_SID_MASK 0xFF #define _RXF8SIDH_SID3_POSN 0x0 #define _RXF8SIDH_SID3_POSITION 0x0 #define _RXF8SIDH_SID3_SIZE 0x1 #define _RXF8SIDH_SID3_LENGTH 0x1 #define _RXF8SIDH_SID3_MASK 0x1 #define _RXF8SIDH_SID4_POSN 0x1 #define _RXF8SIDH_SID4_POSITION 0x1 #define _RXF8SIDH_SID4_SIZE 0x1 #define _RXF8SIDH_SID4_LENGTH 0x1 #define _RXF8SIDH_SID4_MASK 0x2 #define _RXF8SIDH_SID5_POSN 0x2 #define _RXF8SIDH_SID5_POSITION 0x2 #define _RXF8SIDH_SID5_SIZE 0x1 #define _RXF8SIDH_SID5_LENGTH 0x1 #define _RXF8SIDH_SID5_MASK 0x4 #define _RXF8SIDH_SID6_POSN 0x3 #define _RXF8SIDH_SID6_POSITION 0x3 #define _RXF8SIDH_SID6_SIZE 0x1 #define _RXF8SIDH_SID6_LENGTH 0x1 #define _RXF8SIDH_SID6_MASK 0x8 #define _RXF8SIDH_SID7_POSN 0x4 #define _RXF8SIDH_SID7_POSITION 0x4 #define _RXF8SIDH_SID7_SIZE 0x1 #define _RXF8SIDH_SID7_LENGTH 0x1 #define _RXF8SIDH_SID7_MASK 0x10 #define _RXF8SIDH_SID8_POSN 0x5 #define _RXF8SIDH_SID8_POSITION 0x5 #define _RXF8SIDH_SID8_SIZE 0x1 #define _RXF8SIDH_SID8_LENGTH 0x1 #define _RXF8SIDH_SID8_MASK 0x20 #define _RXF8SIDH_SID9_POSN 0x6 #define _RXF8SIDH_SID9_POSITION 0x6 #define _RXF8SIDH_SID9_SIZE 0x1 #define _RXF8SIDH_SID9_LENGTH 0x1 #define _RXF8SIDH_SID9_MASK 0x40 #define _RXF8SIDH_SID10_POSN 0x7 #define _RXF8SIDH_SID10_POSITION 0x7 #define _RXF8SIDH_SID10_SIZE 0x1 #define _RXF8SIDH_SID10_LENGTH 0x1 #define _RXF8SIDH_SID10_MASK 0x80 #define _RXF8SIDH_RXF8SID3_POSN 0x0 #define _RXF8SIDH_RXF8SID3_POSITION 0x0 #define _RXF8SIDH_RXF8SID3_SIZE 0x1 #define _RXF8SIDH_RXF8SID3_LENGTH 0x1 #define _RXF8SIDH_RXF8SID3_MASK 0x1 #define _RXF8SIDH_RXF8SID4_POSN 0x1 #define _RXF8SIDH_RXF8SID4_POSITION 0x1 #define _RXF8SIDH_RXF8SID4_SIZE 0x1 #define _RXF8SIDH_RXF8SID4_LENGTH 0x1 #define _RXF8SIDH_RXF8SID4_MASK 0x2 #define _RXF8SIDH_RXF8SID5_POSN 0x2 #define _RXF8SIDH_RXF8SID5_POSITION 0x2 #define _RXF8SIDH_RXF8SID5_SIZE 0x1 #define _RXF8SIDH_RXF8SID5_LENGTH 0x1 #define _RXF8SIDH_RXF8SID5_MASK 0x4 #define _RXF8SIDH_RXF8SID6_POSN 0x3 #define _RXF8SIDH_RXF8SID6_POSITION 0x3 #define _RXF8SIDH_RXF8SID6_SIZE 0x1 #define _RXF8SIDH_RXF8SID6_LENGTH 0x1 #define _RXF8SIDH_RXF8SID6_MASK 0x8 #define _RXF8SIDH_RXF8SID7_POSN 0x4 #define _RXF8SIDH_RXF8SID7_POSITION 0x4 #define _RXF8SIDH_RXF8SID7_SIZE 0x1 #define _RXF8SIDH_RXF8SID7_LENGTH 0x1 #define _RXF8SIDH_RXF8SID7_MASK 0x10 #define _RXF8SIDH_RXF8SID8_POSN 0x5 #define _RXF8SIDH_RXF8SID8_POSITION 0x5 #define _RXF8SIDH_RXF8SID8_SIZE 0x1 #define _RXF8SIDH_RXF8SID8_LENGTH 0x1 #define _RXF8SIDH_RXF8SID8_MASK 0x20 #define _RXF8SIDH_RXF8SID9_POSN 0x6 #define _RXF8SIDH_RXF8SID9_POSITION 0x6 #define _RXF8SIDH_RXF8SID9_SIZE 0x1 #define _RXF8SIDH_RXF8SID9_LENGTH 0x1 #define _RXF8SIDH_RXF8SID9_MASK 0x40 #define _RXF8SIDH_RXF8SID10_POSN 0x7 #define _RXF8SIDH_RXF8SID10_POSITION 0x7 #define _RXF8SIDH_RXF8SID10_SIZE 0x1 #define _RXF8SIDH_RXF8SID10_LENGTH 0x1 #define _RXF8SIDH_RXF8SID10_MASK 0x80 // Register: RXF8SIDL #define RXF8SIDL RXF8SIDL extern volatile unsigned char RXF8SIDL @ 0xE51; #ifndef _LIB_BUILD asm("RXF8SIDL equ 0E51h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF8EID16 :1; unsigned RXF8EID17 :1; unsigned :1; unsigned RXF8EXIDEN :1; unsigned :1; unsigned RXF8SID0 :1; unsigned RXF8SID1 :1; unsigned RXF8SID2 :1; }; } RXF8SIDLbits_t; extern volatile RXF8SIDLbits_t RXF8SIDLbits @ 0xE51; // bitfield macros #define _RXF8SIDL_EID_POSN 0x0 #define _RXF8SIDL_EID_POSITION 0x0 #define _RXF8SIDL_EID_SIZE 0x2 #define _RXF8SIDL_EID_LENGTH 0x2 #define _RXF8SIDL_EID_MASK 0x3 #define _RXF8SIDL_EXIDEN_POSN 0x3 #define _RXF8SIDL_EXIDEN_POSITION 0x3 #define _RXF8SIDL_EXIDEN_SIZE 0x1 #define _RXF8SIDL_EXIDEN_LENGTH 0x1 #define _RXF8SIDL_EXIDEN_MASK 0x8 #define _RXF8SIDL_SID_POSN 0x5 #define _RXF8SIDL_SID_POSITION 0x5 #define _RXF8SIDL_SID_SIZE 0x3 #define _RXF8SIDL_SID_LENGTH 0x3 #define _RXF8SIDL_SID_MASK 0xE0 #define _RXF8SIDL_EID16_POSN 0x0 #define _RXF8SIDL_EID16_POSITION 0x0 #define _RXF8SIDL_EID16_SIZE 0x1 #define _RXF8SIDL_EID16_LENGTH 0x1 #define _RXF8SIDL_EID16_MASK 0x1 #define _RXF8SIDL_EID17_POSN 0x1 #define _RXF8SIDL_EID17_POSITION 0x1 #define _RXF8SIDL_EID17_SIZE 0x1 #define _RXF8SIDL_EID17_LENGTH 0x1 #define _RXF8SIDL_EID17_MASK 0x2 #define _RXF8SIDL_SID0_POSN 0x5 #define _RXF8SIDL_SID0_POSITION 0x5 #define _RXF8SIDL_SID0_SIZE 0x1 #define _RXF8SIDL_SID0_LENGTH 0x1 #define _RXF8SIDL_SID0_MASK 0x20 #define _RXF8SIDL_SID1_POSN 0x6 #define _RXF8SIDL_SID1_POSITION 0x6 #define _RXF8SIDL_SID1_SIZE 0x1 #define _RXF8SIDL_SID1_LENGTH 0x1 #define _RXF8SIDL_SID1_MASK 0x40 #define _RXF8SIDL_SID2_POSN 0x7 #define _RXF8SIDL_SID2_POSITION 0x7 #define _RXF8SIDL_SID2_SIZE 0x1 #define _RXF8SIDL_SID2_LENGTH 0x1 #define _RXF8SIDL_SID2_MASK 0x80 #define _RXF8SIDL_RXF8EID16_POSN 0x0 #define _RXF8SIDL_RXF8EID16_POSITION 0x0 #define _RXF8SIDL_RXF8EID16_SIZE 0x1 #define _RXF8SIDL_RXF8EID16_LENGTH 0x1 #define _RXF8SIDL_RXF8EID16_MASK 0x1 #define _RXF8SIDL_RXF8EID17_POSN 0x1 #define _RXF8SIDL_RXF8EID17_POSITION 0x1 #define _RXF8SIDL_RXF8EID17_SIZE 0x1 #define _RXF8SIDL_RXF8EID17_LENGTH 0x1 #define _RXF8SIDL_RXF8EID17_MASK 0x2 #define _RXF8SIDL_RXF8EXIDEN_POSN 0x3 #define _RXF8SIDL_RXF8EXIDEN_POSITION 0x3 #define _RXF8SIDL_RXF8EXIDEN_SIZE 0x1 #define _RXF8SIDL_RXF8EXIDEN_LENGTH 0x1 #define _RXF8SIDL_RXF8EXIDEN_MASK 0x8 #define _RXF8SIDL_RXF8SID0_POSN 0x5 #define _RXF8SIDL_RXF8SID0_POSITION 0x5 #define _RXF8SIDL_RXF8SID0_SIZE 0x1 #define _RXF8SIDL_RXF8SID0_LENGTH 0x1 #define _RXF8SIDL_RXF8SID0_MASK 0x20 #define _RXF8SIDL_RXF8SID1_POSN 0x6 #define _RXF8SIDL_RXF8SID1_POSITION 0x6 #define _RXF8SIDL_RXF8SID1_SIZE 0x1 #define _RXF8SIDL_RXF8SID1_LENGTH 0x1 #define _RXF8SIDL_RXF8SID1_MASK 0x40 #define _RXF8SIDL_RXF8SID2_POSN 0x7 #define _RXF8SIDL_RXF8SID2_POSITION 0x7 #define _RXF8SIDL_RXF8SID2_SIZE 0x1 #define _RXF8SIDL_RXF8SID2_LENGTH 0x1 #define _RXF8SIDL_RXF8SID2_MASK 0x80 // Register: RXF8EIDH #define RXF8EIDH RXF8EIDH extern volatile unsigned char RXF8EIDH @ 0xE52; #ifndef _LIB_BUILD asm("RXF8EIDH equ 0E52h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF8EID8 :1; unsigned RXF8EID9 :1; unsigned RXF8EID10 :1; unsigned RXF8EID11 :1; unsigned RXF8EID12 :1; unsigned RXF8EID13 :1; unsigned RXF8EID14 :1; unsigned RXF8EID15 :1; }; } RXF8EIDHbits_t; extern volatile RXF8EIDHbits_t RXF8EIDHbits @ 0xE52; // bitfield macros #define _RXF8EIDH_EID_POSN 0x0 #define _RXF8EIDH_EID_POSITION 0x0 #define _RXF8EIDH_EID_SIZE 0x8 #define _RXF8EIDH_EID_LENGTH 0x8 #define _RXF8EIDH_EID_MASK 0xFF #define _RXF8EIDH_EID8_POSN 0x0 #define _RXF8EIDH_EID8_POSITION 0x0 #define _RXF8EIDH_EID8_SIZE 0x1 #define _RXF8EIDH_EID8_LENGTH 0x1 #define _RXF8EIDH_EID8_MASK 0x1 #define _RXF8EIDH_EID9_POSN 0x1 #define _RXF8EIDH_EID9_POSITION 0x1 #define _RXF8EIDH_EID9_SIZE 0x1 #define _RXF8EIDH_EID9_LENGTH 0x1 #define _RXF8EIDH_EID9_MASK 0x2 #define _RXF8EIDH_EID10_POSN 0x2 #define _RXF8EIDH_EID10_POSITION 0x2 #define _RXF8EIDH_EID10_SIZE 0x1 #define _RXF8EIDH_EID10_LENGTH 0x1 #define _RXF8EIDH_EID10_MASK 0x4 #define _RXF8EIDH_EID11_POSN 0x3 #define _RXF8EIDH_EID11_POSITION 0x3 #define _RXF8EIDH_EID11_SIZE 0x1 #define _RXF8EIDH_EID11_LENGTH 0x1 #define _RXF8EIDH_EID11_MASK 0x8 #define _RXF8EIDH_EID12_POSN 0x4 #define _RXF8EIDH_EID12_POSITION 0x4 #define _RXF8EIDH_EID12_SIZE 0x1 #define _RXF8EIDH_EID12_LENGTH 0x1 #define _RXF8EIDH_EID12_MASK 0x10 #define _RXF8EIDH_EID13_POSN 0x5 #define _RXF8EIDH_EID13_POSITION 0x5 #define _RXF8EIDH_EID13_SIZE 0x1 #define _RXF8EIDH_EID13_LENGTH 0x1 #define _RXF8EIDH_EID13_MASK 0x20 #define _RXF8EIDH_EID14_POSN 0x6 #define _RXF8EIDH_EID14_POSITION 0x6 #define _RXF8EIDH_EID14_SIZE 0x1 #define _RXF8EIDH_EID14_LENGTH 0x1 #define _RXF8EIDH_EID14_MASK 0x40 #define _RXF8EIDH_EID15_POSN 0x7 #define _RXF8EIDH_EID15_POSITION 0x7 #define _RXF8EIDH_EID15_SIZE 0x1 #define _RXF8EIDH_EID15_LENGTH 0x1 #define _RXF8EIDH_EID15_MASK 0x80 #define _RXF8EIDH_RXF8EID8_POSN 0x0 #define _RXF8EIDH_RXF8EID8_POSITION 0x0 #define _RXF8EIDH_RXF8EID8_SIZE 0x1 #define _RXF8EIDH_RXF8EID8_LENGTH 0x1 #define _RXF8EIDH_RXF8EID8_MASK 0x1 #define _RXF8EIDH_RXF8EID9_POSN 0x1 #define _RXF8EIDH_RXF8EID9_POSITION 0x1 #define _RXF8EIDH_RXF8EID9_SIZE 0x1 #define _RXF8EIDH_RXF8EID9_LENGTH 0x1 #define _RXF8EIDH_RXF8EID9_MASK 0x2 #define _RXF8EIDH_RXF8EID10_POSN 0x2 #define _RXF8EIDH_RXF8EID10_POSITION 0x2 #define _RXF8EIDH_RXF8EID10_SIZE 0x1 #define _RXF8EIDH_RXF8EID10_LENGTH 0x1 #define _RXF8EIDH_RXF8EID10_MASK 0x4 #define _RXF8EIDH_RXF8EID11_POSN 0x3 #define _RXF8EIDH_RXF8EID11_POSITION 0x3 #define _RXF8EIDH_RXF8EID11_SIZE 0x1 #define _RXF8EIDH_RXF8EID11_LENGTH 0x1 #define _RXF8EIDH_RXF8EID11_MASK 0x8 #define _RXF8EIDH_RXF8EID12_POSN 0x4 #define _RXF8EIDH_RXF8EID12_POSITION 0x4 #define _RXF8EIDH_RXF8EID12_SIZE 0x1 #define _RXF8EIDH_RXF8EID12_LENGTH 0x1 #define _RXF8EIDH_RXF8EID12_MASK 0x10 #define _RXF8EIDH_RXF8EID13_POSN 0x5 #define _RXF8EIDH_RXF8EID13_POSITION 0x5 #define _RXF8EIDH_RXF8EID13_SIZE 0x1 #define _RXF8EIDH_RXF8EID13_LENGTH 0x1 #define _RXF8EIDH_RXF8EID13_MASK 0x20 #define _RXF8EIDH_RXF8EID14_POSN 0x6 #define _RXF8EIDH_RXF8EID14_POSITION 0x6 #define _RXF8EIDH_RXF8EID14_SIZE 0x1 #define _RXF8EIDH_RXF8EID14_LENGTH 0x1 #define _RXF8EIDH_RXF8EID14_MASK 0x40 #define _RXF8EIDH_RXF8EID15_POSN 0x7 #define _RXF8EIDH_RXF8EID15_POSITION 0x7 #define _RXF8EIDH_RXF8EID15_SIZE 0x1 #define _RXF8EIDH_RXF8EID15_LENGTH 0x1 #define _RXF8EIDH_RXF8EID15_MASK 0x80 // Register: RXF8EIDL #define RXF8EIDL RXF8EIDL extern volatile unsigned char RXF8EIDL @ 0xE53; #ifndef _LIB_BUILD asm("RXF8EIDL equ 0E53h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF8EID0 :1; unsigned RXF8EID1 :1; unsigned RXF8EID2 :1; unsigned RXF8EID3 :1; unsigned RXF8EID4 :1; unsigned RXF8EID5 :1; unsigned RXF8EID6 :1; unsigned RXF8EID7 :1; }; } RXF8EIDLbits_t; extern volatile RXF8EIDLbits_t RXF8EIDLbits @ 0xE53; // bitfield macros #define _RXF8EIDL_EID_POSN 0x0 #define _RXF8EIDL_EID_POSITION 0x0 #define _RXF8EIDL_EID_SIZE 0x8 #define _RXF8EIDL_EID_LENGTH 0x8 #define _RXF8EIDL_EID_MASK 0xFF #define _RXF8EIDL_EID0_POSN 0x0 #define _RXF8EIDL_EID0_POSITION 0x0 #define _RXF8EIDL_EID0_SIZE 0x1 #define _RXF8EIDL_EID0_LENGTH 0x1 #define _RXF8EIDL_EID0_MASK 0x1 #define _RXF8EIDL_EID1_POSN 0x1 #define _RXF8EIDL_EID1_POSITION 0x1 #define _RXF8EIDL_EID1_SIZE 0x1 #define _RXF8EIDL_EID1_LENGTH 0x1 #define _RXF8EIDL_EID1_MASK 0x2 #define _RXF8EIDL_EID2_POSN 0x2 #define _RXF8EIDL_EID2_POSITION 0x2 #define _RXF8EIDL_EID2_SIZE 0x1 #define _RXF8EIDL_EID2_LENGTH 0x1 #define _RXF8EIDL_EID2_MASK 0x4 #define _RXF8EIDL_EID3_POSN 0x3 #define _RXF8EIDL_EID3_POSITION 0x3 #define _RXF8EIDL_EID3_SIZE 0x1 #define _RXF8EIDL_EID3_LENGTH 0x1 #define _RXF8EIDL_EID3_MASK 0x8 #define _RXF8EIDL_EID4_POSN 0x4 #define _RXF8EIDL_EID4_POSITION 0x4 #define _RXF8EIDL_EID4_SIZE 0x1 #define _RXF8EIDL_EID4_LENGTH 0x1 #define _RXF8EIDL_EID4_MASK 0x10 #define _RXF8EIDL_EID5_POSN 0x5 #define _RXF8EIDL_EID5_POSITION 0x5 #define _RXF8EIDL_EID5_SIZE 0x1 #define _RXF8EIDL_EID5_LENGTH 0x1 #define _RXF8EIDL_EID5_MASK 0x20 #define _RXF8EIDL_EID6_POSN 0x6 #define _RXF8EIDL_EID6_POSITION 0x6 #define _RXF8EIDL_EID6_SIZE 0x1 #define _RXF8EIDL_EID6_LENGTH 0x1 #define _RXF8EIDL_EID6_MASK 0x40 #define _RXF8EIDL_EID7_POSN 0x7 #define _RXF8EIDL_EID7_POSITION 0x7 #define _RXF8EIDL_EID7_SIZE 0x1 #define _RXF8EIDL_EID7_LENGTH 0x1 #define _RXF8EIDL_EID7_MASK 0x80 #define _RXF8EIDL_RXF8EID0_POSN 0x0 #define _RXF8EIDL_RXF8EID0_POSITION 0x0 #define _RXF8EIDL_RXF8EID0_SIZE 0x1 #define _RXF8EIDL_RXF8EID0_LENGTH 0x1 #define _RXF8EIDL_RXF8EID0_MASK 0x1 #define _RXF8EIDL_RXF8EID1_POSN 0x1 #define _RXF8EIDL_RXF8EID1_POSITION 0x1 #define _RXF8EIDL_RXF8EID1_SIZE 0x1 #define _RXF8EIDL_RXF8EID1_LENGTH 0x1 #define _RXF8EIDL_RXF8EID1_MASK 0x2 #define _RXF8EIDL_RXF8EID2_POSN 0x2 #define _RXF8EIDL_RXF8EID2_POSITION 0x2 #define _RXF8EIDL_RXF8EID2_SIZE 0x1 #define _RXF8EIDL_RXF8EID2_LENGTH 0x1 #define _RXF8EIDL_RXF8EID2_MASK 0x4 #define _RXF8EIDL_RXF8EID3_POSN 0x3 #define _RXF8EIDL_RXF8EID3_POSITION 0x3 #define _RXF8EIDL_RXF8EID3_SIZE 0x1 #define _RXF8EIDL_RXF8EID3_LENGTH 0x1 #define _RXF8EIDL_RXF8EID3_MASK 0x8 #define _RXF8EIDL_RXF8EID4_POSN 0x4 #define _RXF8EIDL_RXF8EID4_POSITION 0x4 #define _RXF8EIDL_RXF8EID4_SIZE 0x1 #define _RXF8EIDL_RXF8EID4_LENGTH 0x1 #define _RXF8EIDL_RXF8EID4_MASK 0x10 #define _RXF8EIDL_RXF8EID5_POSN 0x5 #define _RXF8EIDL_RXF8EID5_POSITION 0x5 #define _RXF8EIDL_RXF8EID5_SIZE 0x1 #define _RXF8EIDL_RXF8EID5_LENGTH 0x1 #define _RXF8EIDL_RXF8EID5_MASK 0x20 #define _RXF8EIDL_RXF8EID6_POSN 0x6 #define _RXF8EIDL_RXF8EID6_POSITION 0x6 #define _RXF8EIDL_RXF8EID6_SIZE 0x1 #define _RXF8EIDL_RXF8EID6_LENGTH 0x1 #define _RXF8EIDL_RXF8EID6_MASK 0x40 #define _RXF8EIDL_RXF8EID7_POSN 0x7 #define _RXF8EIDL_RXF8EID7_POSITION 0x7 #define _RXF8EIDL_RXF8EID7_SIZE 0x1 #define _RXF8EIDL_RXF8EID7_LENGTH 0x1 #define _RXF8EIDL_RXF8EID7_MASK 0x80 // Register: RXF9SIDH #define RXF9SIDH RXF9SIDH extern volatile unsigned char RXF9SIDH @ 0xE54; #ifndef _LIB_BUILD asm("RXF9SIDH equ 0E54h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF9SID3 :1; unsigned RXF9SID4 :1; unsigned RXF9SID5 :1; unsigned RXF9SID6 :1; unsigned RXF9SID7 :1; unsigned RXF9SID8 :1; unsigned RXF9SID9 :1; unsigned RXF9SID10 :1; }; } RXF9SIDHbits_t; extern volatile RXF9SIDHbits_t RXF9SIDHbits @ 0xE54; // bitfield macros #define _RXF9SIDH_SID_POSN 0x0 #define _RXF9SIDH_SID_POSITION 0x0 #define _RXF9SIDH_SID_SIZE 0x8 #define _RXF9SIDH_SID_LENGTH 0x8 #define _RXF9SIDH_SID_MASK 0xFF #define _RXF9SIDH_SID3_POSN 0x0 #define _RXF9SIDH_SID3_POSITION 0x0 #define _RXF9SIDH_SID3_SIZE 0x1 #define _RXF9SIDH_SID3_LENGTH 0x1 #define _RXF9SIDH_SID3_MASK 0x1 #define _RXF9SIDH_SID4_POSN 0x1 #define _RXF9SIDH_SID4_POSITION 0x1 #define _RXF9SIDH_SID4_SIZE 0x1 #define _RXF9SIDH_SID4_LENGTH 0x1 #define _RXF9SIDH_SID4_MASK 0x2 #define _RXF9SIDH_SID5_POSN 0x2 #define _RXF9SIDH_SID5_POSITION 0x2 #define _RXF9SIDH_SID5_SIZE 0x1 #define _RXF9SIDH_SID5_LENGTH 0x1 #define _RXF9SIDH_SID5_MASK 0x4 #define _RXF9SIDH_SID6_POSN 0x3 #define _RXF9SIDH_SID6_POSITION 0x3 #define _RXF9SIDH_SID6_SIZE 0x1 #define _RXF9SIDH_SID6_LENGTH 0x1 #define _RXF9SIDH_SID6_MASK 0x8 #define _RXF9SIDH_SID7_POSN 0x4 #define _RXF9SIDH_SID7_POSITION 0x4 #define _RXF9SIDH_SID7_SIZE 0x1 #define _RXF9SIDH_SID7_LENGTH 0x1 #define _RXF9SIDH_SID7_MASK 0x10 #define _RXF9SIDH_SID8_POSN 0x5 #define _RXF9SIDH_SID8_POSITION 0x5 #define _RXF9SIDH_SID8_SIZE 0x1 #define _RXF9SIDH_SID8_LENGTH 0x1 #define _RXF9SIDH_SID8_MASK 0x20 #define _RXF9SIDH_SID9_POSN 0x6 #define _RXF9SIDH_SID9_POSITION 0x6 #define _RXF9SIDH_SID9_SIZE 0x1 #define _RXF9SIDH_SID9_LENGTH 0x1 #define _RXF9SIDH_SID9_MASK 0x40 #define _RXF9SIDH_SID10_POSN 0x7 #define _RXF9SIDH_SID10_POSITION 0x7 #define _RXF9SIDH_SID10_SIZE 0x1 #define _RXF9SIDH_SID10_LENGTH 0x1 #define _RXF9SIDH_SID10_MASK 0x80 #define _RXF9SIDH_RXF9SID3_POSN 0x0 #define _RXF9SIDH_RXF9SID3_POSITION 0x0 #define _RXF9SIDH_RXF9SID3_SIZE 0x1 #define _RXF9SIDH_RXF9SID3_LENGTH 0x1 #define _RXF9SIDH_RXF9SID3_MASK 0x1 #define _RXF9SIDH_RXF9SID4_POSN 0x1 #define _RXF9SIDH_RXF9SID4_POSITION 0x1 #define _RXF9SIDH_RXF9SID4_SIZE 0x1 #define _RXF9SIDH_RXF9SID4_LENGTH 0x1 #define _RXF9SIDH_RXF9SID4_MASK 0x2 #define _RXF9SIDH_RXF9SID5_POSN 0x2 #define _RXF9SIDH_RXF9SID5_POSITION 0x2 #define _RXF9SIDH_RXF9SID5_SIZE 0x1 #define _RXF9SIDH_RXF9SID5_LENGTH 0x1 #define _RXF9SIDH_RXF9SID5_MASK 0x4 #define _RXF9SIDH_RXF9SID6_POSN 0x3 #define _RXF9SIDH_RXF9SID6_POSITION 0x3 #define _RXF9SIDH_RXF9SID6_SIZE 0x1 #define _RXF9SIDH_RXF9SID6_LENGTH 0x1 #define _RXF9SIDH_RXF9SID6_MASK 0x8 #define _RXF9SIDH_RXF9SID7_POSN 0x4 #define _RXF9SIDH_RXF9SID7_POSITION 0x4 #define _RXF9SIDH_RXF9SID7_SIZE 0x1 #define _RXF9SIDH_RXF9SID7_LENGTH 0x1 #define _RXF9SIDH_RXF9SID7_MASK 0x10 #define _RXF9SIDH_RXF9SID8_POSN 0x5 #define _RXF9SIDH_RXF9SID8_POSITION 0x5 #define _RXF9SIDH_RXF9SID8_SIZE 0x1 #define _RXF9SIDH_RXF9SID8_LENGTH 0x1 #define _RXF9SIDH_RXF9SID8_MASK 0x20 #define _RXF9SIDH_RXF9SID9_POSN 0x6 #define _RXF9SIDH_RXF9SID9_POSITION 0x6 #define _RXF9SIDH_RXF9SID9_SIZE 0x1 #define _RXF9SIDH_RXF9SID9_LENGTH 0x1 #define _RXF9SIDH_RXF9SID9_MASK 0x40 #define _RXF9SIDH_RXF9SID10_POSN 0x7 #define _RXF9SIDH_RXF9SID10_POSITION 0x7 #define _RXF9SIDH_RXF9SID10_SIZE 0x1 #define _RXF9SIDH_RXF9SID10_LENGTH 0x1 #define _RXF9SIDH_RXF9SID10_MASK 0x80 // Register: RXF9SIDL #define RXF9SIDL RXF9SIDL extern volatile unsigned char RXF9SIDL @ 0xE55; #ifndef _LIB_BUILD asm("RXF9SIDL equ 0E55h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF9EID16 :1; unsigned RXF9EID17 :1; unsigned :1; unsigned RXF9EXIDEN :1; unsigned :1; unsigned RXF9SID0 :1; unsigned RXF9SID1 :1; unsigned RXF9SID2 :1; }; } RXF9SIDLbits_t; extern volatile RXF9SIDLbits_t RXF9SIDLbits @ 0xE55; // bitfield macros #define _RXF9SIDL_EID_POSN 0x0 #define _RXF9SIDL_EID_POSITION 0x0 #define _RXF9SIDL_EID_SIZE 0x2 #define _RXF9SIDL_EID_LENGTH 0x2 #define _RXF9SIDL_EID_MASK 0x3 #define _RXF9SIDL_EXIDEN_POSN 0x3 #define _RXF9SIDL_EXIDEN_POSITION 0x3 #define _RXF9SIDL_EXIDEN_SIZE 0x1 #define _RXF9SIDL_EXIDEN_LENGTH 0x1 #define _RXF9SIDL_EXIDEN_MASK 0x8 #define _RXF9SIDL_SID_POSN 0x5 #define _RXF9SIDL_SID_POSITION 0x5 #define _RXF9SIDL_SID_SIZE 0x3 #define _RXF9SIDL_SID_LENGTH 0x3 #define _RXF9SIDL_SID_MASK 0xE0 #define _RXF9SIDL_EID16_POSN 0x0 #define _RXF9SIDL_EID16_POSITION 0x0 #define _RXF9SIDL_EID16_SIZE 0x1 #define _RXF9SIDL_EID16_LENGTH 0x1 #define _RXF9SIDL_EID16_MASK 0x1 #define _RXF9SIDL_EID17_POSN 0x1 #define _RXF9SIDL_EID17_POSITION 0x1 #define _RXF9SIDL_EID17_SIZE 0x1 #define _RXF9SIDL_EID17_LENGTH 0x1 #define _RXF9SIDL_EID17_MASK 0x2 #define _RXF9SIDL_SID0_POSN 0x5 #define _RXF9SIDL_SID0_POSITION 0x5 #define _RXF9SIDL_SID0_SIZE 0x1 #define _RXF9SIDL_SID0_LENGTH 0x1 #define _RXF9SIDL_SID0_MASK 0x20 #define _RXF9SIDL_SID1_POSN 0x6 #define _RXF9SIDL_SID1_POSITION 0x6 #define _RXF9SIDL_SID1_SIZE 0x1 #define _RXF9SIDL_SID1_LENGTH 0x1 #define _RXF9SIDL_SID1_MASK 0x40 #define _RXF9SIDL_SID2_POSN 0x7 #define _RXF9SIDL_SID2_POSITION 0x7 #define _RXF9SIDL_SID2_SIZE 0x1 #define _RXF9SIDL_SID2_LENGTH 0x1 #define _RXF9SIDL_SID2_MASK 0x80 #define _RXF9SIDL_RXF9EID16_POSN 0x0 #define _RXF9SIDL_RXF9EID16_POSITION 0x0 #define _RXF9SIDL_RXF9EID16_SIZE 0x1 #define _RXF9SIDL_RXF9EID16_LENGTH 0x1 #define _RXF9SIDL_RXF9EID16_MASK 0x1 #define _RXF9SIDL_RXF9EID17_POSN 0x1 #define _RXF9SIDL_RXF9EID17_POSITION 0x1 #define _RXF9SIDL_RXF9EID17_SIZE 0x1 #define _RXF9SIDL_RXF9EID17_LENGTH 0x1 #define _RXF9SIDL_RXF9EID17_MASK 0x2 #define _RXF9SIDL_RXF9EXIDEN_POSN 0x3 #define _RXF9SIDL_RXF9EXIDEN_POSITION 0x3 #define _RXF9SIDL_RXF9EXIDEN_SIZE 0x1 #define _RXF9SIDL_RXF9EXIDEN_LENGTH 0x1 #define _RXF9SIDL_RXF9EXIDEN_MASK 0x8 #define _RXF9SIDL_RXF9SID0_POSN 0x5 #define _RXF9SIDL_RXF9SID0_POSITION 0x5 #define _RXF9SIDL_RXF9SID0_SIZE 0x1 #define _RXF9SIDL_RXF9SID0_LENGTH 0x1 #define _RXF9SIDL_RXF9SID0_MASK 0x20 #define _RXF9SIDL_RXF9SID1_POSN 0x6 #define _RXF9SIDL_RXF9SID1_POSITION 0x6 #define _RXF9SIDL_RXF9SID1_SIZE 0x1 #define _RXF9SIDL_RXF9SID1_LENGTH 0x1 #define _RXF9SIDL_RXF9SID1_MASK 0x40 #define _RXF9SIDL_RXF9SID2_POSN 0x7 #define _RXF9SIDL_RXF9SID2_POSITION 0x7 #define _RXF9SIDL_RXF9SID2_SIZE 0x1 #define _RXF9SIDL_RXF9SID2_LENGTH 0x1 #define _RXF9SIDL_RXF9SID2_MASK 0x80 // Register: RXF9EIDH #define RXF9EIDH RXF9EIDH extern volatile unsigned char RXF9EIDH @ 0xE56; #ifndef _LIB_BUILD asm("RXF9EIDH equ 0E56h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF9EID8 :1; unsigned RXF9EID9 :1; unsigned RXF9EID10 :1; unsigned RXF9EID11 :1; unsigned RXF9EID12 :1; unsigned RXF9EID13 :1; unsigned RXF9EID14 :1; unsigned RXF9EID15 :1; }; } RXF9EIDHbits_t; extern volatile RXF9EIDHbits_t RXF9EIDHbits @ 0xE56; // bitfield macros #define _RXF9EIDH_EID_POSN 0x0 #define _RXF9EIDH_EID_POSITION 0x0 #define _RXF9EIDH_EID_SIZE 0x8 #define _RXF9EIDH_EID_LENGTH 0x8 #define _RXF9EIDH_EID_MASK 0xFF #define _RXF9EIDH_EID8_POSN 0x0 #define _RXF9EIDH_EID8_POSITION 0x0 #define _RXF9EIDH_EID8_SIZE 0x1 #define _RXF9EIDH_EID8_LENGTH 0x1 #define _RXF9EIDH_EID8_MASK 0x1 #define _RXF9EIDH_EID9_POSN 0x1 #define _RXF9EIDH_EID9_POSITION 0x1 #define _RXF9EIDH_EID9_SIZE 0x1 #define _RXF9EIDH_EID9_LENGTH 0x1 #define _RXF9EIDH_EID9_MASK 0x2 #define _RXF9EIDH_EID10_POSN 0x2 #define _RXF9EIDH_EID10_POSITION 0x2 #define _RXF9EIDH_EID10_SIZE 0x1 #define _RXF9EIDH_EID10_LENGTH 0x1 #define _RXF9EIDH_EID10_MASK 0x4 #define _RXF9EIDH_EID11_POSN 0x3 #define _RXF9EIDH_EID11_POSITION 0x3 #define _RXF9EIDH_EID11_SIZE 0x1 #define _RXF9EIDH_EID11_LENGTH 0x1 #define _RXF9EIDH_EID11_MASK 0x8 #define _RXF9EIDH_EID12_POSN 0x4 #define _RXF9EIDH_EID12_POSITION 0x4 #define _RXF9EIDH_EID12_SIZE 0x1 #define _RXF9EIDH_EID12_LENGTH 0x1 #define _RXF9EIDH_EID12_MASK 0x10 #define _RXF9EIDH_EID13_POSN 0x5 #define _RXF9EIDH_EID13_POSITION 0x5 #define _RXF9EIDH_EID13_SIZE 0x1 #define _RXF9EIDH_EID13_LENGTH 0x1 #define _RXF9EIDH_EID13_MASK 0x20 #define _RXF9EIDH_EID14_POSN 0x6 #define _RXF9EIDH_EID14_POSITION 0x6 #define _RXF9EIDH_EID14_SIZE 0x1 #define _RXF9EIDH_EID14_LENGTH 0x1 #define _RXF9EIDH_EID14_MASK 0x40 #define _RXF9EIDH_EID15_POSN 0x7 #define _RXF9EIDH_EID15_POSITION 0x7 #define _RXF9EIDH_EID15_SIZE 0x1 #define _RXF9EIDH_EID15_LENGTH 0x1 #define _RXF9EIDH_EID15_MASK 0x80 #define _RXF9EIDH_RXF9EID8_POSN 0x0 #define _RXF9EIDH_RXF9EID8_POSITION 0x0 #define _RXF9EIDH_RXF9EID8_SIZE 0x1 #define _RXF9EIDH_RXF9EID8_LENGTH 0x1 #define _RXF9EIDH_RXF9EID8_MASK 0x1 #define _RXF9EIDH_RXF9EID9_POSN 0x1 #define _RXF9EIDH_RXF9EID9_POSITION 0x1 #define _RXF9EIDH_RXF9EID9_SIZE 0x1 #define _RXF9EIDH_RXF9EID9_LENGTH 0x1 #define _RXF9EIDH_RXF9EID9_MASK 0x2 #define _RXF9EIDH_RXF9EID10_POSN 0x2 #define _RXF9EIDH_RXF9EID10_POSITION 0x2 #define _RXF9EIDH_RXF9EID10_SIZE 0x1 #define _RXF9EIDH_RXF9EID10_LENGTH 0x1 #define _RXF9EIDH_RXF9EID10_MASK 0x4 #define _RXF9EIDH_RXF9EID11_POSN 0x3 #define _RXF9EIDH_RXF9EID11_POSITION 0x3 #define _RXF9EIDH_RXF9EID11_SIZE 0x1 #define _RXF9EIDH_RXF9EID11_LENGTH 0x1 #define _RXF9EIDH_RXF9EID11_MASK 0x8 #define _RXF9EIDH_RXF9EID12_POSN 0x4 #define _RXF9EIDH_RXF9EID12_POSITION 0x4 #define _RXF9EIDH_RXF9EID12_SIZE 0x1 #define _RXF9EIDH_RXF9EID12_LENGTH 0x1 #define _RXF9EIDH_RXF9EID12_MASK 0x10 #define _RXF9EIDH_RXF9EID13_POSN 0x5 #define _RXF9EIDH_RXF9EID13_POSITION 0x5 #define _RXF9EIDH_RXF9EID13_SIZE 0x1 #define _RXF9EIDH_RXF9EID13_LENGTH 0x1 #define _RXF9EIDH_RXF9EID13_MASK 0x20 #define _RXF9EIDH_RXF9EID14_POSN 0x6 #define _RXF9EIDH_RXF9EID14_POSITION 0x6 #define _RXF9EIDH_RXF9EID14_SIZE 0x1 #define _RXF9EIDH_RXF9EID14_LENGTH 0x1 #define _RXF9EIDH_RXF9EID14_MASK 0x40 #define _RXF9EIDH_RXF9EID15_POSN 0x7 #define _RXF9EIDH_RXF9EID15_POSITION 0x7 #define _RXF9EIDH_RXF9EID15_SIZE 0x1 #define _RXF9EIDH_RXF9EID15_LENGTH 0x1 #define _RXF9EIDH_RXF9EID15_MASK 0x80 // Register: RXF9EIDL #define RXF9EIDL RXF9EIDL extern volatile unsigned char RXF9EIDL @ 0xE57; #ifndef _LIB_BUILD asm("RXF9EIDL equ 0E57h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF9EID0 :1; unsigned RXF9EID1 :1; unsigned RXF9EID2 :1; unsigned RXF9EID3 :1; unsigned RXF9EID4 :1; unsigned RXF9EID5 :1; unsigned RXF9EID6 :1; unsigned RXF9EID7 :1; }; } RXF9EIDLbits_t; extern volatile RXF9EIDLbits_t RXF9EIDLbits @ 0xE57; // bitfield macros #define _RXF9EIDL_EID_POSN 0x0 #define _RXF9EIDL_EID_POSITION 0x0 #define _RXF9EIDL_EID_SIZE 0x8 #define _RXF9EIDL_EID_LENGTH 0x8 #define _RXF9EIDL_EID_MASK 0xFF #define _RXF9EIDL_EID0_POSN 0x0 #define _RXF9EIDL_EID0_POSITION 0x0 #define _RXF9EIDL_EID0_SIZE 0x1 #define _RXF9EIDL_EID0_LENGTH 0x1 #define _RXF9EIDL_EID0_MASK 0x1 #define _RXF9EIDL_EID1_POSN 0x1 #define _RXF9EIDL_EID1_POSITION 0x1 #define _RXF9EIDL_EID1_SIZE 0x1 #define _RXF9EIDL_EID1_LENGTH 0x1 #define _RXF9EIDL_EID1_MASK 0x2 #define _RXF9EIDL_EID2_POSN 0x2 #define _RXF9EIDL_EID2_POSITION 0x2 #define _RXF9EIDL_EID2_SIZE 0x1 #define _RXF9EIDL_EID2_LENGTH 0x1 #define _RXF9EIDL_EID2_MASK 0x4 #define _RXF9EIDL_EID3_POSN 0x3 #define _RXF9EIDL_EID3_POSITION 0x3 #define _RXF9EIDL_EID3_SIZE 0x1 #define _RXF9EIDL_EID3_LENGTH 0x1 #define _RXF9EIDL_EID3_MASK 0x8 #define _RXF9EIDL_EID4_POSN 0x4 #define _RXF9EIDL_EID4_POSITION 0x4 #define _RXF9EIDL_EID4_SIZE 0x1 #define _RXF9EIDL_EID4_LENGTH 0x1 #define _RXF9EIDL_EID4_MASK 0x10 #define _RXF9EIDL_EID5_POSN 0x5 #define _RXF9EIDL_EID5_POSITION 0x5 #define _RXF9EIDL_EID5_SIZE 0x1 #define _RXF9EIDL_EID5_LENGTH 0x1 #define _RXF9EIDL_EID5_MASK 0x20 #define _RXF9EIDL_EID6_POSN 0x6 #define _RXF9EIDL_EID6_POSITION 0x6 #define _RXF9EIDL_EID6_SIZE 0x1 #define _RXF9EIDL_EID6_LENGTH 0x1 #define _RXF9EIDL_EID6_MASK 0x40 #define _RXF9EIDL_EID7_POSN 0x7 #define _RXF9EIDL_EID7_POSITION 0x7 #define _RXF9EIDL_EID7_SIZE 0x1 #define _RXF9EIDL_EID7_LENGTH 0x1 #define _RXF9EIDL_EID7_MASK 0x80 #define _RXF9EIDL_RXF9EID0_POSN 0x0 #define _RXF9EIDL_RXF9EID0_POSITION 0x0 #define _RXF9EIDL_RXF9EID0_SIZE 0x1 #define _RXF9EIDL_RXF9EID0_LENGTH 0x1 #define _RXF9EIDL_RXF9EID0_MASK 0x1 #define _RXF9EIDL_RXF9EID1_POSN 0x1 #define _RXF9EIDL_RXF9EID1_POSITION 0x1 #define _RXF9EIDL_RXF9EID1_SIZE 0x1 #define _RXF9EIDL_RXF9EID1_LENGTH 0x1 #define _RXF9EIDL_RXF9EID1_MASK 0x2 #define _RXF9EIDL_RXF9EID2_POSN 0x2 #define _RXF9EIDL_RXF9EID2_POSITION 0x2 #define _RXF9EIDL_RXF9EID2_SIZE 0x1 #define _RXF9EIDL_RXF9EID2_LENGTH 0x1 #define _RXF9EIDL_RXF9EID2_MASK 0x4 #define _RXF9EIDL_RXF9EID3_POSN 0x3 #define _RXF9EIDL_RXF9EID3_POSITION 0x3 #define _RXF9EIDL_RXF9EID3_SIZE 0x1 #define _RXF9EIDL_RXF9EID3_LENGTH 0x1 #define _RXF9EIDL_RXF9EID3_MASK 0x8 #define _RXF9EIDL_RXF9EID4_POSN 0x4 #define _RXF9EIDL_RXF9EID4_POSITION 0x4 #define _RXF9EIDL_RXF9EID4_SIZE 0x1 #define _RXF9EIDL_RXF9EID4_LENGTH 0x1 #define _RXF9EIDL_RXF9EID4_MASK 0x10 #define _RXF9EIDL_RXF9EID5_POSN 0x5 #define _RXF9EIDL_RXF9EID5_POSITION 0x5 #define _RXF9EIDL_RXF9EID5_SIZE 0x1 #define _RXF9EIDL_RXF9EID5_LENGTH 0x1 #define _RXF9EIDL_RXF9EID5_MASK 0x20 #define _RXF9EIDL_RXF9EID6_POSN 0x6 #define _RXF9EIDL_RXF9EID6_POSITION 0x6 #define _RXF9EIDL_RXF9EID6_SIZE 0x1 #define _RXF9EIDL_RXF9EID6_LENGTH 0x1 #define _RXF9EIDL_RXF9EID6_MASK 0x40 #define _RXF9EIDL_RXF9EID7_POSN 0x7 #define _RXF9EIDL_RXF9EID7_POSITION 0x7 #define _RXF9EIDL_RXF9EID7_SIZE 0x1 #define _RXF9EIDL_RXF9EID7_LENGTH 0x1 #define _RXF9EIDL_RXF9EID7_MASK 0x80 // Register: RXF10SIDH #define RXF10SIDH RXF10SIDH extern volatile unsigned char RXF10SIDH @ 0xE58; #ifndef _LIB_BUILD asm("RXF10SIDH equ 0E58h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF10SID3 :1; unsigned RXF10SID4 :1; unsigned RXF10SID5 :1; unsigned RXF10SID6 :1; unsigned RXF10SID7 :1; unsigned RXF10SID8 :1; unsigned RXF10SID9 :1; unsigned RXF10SID10 :1; }; } RXF10SIDHbits_t; extern volatile RXF10SIDHbits_t RXF10SIDHbits @ 0xE58; // bitfield macros #define _RXF10SIDH_SID_POSN 0x0 #define _RXF10SIDH_SID_POSITION 0x0 #define _RXF10SIDH_SID_SIZE 0x8 #define _RXF10SIDH_SID_LENGTH 0x8 #define _RXF10SIDH_SID_MASK 0xFF #define _RXF10SIDH_SID3_POSN 0x0 #define _RXF10SIDH_SID3_POSITION 0x0 #define _RXF10SIDH_SID3_SIZE 0x1 #define _RXF10SIDH_SID3_LENGTH 0x1 #define _RXF10SIDH_SID3_MASK 0x1 #define _RXF10SIDH_SID4_POSN 0x1 #define _RXF10SIDH_SID4_POSITION 0x1 #define _RXF10SIDH_SID4_SIZE 0x1 #define _RXF10SIDH_SID4_LENGTH 0x1 #define _RXF10SIDH_SID4_MASK 0x2 #define _RXF10SIDH_SID5_POSN 0x2 #define _RXF10SIDH_SID5_POSITION 0x2 #define _RXF10SIDH_SID5_SIZE 0x1 #define _RXF10SIDH_SID5_LENGTH 0x1 #define _RXF10SIDH_SID5_MASK 0x4 #define _RXF10SIDH_SID6_POSN 0x3 #define _RXF10SIDH_SID6_POSITION 0x3 #define _RXF10SIDH_SID6_SIZE 0x1 #define _RXF10SIDH_SID6_LENGTH 0x1 #define _RXF10SIDH_SID6_MASK 0x8 #define _RXF10SIDH_SID7_POSN 0x4 #define _RXF10SIDH_SID7_POSITION 0x4 #define _RXF10SIDH_SID7_SIZE 0x1 #define _RXF10SIDH_SID7_LENGTH 0x1 #define _RXF10SIDH_SID7_MASK 0x10 #define _RXF10SIDH_SID8_POSN 0x5 #define _RXF10SIDH_SID8_POSITION 0x5 #define _RXF10SIDH_SID8_SIZE 0x1 #define _RXF10SIDH_SID8_LENGTH 0x1 #define _RXF10SIDH_SID8_MASK 0x20 #define _RXF10SIDH_SID9_POSN 0x6 #define _RXF10SIDH_SID9_POSITION 0x6 #define _RXF10SIDH_SID9_SIZE 0x1 #define _RXF10SIDH_SID9_LENGTH 0x1 #define _RXF10SIDH_SID9_MASK 0x40 #define _RXF10SIDH_SID10_POSN 0x7 #define _RXF10SIDH_SID10_POSITION 0x7 #define _RXF10SIDH_SID10_SIZE 0x1 #define _RXF10SIDH_SID10_LENGTH 0x1 #define _RXF10SIDH_SID10_MASK 0x80 #define _RXF10SIDH_RXF10SID3_POSN 0x0 #define _RXF10SIDH_RXF10SID3_POSITION 0x0 #define _RXF10SIDH_RXF10SID3_SIZE 0x1 #define _RXF10SIDH_RXF10SID3_LENGTH 0x1 #define _RXF10SIDH_RXF10SID3_MASK 0x1 #define _RXF10SIDH_RXF10SID4_POSN 0x1 #define _RXF10SIDH_RXF10SID4_POSITION 0x1 #define _RXF10SIDH_RXF10SID4_SIZE 0x1 #define _RXF10SIDH_RXF10SID4_LENGTH 0x1 #define _RXF10SIDH_RXF10SID4_MASK 0x2 #define _RXF10SIDH_RXF10SID5_POSN 0x2 #define _RXF10SIDH_RXF10SID5_POSITION 0x2 #define _RXF10SIDH_RXF10SID5_SIZE 0x1 #define _RXF10SIDH_RXF10SID5_LENGTH 0x1 #define _RXF10SIDH_RXF10SID5_MASK 0x4 #define _RXF10SIDH_RXF10SID6_POSN 0x3 #define _RXF10SIDH_RXF10SID6_POSITION 0x3 #define _RXF10SIDH_RXF10SID6_SIZE 0x1 #define _RXF10SIDH_RXF10SID6_LENGTH 0x1 #define _RXF10SIDH_RXF10SID6_MASK 0x8 #define _RXF10SIDH_RXF10SID7_POSN 0x4 #define _RXF10SIDH_RXF10SID7_POSITION 0x4 #define _RXF10SIDH_RXF10SID7_SIZE 0x1 #define _RXF10SIDH_RXF10SID7_LENGTH 0x1 #define _RXF10SIDH_RXF10SID7_MASK 0x10 #define _RXF10SIDH_RXF10SID8_POSN 0x5 #define _RXF10SIDH_RXF10SID8_POSITION 0x5 #define _RXF10SIDH_RXF10SID8_SIZE 0x1 #define _RXF10SIDH_RXF10SID8_LENGTH 0x1 #define _RXF10SIDH_RXF10SID8_MASK 0x20 #define _RXF10SIDH_RXF10SID9_POSN 0x6 #define _RXF10SIDH_RXF10SID9_POSITION 0x6 #define _RXF10SIDH_RXF10SID9_SIZE 0x1 #define _RXF10SIDH_RXF10SID9_LENGTH 0x1 #define _RXF10SIDH_RXF10SID9_MASK 0x40 #define _RXF10SIDH_RXF10SID10_POSN 0x7 #define _RXF10SIDH_RXF10SID10_POSITION 0x7 #define _RXF10SIDH_RXF10SID10_SIZE 0x1 #define _RXF10SIDH_RXF10SID10_LENGTH 0x1 #define _RXF10SIDH_RXF10SID10_MASK 0x80 // Register: RXF10SIDL #define RXF10SIDL RXF10SIDL extern volatile unsigned char RXF10SIDL @ 0xE59; #ifndef _LIB_BUILD asm("RXF10SIDL equ 0E59h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF10EID16 :1; unsigned RXF10EID17 :1; unsigned :1; unsigned RXF10EXIDEN :1; unsigned :1; unsigned RXF10SID0 :1; unsigned RXF10SID1 :1; unsigned RXF10SID2 :1; }; } RXF10SIDLbits_t; extern volatile RXF10SIDLbits_t RXF10SIDLbits @ 0xE59; // bitfield macros #define _RXF10SIDL_EID_POSN 0x0 #define _RXF10SIDL_EID_POSITION 0x0 #define _RXF10SIDL_EID_SIZE 0x2 #define _RXF10SIDL_EID_LENGTH 0x2 #define _RXF10SIDL_EID_MASK 0x3 #define _RXF10SIDL_EXIDEN_POSN 0x3 #define _RXF10SIDL_EXIDEN_POSITION 0x3 #define _RXF10SIDL_EXIDEN_SIZE 0x1 #define _RXF10SIDL_EXIDEN_LENGTH 0x1 #define _RXF10SIDL_EXIDEN_MASK 0x8 #define _RXF10SIDL_SID_POSN 0x5 #define _RXF10SIDL_SID_POSITION 0x5 #define _RXF10SIDL_SID_SIZE 0x3 #define _RXF10SIDL_SID_LENGTH 0x3 #define _RXF10SIDL_SID_MASK 0xE0 #define _RXF10SIDL_EID16_POSN 0x0 #define _RXF10SIDL_EID16_POSITION 0x0 #define _RXF10SIDL_EID16_SIZE 0x1 #define _RXF10SIDL_EID16_LENGTH 0x1 #define _RXF10SIDL_EID16_MASK 0x1 #define _RXF10SIDL_EID17_POSN 0x1 #define _RXF10SIDL_EID17_POSITION 0x1 #define _RXF10SIDL_EID17_SIZE 0x1 #define _RXF10SIDL_EID17_LENGTH 0x1 #define _RXF10SIDL_EID17_MASK 0x2 #define _RXF10SIDL_SID0_POSN 0x5 #define _RXF10SIDL_SID0_POSITION 0x5 #define _RXF10SIDL_SID0_SIZE 0x1 #define _RXF10SIDL_SID0_LENGTH 0x1 #define _RXF10SIDL_SID0_MASK 0x20 #define _RXF10SIDL_SID1_POSN 0x6 #define _RXF10SIDL_SID1_POSITION 0x6 #define _RXF10SIDL_SID1_SIZE 0x1 #define _RXF10SIDL_SID1_LENGTH 0x1 #define _RXF10SIDL_SID1_MASK 0x40 #define _RXF10SIDL_SID2_POSN 0x7 #define _RXF10SIDL_SID2_POSITION 0x7 #define _RXF10SIDL_SID2_SIZE 0x1 #define _RXF10SIDL_SID2_LENGTH 0x1 #define _RXF10SIDL_SID2_MASK 0x80 #define _RXF10SIDL_RXF10EID16_POSN 0x0 #define _RXF10SIDL_RXF10EID16_POSITION 0x0 #define _RXF10SIDL_RXF10EID16_SIZE 0x1 #define _RXF10SIDL_RXF10EID16_LENGTH 0x1 #define _RXF10SIDL_RXF10EID16_MASK 0x1 #define _RXF10SIDL_RXF10EID17_POSN 0x1 #define _RXF10SIDL_RXF10EID17_POSITION 0x1 #define _RXF10SIDL_RXF10EID17_SIZE 0x1 #define _RXF10SIDL_RXF10EID17_LENGTH 0x1 #define _RXF10SIDL_RXF10EID17_MASK 0x2 #define _RXF10SIDL_RXF10EXIDEN_POSN 0x3 #define _RXF10SIDL_RXF10EXIDEN_POSITION 0x3 #define _RXF10SIDL_RXF10EXIDEN_SIZE 0x1 #define _RXF10SIDL_RXF10EXIDEN_LENGTH 0x1 #define _RXF10SIDL_RXF10EXIDEN_MASK 0x8 #define _RXF10SIDL_RXF10SID0_POSN 0x5 #define _RXF10SIDL_RXF10SID0_POSITION 0x5 #define _RXF10SIDL_RXF10SID0_SIZE 0x1 #define _RXF10SIDL_RXF10SID0_LENGTH 0x1 #define _RXF10SIDL_RXF10SID0_MASK 0x20 #define _RXF10SIDL_RXF10SID1_POSN 0x6 #define _RXF10SIDL_RXF10SID1_POSITION 0x6 #define _RXF10SIDL_RXF10SID1_SIZE 0x1 #define _RXF10SIDL_RXF10SID1_LENGTH 0x1 #define _RXF10SIDL_RXF10SID1_MASK 0x40 #define _RXF10SIDL_RXF10SID2_POSN 0x7 #define _RXF10SIDL_RXF10SID2_POSITION 0x7 #define _RXF10SIDL_RXF10SID2_SIZE 0x1 #define _RXF10SIDL_RXF10SID2_LENGTH 0x1 #define _RXF10SIDL_RXF10SID2_MASK 0x80 // Register: RXF10EIDH #define RXF10EIDH RXF10EIDH extern volatile unsigned char RXF10EIDH @ 0xE5A; #ifndef _LIB_BUILD asm("RXF10EIDH equ 0E5Ah"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF10EID8 :1; unsigned RXF10EID9 :1; unsigned RXF10EID10 :1; unsigned RXF10EID11 :1; unsigned RXF10EID12 :1; unsigned RXF10EID13 :1; unsigned RXF10EID14 :1; unsigned RXF10EID15 :1; }; } RXF10EIDHbits_t; extern volatile RXF10EIDHbits_t RXF10EIDHbits @ 0xE5A; // bitfield macros #define _RXF10EIDH_EID_POSN 0x0 #define _RXF10EIDH_EID_POSITION 0x0 #define _RXF10EIDH_EID_SIZE 0x8 #define _RXF10EIDH_EID_LENGTH 0x8 #define _RXF10EIDH_EID_MASK 0xFF #define _RXF10EIDH_EID8_POSN 0x0 #define _RXF10EIDH_EID8_POSITION 0x0 #define _RXF10EIDH_EID8_SIZE 0x1 #define _RXF10EIDH_EID8_LENGTH 0x1 #define _RXF10EIDH_EID8_MASK 0x1 #define _RXF10EIDH_EID9_POSN 0x1 #define _RXF10EIDH_EID9_POSITION 0x1 #define _RXF10EIDH_EID9_SIZE 0x1 #define _RXF10EIDH_EID9_LENGTH 0x1 #define _RXF10EIDH_EID9_MASK 0x2 #define _RXF10EIDH_EID10_POSN 0x2 #define _RXF10EIDH_EID10_POSITION 0x2 #define _RXF10EIDH_EID10_SIZE 0x1 #define _RXF10EIDH_EID10_LENGTH 0x1 #define _RXF10EIDH_EID10_MASK 0x4 #define _RXF10EIDH_EID11_POSN 0x3 #define _RXF10EIDH_EID11_POSITION 0x3 #define _RXF10EIDH_EID11_SIZE 0x1 #define _RXF10EIDH_EID11_LENGTH 0x1 #define _RXF10EIDH_EID11_MASK 0x8 #define _RXF10EIDH_EID12_POSN 0x4 #define _RXF10EIDH_EID12_POSITION 0x4 #define _RXF10EIDH_EID12_SIZE 0x1 #define _RXF10EIDH_EID12_LENGTH 0x1 #define _RXF10EIDH_EID12_MASK 0x10 #define _RXF10EIDH_EID13_POSN 0x5 #define _RXF10EIDH_EID13_POSITION 0x5 #define _RXF10EIDH_EID13_SIZE 0x1 #define _RXF10EIDH_EID13_LENGTH 0x1 #define _RXF10EIDH_EID13_MASK 0x20 #define _RXF10EIDH_EID14_POSN 0x6 #define _RXF10EIDH_EID14_POSITION 0x6 #define _RXF10EIDH_EID14_SIZE 0x1 #define _RXF10EIDH_EID14_LENGTH 0x1 #define _RXF10EIDH_EID14_MASK 0x40 #define _RXF10EIDH_EID15_POSN 0x7 #define _RXF10EIDH_EID15_POSITION 0x7 #define _RXF10EIDH_EID15_SIZE 0x1 #define _RXF10EIDH_EID15_LENGTH 0x1 #define _RXF10EIDH_EID15_MASK 0x80 #define _RXF10EIDH_RXF10EID8_POSN 0x0 #define _RXF10EIDH_RXF10EID8_POSITION 0x0 #define _RXF10EIDH_RXF10EID8_SIZE 0x1 #define _RXF10EIDH_RXF10EID8_LENGTH 0x1 #define _RXF10EIDH_RXF10EID8_MASK 0x1 #define _RXF10EIDH_RXF10EID9_POSN 0x1 #define _RXF10EIDH_RXF10EID9_POSITION 0x1 #define _RXF10EIDH_RXF10EID9_SIZE 0x1 #define _RXF10EIDH_RXF10EID9_LENGTH 0x1 #define _RXF10EIDH_RXF10EID9_MASK 0x2 #define _RXF10EIDH_RXF10EID10_POSN 0x2 #define _RXF10EIDH_RXF10EID10_POSITION 0x2 #define _RXF10EIDH_RXF10EID10_SIZE 0x1 #define _RXF10EIDH_RXF10EID10_LENGTH 0x1 #define _RXF10EIDH_RXF10EID10_MASK 0x4 #define _RXF10EIDH_RXF10EID11_POSN 0x3 #define _RXF10EIDH_RXF10EID11_POSITION 0x3 #define _RXF10EIDH_RXF10EID11_SIZE 0x1 #define _RXF10EIDH_RXF10EID11_LENGTH 0x1 #define _RXF10EIDH_RXF10EID11_MASK 0x8 #define _RXF10EIDH_RXF10EID12_POSN 0x4 #define _RXF10EIDH_RXF10EID12_POSITION 0x4 #define _RXF10EIDH_RXF10EID12_SIZE 0x1 #define _RXF10EIDH_RXF10EID12_LENGTH 0x1 #define _RXF10EIDH_RXF10EID12_MASK 0x10 #define _RXF10EIDH_RXF10EID13_POSN 0x5 #define _RXF10EIDH_RXF10EID13_POSITION 0x5 #define _RXF10EIDH_RXF10EID13_SIZE 0x1 #define _RXF10EIDH_RXF10EID13_LENGTH 0x1 #define _RXF10EIDH_RXF10EID13_MASK 0x20 #define _RXF10EIDH_RXF10EID14_POSN 0x6 #define _RXF10EIDH_RXF10EID14_POSITION 0x6 #define _RXF10EIDH_RXF10EID14_SIZE 0x1 #define _RXF10EIDH_RXF10EID14_LENGTH 0x1 #define _RXF10EIDH_RXF10EID14_MASK 0x40 #define _RXF10EIDH_RXF10EID15_POSN 0x7 #define _RXF10EIDH_RXF10EID15_POSITION 0x7 #define _RXF10EIDH_RXF10EID15_SIZE 0x1 #define _RXF10EIDH_RXF10EID15_LENGTH 0x1 #define _RXF10EIDH_RXF10EID15_MASK 0x80 // Register: RXF10EIDL #define RXF10EIDL RXF10EIDL extern volatile unsigned char RXF10EIDL @ 0xE5B; #ifndef _LIB_BUILD asm("RXF10EIDL equ 0E5Bh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF10EID0 :1; unsigned RXF10EID1 :1; unsigned RXF10EID2 :1; unsigned RXF10EID3 :1; unsigned RXF10EID4 :1; unsigned RXF10EID5 :1; unsigned RXF10EID6 :1; unsigned RXF10EID7 :1; }; } RXF10EIDLbits_t; extern volatile RXF10EIDLbits_t RXF10EIDLbits @ 0xE5B; // bitfield macros #define _RXF10EIDL_EID_POSN 0x0 #define _RXF10EIDL_EID_POSITION 0x0 #define _RXF10EIDL_EID_SIZE 0x8 #define _RXF10EIDL_EID_LENGTH 0x8 #define _RXF10EIDL_EID_MASK 0xFF #define _RXF10EIDL_EID0_POSN 0x0 #define _RXF10EIDL_EID0_POSITION 0x0 #define _RXF10EIDL_EID0_SIZE 0x1 #define _RXF10EIDL_EID0_LENGTH 0x1 #define _RXF10EIDL_EID0_MASK 0x1 #define _RXF10EIDL_EID1_POSN 0x1 #define _RXF10EIDL_EID1_POSITION 0x1 #define _RXF10EIDL_EID1_SIZE 0x1 #define _RXF10EIDL_EID1_LENGTH 0x1 #define _RXF10EIDL_EID1_MASK 0x2 #define _RXF10EIDL_EID2_POSN 0x2 #define _RXF10EIDL_EID2_POSITION 0x2 #define _RXF10EIDL_EID2_SIZE 0x1 #define _RXF10EIDL_EID2_LENGTH 0x1 #define _RXF10EIDL_EID2_MASK 0x4 #define _RXF10EIDL_EID3_POSN 0x3 #define _RXF10EIDL_EID3_POSITION 0x3 #define _RXF10EIDL_EID3_SIZE 0x1 #define _RXF10EIDL_EID3_LENGTH 0x1 #define _RXF10EIDL_EID3_MASK 0x8 #define _RXF10EIDL_EID4_POSN 0x4 #define _RXF10EIDL_EID4_POSITION 0x4 #define _RXF10EIDL_EID4_SIZE 0x1 #define _RXF10EIDL_EID4_LENGTH 0x1 #define _RXF10EIDL_EID4_MASK 0x10 #define _RXF10EIDL_EID5_POSN 0x5 #define _RXF10EIDL_EID5_POSITION 0x5 #define _RXF10EIDL_EID5_SIZE 0x1 #define _RXF10EIDL_EID5_LENGTH 0x1 #define _RXF10EIDL_EID5_MASK 0x20 #define _RXF10EIDL_EID6_POSN 0x6 #define _RXF10EIDL_EID6_POSITION 0x6 #define _RXF10EIDL_EID6_SIZE 0x1 #define _RXF10EIDL_EID6_LENGTH 0x1 #define _RXF10EIDL_EID6_MASK 0x40 #define _RXF10EIDL_EID7_POSN 0x7 #define _RXF10EIDL_EID7_POSITION 0x7 #define _RXF10EIDL_EID7_SIZE 0x1 #define _RXF10EIDL_EID7_LENGTH 0x1 #define _RXF10EIDL_EID7_MASK 0x80 #define _RXF10EIDL_RXF10EID0_POSN 0x0 #define _RXF10EIDL_RXF10EID0_POSITION 0x0 #define _RXF10EIDL_RXF10EID0_SIZE 0x1 #define _RXF10EIDL_RXF10EID0_LENGTH 0x1 #define _RXF10EIDL_RXF10EID0_MASK 0x1 #define _RXF10EIDL_RXF10EID1_POSN 0x1 #define _RXF10EIDL_RXF10EID1_POSITION 0x1 #define _RXF10EIDL_RXF10EID1_SIZE 0x1 #define _RXF10EIDL_RXF10EID1_LENGTH 0x1 #define _RXF10EIDL_RXF10EID1_MASK 0x2 #define _RXF10EIDL_RXF10EID2_POSN 0x2 #define _RXF10EIDL_RXF10EID2_POSITION 0x2 #define _RXF10EIDL_RXF10EID2_SIZE 0x1 #define _RXF10EIDL_RXF10EID2_LENGTH 0x1 #define _RXF10EIDL_RXF10EID2_MASK 0x4 #define _RXF10EIDL_RXF10EID3_POSN 0x3 #define _RXF10EIDL_RXF10EID3_POSITION 0x3 #define _RXF10EIDL_RXF10EID3_SIZE 0x1 #define _RXF10EIDL_RXF10EID3_LENGTH 0x1 #define _RXF10EIDL_RXF10EID3_MASK 0x8 #define _RXF10EIDL_RXF10EID4_POSN 0x4 #define _RXF10EIDL_RXF10EID4_POSITION 0x4 #define _RXF10EIDL_RXF10EID4_SIZE 0x1 #define _RXF10EIDL_RXF10EID4_LENGTH 0x1 #define _RXF10EIDL_RXF10EID4_MASK 0x10 #define _RXF10EIDL_RXF10EID5_POSN 0x5 #define _RXF10EIDL_RXF10EID5_POSITION 0x5 #define _RXF10EIDL_RXF10EID5_SIZE 0x1 #define _RXF10EIDL_RXF10EID5_LENGTH 0x1 #define _RXF10EIDL_RXF10EID5_MASK 0x20 #define _RXF10EIDL_RXF10EID6_POSN 0x6 #define _RXF10EIDL_RXF10EID6_POSITION 0x6 #define _RXF10EIDL_RXF10EID6_SIZE 0x1 #define _RXF10EIDL_RXF10EID6_LENGTH 0x1 #define _RXF10EIDL_RXF10EID6_MASK 0x40 #define _RXF10EIDL_RXF10EID7_POSN 0x7 #define _RXF10EIDL_RXF10EID7_POSITION 0x7 #define _RXF10EIDL_RXF10EID7_SIZE 0x1 #define _RXF10EIDL_RXF10EID7_LENGTH 0x1 #define _RXF10EIDL_RXF10EID7_MASK 0x80 // Register: RXF11SIDH #define RXF11SIDH RXF11SIDH extern volatile unsigned char RXF11SIDH @ 0xE5C; #ifndef _LIB_BUILD asm("RXF11SIDH equ 0E5Ch"); #endif // bitfield definitions typedef union { struct { unsigned RXFSID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF11SID3 :1; unsigned RXF11SID4 :1; unsigned RXF11SID5 :1; unsigned RXF11SID6 :1; unsigned RXF11SID7 :1; unsigned RXF11SID8 :1; unsigned RXF11SID9 :1; unsigned RXF11SID10 :1; }; } RXF11SIDHbits_t; extern volatile RXF11SIDHbits_t RXF11SIDHbits @ 0xE5C; // bitfield macros #define _RXF11SIDH_RXFSID_POSN 0x0 #define _RXF11SIDH_RXFSID_POSITION 0x0 #define _RXF11SIDH_RXFSID_SIZE 0x8 #define _RXF11SIDH_RXFSID_LENGTH 0x8 #define _RXF11SIDH_RXFSID_MASK 0xFF #define _RXF11SIDH_SID3_POSN 0x0 #define _RXF11SIDH_SID3_POSITION 0x0 #define _RXF11SIDH_SID3_SIZE 0x1 #define _RXF11SIDH_SID3_LENGTH 0x1 #define _RXF11SIDH_SID3_MASK 0x1 #define _RXF11SIDH_SID4_POSN 0x1 #define _RXF11SIDH_SID4_POSITION 0x1 #define _RXF11SIDH_SID4_SIZE 0x1 #define _RXF11SIDH_SID4_LENGTH 0x1 #define _RXF11SIDH_SID4_MASK 0x2 #define _RXF11SIDH_SID5_POSN 0x2 #define _RXF11SIDH_SID5_POSITION 0x2 #define _RXF11SIDH_SID5_SIZE 0x1 #define _RXF11SIDH_SID5_LENGTH 0x1 #define _RXF11SIDH_SID5_MASK 0x4 #define _RXF11SIDH_SID6_POSN 0x3 #define _RXF11SIDH_SID6_POSITION 0x3 #define _RXF11SIDH_SID6_SIZE 0x1 #define _RXF11SIDH_SID6_LENGTH 0x1 #define _RXF11SIDH_SID6_MASK 0x8 #define _RXF11SIDH_SID7_POSN 0x4 #define _RXF11SIDH_SID7_POSITION 0x4 #define _RXF11SIDH_SID7_SIZE 0x1 #define _RXF11SIDH_SID7_LENGTH 0x1 #define _RXF11SIDH_SID7_MASK 0x10 #define _RXF11SIDH_SID8_POSN 0x5 #define _RXF11SIDH_SID8_POSITION 0x5 #define _RXF11SIDH_SID8_SIZE 0x1 #define _RXF11SIDH_SID8_LENGTH 0x1 #define _RXF11SIDH_SID8_MASK 0x20 #define _RXF11SIDH_SID9_POSN 0x6 #define _RXF11SIDH_SID9_POSITION 0x6 #define _RXF11SIDH_SID9_SIZE 0x1 #define _RXF11SIDH_SID9_LENGTH 0x1 #define _RXF11SIDH_SID9_MASK 0x40 #define _RXF11SIDH_SID10_POSN 0x7 #define _RXF11SIDH_SID10_POSITION 0x7 #define _RXF11SIDH_SID10_SIZE 0x1 #define _RXF11SIDH_SID10_LENGTH 0x1 #define _RXF11SIDH_SID10_MASK 0x80 #define _RXF11SIDH_RXF11SID3_POSN 0x0 #define _RXF11SIDH_RXF11SID3_POSITION 0x0 #define _RXF11SIDH_RXF11SID3_SIZE 0x1 #define _RXF11SIDH_RXF11SID3_LENGTH 0x1 #define _RXF11SIDH_RXF11SID3_MASK 0x1 #define _RXF11SIDH_RXF11SID4_POSN 0x1 #define _RXF11SIDH_RXF11SID4_POSITION 0x1 #define _RXF11SIDH_RXF11SID4_SIZE 0x1 #define _RXF11SIDH_RXF11SID4_LENGTH 0x1 #define _RXF11SIDH_RXF11SID4_MASK 0x2 #define _RXF11SIDH_RXF11SID5_POSN 0x2 #define _RXF11SIDH_RXF11SID5_POSITION 0x2 #define _RXF11SIDH_RXF11SID5_SIZE 0x1 #define _RXF11SIDH_RXF11SID5_LENGTH 0x1 #define _RXF11SIDH_RXF11SID5_MASK 0x4 #define _RXF11SIDH_RXF11SID6_POSN 0x3 #define _RXF11SIDH_RXF11SID6_POSITION 0x3 #define _RXF11SIDH_RXF11SID6_SIZE 0x1 #define _RXF11SIDH_RXF11SID6_LENGTH 0x1 #define _RXF11SIDH_RXF11SID6_MASK 0x8 #define _RXF11SIDH_RXF11SID7_POSN 0x4 #define _RXF11SIDH_RXF11SID7_POSITION 0x4 #define _RXF11SIDH_RXF11SID7_SIZE 0x1 #define _RXF11SIDH_RXF11SID7_LENGTH 0x1 #define _RXF11SIDH_RXF11SID7_MASK 0x10 #define _RXF11SIDH_RXF11SID8_POSN 0x5 #define _RXF11SIDH_RXF11SID8_POSITION 0x5 #define _RXF11SIDH_RXF11SID8_SIZE 0x1 #define _RXF11SIDH_RXF11SID8_LENGTH 0x1 #define _RXF11SIDH_RXF11SID8_MASK 0x20 #define _RXF11SIDH_RXF11SID9_POSN 0x6 #define _RXF11SIDH_RXF11SID9_POSITION 0x6 #define _RXF11SIDH_RXF11SID9_SIZE 0x1 #define _RXF11SIDH_RXF11SID9_LENGTH 0x1 #define _RXF11SIDH_RXF11SID9_MASK 0x40 #define _RXF11SIDH_RXF11SID10_POSN 0x7 #define _RXF11SIDH_RXF11SID10_POSITION 0x7 #define _RXF11SIDH_RXF11SID10_SIZE 0x1 #define _RXF11SIDH_RXF11SID10_LENGTH 0x1 #define _RXF11SIDH_RXF11SID10_MASK 0x80 // Register: RXF11SIDL #define RXF11SIDL RXF11SIDL extern volatile unsigned char RXF11SIDL @ 0xE5D; #ifndef _LIB_BUILD asm("RXF11SIDL equ 0E5Dh"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF11EID16 :1; unsigned RXF11EID17 :1; unsigned :1; unsigned RXF11EXIDEN :1; unsigned :1; unsigned RXF11SID0 :1; unsigned RXF11SID1 :1; unsigned RXF11SID2 :1; }; } RXF11SIDLbits_t; extern volatile RXF11SIDLbits_t RXF11SIDLbits @ 0xE5D; // bitfield macros #define _RXF11SIDL_EID_POSN 0x0 #define _RXF11SIDL_EID_POSITION 0x0 #define _RXF11SIDL_EID_SIZE 0x2 #define _RXF11SIDL_EID_LENGTH 0x2 #define _RXF11SIDL_EID_MASK 0x3 #define _RXF11SIDL_EXIDEN_POSN 0x3 #define _RXF11SIDL_EXIDEN_POSITION 0x3 #define _RXF11SIDL_EXIDEN_SIZE 0x1 #define _RXF11SIDL_EXIDEN_LENGTH 0x1 #define _RXF11SIDL_EXIDEN_MASK 0x8 #define _RXF11SIDL_SID_POSN 0x5 #define _RXF11SIDL_SID_POSITION 0x5 #define _RXF11SIDL_SID_SIZE 0x3 #define _RXF11SIDL_SID_LENGTH 0x3 #define _RXF11SIDL_SID_MASK 0xE0 #define _RXF11SIDL_EID16_POSN 0x0 #define _RXF11SIDL_EID16_POSITION 0x0 #define _RXF11SIDL_EID16_SIZE 0x1 #define _RXF11SIDL_EID16_LENGTH 0x1 #define _RXF11SIDL_EID16_MASK 0x1 #define _RXF11SIDL_EID17_POSN 0x1 #define _RXF11SIDL_EID17_POSITION 0x1 #define _RXF11SIDL_EID17_SIZE 0x1 #define _RXF11SIDL_EID17_LENGTH 0x1 #define _RXF11SIDL_EID17_MASK 0x2 #define _RXF11SIDL_SID0_POSN 0x5 #define _RXF11SIDL_SID0_POSITION 0x5 #define _RXF11SIDL_SID0_SIZE 0x1 #define _RXF11SIDL_SID0_LENGTH 0x1 #define _RXF11SIDL_SID0_MASK 0x20 #define _RXF11SIDL_SID1_POSN 0x6 #define _RXF11SIDL_SID1_POSITION 0x6 #define _RXF11SIDL_SID1_SIZE 0x1 #define _RXF11SIDL_SID1_LENGTH 0x1 #define _RXF11SIDL_SID1_MASK 0x40 #define _RXF11SIDL_SID2_POSN 0x7 #define _RXF11SIDL_SID2_POSITION 0x7 #define _RXF11SIDL_SID2_SIZE 0x1 #define _RXF11SIDL_SID2_LENGTH 0x1 #define _RXF11SIDL_SID2_MASK 0x80 #define _RXF11SIDL_RXF11EID16_POSN 0x0 #define _RXF11SIDL_RXF11EID16_POSITION 0x0 #define _RXF11SIDL_RXF11EID16_SIZE 0x1 #define _RXF11SIDL_RXF11EID16_LENGTH 0x1 #define _RXF11SIDL_RXF11EID16_MASK 0x1 #define _RXF11SIDL_RXF11EID17_POSN 0x1 #define _RXF11SIDL_RXF11EID17_POSITION 0x1 #define _RXF11SIDL_RXF11EID17_SIZE 0x1 #define _RXF11SIDL_RXF11EID17_LENGTH 0x1 #define _RXF11SIDL_RXF11EID17_MASK 0x2 #define _RXF11SIDL_RXF11EXIDEN_POSN 0x3 #define _RXF11SIDL_RXF11EXIDEN_POSITION 0x3 #define _RXF11SIDL_RXF11EXIDEN_SIZE 0x1 #define _RXF11SIDL_RXF11EXIDEN_LENGTH 0x1 #define _RXF11SIDL_RXF11EXIDEN_MASK 0x8 #define _RXF11SIDL_RXF11SID0_POSN 0x5 #define _RXF11SIDL_RXF11SID0_POSITION 0x5 #define _RXF11SIDL_RXF11SID0_SIZE 0x1 #define _RXF11SIDL_RXF11SID0_LENGTH 0x1 #define _RXF11SIDL_RXF11SID0_MASK 0x20 #define _RXF11SIDL_RXF11SID1_POSN 0x6 #define _RXF11SIDL_RXF11SID1_POSITION 0x6 #define _RXF11SIDL_RXF11SID1_SIZE 0x1 #define _RXF11SIDL_RXF11SID1_LENGTH 0x1 #define _RXF11SIDL_RXF11SID1_MASK 0x40 #define _RXF11SIDL_RXF11SID2_POSN 0x7 #define _RXF11SIDL_RXF11SID2_POSITION 0x7 #define _RXF11SIDL_RXF11SID2_SIZE 0x1 #define _RXF11SIDL_RXF11SID2_LENGTH 0x1 #define _RXF11SIDL_RXF11SID2_MASK 0x80 // Register: RXF11EIDH #define RXF11EIDH RXF11EIDH extern volatile unsigned char RXF11EIDH @ 0xE5E; #ifndef _LIB_BUILD asm("RXF11EIDH equ 0E5Eh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF11EID8 :1; unsigned RXF11EID9 :1; unsigned RXF11EID10 :1; unsigned RXF11EID11 :1; unsigned RXF11EID12 :1; unsigned RXF11EID13 :1; unsigned RXF11EID14 :1; unsigned RXF11EID15 :1; }; } RXF11EIDHbits_t; extern volatile RXF11EIDHbits_t RXF11EIDHbits @ 0xE5E; // bitfield macros #define _RXF11EIDH_EID_POSN 0x0 #define _RXF11EIDH_EID_POSITION 0x0 #define _RXF11EIDH_EID_SIZE 0x8 #define _RXF11EIDH_EID_LENGTH 0x8 #define _RXF11EIDH_EID_MASK 0xFF #define _RXF11EIDH_EID8_POSN 0x0 #define _RXF11EIDH_EID8_POSITION 0x0 #define _RXF11EIDH_EID8_SIZE 0x1 #define _RXF11EIDH_EID8_LENGTH 0x1 #define _RXF11EIDH_EID8_MASK 0x1 #define _RXF11EIDH_EID9_POSN 0x1 #define _RXF11EIDH_EID9_POSITION 0x1 #define _RXF11EIDH_EID9_SIZE 0x1 #define _RXF11EIDH_EID9_LENGTH 0x1 #define _RXF11EIDH_EID9_MASK 0x2 #define _RXF11EIDH_EID10_POSN 0x2 #define _RXF11EIDH_EID10_POSITION 0x2 #define _RXF11EIDH_EID10_SIZE 0x1 #define _RXF11EIDH_EID10_LENGTH 0x1 #define _RXF11EIDH_EID10_MASK 0x4 #define _RXF11EIDH_EID11_POSN 0x3 #define _RXF11EIDH_EID11_POSITION 0x3 #define _RXF11EIDH_EID11_SIZE 0x1 #define _RXF11EIDH_EID11_LENGTH 0x1 #define _RXF11EIDH_EID11_MASK 0x8 #define _RXF11EIDH_EID12_POSN 0x4 #define _RXF11EIDH_EID12_POSITION 0x4 #define _RXF11EIDH_EID12_SIZE 0x1 #define _RXF11EIDH_EID12_LENGTH 0x1 #define _RXF11EIDH_EID12_MASK 0x10 #define _RXF11EIDH_EID13_POSN 0x5 #define _RXF11EIDH_EID13_POSITION 0x5 #define _RXF11EIDH_EID13_SIZE 0x1 #define _RXF11EIDH_EID13_LENGTH 0x1 #define _RXF11EIDH_EID13_MASK 0x20 #define _RXF11EIDH_EID14_POSN 0x6 #define _RXF11EIDH_EID14_POSITION 0x6 #define _RXF11EIDH_EID14_SIZE 0x1 #define _RXF11EIDH_EID14_LENGTH 0x1 #define _RXF11EIDH_EID14_MASK 0x40 #define _RXF11EIDH_EID15_POSN 0x7 #define _RXF11EIDH_EID15_POSITION 0x7 #define _RXF11EIDH_EID15_SIZE 0x1 #define _RXF11EIDH_EID15_LENGTH 0x1 #define _RXF11EIDH_EID15_MASK 0x80 #define _RXF11EIDH_RXF11EID8_POSN 0x0 #define _RXF11EIDH_RXF11EID8_POSITION 0x0 #define _RXF11EIDH_RXF11EID8_SIZE 0x1 #define _RXF11EIDH_RXF11EID8_LENGTH 0x1 #define _RXF11EIDH_RXF11EID8_MASK 0x1 #define _RXF11EIDH_RXF11EID9_POSN 0x1 #define _RXF11EIDH_RXF11EID9_POSITION 0x1 #define _RXF11EIDH_RXF11EID9_SIZE 0x1 #define _RXF11EIDH_RXF11EID9_LENGTH 0x1 #define _RXF11EIDH_RXF11EID9_MASK 0x2 #define _RXF11EIDH_RXF11EID10_POSN 0x2 #define _RXF11EIDH_RXF11EID10_POSITION 0x2 #define _RXF11EIDH_RXF11EID10_SIZE 0x1 #define _RXF11EIDH_RXF11EID10_LENGTH 0x1 #define _RXF11EIDH_RXF11EID10_MASK 0x4 #define _RXF11EIDH_RXF11EID11_POSN 0x3 #define _RXF11EIDH_RXF11EID11_POSITION 0x3 #define _RXF11EIDH_RXF11EID11_SIZE 0x1 #define _RXF11EIDH_RXF11EID11_LENGTH 0x1 #define _RXF11EIDH_RXF11EID11_MASK 0x8 #define _RXF11EIDH_RXF11EID12_POSN 0x4 #define _RXF11EIDH_RXF11EID12_POSITION 0x4 #define _RXF11EIDH_RXF11EID12_SIZE 0x1 #define _RXF11EIDH_RXF11EID12_LENGTH 0x1 #define _RXF11EIDH_RXF11EID12_MASK 0x10 #define _RXF11EIDH_RXF11EID13_POSN 0x5 #define _RXF11EIDH_RXF11EID13_POSITION 0x5 #define _RXF11EIDH_RXF11EID13_SIZE 0x1 #define _RXF11EIDH_RXF11EID13_LENGTH 0x1 #define _RXF11EIDH_RXF11EID13_MASK 0x20 #define _RXF11EIDH_RXF11EID14_POSN 0x6 #define _RXF11EIDH_RXF11EID14_POSITION 0x6 #define _RXF11EIDH_RXF11EID14_SIZE 0x1 #define _RXF11EIDH_RXF11EID14_LENGTH 0x1 #define _RXF11EIDH_RXF11EID14_MASK 0x40 #define _RXF11EIDH_RXF11EID15_POSN 0x7 #define _RXF11EIDH_RXF11EID15_POSITION 0x7 #define _RXF11EIDH_RXF11EID15_SIZE 0x1 #define _RXF11EIDH_RXF11EID15_LENGTH 0x1 #define _RXF11EIDH_RXF11EID15_MASK 0x80 // Register: RXF11EIDL #define RXF11EIDL RXF11EIDL extern volatile unsigned char RXF11EIDL @ 0xE5F; #ifndef _LIB_BUILD asm("RXF11EIDL equ 0E5Fh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF11EID0 :1; unsigned RXF11EID1 :1; unsigned RXF11EID2 :1; unsigned RXF11EID3 :1; unsigned RXF11EID4 :1; unsigned RXF11EID5 :1; unsigned RXF11EID6 :1; unsigned RXF11EID7 :1; }; } RXF11EIDLbits_t; extern volatile RXF11EIDLbits_t RXF11EIDLbits @ 0xE5F; // bitfield macros #define _RXF11EIDL_EID_POSN 0x0 #define _RXF11EIDL_EID_POSITION 0x0 #define _RXF11EIDL_EID_SIZE 0x8 #define _RXF11EIDL_EID_LENGTH 0x8 #define _RXF11EIDL_EID_MASK 0xFF #define _RXF11EIDL_EID0_POSN 0x0 #define _RXF11EIDL_EID0_POSITION 0x0 #define _RXF11EIDL_EID0_SIZE 0x1 #define _RXF11EIDL_EID0_LENGTH 0x1 #define _RXF11EIDL_EID0_MASK 0x1 #define _RXF11EIDL_EID1_POSN 0x1 #define _RXF11EIDL_EID1_POSITION 0x1 #define _RXF11EIDL_EID1_SIZE 0x1 #define _RXF11EIDL_EID1_LENGTH 0x1 #define _RXF11EIDL_EID1_MASK 0x2 #define _RXF11EIDL_EID2_POSN 0x2 #define _RXF11EIDL_EID2_POSITION 0x2 #define _RXF11EIDL_EID2_SIZE 0x1 #define _RXF11EIDL_EID2_LENGTH 0x1 #define _RXF11EIDL_EID2_MASK 0x4 #define _RXF11EIDL_EID3_POSN 0x3 #define _RXF11EIDL_EID3_POSITION 0x3 #define _RXF11EIDL_EID3_SIZE 0x1 #define _RXF11EIDL_EID3_LENGTH 0x1 #define _RXF11EIDL_EID3_MASK 0x8 #define _RXF11EIDL_EID4_POSN 0x4 #define _RXF11EIDL_EID4_POSITION 0x4 #define _RXF11EIDL_EID4_SIZE 0x1 #define _RXF11EIDL_EID4_LENGTH 0x1 #define _RXF11EIDL_EID4_MASK 0x10 #define _RXF11EIDL_EID5_POSN 0x5 #define _RXF11EIDL_EID5_POSITION 0x5 #define _RXF11EIDL_EID5_SIZE 0x1 #define _RXF11EIDL_EID5_LENGTH 0x1 #define _RXF11EIDL_EID5_MASK 0x20 #define _RXF11EIDL_EID6_POSN 0x6 #define _RXF11EIDL_EID6_POSITION 0x6 #define _RXF11EIDL_EID6_SIZE 0x1 #define _RXF11EIDL_EID6_LENGTH 0x1 #define _RXF11EIDL_EID6_MASK 0x40 #define _RXF11EIDL_EID7_POSN 0x7 #define _RXF11EIDL_EID7_POSITION 0x7 #define _RXF11EIDL_EID7_SIZE 0x1 #define _RXF11EIDL_EID7_LENGTH 0x1 #define _RXF11EIDL_EID7_MASK 0x80 #define _RXF11EIDL_RXF11EID0_POSN 0x0 #define _RXF11EIDL_RXF11EID0_POSITION 0x0 #define _RXF11EIDL_RXF11EID0_SIZE 0x1 #define _RXF11EIDL_RXF11EID0_LENGTH 0x1 #define _RXF11EIDL_RXF11EID0_MASK 0x1 #define _RXF11EIDL_RXF11EID1_POSN 0x1 #define _RXF11EIDL_RXF11EID1_POSITION 0x1 #define _RXF11EIDL_RXF11EID1_SIZE 0x1 #define _RXF11EIDL_RXF11EID1_LENGTH 0x1 #define _RXF11EIDL_RXF11EID1_MASK 0x2 #define _RXF11EIDL_RXF11EID2_POSN 0x2 #define _RXF11EIDL_RXF11EID2_POSITION 0x2 #define _RXF11EIDL_RXF11EID2_SIZE 0x1 #define _RXF11EIDL_RXF11EID2_LENGTH 0x1 #define _RXF11EIDL_RXF11EID2_MASK 0x4 #define _RXF11EIDL_RXF11EID3_POSN 0x3 #define _RXF11EIDL_RXF11EID3_POSITION 0x3 #define _RXF11EIDL_RXF11EID3_SIZE 0x1 #define _RXF11EIDL_RXF11EID3_LENGTH 0x1 #define _RXF11EIDL_RXF11EID3_MASK 0x8 #define _RXF11EIDL_RXF11EID4_POSN 0x4 #define _RXF11EIDL_RXF11EID4_POSITION 0x4 #define _RXF11EIDL_RXF11EID4_SIZE 0x1 #define _RXF11EIDL_RXF11EID4_LENGTH 0x1 #define _RXF11EIDL_RXF11EID4_MASK 0x10 #define _RXF11EIDL_RXF11EID5_POSN 0x5 #define _RXF11EIDL_RXF11EID5_POSITION 0x5 #define _RXF11EIDL_RXF11EID5_SIZE 0x1 #define _RXF11EIDL_RXF11EID5_LENGTH 0x1 #define _RXF11EIDL_RXF11EID5_MASK 0x20 #define _RXF11EIDL_RXF11EID6_POSN 0x6 #define _RXF11EIDL_RXF11EID6_POSITION 0x6 #define _RXF11EIDL_RXF11EID6_SIZE 0x1 #define _RXF11EIDL_RXF11EID6_LENGTH 0x1 #define _RXF11EIDL_RXF11EID6_MASK 0x40 #define _RXF11EIDL_RXF11EID7_POSN 0x7 #define _RXF11EIDL_RXF11EID7_POSITION 0x7 #define _RXF11EIDL_RXF11EID7_SIZE 0x1 #define _RXF11EIDL_RXF11EID7_LENGTH 0x1 #define _RXF11EIDL_RXF11EID7_MASK 0x80 // Register: RXF12SIDH #define RXF12SIDH RXF12SIDH extern volatile unsigned char RXF12SIDH @ 0xE60; #ifndef _LIB_BUILD asm("RXF12SIDH equ 0E60h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF12SID3 :1; unsigned RXF12SID4 :1; unsigned RXF12SID5 :1; unsigned RXF12SID6 :1; unsigned RXF12SID7 :1; unsigned RXF12SID8 :1; unsigned RXF12SID9 :1; unsigned RXF12SID10 :1; }; } RXF12SIDHbits_t; extern volatile RXF12SIDHbits_t RXF12SIDHbits @ 0xE60; // bitfield macros #define _RXF12SIDH_SID_POSN 0x0 #define _RXF12SIDH_SID_POSITION 0x0 #define _RXF12SIDH_SID_SIZE 0x8 #define _RXF12SIDH_SID_LENGTH 0x8 #define _RXF12SIDH_SID_MASK 0xFF #define _RXF12SIDH_SID3_POSN 0x0 #define _RXF12SIDH_SID3_POSITION 0x0 #define _RXF12SIDH_SID3_SIZE 0x1 #define _RXF12SIDH_SID3_LENGTH 0x1 #define _RXF12SIDH_SID3_MASK 0x1 #define _RXF12SIDH_SID4_POSN 0x1 #define _RXF12SIDH_SID4_POSITION 0x1 #define _RXF12SIDH_SID4_SIZE 0x1 #define _RXF12SIDH_SID4_LENGTH 0x1 #define _RXF12SIDH_SID4_MASK 0x2 #define _RXF12SIDH_SID5_POSN 0x2 #define _RXF12SIDH_SID5_POSITION 0x2 #define _RXF12SIDH_SID5_SIZE 0x1 #define _RXF12SIDH_SID5_LENGTH 0x1 #define _RXF12SIDH_SID5_MASK 0x4 #define _RXF12SIDH_SID6_POSN 0x3 #define _RXF12SIDH_SID6_POSITION 0x3 #define _RXF12SIDH_SID6_SIZE 0x1 #define _RXF12SIDH_SID6_LENGTH 0x1 #define _RXF12SIDH_SID6_MASK 0x8 #define _RXF12SIDH_SID7_POSN 0x4 #define _RXF12SIDH_SID7_POSITION 0x4 #define _RXF12SIDH_SID7_SIZE 0x1 #define _RXF12SIDH_SID7_LENGTH 0x1 #define _RXF12SIDH_SID7_MASK 0x10 #define _RXF12SIDH_SID8_POSN 0x5 #define _RXF12SIDH_SID8_POSITION 0x5 #define _RXF12SIDH_SID8_SIZE 0x1 #define _RXF12SIDH_SID8_LENGTH 0x1 #define _RXF12SIDH_SID8_MASK 0x20 #define _RXF12SIDH_SID9_POSN 0x6 #define _RXF12SIDH_SID9_POSITION 0x6 #define _RXF12SIDH_SID9_SIZE 0x1 #define _RXF12SIDH_SID9_LENGTH 0x1 #define _RXF12SIDH_SID9_MASK 0x40 #define _RXF12SIDH_SID10_POSN 0x7 #define _RXF12SIDH_SID10_POSITION 0x7 #define _RXF12SIDH_SID10_SIZE 0x1 #define _RXF12SIDH_SID10_LENGTH 0x1 #define _RXF12SIDH_SID10_MASK 0x80 #define _RXF12SIDH_RXF12SID3_POSN 0x0 #define _RXF12SIDH_RXF12SID3_POSITION 0x0 #define _RXF12SIDH_RXF12SID3_SIZE 0x1 #define _RXF12SIDH_RXF12SID3_LENGTH 0x1 #define _RXF12SIDH_RXF12SID3_MASK 0x1 #define _RXF12SIDH_RXF12SID4_POSN 0x1 #define _RXF12SIDH_RXF12SID4_POSITION 0x1 #define _RXF12SIDH_RXF12SID4_SIZE 0x1 #define _RXF12SIDH_RXF12SID4_LENGTH 0x1 #define _RXF12SIDH_RXF12SID4_MASK 0x2 #define _RXF12SIDH_RXF12SID5_POSN 0x2 #define _RXF12SIDH_RXF12SID5_POSITION 0x2 #define _RXF12SIDH_RXF12SID5_SIZE 0x1 #define _RXF12SIDH_RXF12SID5_LENGTH 0x1 #define _RXF12SIDH_RXF12SID5_MASK 0x4 #define _RXF12SIDH_RXF12SID6_POSN 0x3 #define _RXF12SIDH_RXF12SID6_POSITION 0x3 #define _RXF12SIDH_RXF12SID6_SIZE 0x1 #define _RXF12SIDH_RXF12SID6_LENGTH 0x1 #define _RXF12SIDH_RXF12SID6_MASK 0x8 #define _RXF12SIDH_RXF12SID7_POSN 0x4 #define _RXF12SIDH_RXF12SID7_POSITION 0x4 #define _RXF12SIDH_RXF12SID7_SIZE 0x1 #define _RXF12SIDH_RXF12SID7_LENGTH 0x1 #define _RXF12SIDH_RXF12SID7_MASK 0x10 #define _RXF12SIDH_RXF12SID8_POSN 0x5 #define _RXF12SIDH_RXF12SID8_POSITION 0x5 #define _RXF12SIDH_RXF12SID8_SIZE 0x1 #define _RXF12SIDH_RXF12SID8_LENGTH 0x1 #define _RXF12SIDH_RXF12SID8_MASK 0x20 #define _RXF12SIDH_RXF12SID9_POSN 0x6 #define _RXF12SIDH_RXF12SID9_POSITION 0x6 #define _RXF12SIDH_RXF12SID9_SIZE 0x1 #define _RXF12SIDH_RXF12SID9_LENGTH 0x1 #define _RXF12SIDH_RXF12SID9_MASK 0x40 #define _RXF12SIDH_RXF12SID10_POSN 0x7 #define _RXF12SIDH_RXF12SID10_POSITION 0x7 #define _RXF12SIDH_RXF12SID10_SIZE 0x1 #define _RXF12SIDH_RXF12SID10_LENGTH 0x1 #define _RXF12SIDH_RXF12SID10_MASK 0x80 // Register: RXF12SIDL #define RXF12SIDL RXF12SIDL extern volatile unsigned char RXF12SIDL @ 0xE61; #ifndef _LIB_BUILD asm("RXF12SIDL equ 0E61h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF12EID16 :1; unsigned RXF12EID17 :1; unsigned :1; unsigned RXF12EXIDEN :1; unsigned :1; unsigned RXF12SID0 :1; unsigned RXF12SID1 :1; unsigned RXF12SID2 :1; }; } RXF12SIDLbits_t; extern volatile RXF12SIDLbits_t RXF12SIDLbits @ 0xE61; // bitfield macros #define _RXF12SIDL_EID_POSN 0x0 #define _RXF12SIDL_EID_POSITION 0x0 #define _RXF12SIDL_EID_SIZE 0x2 #define _RXF12SIDL_EID_LENGTH 0x2 #define _RXF12SIDL_EID_MASK 0x3 #define _RXF12SIDL_EXIDEN_POSN 0x3 #define _RXF12SIDL_EXIDEN_POSITION 0x3 #define _RXF12SIDL_EXIDEN_SIZE 0x1 #define _RXF12SIDL_EXIDEN_LENGTH 0x1 #define _RXF12SIDL_EXIDEN_MASK 0x8 #define _RXF12SIDL_SID_POSN 0x5 #define _RXF12SIDL_SID_POSITION 0x5 #define _RXF12SIDL_SID_SIZE 0x3 #define _RXF12SIDL_SID_LENGTH 0x3 #define _RXF12SIDL_SID_MASK 0xE0 #define _RXF12SIDL_EID16_POSN 0x0 #define _RXF12SIDL_EID16_POSITION 0x0 #define _RXF12SIDL_EID16_SIZE 0x1 #define _RXF12SIDL_EID16_LENGTH 0x1 #define _RXF12SIDL_EID16_MASK 0x1 #define _RXF12SIDL_EID17_POSN 0x1 #define _RXF12SIDL_EID17_POSITION 0x1 #define _RXF12SIDL_EID17_SIZE 0x1 #define _RXF12SIDL_EID17_LENGTH 0x1 #define _RXF12SIDL_EID17_MASK 0x2 #define _RXF12SIDL_SID0_POSN 0x5 #define _RXF12SIDL_SID0_POSITION 0x5 #define _RXF12SIDL_SID0_SIZE 0x1 #define _RXF12SIDL_SID0_LENGTH 0x1 #define _RXF12SIDL_SID0_MASK 0x20 #define _RXF12SIDL_SID1_POSN 0x6 #define _RXF12SIDL_SID1_POSITION 0x6 #define _RXF12SIDL_SID1_SIZE 0x1 #define _RXF12SIDL_SID1_LENGTH 0x1 #define _RXF12SIDL_SID1_MASK 0x40 #define _RXF12SIDL_SID2_POSN 0x7 #define _RXF12SIDL_SID2_POSITION 0x7 #define _RXF12SIDL_SID2_SIZE 0x1 #define _RXF12SIDL_SID2_LENGTH 0x1 #define _RXF12SIDL_SID2_MASK 0x80 #define _RXF12SIDL_RXF12EID16_POSN 0x0 #define _RXF12SIDL_RXF12EID16_POSITION 0x0 #define _RXF12SIDL_RXF12EID16_SIZE 0x1 #define _RXF12SIDL_RXF12EID16_LENGTH 0x1 #define _RXF12SIDL_RXF12EID16_MASK 0x1 #define _RXF12SIDL_RXF12EID17_POSN 0x1 #define _RXF12SIDL_RXF12EID17_POSITION 0x1 #define _RXF12SIDL_RXF12EID17_SIZE 0x1 #define _RXF12SIDL_RXF12EID17_LENGTH 0x1 #define _RXF12SIDL_RXF12EID17_MASK 0x2 #define _RXF12SIDL_RXF12EXIDEN_POSN 0x3 #define _RXF12SIDL_RXF12EXIDEN_POSITION 0x3 #define _RXF12SIDL_RXF12EXIDEN_SIZE 0x1 #define _RXF12SIDL_RXF12EXIDEN_LENGTH 0x1 #define _RXF12SIDL_RXF12EXIDEN_MASK 0x8 #define _RXF12SIDL_RXF12SID0_POSN 0x5 #define _RXF12SIDL_RXF12SID0_POSITION 0x5 #define _RXF12SIDL_RXF12SID0_SIZE 0x1 #define _RXF12SIDL_RXF12SID0_LENGTH 0x1 #define _RXF12SIDL_RXF12SID0_MASK 0x20 #define _RXF12SIDL_RXF12SID1_POSN 0x6 #define _RXF12SIDL_RXF12SID1_POSITION 0x6 #define _RXF12SIDL_RXF12SID1_SIZE 0x1 #define _RXF12SIDL_RXF12SID1_LENGTH 0x1 #define _RXF12SIDL_RXF12SID1_MASK 0x40 #define _RXF12SIDL_RXF12SID2_POSN 0x7 #define _RXF12SIDL_RXF12SID2_POSITION 0x7 #define _RXF12SIDL_RXF12SID2_SIZE 0x1 #define _RXF12SIDL_RXF12SID2_LENGTH 0x1 #define _RXF12SIDL_RXF12SID2_MASK 0x80 // Register: RXF12EIDH #define RXF12EIDH RXF12EIDH extern volatile unsigned char RXF12EIDH @ 0xE62; #ifndef _LIB_BUILD asm("RXF12EIDH equ 0E62h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF12EID8 :1; unsigned RXF12EID9 :1; unsigned RXF12EID10 :1; unsigned RXF12EID11 :1; unsigned RXF12EID12 :1; unsigned RXF12EID13 :1; unsigned RXF12EID14 :1; unsigned RXF12EID15 :1; }; } RXF12EIDHbits_t; extern volatile RXF12EIDHbits_t RXF12EIDHbits @ 0xE62; // bitfield macros #define _RXF12EIDH_EID_POSN 0x0 #define _RXF12EIDH_EID_POSITION 0x0 #define _RXF12EIDH_EID_SIZE 0x8 #define _RXF12EIDH_EID_LENGTH 0x8 #define _RXF12EIDH_EID_MASK 0xFF #define _RXF12EIDH_EID8_POSN 0x0 #define _RXF12EIDH_EID8_POSITION 0x0 #define _RXF12EIDH_EID8_SIZE 0x1 #define _RXF12EIDH_EID8_LENGTH 0x1 #define _RXF12EIDH_EID8_MASK 0x1 #define _RXF12EIDH_EID9_POSN 0x1 #define _RXF12EIDH_EID9_POSITION 0x1 #define _RXF12EIDH_EID9_SIZE 0x1 #define _RXF12EIDH_EID9_LENGTH 0x1 #define _RXF12EIDH_EID9_MASK 0x2 #define _RXF12EIDH_EID10_POSN 0x2 #define _RXF12EIDH_EID10_POSITION 0x2 #define _RXF12EIDH_EID10_SIZE 0x1 #define _RXF12EIDH_EID10_LENGTH 0x1 #define _RXF12EIDH_EID10_MASK 0x4 #define _RXF12EIDH_EID11_POSN 0x3 #define _RXF12EIDH_EID11_POSITION 0x3 #define _RXF12EIDH_EID11_SIZE 0x1 #define _RXF12EIDH_EID11_LENGTH 0x1 #define _RXF12EIDH_EID11_MASK 0x8 #define _RXF12EIDH_EID12_POSN 0x4 #define _RXF12EIDH_EID12_POSITION 0x4 #define _RXF12EIDH_EID12_SIZE 0x1 #define _RXF12EIDH_EID12_LENGTH 0x1 #define _RXF12EIDH_EID12_MASK 0x10 #define _RXF12EIDH_EID13_POSN 0x5 #define _RXF12EIDH_EID13_POSITION 0x5 #define _RXF12EIDH_EID13_SIZE 0x1 #define _RXF12EIDH_EID13_LENGTH 0x1 #define _RXF12EIDH_EID13_MASK 0x20 #define _RXF12EIDH_EID14_POSN 0x6 #define _RXF12EIDH_EID14_POSITION 0x6 #define _RXF12EIDH_EID14_SIZE 0x1 #define _RXF12EIDH_EID14_LENGTH 0x1 #define _RXF12EIDH_EID14_MASK 0x40 #define _RXF12EIDH_EID15_POSN 0x7 #define _RXF12EIDH_EID15_POSITION 0x7 #define _RXF12EIDH_EID15_SIZE 0x1 #define _RXF12EIDH_EID15_LENGTH 0x1 #define _RXF12EIDH_EID15_MASK 0x80 #define _RXF12EIDH_RXF12EID8_POSN 0x0 #define _RXF12EIDH_RXF12EID8_POSITION 0x0 #define _RXF12EIDH_RXF12EID8_SIZE 0x1 #define _RXF12EIDH_RXF12EID8_LENGTH 0x1 #define _RXF12EIDH_RXF12EID8_MASK 0x1 #define _RXF12EIDH_RXF12EID9_POSN 0x1 #define _RXF12EIDH_RXF12EID9_POSITION 0x1 #define _RXF12EIDH_RXF12EID9_SIZE 0x1 #define _RXF12EIDH_RXF12EID9_LENGTH 0x1 #define _RXF12EIDH_RXF12EID9_MASK 0x2 #define _RXF12EIDH_RXF12EID10_POSN 0x2 #define _RXF12EIDH_RXF12EID10_POSITION 0x2 #define _RXF12EIDH_RXF12EID10_SIZE 0x1 #define _RXF12EIDH_RXF12EID10_LENGTH 0x1 #define _RXF12EIDH_RXF12EID10_MASK 0x4 #define _RXF12EIDH_RXF12EID11_POSN 0x3 #define _RXF12EIDH_RXF12EID11_POSITION 0x3 #define _RXF12EIDH_RXF12EID11_SIZE 0x1 #define _RXF12EIDH_RXF12EID11_LENGTH 0x1 #define _RXF12EIDH_RXF12EID11_MASK 0x8 #define _RXF12EIDH_RXF12EID12_POSN 0x4 #define _RXF12EIDH_RXF12EID12_POSITION 0x4 #define _RXF12EIDH_RXF12EID12_SIZE 0x1 #define _RXF12EIDH_RXF12EID12_LENGTH 0x1 #define _RXF12EIDH_RXF12EID12_MASK 0x10 #define _RXF12EIDH_RXF12EID13_POSN 0x5 #define _RXF12EIDH_RXF12EID13_POSITION 0x5 #define _RXF12EIDH_RXF12EID13_SIZE 0x1 #define _RXF12EIDH_RXF12EID13_LENGTH 0x1 #define _RXF12EIDH_RXF12EID13_MASK 0x20 #define _RXF12EIDH_RXF12EID14_POSN 0x6 #define _RXF12EIDH_RXF12EID14_POSITION 0x6 #define _RXF12EIDH_RXF12EID14_SIZE 0x1 #define _RXF12EIDH_RXF12EID14_LENGTH 0x1 #define _RXF12EIDH_RXF12EID14_MASK 0x40 #define _RXF12EIDH_RXF12EID15_POSN 0x7 #define _RXF12EIDH_RXF12EID15_POSITION 0x7 #define _RXF12EIDH_RXF12EID15_SIZE 0x1 #define _RXF12EIDH_RXF12EID15_LENGTH 0x1 #define _RXF12EIDH_RXF12EID15_MASK 0x80 // Register: RXF12EIDL #define RXF12EIDL RXF12EIDL extern volatile unsigned char RXF12EIDL @ 0xE63; #ifndef _LIB_BUILD asm("RXF12EIDL equ 0E63h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF12EID0 :1; unsigned RXF12EID1 :1; unsigned RXF12EID2 :1; unsigned RXF12EID3 :1; unsigned RXF12EID4 :1; unsigned RXF12EID5 :1; unsigned RXF12EID6 :1; unsigned RXF12EID7 :1; }; } RXF12EIDLbits_t; extern volatile RXF12EIDLbits_t RXF12EIDLbits @ 0xE63; // bitfield macros #define _RXF12EIDL_EID_POSN 0x0 #define _RXF12EIDL_EID_POSITION 0x0 #define _RXF12EIDL_EID_SIZE 0x8 #define _RXF12EIDL_EID_LENGTH 0x8 #define _RXF12EIDL_EID_MASK 0xFF #define _RXF12EIDL_EID0_POSN 0x0 #define _RXF12EIDL_EID0_POSITION 0x0 #define _RXF12EIDL_EID0_SIZE 0x1 #define _RXF12EIDL_EID0_LENGTH 0x1 #define _RXF12EIDL_EID0_MASK 0x1 #define _RXF12EIDL_EID1_POSN 0x1 #define _RXF12EIDL_EID1_POSITION 0x1 #define _RXF12EIDL_EID1_SIZE 0x1 #define _RXF12EIDL_EID1_LENGTH 0x1 #define _RXF12EIDL_EID1_MASK 0x2 #define _RXF12EIDL_EID2_POSN 0x2 #define _RXF12EIDL_EID2_POSITION 0x2 #define _RXF12EIDL_EID2_SIZE 0x1 #define _RXF12EIDL_EID2_LENGTH 0x1 #define _RXF12EIDL_EID2_MASK 0x4 #define _RXF12EIDL_EID3_POSN 0x3 #define _RXF12EIDL_EID3_POSITION 0x3 #define _RXF12EIDL_EID3_SIZE 0x1 #define _RXF12EIDL_EID3_LENGTH 0x1 #define _RXF12EIDL_EID3_MASK 0x8 #define _RXF12EIDL_EID4_POSN 0x4 #define _RXF12EIDL_EID4_POSITION 0x4 #define _RXF12EIDL_EID4_SIZE 0x1 #define _RXF12EIDL_EID4_LENGTH 0x1 #define _RXF12EIDL_EID4_MASK 0x10 #define _RXF12EIDL_EID5_POSN 0x5 #define _RXF12EIDL_EID5_POSITION 0x5 #define _RXF12EIDL_EID5_SIZE 0x1 #define _RXF12EIDL_EID5_LENGTH 0x1 #define _RXF12EIDL_EID5_MASK 0x20 #define _RXF12EIDL_EID6_POSN 0x6 #define _RXF12EIDL_EID6_POSITION 0x6 #define _RXF12EIDL_EID6_SIZE 0x1 #define _RXF12EIDL_EID6_LENGTH 0x1 #define _RXF12EIDL_EID6_MASK 0x40 #define _RXF12EIDL_EID7_POSN 0x7 #define _RXF12EIDL_EID7_POSITION 0x7 #define _RXF12EIDL_EID7_SIZE 0x1 #define _RXF12EIDL_EID7_LENGTH 0x1 #define _RXF12EIDL_EID7_MASK 0x80 #define _RXF12EIDL_RXF12EID0_POSN 0x0 #define _RXF12EIDL_RXF12EID0_POSITION 0x0 #define _RXF12EIDL_RXF12EID0_SIZE 0x1 #define _RXF12EIDL_RXF12EID0_LENGTH 0x1 #define _RXF12EIDL_RXF12EID0_MASK 0x1 #define _RXF12EIDL_RXF12EID1_POSN 0x1 #define _RXF12EIDL_RXF12EID1_POSITION 0x1 #define _RXF12EIDL_RXF12EID1_SIZE 0x1 #define _RXF12EIDL_RXF12EID1_LENGTH 0x1 #define _RXF12EIDL_RXF12EID1_MASK 0x2 #define _RXF12EIDL_RXF12EID2_POSN 0x2 #define _RXF12EIDL_RXF12EID2_POSITION 0x2 #define _RXF12EIDL_RXF12EID2_SIZE 0x1 #define _RXF12EIDL_RXF12EID2_LENGTH 0x1 #define _RXF12EIDL_RXF12EID2_MASK 0x4 #define _RXF12EIDL_RXF12EID3_POSN 0x3 #define _RXF12EIDL_RXF12EID3_POSITION 0x3 #define _RXF12EIDL_RXF12EID3_SIZE 0x1 #define _RXF12EIDL_RXF12EID3_LENGTH 0x1 #define _RXF12EIDL_RXF12EID3_MASK 0x8 #define _RXF12EIDL_RXF12EID4_POSN 0x4 #define _RXF12EIDL_RXF12EID4_POSITION 0x4 #define _RXF12EIDL_RXF12EID4_SIZE 0x1 #define _RXF12EIDL_RXF12EID4_LENGTH 0x1 #define _RXF12EIDL_RXF12EID4_MASK 0x10 #define _RXF12EIDL_RXF12EID5_POSN 0x5 #define _RXF12EIDL_RXF12EID5_POSITION 0x5 #define _RXF12EIDL_RXF12EID5_SIZE 0x1 #define _RXF12EIDL_RXF12EID5_LENGTH 0x1 #define _RXF12EIDL_RXF12EID5_MASK 0x20 #define _RXF12EIDL_RXF12EID6_POSN 0x6 #define _RXF12EIDL_RXF12EID6_POSITION 0x6 #define _RXF12EIDL_RXF12EID6_SIZE 0x1 #define _RXF12EIDL_RXF12EID6_LENGTH 0x1 #define _RXF12EIDL_RXF12EID6_MASK 0x40 #define _RXF12EIDL_RXF12EID7_POSN 0x7 #define _RXF12EIDL_RXF12EID7_POSITION 0x7 #define _RXF12EIDL_RXF12EID7_SIZE 0x1 #define _RXF12EIDL_RXF12EID7_LENGTH 0x1 #define _RXF12EIDL_RXF12EID7_MASK 0x80 // Register: RXF13SIDH #define RXF13SIDH RXF13SIDH extern volatile unsigned char RXF13SIDH @ 0xE64; #ifndef _LIB_BUILD asm("RXF13SIDH equ 0E64h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF13SID3 :1; unsigned RXF13SID4 :1; unsigned RXF13SID5 :1; unsigned RXF13SID6 :1; unsigned RXF13SID7 :1; unsigned RXF13SID8 :1; unsigned RXF13SID9 :1; unsigned RXF13SID10 :1; }; } RXF13SIDHbits_t; extern volatile RXF13SIDHbits_t RXF13SIDHbits @ 0xE64; // bitfield macros #define _RXF13SIDH_SID_POSN 0x0 #define _RXF13SIDH_SID_POSITION 0x0 #define _RXF13SIDH_SID_SIZE 0x8 #define _RXF13SIDH_SID_LENGTH 0x8 #define _RXF13SIDH_SID_MASK 0xFF #define _RXF13SIDH_SID3_POSN 0x0 #define _RXF13SIDH_SID3_POSITION 0x0 #define _RXF13SIDH_SID3_SIZE 0x1 #define _RXF13SIDH_SID3_LENGTH 0x1 #define _RXF13SIDH_SID3_MASK 0x1 #define _RXF13SIDH_SID4_POSN 0x1 #define _RXF13SIDH_SID4_POSITION 0x1 #define _RXF13SIDH_SID4_SIZE 0x1 #define _RXF13SIDH_SID4_LENGTH 0x1 #define _RXF13SIDH_SID4_MASK 0x2 #define _RXF13SIDH_SID5_POSN 0x2 #define _RXF13SIDH_SID5_POSITION 0x2 #define _RXF13SIDH_SID5_SIZE 0x1 #define _RXF13SIDH_SID5_LENGTH 0x1 #define _RXF13SIDH_SID5_MASK 0x4 #define _RXF13SIDH_SID6_POSN 0x3 #define _RXF13SIDH_SID6_POSITION 0x3 #define _RXF13SIDH_SID6_SIZE 0x1 #define _RXF13SIDH_SID6_LENGTH 0x1 #define _RXF13SIDH_SID6_MASK 0x8 #define _RXF13SIDH_SID7_POSN 0x4 #define _RXF13SIDH_SID7_POSITION 0x4 #define _RXF13SIDH_SID7_SIZE 0x1 #define _RXF13SIDH_SID7_LENGTH 0x1 #define _RXF13SIDH_SID7_MASK 0x10 #define _RXF13SIDH_SID8_POSN 0x5 #define _RXF13SIDH_SID8_POSITION 0x5 #define _RXF13SIDH_SID8_SIZE 0x1 #define _RXF13SIDH_SID8_LENGTH 0x1 #define _RXF13SIDH_SID8_MASK 0x20 #define _RXF13SIDH_SID9_POSN 0x6 #define _RXF13SIDH_SID9_POSITION 0x6 #define _RXF13SIDH_SID9_SIZE 0x1 #define _RXF13SIDH_SID9_LENGTH 0x1 #define _RXF13SIDH_SID9_MASK 0x40 #define _RXF13SIDH_SID10_POSN 0x7 #define _RXF13SIDH_SID10_POSITION 0x7 #define _RXF13SIDH_SID10_SIZE 0x1 #define _RXF13SIDH_SID10_LENGTH 0x1 #define _RXF13SIDH_SID10_MASK 0x80 #define _RXF13SIDH_RXF13SID3_POSN 0x0 #define _RXF13SIDH_RXF13SID3_POSITION 0x0 #define _RXF13SIDH_RXF13SID3_SIZE 0x1 #define _RXF13SIDH_RXF13SID3_LENGTH 0x1 #define _RXF13SIDH_RXF13SID3_MASK 0x1 #define _RXF13SIDH_RXF13SID4_POSN 0x1 #define _RXF13SIDH_RXF13SID4_POSITION 0x1 #define _RXF13SIDH_RXF13SID4_SIZE 0x1 #define _RXF13SIDH_RXF13SID4_LENGTH 0x1 #define _RXF13SIDH_RXF13SID4_MASK 0x2 #define _RXF13SIDH_RXF13SID5_POSN 0x2 #define _RXF13SIDH_RXF13SID5_POSITION 0x2 #define _RXF13SIDH_RXF13SID5_SIZE 0x1 #define _RXF13SIDH_RXF13SID5_LENGTH 0x1 #define _RXF13SIDH_RXF13SID5_MASK 0x4 #define _RXF13SIDH_RXF13SID6_POSN 0x3 #define _RXF13SIDH_RXF13SID6_POSITION 0x3 #define _RXF13SIDH_RXF13SID6_SIZE 0x1 #define _RXF13SIDH_RXF13SID6_LENGTH 0x1 #define _RXF13SIDH_RXF13SID6_MASK 0x8 #define _RXF13SIDH_RXF13SID7_POSN 0x4 #define _RXF13SIDH_RXF13SID7_POSITION 0x4 #define _RXF13SIDH_RXF13SID7_SIZE 0x1 #define _RXF13SIDH_RXF13SID7_LENGTH 0x1 #define _RXF13SIDH_RXF13SID7_MASK 0x10 #define _RXF13SIDH_RXF13SID8_POSN 0x5 #define _RXF13SIDH_RXF13SID8_POSITION 0x5 #define _RXF13SIDH_RXF13SID8_SIZE 0x1 #define _RXF13SIDH_RXF13SID8_LENGTH 0x1 #define _RXF13SIDH_RXF13SID8_MASK 0x20 #define _RXF13SIDH_RXF13SID9_POSN 0x6 #define _RXF13SIDH_RXF13SID9_POSITION 0x6 #define _RXF13SIDH_RXF13SID9_SIZE 0x1 #define _RXF13SIDH_RXF13SID9_LENGTH 0x1 #define _RXF13SIDH_RXF13SID9_MASK 0x40 #define _RXF13SIDH_RXF13SID10_POSN 0x7 #define _RXF13SIDH_RXF13SID10_POSITION 0x7 #define _RXF13SIDH_RXF13SID10_SIZE 0x1 #define _RXF13SIDH_RXF13SID10_LENGTH 0x1 #define _RXF13SIDH_RXF13SID10_MASK 0x80 // Register: RXF13SIDL #define RXF13SIDL RXF13SIDL extern volatile unsigned char RXF13SIDL @ 0xE65; #ifndef _LIB_BUILD asm("RXF13SIDL equ 0E65h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF13EID16 :1; unsigned RXF13EID17 :1; unsigned :1; unsigned RXF13EXIDEN :1; unsigned :1; unsigned RXF13SID0 :1; unsigned RXF13SID1 :1; unsigned RXF13SID2 :1; }; } RXF13SIDLbits_t; extern volatile RXF13SIDLbits_t RXF13SIDLbits @ 0xE65; // bitfield macros #define _RXF13SIDL_EID_POSN 0x0 #define _RXF13SIDL_EID_POSITION 0x0 #define _RXF13SIDL_EID_SIZE 0x2 #define _RXF13SIDL_EID_LENGTH 0x2 #define _RXF13SIDL_EID_MASK 0x3 #define _RXF13SIDL_EXIDEN_POSN 0x3 #define _RXF13SIDL_EXIDEN_POSITION 0x3 #define _RXF13SIDL_EXIDEN_SIZE 0x1 #define _RXF13SIDL_EXIDEN_LENGTH 0x1 #define _RXF13SIDL_EXIDEN_MASK 0x8 #define _RXF13SIDL_SID_POSN 0x5 #define _RXF13SIDL_SID_POSITION 0x5 #define _RXF13SIDL_SID_SIZE 0x3 #define _RXF13SIDL_SID_LENGTH 0x3 #define _RXF13SIDL_SID_MASK 0xE0 #define _RXF13SIDL_EID16_POSN 0x0 #define _RXF13SIDL_EID16_POSITION 0x0 #define _RXF13SIDL_EID16_SIZE 0x1 #define _RXF13SIDL_EID16_LENGTH 0x1 #define _RXF13SIDL_EID16_MASK 0x1 #define _RXF13SIDL_EID17_POSN 0x1 #define _RXF13SIDL_EID17_POSITION 0x1 #define _RXF13SIDL_EID17_SIZE 0x1 #define _RXF13SIDL_EID17_LENGTH 0x1 #define _RXF13SIDL_EID17_MASK 0x2 #define _RXF13SIDL_SID0_POSN 0x5 #define _RXF13SIDL_SID0_POSITION 0x5 #define _RXF13SIDL_SID0_SIZE 0x1 #define _RXF13SIDL_SID0_LENGTH 0x1 #define _RXF13SIDL_SID0_MASK 0x20 #define _RXF13SIDL_SID1_POSN 0x6 #define _RXF13SIDL_SID1_POSITION 0x6 #define _RXF13SIDL_SID1_SIZE 0x1 #define _RXF13SIDL_SID1_LENGTH 0x1 #define _RXF13SIDL_SID1_MASK 0x40 #define _RXF13SIDL_SID2_POSN 0x7 #define _RXF13SIDL_SID2_POSITION 0x7 #define _RXF13SIDL_SID2_SIZE 0x1 #define _RXF13SIDL_SID2_LENGTH 0x1 #define _RXF13SIDL_SID2_MASK 0x80 #define _RXF13SIDL_RXF13EID16_POSN 0x0 #define _RXF13SIDL_RXF13EID16_POSITION 0x0 #define _RXF13SIDL_RXF13EID16_SIZE 0x1 #define _RXF13SIDL_RXF13EID16_LENGTH 0x1 #define _RXF13SIDL_RXF13EID16_MASK 0x1 #define _RXF13SIDL_RXF13EID17_POSN 0x1 #define _RXF13SIDL_RXF13EID17_POSITION 0x1 #define _RXF13SIDL_RXF13EID17_SIZE 0x1 #define _RXF13SIDL_RXF13EID17_LENGTH 0x1 #define _RXF13SIDL_RXF13EID17_MASK 0x2 #define _RXF13SIDL_RXF13EXIDEN_POSN 0x3 #define _RXF13SIDL_RXF13EXIDEN_POSITION 0x3 #define _RXF13SIDL_RXF13EXIDEN_SIZE 0x1 #define _RXF13SIDL_RXF13EXIDEN_LENGTH 0x1 #define _RXF13SIDL_RXF13EXIDEN_MASK 0x8 #define _RXF13SIDL_RXF13SID0_POSN 0x5 #define _RXF13SIDL_RXF13SID0_POSITION 0x5 #define _RXF13SIDL_RXF13SID0_SIZE 0x1 #define _RXF13SIDL_RXF13SID0_LENGTH 0x1 #define _RXF13SIDL_RXF13SID0_MASK 0x20 #define _RXF13SIDL_RXF13SID1_POSN 0x6 #define _RXF13SIDL_RXF13SID1_POSITION 0x6 #define _RXF13SIDL_RXF13SID1_SIZE 0x1 #define _RXF13SIDL_RXF13SID1_LENGTH 0x1 #define _RXF13SIDL_RXF13SID1_MASK 0x40 #define _RXF13SIDL_RXF13SID2_POSN 0x7 #define _RXF13SIDL_RXF13SID2_POSITION 0x7 #define _RXF13SIDL_RXF13SID2_SIZE 0x1 #define _RXF13SIDL_RXF13SID2_LENGTH 0x1 #define _RXF13SIDL_RXF13SID2_MASK 0x80 // Register: RXF13EIDH #define RXF13EIDH RXF13EIDH extern volatile unsigned char RXF13EIDH @ 0xE66; #ifndef _LIB_BUILD asm("RXF13EIDH equ 0E66h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF13EID8 :1; unsigned RXF13EID9 :1; unsigned RXF13EID10 :1; unsigned RXF13EID11 :1; unsigned RXF13EID12 :1; unsigned RXF13EID13 :1; unsigned RXF13EID14 :1; unsigned RXF13EID15 :1; }; } RXF13EIDHbits_t; extern volatile RXF13EIDHbits_t RXF13EIDHbits @ 0xE66; // bitfield macros #define _RXF13EIDH_EID_POSN 0x0 #define _RXF13EIDH_EID_POSITION 0x0 #define _RXF13EIDH_EID_SIZE 0x8 #define _RXF13EIDH_EID_LENGTH 0x8 #define _RXF13EIDH_EID_MASK 0xFF #define _RXF13EIDH_EID8_POSN 0x0 #define _RXF13EIDH_EID8_POSITION 0x0 #define _RXF13EIDH_EID8_SIZE 0x1 #define _RXF13EIDH_EID8_LENGTH 0x1 #define _RXF13EIDH_EID8_MASK 0x1 #define _RXF13EIDH_EID9_POSN 0x1 #define _RXF13EIDH_EID9_POSITION 0x1 #define _RXF13EIDH_EID9_SIZE 0x1 #define _RXF13EIDH_EID9_LENGTH 0x1 #define _RXF13EIDH_EID9_MASK 0x2 #define _RXF13EIDH_EID10_POSN 0x2 #define _RXF13EIDH_EID10_POSITION 0x2 #define _RXF13EIDH_EID10_SIZE 0x1 #define _RXF13EIDH_EID10_LENGTH 0x1 #define _RXF13EIDH_EID10_MASK 0x4 #define _RXF13EIDH_EID11_POSN 0x3 #define _RXF13EIDH_EID11_POSITION 0x3 #define _RXF13EIDH_EID11_SIZE 0x1 #define _RXF13EIDH_EID11_LENGTH 0x1 #define _RXF13EIDH_EID11_MASK 0x8 #define _RXF13EIDH_EID12_POSN 0x4 #define _RXF13EIDH_EID12_POSITION 0x4 #define _RXF13EIDH_EID12_SIZE 0x1 #define _RXF13EIDH_EID12_LENGTH 0x1 #define _RXF13EIDH_EID12_MASK 0x10 #define _RXF13EIDH_EID13_POSN 0x5 #define _RXF13EIDH_EID13_POSITION 0x5 #define _RXF13EIDH_EID13_SIZE 0x1 #define _RXF13EIDH_EID13_LENGTH 0x1 #define _RXF13EIDH_EID13_MASK 0x20 #define _RXF13EIDH_EID14_POSN 0x6 #define _RXF13EIDH_EID14_POSITION 0x6 #define _RXF13EIDH_EID14_SIZE 0x1 #define _RXF13EIDH_EID14_LENGTH 0x1 #define _RXF13EIDH_EID14_MASK 0x40 #define _RXF13EIDH_EID15_POSN 0x7 #define _RXF13EIDH_EID15_POSITION 0x7 #define _RXF13EIDH_EID15_SIZE 0x1 #define _RXF13EIDH_EID15_LENGTH 0x1 #define _RXF13EIDH_EID15_MASK 0x80 #define _RXF13EIDH_RXF13EID8_POSN 0x0 #define _RXF13EIDH_RXF13EID8_POSITION 0x0 #define _RXF13EIDH_RXF13EID8_SIZE 0x1 #define _RXF13EIDH_RXF13EID8_LENGTH 0x1 #define _RXF13EIDH_RXF13EID8_MASK 0x1 #define _RXF13EIDH_RXF13EID9_POSN 0x1 #define _RXF13EIDH_RXF13EID9_POSITION 0x1 #define _RXF13EIDH_RXF13EID9_SIZE 0x1 #define _RXF13EIDH_RXF13EID9_LENGTH 0x1 #define _RXF13EIDH_RXF13EID9_MASK 0x2 #define _RXF13EIDH_RXF13EID10_POSN 0x2 #define _RXF13EIDH_RXF13EID10_POSITION 0x2 #define _RXF13EIDH_RXF13EID10_SIZE 0x1 #define _RXF13EIDH_RXF13EID10_LENGTH 0x1 #define _RXF13EIDH_RXF13EID10_MASK 0x4 #define _RXF13EIDH_RXF13EID11_POSN 0x3 #define _RXF13EIDH_RXF13EID11_POSITION 0x3 #define _RXF13EIDH_RXF13EID11_SIZE 0x1 #define _RXF13EIDH_RXF13EID11_LENGTH 0x1 #define _RXF13EIDH_RXF13EID11_MASK 0x8 #define _RXF13EIDH_RXF13EID12_POSN 0x4 #define _RXF13EIDH_RXF13EID12_POSITION 0x4 #define _RXF13EIDH_RXF13EID12_SIZE 0x1 #define _RXF13EIDH_RXF13EID12_LENGTH 0x1 #define _RXF13EIDH_RXF13EID12_MASK 0x10 #define _RXF13EIDH_RXF13EID13_POSN 0x5 #define _RXF13EIDH_RXF13EID13_POSITION 0x5 #define _RXF13EIDH_RXF13EID13_SIZE 0x1 #define _RXF13EIDH_RXF13EID13_LENGTH 0x1 #define _RXF13EIDH_RXF13EID13_MASK 0x20 #define _RXF13EIDH_RXF13EID14_POSN 0x6 #define _RXF13EIDH_RXF13EID14_POSITION 0x6 #define _RXF13EIDH_RXF13EID14_SIZE 0x1 #define _RXF13EIDH_RXF13EID14_LENGTH 0x1 #define _RXF13EIDH_RXF13EID14_MASK 0x40 #define _RXF13EIDH_RXF13EID15_POSN 0x7 #define _RXF13EIDH_RXF13EID15_POSITION 0x7 #define _RXF13EIDH_RXF13EID15_SIZE 0x1 #define _RXF13EIDH_RXF13EID15_LENGTH 0x1 #define _RXF13EIDH_RXF13EID15_MASK 0x80 // Register: RXF13EIDL #define RXF13EIDL RXF13EIDL extern volatile unsigned char RXF13EIDL @ 0xE67; #ifndef _LIB_BUILD asm("RXF13EIDL equ 0E67h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF13EID0 :1; unsigned RXF13EID1 :1; unsigned RXF13EID2 :1; unsigned RXF13EID3 :1; unsigned RXF13EID4 :1; unsigned RXF13EID5 :1; unsigned RXF13EID6 :1; unsigned RXF13EID7 :1; }; } RXF13EIDLbits_t; extern volatile RXF13EIDLbits_t RXF13EIDLbits @ 0xE67; // bitfield macros #define _RXF13EIDL_EID_POSN 0x0 #define _RXF13EIDL_EID_POSITION 0x0 #define _RXF13EIDL_EID_SIZE 0x8 #define _RXF13EIDL_EID_LENGTH 0x8 #define _RXF13EIDL_EID_MASK 0xFF #define _RXF13EIDL_EID0_POSN 0x0 #define _RXF13EIDL_EID0_POSITION 0x0 #define _RXF13EIDL_EID0_SIZE 0x1 #define _RXF13EIDL_EID0_LENGTH 0x1 #define _RXF13EIDL_EID0_MASK 0x1 #define _RXF13EIDL_EID1_POSN 0x1 #define _RXF13EIDL_EID1_POSITION 0x1 #define _RXF13EIDL_EID1_SIZE 0x1 #define _RXF13EIDL_EID1_LENGTH 0x1 #define _RXF13EIDL_EID1_MASK 0x2 #define _RXF13EIDL_EID2_POSN 0x2 #define _RXF13EIDL_EID2_POSITION 0x2 #define _RXF13EIDL_EID2_SIZE 0x1 #define _RXF13EIDL_EID2_LENGTH 0x1 #define _RXF13EIDL_EID2_MASK 0x4 #define _RXF13EIDL_EID3_POSN 0x3 #define _RXF13EIDL_EID3_POSITION 0x3 #define _RXF13EIDL_EID3_SIZE 0x1 #define _RXF13EIDL_EID3_LENGTH 0x1 #define _RXF13EIDL_EID3_MASK 0x8 #define _RXF13EIDL_EID4_POSN 0x4 #define _RXF13EIDL_EID4_POSITION 0x4 #define _RXF13EIDL_EID4_SIZE 0x1 #define _RXF13EIDL_EID4_LENGTH 0x1 #define _RXF13EIDL_EID4_MASK 0x10 #define _RXF13EIDL_EID5_POSN 0x5 #define _RXF13EIDL_EID5_POSITION 0x5 #define _RXF13EIDL_EID5_SIZE 0x1 #define _RXF13EIDL_EID5_LENGTH 0x1 #define _RXF13EIDL_EID5_MASK 0x20 #define _RXF13EIDL_EID6_POSN 0x6 #define _RXF13EIDL_EID6_POSITION 0x6 #define _RXF13EIDL_EID6_SIZE 0x1 #define _RXF13EIDL_EID6_LENGTH 0x1 #define _RXF13EIDL_EID6_MASK 0x40 #define _RXF13EIDL_EID7_POSN 0x7 #define _RXF13EIDL_EID7_POSITION 0x7 #define _RXF13EIDL_EID7_SIZE 0x1 #define _RXF13EIDL_EID7_LENGTH 0x1 #define _RXF13EIDL_EID7_MASK 0x80 #define _RXF13EIDL_RXF13EID0_POSN 0x0 #define _RXF13EIDL_RXF13EID0_POSITION 0x0 #define _RXF13EIDL_RXF13EID0_SIZE 0x1 #define _RXF13EIDL_RXF13EID0_LENGTH 0x1 #define _RXF13EIDL_RXF13EID0_MASK 0x1 #define _RXF13EIDL_RXF13EID1_POSN 0x1 #define _RXF13EIDL_RXF13EID1_POSITION 0x1 #define _RXF13EIDL_RXF13EID1_SIZE 0x1 #define _RXF13EIDL_RXF13EID1_LENGTH 0x1 #define _RXF13EIDL_RXF13EID1_MASK 0x2 #define _RXF13EIDL_RXF13EID2_POSN 0x2 #define _RXF13EIDL_RXF13EID2_POSITION 0x2 #define _RXF13EIDL_RXF13EID2_SIZE 0x1 #define _RXF13EIDL_RXF13EID2_LENGTH 0x1 #define _RXF13EIDL_RXF13EID2_MASK 0x4 #define _RXF13EIDL_RXF13EID3_POSN 0x3 #define _RXF13EIDL_RXF13EID3_POSITION 0x3 #define _RXF13EIDL_RXF13EID3_SIZE 0x1 #define _RXF13EIDL_RXF13EID3_LENGTH 0x1 #define _RXF13EIDL_RXF13EID3_MASK 0x8 #define _RXF13EIDL_RXF13EID4_POSN 0x4 #define _RXF13EIDL_RXF13EID4_POSITION 0x4 #define _RXF13EIDL_RXF13EID4_SIZE 0x1 #define _RXF13EIDL_RXF13EID4_LENGTH 0x1 #define _RXF13EIDL_RXF13EID4_MASK 0x10 #define _RXF13EIDL_RXF13EID5_POSN 0x5 #define _RXF13EIDL_RXF13EID5_POSITION 0x5 #define _RXF13EIDL_RXF13EID5_SIZE 0x1 #define _RXF13EIDL_RXF13EID5_LENGTH 0x1 #define _RXF13EIDL_RXF13EID5_MASK 0x20 #define _RXF13EIDL_RXF13EID6_POSN 0x6 #define _RXF13EIDL_RXF13EID6_POSITION 0x6 #define _RXF13EIDL_RXF13EID6_SIZE 0x1 #define _RXF13EIDL_RXF13EID6_LENGTH 0x1 #define _RXF13EIDL_RXF13EID6_MASK 0x40 #define _RXF13EIDL_RXF13EID7_POSN 0x7 #define _RXF13EIDL_RXF13EID7_POSITION 0x7 #define _RXF13EIDL_RXF13EID7_SIZE 0x1 #define _RXF13EIDL_RXF13EID7_LENGTH 0x1 #define _RXF13EIDL_RXF13EID7_MASK 0x80 // Register: RXF14SIDH #define RXF14SIDH RXF14SIDH extern volatile unsigned char RXF14SIDH @ 0xE68; #ifndef _LIB_BUILD asm("RXF14SIDH equ 0E68h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF14SID3 :1; unsigned RXF14SID4 :1; unsigned RXF14SID5 :1; unsigned RXF14SID6 :1; unsigned RXF14SID7 :1; unsigned RXF14SID8 :1; unsigned RXF14SID9 :1; unsigned RXF14SID10 :1; }; } RXF14SIDHbits_t; extern volatile RXF14SIDHbits_t RXF14SIDHbits @ 0xE68; // bitfield macros #define _RXF14SIDH_SID_POSN 0x0 #define _RXF14SIDH_SID_POSITION 0x0 #define _RXF14SIDH_SID_SIZE 0x8 #define _RXF14SIDH_SID_LENGTH 0x8 #define _RXF14SIDH_SID_MASK 0xFF #define _RXF14SIDH_SID3_POSN 0x0 #define _RXF14SIDH_SID3_POSITION 0x0 #define _RXF14SIDH_SID3_SIZE 0x1 #define _RXF14SIDH_SID3_LENGTH 0x1 #define _RXF14SIDH_SID3_MASK 0x1 #define _RXF14SIDH_SID4_POSN 0x1 #define _RXF14SIDH_SID4_POSITION 0x1 #define _RXF14SIDH_SID4_SIZE 0x1 #define _RXF14SIDH_SID4_LENGTH 0x1 #define _RXF14SIDH_SID4_MASK 0x2 #define _RXF14SIDH_SID5_POSN 0x2 #define _RXF14SIDH_SID5_POSITION 0x2 #define _RXF14SIDH_SID5_SIZE 0x1 #define _RXF14SIDH_SID5_LENGTH 0x1 #define _RXF14SIDH_SID5_MASK 0x4 #define _RXF14SIDH_SID6_POSN 0x3 #define _RXF14SIDH_SID6_POSITION 0x3 #define _RXF14SIDH_SID6_SIZE 0x1 #define _RXF14SIDH_SID6_LENGTH 0x1 #define _RXF14SIDH_SID6_MASK 0x8 #define _RXF14SIDH_SID7_POSN 0x4 #define _RXF14SIDH_SID7_POSITION 0x4 #define _RXF14SIDH_SID7_SIZE 0x1 #define _RXF14SIDH_SID7_LENGTH 0x1 #define _RXF14SIDH_SID7_MASK 0x10 #define _RXF14SIDH_SID8_POSN 0x5 #define _RXF14SIDH_SID8_POSITION 0x5 #define _RXF14SIDH_SID8_SIZE 0x1 #define _RXF14SIDH_SID8_LENGTH 0x1 #define _RXF14SIDH_SID8_MASK 0x20 #define _RXF14SIDH_SID9_POSN 0x6 #define _RXF14SIDH_SID9_POSITION 0x6 #define _RXF14SIDH_SID9_SIZE 0x1 #define _RXF14SIDH_SID9_LENGTH 0x1 #define _RXF14SIDH_SID9_MASK 0x40 #define _RXF14SIDH_SID10_POSN 0x7 #define _RXF14SIDH_SID10_POSITION 0x7 #define _RXF14SIDH_SID10_SIZE 0x1 #define _RXF14SIDH_SID10_LENGTH 0x1 #define _RXF14SIDH_SID10_MASK 0x80 #define _RXF14SIDH_RXF14SID3_POSN 0x0 #define _RXF14SIDH_RXF14SID3_POSITION 0x0 #define _RXF14SIDH_RXF14SID3_SIZE 0x1 #define _RXF14SIDH_RXF14SID3_LENGTH 0x1 #define _RXF14SIDH_RXF14SID3_MASK 0x1 #define _RXF14SIDH_RXF14SID4_POSN 0x1 #define _RXF14SIDH_RXF14SID4_POSITION 0x1 #define _RXF14SIDH_RXF14SID4_SIZE 0x1 #define _RXF14SIDH_RXF14SID4_LENGTH 0x1 #define _RXF14SIDH_RXF14SID4_MASK 0x2 #define _RXF14SIDH_RXF14SID5_POSN 0x2 #define _RXF14SIDH_RXF14SID5_POSITION 0x2 #define _RXF14SIDH_RXF14SID5_SIZE 0x1 #define _RXF14SIDH_RXF14SID5_LENGTH 0x1 #define _RXF14SIDH_RXF14SID5_MASK 0x4 #define _RXF14SIDH_RXF14SID6_POSN 0x3 #define _RXF14SIDH_RXF14SID6_POSITION 0x3 #define _RXF14SIDH_RXF14SID6_SIZE 0x1 #define _RXF14SIDH_RXF14SID6_LENGTH 0x1 #define _RXF14SIDH_RXF14SID6_MASK 0x8 #define _RXF14SIDH_RXF14SID7_POSN 0x4 #define _RXF14SIDH_RXF14SID7_POSITION 0x4 #define _RXF14SIDH_RXF14SID7_SIZE 0x1 #define _RXF14SIDH_RXF14SID7_LENGTH 0x1 #define _RXF14SIDH_RXF14SID7_MASK 0x10 #define _RXF14SIDH_RXF14SID8_POSN 0x5 #define _RXF14SIDH_RXF14SID8_POSITION 0x5 #define _RXF14SIDH_RXF14SID8_SIZE 0x1 #define _RXF14SIDH_RXF14SID8_LENGTH 0x1 #define _RXF14SIDH_RXF14SID8_MASK 0x20 #define _RXF14SIDH_RXF14SID9_POSN 0x6 #define _RXF14SIDH_RXF14SID9_POSITION 0x6 #define _RXF14SIDH_RXF14SID9_SIZE 0x1 #define _RXF14SIDH_RXF14SID9_LENGTH 0x1 #define _RXF14SIDH_RXF14SID9_MASK 0x40 #define _RXF14SIDH_RXF14SID10_POSN 0x7 #define _RXF14SIDH_RXF14SID10_POSITION 0x7 #define _RXF14SIDH_RXF14SID10_SIZE 0x1 #define _RXF14SIDH_RXF14SID10_LENGTH 0x1 #define _RXF14SIDH_RXF14SID10_MASK 0x80 // Register: RXF14SIDL #define RXF14SIDL RXF14SIDL extern volatile unsigned char RXF14SIDL @ 0xE69; #ifndef _LIB_BUILD asm("RXF14SIDL equ 0E69h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF14EID16 :1; unsigned RXF14EID17 :1; unsigned :1; unsigned RXF14EXIDEN :1; unsigned :1; unsigned RXF14SID0 :1; unsigned RXF14SID1 :1; unsigned RXF14SID2 :1; }; } RXF14SIDLbits_t; extern volatile RXF14SIDLbits_t RXF14SIDLbits @ 0xE69; // bitfield macros #define _RXF14SIDL_EID_POSN 0x0 #define _RXF14SIDL_EID_POSITION 0x0 #define _RXF14SIDL_EID_SIZE 0x2 #define _RXF14SIDL_EID_LENGTH 0x2 #define _RXF14SIDL_EID_MASK 0x3 #define _RXF14SIDL_EXIDEN_POSN 0x3 #define _RXF14SIDL_EXIDEN_POSITION 0x3 #define _RXF14SIDL_EXIDEN_SIZE 0x1 #define _RXF14SIDL_EXIDEN_LENGTH 0x1 #define _RXF14SIDL_EXIDEN_MASK 0x8 #define _RXF14SIDL_SID_POSN 0x5 #define _RXF14SIDL_SID_POSITION 0x5 #define _RXF14SIDL_SID_SIZE 0x3 #define _RXF14SIDL_SID_LENGTH 0x3 #define _RXF14SIDL_SID_MASK 0xE0 #define _RXF14SIDL_EID16_POSN 0x0 #define _RXF14SIDL_EID16_POSITION 0x0 #define _RXF14SIDL_EID16_SIZE 0x1 #define _RXF14SIDL_EID16_LENGTH 0x1 #define _RXF14SIDL_EID16_MASK 0x1 #define _RXF14SIDL_EID17_POSN 0x1 #define _RXF14SIDL_EID17_POSITION 0x1 #define _RXF14SIDL_EID17_SIZE 0x1 #define _RXF14SIDL_EID17_LENGTH 0x1 #define _RXF14SIDL_EID17_MASK 0x2 #define _RXF14SIDL_SID0_POSN 0x5 #define _RXF14SIDL_SID0_POSITION 0x5 #define _RXF14SIDL_SID0_SIZE 0x1 #define _RXF14SIDL_SID0_LENGTH 0x1 #define _RXF14SIDL_SID0_MASK 0x20 #define _RXF14SIDL_SID1_POSN 0x6 #define _RXF14SIDL_SID1_POSITION 0x6 #define _RXF14SIDL_SID1_SIZE 0x1 #define _RXF14SIDL_SID1_LENGTH 0x1 #define _RXF14SIDL_SID1_MASK 0x40 #define _RXF14SIDL_SID2_POSN 0x7 #define _RXF14SIDL_SID2_POSITION 0x7 #define _RXF14SIDL_SID2_SIZE 0x1 #define _RXF14SIDL_SID2_LENGTH 0x1 #define _RXF14SIDL_SID2_MASK 0x80 #define _RXF14SIDL_RXF14EID16_POSN 0x0 #define _RXF14SIDL_RXF14EID16_POSITION 0x0 #define _RXF14SIDL_RXF14EID16_SIZE 0x1 #define _RXF14SIDL_RXF14EID16_LENGTH 0x1 #define _RXF14SIDL_RXF14EID16_MASK 0x1 #define _RXF14SIDL_RXF14EID17_POSN 0x1 #define _RXF14SIDL_RXF14EID17_POSITION 0x1 #define _RXF14SIDL_RXF14EID17_SIZE 0x1 #define _RXF14SIDL_RXF14EID17_LENGTH 0x1 #define _RXF14SIDL_RXF14EID17_MASK 0x2 #define _RXF14SIDL_RXF14EXIDEN_POSN 0x3 #define _RXF14SIDL_RXF14EXIDEN_POSITION 0x3 #define _RXF14SIDL_RXF14EXIDEN_SIZE 0x1 #define _RXF14SIDL_RXF14EXIDEN_LENGTH 0x1 #define _RXF14SIDL_RXF14EXIDEN_MASK 0x8 #define _RXF14SIDL_RXF14SID0_POSN 0x5 #define _RXF14SIDL_RXF14SID0_POSITION 0x5 #define _RXF14SIDL_RXF14SID0_SIZE 0x1 #define _RXF14SIDL_RXF14SID0_LENGTH 0x1 #define _RXF14SIDL_RXF14SID0_MASK 0x20 #define _RXF14SIDL_RXF14SID1_POSN 0x6 #define _RXF14SIDL_RXF14SID1_POSITION 0x6 #define _RXF14SIDL_RXF14SID1_SIZE 0x1 #define _RXF14SIDL_RXF14SID1_LENGTH 0x1 #define _RXF14SIDL_RXF14SID1_MASK 0x40 #define _RXF14SIDL_RXF14SID2_POSN 0x7 #define _RXF14SIDL_RXF14SID2_POSITION 0x7 #define _RXF14SIDL_RXF14SID2_SIZE 0x1 #define _RXF14SIDL_RXF14SID2_LENGTH 0x1 #define _RXF14SIDL_RXF14SID2_MASK 0x80 // Register: RXF14EIDH #define RXF14EIDH RXF14EIDH extern volatile unsigned char RXF14EIDH @ 0xE6A; #ifndef _LIB_BUILD asm("RXF14EIDH equ 0E6Ah"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF14EID8 :1; unsigned RXF14EID9 :1; unsigned RXF14EID10 :1; unsigned RXF14EID11 :1; unsigned RXF14EID12 :1; unsigned RXF14EID13 :1; unsigned RXF14EID14 :1; unsigned RXF14EID15 :1; }; } RXF14EIDHbits_t; extern volatile RXF14EIDHbits_t RXF14EIDHbits @ 0xE6A; // bitfield macros #define _RXF14EIDH_EID_POSN 0x0 #define _RXF14EIDH_EID_POSITION 0x0 #define _RXF14EIDH_EID_SIZE 0x8 #define _RXF14EIDH_EID_LENGTH 0x8 #define _RXF14EIDH_EID_MASK 0xFF #define _RXF14EIDH_EID8_POSN 0x0 #define _RXF14EIDH_EID8_POSITION 0x0 #define _RXF14EIDH_EID8_SIZE 0x1 #define _RXF14EIDH_EID8_LENGTH 0x1 #define _RXF14EIDH_EID8_MASK 0x1 #define _RXF14EIDH_EID9_POSN 0x1 #define _RXF14EIDH_EID9_POSITION 0x1 #define _RXF14EIDH_EID9_SIZE 0x1 #define _RXF14EIDH_EID9_LENGTH 0x1 #define _RXF14EIDH_EID9_MASK 0x2 #define _RXF14EIDH_EID10_POSN 0x2 #define _RXF14EIDH_EID10_POSITION 0x2 #define _RXF14EIDH_EID10_SIZE 0x1 #define _RXF14EIDH_EID10_LENGTH 0x1 #define _RXF14EIDH_EID10_MASK 0x4 #define _RXF14EIDH_EID11_POSN 0x3 #define _RXF14EIDH_EID11_POSITION 0x3 #define _RXF14EIDH_EID11_SIZE 0x1 #define _RXF14EIDH_EID11_LENGTH 0x1 #define _RXF14EIDH_EID11_MASK 0x8 #define _RXF14EIDH_EID12_POSN 0x4 #define _RXF14EIDH_EID12_POSITION 0x4 #define _RXF14EIDH_EID12_SIZE 0x1 #define _RXF14EIDH_EID12_LENGTH 0x1 #define _RXF14EIDH_EID12_MASK 0x10 #define _RXF14EIDH_EID13_POSN 0x5 #define _RXF14EIDH_EID13_POSITION 0x5 #define _RXF14EIDH_EID13_SIZE 0x1 #define _RXF14EIDH_EID13_LENGTH 0x1 #define _RXF14EIDH_EID13_MASK 0x20 #define _RXF14EIDH_EID14_POSN 0x6 #define _RXF14EIDH_EID14_POSITION 0x6 #define _RXF14EIDH_EID14_SIZE 0x1 #define _RXF14EIDH_EID14_LENGTH 0x1 #define _RXF14EIDH_EID14_MASK 0x40 #define _RXF14EIDH_EID15_POSN 0x7 #define _RXF14EIDH_EID15_POSITION 0x7 #define _RXF14EIDH_EID15_SIZE 0x1 #define _RXF14EIDH_EID15_LENGTH 0x1 #define _RXF14EIDH_EID15_MASK 0x80 #define _RXF14EIDH_RXF14EID8_POSN 0x0 #define _RXF14EIDH_RXF14EID8_POSITION 0x0 #define _RXF14EIDH_RXF14EID8_SIZE 0x1 #define _RXF14EIDH_RXF14EID8_LENGTH 0x1 #define _RXF14EIDH_RXF14EID8_MASK 0x1 #define _RXF14EIDH_RXF14EID9_POSN 0x1 #define _RXF14EIDH_RXF14EID9_POSITION 0x1 #define _RXF14EIDH_RXF14EID9_SIZE 0x1 #define _RXF14EIDH_RXF14EID9_LENGTH 0x1 #define _RXF14EIDH_RXF14EID9_MASK 0x2 #define _RXF14EIDH_RXF14EID10_POSN 0x2 #define _RXF14EIDH_RXF14EID10_POSITION 0x2 #define _RXF14EIDH_RXF14EID10_SIZE 0x1 #define _RXF14EIDH_RXF14EID10_LENGTH 0x1 #define _RXF14EIDH_RXF14EID10_MASK 0x4 #define _RXF14EIDH_RXF14EID11_POSN 0x3 #define _RXF14EIDH_RXF14EID11_POSITION 0x3 #define _RXF14EIDH_RXF14EID11_SIZE 0x1 #define _RXF14EIDH_RXF14EID11_LENGTH 0x1 #define _RXF14EIDH_RXF14EID11_MASK 0x8 #define _RXF14EIDH_RXF14EID12_POSN 0x4 #define _RXF14EIDH_RXF14EID12_POSITION 0x4 #define _RXF14EIDH_RXF14EID12_SIZE 0x1 #define _RXF14EIDH_RXF14EID12_LENGTH 0x1 #define _RXF14EIDH_RXF14EID12_MASK 0x10 #define _RXF14EIDH_RXF14EID13_POSN 0x5 #define _RXF14EIDH_RXF14EID13_POSITION 0x5 #define _RXF14EIDH_RXF14EID13_SIZE 0x1 #define _RXF14EIDH_RXF14EID13_LENGTH 0x1 #define _RXF14EIDH_RXF14EID13_MASK 0x20 #define _RXF14EIDH_RXF14EID14_POSN 0x6 #define _RXF14EIDH_RXF14EID14_POSITION 0x6 #define _RXF14EIDH_RXF14EID14_SIZE 0x1 #define _RXF14EIDH_RXF14EID14_LENGTH 0x1 #define _RXF14EIDH_RXF14EID14_MASK 0x40 #define _RXF14EIDH_RXF14EID15_POSN 0x7 #define _RXF14EIDH_RXF14EID15_POSITION 0x7 #define _RXF14EIDH_RXF14EID15_SIZE 0x1 #define _RXF14EIDH_RXF14EID15_LENGTH 0x1 #define _RXF14EIDH_RXF14EID15_MASK 0x80 // Register: RXF14EIDL #define RXF14EIDL RXF14EIDL extern volatile unsigned char RXF14EIDL @ 0xE6B; #ifndef _LIB_BUILD asm("RXF14EIDL equ 0E6Bh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF14EID0 :1; unsigned RXF14EID1 :1; unsigned RXF14EID2 :1; unsigned RXF14EID3 :1; unsigned RXF14EID4 :1; unsigned RXF14EID5 :1; unsigned RXF14EID6 :1; unsigned RXF14EID7 :1; }; } RXF14EIDLbits_t; extern volatile RXF14EIDLbits_t RXF14EIDLbits @ 0xE6B; // bitfield macros #define _RXF14EIDL_EID_POSN 0x0 #define _RXF14EIDL_EID_POSITION 0x0 #define _RXF14EIDL_EID_SIZE 0x8 #define _RXF14EIDL_EID_LENGTH 0x8 #define _RXF14EIDL_EID_MASK 0xFF #define _RXF14EIDL_EID0_POSN 0x0 #define _RXF14EIDL_EID0_POSITION 0x0 #define _RXF14EIDL_EID0_SIZE 0x1 #define _RXF14EIDL_EID0_LENGTH 0x1 #define _RXF14EIDL_EID0_MASK 0x1 #define _RXF14EIDL_EID1_POSN 0x1 #define _RXF14EIDL_EID1_POSITION 0x1 #define _RXF14EIDL_EID1_SIZE 0x1 #define _RXF14EIDL_EID1_LENGTH 0x1 #define _RXF14EIDL_EID1_MASK 0x2 #define _RXF14EIDL_EID2_POSN 0x2 #define _RXF14EIDL_EID2_POSITION 0x2 #define _RXF14EIDL_EID2_SIZE 0x1 #define _RXF14EIDL_EID2_LENGTH 0x1 #define _RXF14EIDL_EID2_MASK 0x4 #define _RXF14EIDL_EID3_POSN 0x3 #define _RXF14EIDL_EID3_POSITION 0x3 #define _RXF14EIDL_EID3_SIZE 0x1 #define _RXF14EIDL_EID3_LENGTH 0x1 #define _RXF14EIDL_EID3_MASK 0x8 #define _RXF14EIDL_EID4_POSN 0x4 #define _RXF14EIDL_EID4_POSITION 0x4 #define _RXF14EIDL_EID4_SIZE 0x1 #define _RXF14EIDL_EID4_LENGTH 0x1 #define _RXF14EIDL_EID4_MASK 0x10 #define _RXF14EIDL_EID5_POSN 0x5 #define _RXF14EIDL_EID5_POSITION 0x5 #define _RXF14EIDL_EID5_SIZE 0x1 #define _RXF14EIDL_EID5_LENGTH 0x1 #define _RXF14EIDL_EID5_MASK 0x20 #define _RXF14EIDL_EID6_POSN 0x6 #define _RXF14EIDL_EID6_POSITION 0x6 #define _RXF14EIDL_EID6_SIZE 0x1 #define _RXF14EIDL_EID6_LENGTH 0x1 #define _RXF14EIDL_EID6_MASK 0x40 #define _RXF14EIDL_EID7_POSN 0x7 #define _RXF14EIDL_EID7_POSITION 0x7 #define _RXF14EIDL_EID7_SIZE 0x1 #define _RXF14EIDL_EID7_LENGTH 0x1 #define _RXF14EIDL_EID7_MASK 0x80 #define _RXF14EIDL_RXF14EID0_POSN 0x0 #define _RXF14EIDL_RXF14EID0_POSITION 0x0 #define _RXF14EIDL_RXF14EID0_SIZE 0x1 #define _RXF14EIDL_RXF14EID0_LENGTH 0x1 #define _RXF14EIDL_RXF14EID0_MASK 0x1 #define _RXF14EIDL_RXF14EID1_POSN 0x1 #define _RXF14EIDL_RXF14EID1_POSITION 0x1 #define _RXF14EIDL_RXF14EID1_SIZE 0x1 #define _RXF14EIDL_RXF14EID1_LENGTH 0x1 #define _RXF14EIDL_RXF14EID1_MASK 0x2 #define _RXF14EIDL_RXF14EID2_POSN 0x2 #define _RXF14EIDL_RXF14EID2_POSITION 0x2 #define _RXF14EIDL_RXF14EID2_SIZE 0x1 #define _RXF14EIDL_RXF14EID2_LENGTH 0x1 #define _RXF14EIDL_RXF14EID2_MASK 0x4 #define _RXF14EIDL_RXF14EID3_POSN 0x3 #define _RXF14EIDL_RXF14EID3_POSITION 0x3 #define _RXF14EIDL_RXF14EID3_SIZE 0x1 #define _RXF14EIDL_RXF14EID3_LENGTH 0x1 #define _RXF14EIDL_RXF14EID3_MASK 0x8 #define _RXF14EIDL_RXF14EID4_POSN 0x4 #define _RXF14EIDL_RXF14EID4_POSITION 0x4 #define _RXF14EIDL_RXF14EID4_SIZE 0x1 #define _RXF14EIDL_RXF14EID4_LENGTH 0x1 #define _RXF14EIDL_RXF14EID4_MASK 0x10 #define _RXF14EIDL_RXF14EID5_POSN 0x5 #define _RXF14EIDL_RXF14EID5_POSITION 0x5 #define _RXF14EIDL_RXF14EID5_SIZE 0x1 #define _RXF14EIDL_RXF14EID5_LENGTH 0x1 #define _RXF14EIDL_RXF14EID5_MASK 0x20 #define _RXF14EIDL_RXF14EID6_POSN 0x6 #define _RXF14EIDL_RXF14EID6_POSITION 0x6 #define _RXF14EIDL_RXF14EID6_SIZE 0x1 #define _RXF14EIDL_RXF14EID6_LENGTH 0x1 #define _RXF14EIDL_RXF14EID6_MASK 0x40 #define _RXF14EIDL_RXF14EID7_POSN 0x7 #define _RXF14EIDL_RXF14EID7_POSITION 0x7 #define _RXF14EIDL_RXF14EID7_SIZE 0x1 #define _RXF14EIDL_RXF14EID7_LENGTH 0x1 #define _RXF14EIDL_RXF14EID7_MASK 0x80 // Register: RXF15SIDH #define RXF15SIDH RXF15SIDH extern volatile unsigned char RXF15SIDH @ 0xE6C; #ifndef _LIB_BUILD asm("RXF15SIDH equ 0E6Ch"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF15SID3 :1; unsigned RXF15SID4 :1; unsigned RXF15SID5 :1; unsigned RXF15SID6 :1; unsigned RXF15SID7 :1; unsigned RXF15SID8 :1; unsigned RXF15SID9 :1; unsigned RXF15SID10 :1; }; } RXF15SIDHbits_t; extern volatile RXF15SIDHbits_t RXF15SIDHbits @ 0xE6C; // bitfield macros #define _RXF15SIDH_SID_POSN 0x0 #define _RXF15SIDH_SID_POSITION 0x0 #define _RXF15SIDH_SID_SIZE 0x8 #define _RXF15SIDH_SID_LENGTH 0x8 #define _RXF15SIDH_SID_MASK 0xFF #define _RXF15SIDH_SID3_POSN 0x0 #define _RXF15SIDH_SID3_POSITION 0x0 #define _RXF15SIDH_SID3_SIZE 0x1 #define _RXF15SIDH_SID3_LENGTH 0x1 #define _RXF15SIDH_SID3_MASK 0x1 #define _RXF15SIDH_SID4_POSN 0x1 #define _RXF15SIDH_SID4_POSITION 0x1 #define _RXF15SIDH_SID4_SIZE 0x1 #define _RXF15SIDH_SID4_LENGTH 0x1 #define _RXF15SIDH_SID4_MASK 0x2 #define _RXF15SIDH_SID5_POSN 0x2 #define _RXF15SIDH_SID5_POSITION 0x2 #define _RXF15SIDH_SID5_SIZE 0x1 #define _RXF15SIDH_SID5_LENGTH 0x1 #define _RXF15SIDH_SID5_MASK 0x4 #define _RXF15SIDH_SID6_POSN 0x3 #define _RXF15SIDH_SID6_POSITION 0x3 #define _RXF15SIDH_SID6_SIZE 0x1 #define _RXF15SIDH_SID6_LENGTH 0x1 #define _RXF15SIDH_SID6_MASK 0x8 #define _RXF15SIDH_SID7_POSN 0x4 #define _RXF15SIDH_SID7_POSITION 0x4 #define _RXF15SIDH_SID7_SIZE 0x1 #define _RXF15SIDH_SID7_LENGTH 0x1 #define _RXF15SIDH_SID7_MASK 0x10 #define _RXF15SIDH_SID8_POSN 0x5 #define _RXF15SIDH_SID8_POSITION 0x5 #define _RXF15SIDH_SID8_SIZE 0x1 #define _RXF15SIDH_SID8_LENGTH 0x1 #define _RXF15SIDH_SID8_MASK 0x20 #define _RXF15SIDH_SID9_POSN 0x6 #define _RXF15SIDH_SID9_POSITION 0x6 #define _RXF15SIDH_SID9_SIZE 0x1 #define _RXF15SIDH_SID9_LENGTH 0x1 #define _RXF15SIDH_SID9_MASK 0x40 #define _RXF15SIDH_SID10_POSN 0x7 #define _RXF15SIDH_SID10_POSITION 0x7 #define _RXF15SIDH_SID10_SIZE 0x1 #define _RXF15SIDH_SID10_LENGTH 0x1 #define _RXF15SIDH_SID10_MASK 0x80 #define _RXF15SIDH_RXF15SID3_POSN 0x0 #define _RXF15SIDH_RXF15SID3_POSITION 0x0 #define _RXF15SIDH_RXF15SID3_SIZE 0x1 #define _RXF15SIDH_RXF15SID3_LENGTH 0x1 #define _RXF15SIDH_RXF15SID3_MASK 0x1 #define _RXF15SIDH_RXF15SID4_POSN 0x1 #define _RXF15SIDH_RXF15SID4_POSITION 0x1 #define _RXF15SIDH_RXF15SID4_SIZE 0x1 #define _RXF15SIDH_RXF15SID4_LENGTH 0x1 #define _RXF15SIDH_RXF15SID4_MASK 0x2 #define _RXF15SIDH_RXF15SID5_POSN 0x2 #define _RXF15SIDH_RXF15SID5_POSITION 0x2 #define _RXF15SIDH_RXF15SID5_SIZE 0x1 #define _RXF15SIDH_RXF15SID5_LENGTH 0x1 #define _RXF15SIDH_RXF15SID5_MASK 0x4 #define _RXF15SIDH_RXF15SID6_POSN 0x3 #define _RXF15SIDH_RXF15SID6_POSITION 0x3 #define _RXF15SIDH_RXF15SID6_SIZE 0x1 #define _RXF15SIDH_RXF15SID6_LENGTH 0x1 #define _RXF15SIDH_RXF15SID6_MASK 0x8 #define _RXF15SIDH_RXF15SID7_POSN 0x4 #define _RXF15SIDH_RXF15SID7_POSITION 0x4 #define _RXF15SIDH_RXF15SID7_SIZE 0x1 #define _RXF15SIDH_RXF15SID7_LENGTH 0x1 #define _RXF15SIDH_RXF15SID7_MASK 0x10 #define _RXF15SIDH_RXF15SID8_POSN 0x5 #define _RXF15SIDH_RXF15SID8_POSITION 0x5 #define _RXF15SIDH_RXF15SID8_SIZE 0x1 #define _RXF15SIDH_RXF15SID8_LENGTH 0x1 #define _RXF15SIDH_RXF15SID8_MASK 0x20 #define _RXF15SIDH_RXF15SID9_POSN 0x6 #define _RXF15SIDH_RXF15SID9_POSITION 0x6 #define _RXF15SIDH_RXF15SID9_SIZE 0x1 #define _RXF15SIDH_RXF15SID9_LENGTH 0x1 #define _RXF15SIDH_RXF15SID9_MASK 0x40 #define _RXF15SIDH_RXF15SID10_POSN 0x7 #define _RXF15SIDH_RXF15SID10_POSITION 0x7 #define _RXF15SIDH_RXF15SID10_SIZE 0x1 #define _RXF15SIDH_RXF15SID10_LENGTH 0x1 #define _RXF15SIDH_RXF15SID10_MASK 0x80 // Register: RXF15SIDL #define RXF15SIDL RXF15SIDL extern volatile unsigned char RXF15SIDL @ 0xE6D; #ifndef _LIB_BUILD asm("RXF15SIDL equ 0E6Dh"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF15EID16 :1; unsigned RXF15EID17 :1; unsigned :1; unsigned RXF15EXIDEN :1; unsigned :1; unsigned RXF15SID0 :1; unsigned RXF15SID1 :1; unsigned RXF15SID2 :1; }; } RXF15SIDLbits_t; extern volatile RXF15SIDLbits_t RXF15SIDLbits @ 0xE6D; // bitfield macros #define _RXF15SIDL_EID_POSN 0x0 #define _RXF15SIDL_EID_POSITION 0x0 #define _RXF15SIDL_EID_SIZE 0x2 #define _RXF15SIDL_EID_LENGTH 0x2 #define _RXF15SIDL_EID_MASK 0x3 #define _RXF15SIDL_EXIDEN_POSN 0x3 #define _RXF15SIDL_EXIDEN_POSITION 0x3 #define _RXF15SIDL_EXIDEN_SIZE 0x1 #define _RXF15SIDL_EXIDEN_LENGTH 0x1 #define _RXF15SIDL_EXIDEN_MASK 0x8 #define _RXF15SIDL_SID_POSN 0x5 #define _RXF15SIDL_SID_POSITION 0x5 #define _RXF15SIDL_SID_SIZE 0x3 #define _RXF15SIDL_SID_LENGTH 0x3 #define _RXF15SIDL_SID_MASK 0xE0 #define _RXF15SIDL_EID16_POSN 0x0 #define _RXF15SIDL_EID16_POSITION 0x0 #define _RXF15SIDL_EID16_SIZE 0x1 #define _RXF15SIDL_EID16_LENGTH 0x1 #define _RXF15SIDL_EID16_MASK 0x1 #define _RXF15SIDL_EID17_POSN 0x1 #define _RXF15SIDL_EID17_POSITION 0x1 #define _RXF15SIDL_EID17_SIZE 0x1 #define _RXF15SIDL_EID17_LENGTH 0x1 #define _RXF15SIDL_EID17_MASK 0x2 #define _RXF15SIDL_SID0_POSN 0x5 #define _RXF15SIDL_SID0_POSITION 0x5 #define _RXF15SIDL_SID0_SIZE 0x1 #define _RXF15SIDL_SID0_LENGTH 0x1 #define _RXF15SIDL_SID0_MASK 0x20 #define _RXF15SIDL_SID1_POSN 0x6 #define _RXF15SIDL_SID1_POSITION 0x6 #define _RXF15SIDL_SID1_SIZE 0x1 #define _RXF15SIDL_SID1_LENGTH 0x1 #define _RXF15SIDL_SID1_MASK 0x40 #define _RXF15SIDL_SID2_POSN 0x7 #define _RXF15SIDL_SID2_POSITION 0x7 #define _RXF15SIDL_SID2_SIZE 0x1 #define _RXF15SIDL_SID2_LENGTH 0x1 #define _RXF15SIDL_SID2_MASK 0x80 #define _RXF15SIDL_RXF15EID16_POSN 0x0 #define _RXF15SIDL_RXF15EID16_POSITION 0x0 #define _RXF15SIDL_RXF15EID16_SIZE 0x1 #define _RXF15SIDL_RXF15EID16_LENGTH 0x1 #define _RXF15SIDL_RXF15EID16_MASK 0x1 #define _RXF15SIDL_RXF15EID17_POSN 0x1 #define _RXF15SIDL_RXF15EID17_POSITION 0x1 #define _RXF15SIDL_RXF15EID17_SIZE 0x1 #define _RXF15SIDL_RXF15EID17_LENGTH 0x1 #define _RXF15SIDL_RXF15EID17_MASK 0x2 #define _RXF15SIDL_RXF15EXIDEN_POSN 0x3 #define _RXF15SIDL_RXF15EXIDEN_POSITION 0x3 #define _RXF15SIDL_RXF15EXIDEN_SIZE 0x1 #define _RXF15SIDL_RXF15EXIDEN_LENGTH 0x1 #define _RXF15SIDL_RXF15EXIDEN_MASK 0x8 #define _RXF15SIDL_RXF15SID0_POSN 0x5 #define _RXF15SIDL_RXF15SID0_POSITION 0x5 #define _RXF15SIDL_RXF15SID0_SIZE 0x1 #define _RXF15SIDL_RXF15SID0_LENGTH 0x1 #define _RXF15SIDL_RXF15SID0_MASK 0x20 #define _RXF15SIDL_RXF15SID1_POSN 0x6 #define _RXF15SIDL_RXF15SID1_POSITION 0x6 #define _RXF15SIDL_RXF15SID1_SIZE 0x1 #define _RXF15SIDL_RXF15SID1_LENGTH 0x1 #define _RXF15SIDL_RXF15SID1_MASK 0x40 #define _RXF15SIDL_RXF15SID2_POSN 0x7 #define _RXF15SIDL_RXF15SID2_POSITION 0x7 #define _RXF15SIDL_RXF15SID2_SIZE 0x1 #define _RXF15SIDL_RXF15SID2_LENGTH 0x1 #define _RXF15SIDL_RXF15SID2_MASK 0x80 // Register: RXF15EIDH #define RXF15EIDH RXF15EIDH extern volatile unsigned char RXF15EIDH @ 0xE6E; #ifndef _LIB_BUILD asm("RXF15EIDH equ 0E6Eh"); #endif // bitfield definitions typedef union { struct { unsigned RXFEID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF15EID8 :1; unsigned RXF15EID9 :1; unsigned RXF15EID10 :1; unsigned RXF15EID11 :1; unsigned RXF15EID12 :1; unsigned RXF15EID13 :1; unsigned RXF15EID14 :1; unsigned RXF15EID15 :1; }; } RXF15EIDHbits_t; extern volatile RXF15EIDHbits_t RXF15EIDHbits @ 0xE6E; // bitfield macros #define _RXF15EIDH_RXFEID_POSN 0x0 #define _RXF15EIDH_RXFEID_POSITION 0x0 #define _RXF15EIDH_RXFEID_SIZE 0x8 #define _RXF15EIDH_RXFEID_LENGTH 0x8 #define _RXF15EIDH_RXFEID_MASK 0xFF #define _RXF15EIDH_EID8_POSN 0x0 #define _RXF15EIDH_EID8_POSITION 0x0 #define _RXF15EIDH_EID8_SIZE 0x1 #define _RXF15EIDH_EID8_LENGTH 0x1 #define _RXF15EIDH_EID8_MASK 0x1 #define _RXF15EIDH_EID9_POSN 0x1 #define _RXF15EIDH_EID9_POSITION 0x1 #define _RXF15EIDH_EID9_SIZE 0x1 #define _RXF15EIDH_EID9_LENGTH 0x1 #define _RXF15EIDH_EID9_MASK 0x2 #define _RXF15EIDH_EID10_POSN 0x2 #define _RXF15EIDH_EID10_POSITION 0x2 #define _RXF15EIDH_EID10_SIZE 0x1 #define _RXF15EIDH_EID10_LENGTH 0x1 #define _RXF15EIDH_EID10_MASK 0x4 #define _RXF15EIDH_EID11_POSN 0x3 #define _RXF15EIDH_EID11_POSITION 0x3 #define _RXF15EIDH_EID11_SIZE 0x1 #define _RXF15EIDH_EID11_LENGTH 0x1 #define _RXF15EIDH_EID11_MASK 0x8 #define _RXF15EIDH_EID12_POSN 0x4 #define _RXF15EIDH_EID12_POSITION 0x4 #define _RXF15EIDH_EID12_SIZE 0x1 #define _RXF15EIDH_EID12_LENGTH 0x1 #define _RXF15EIDH_EID12_MASK 0x10 #define _RXF15EIDH_EID13_POSN 0x5 #define _RXF15EIDH_EID13_POSITION 0x5 #define _RXF15EIDH_EID13_SIZE 0x1 #define _RXF15EIDH_EID13_LENGTH 0x1 #define _RXF15EIDH_EID13_MASK 0x20 #define _RXF15EIDH_EID14_POSN 0x6 #define _RXF15EIDH_EID14_POSITION 0x6 #define _RXF15EIDH_EID14_SIZE 0x1 #define _RXF15EIDH_EID14_LENGTH 0x1 #define _RXF15EIDH_EID14_MASK 0x40 #define _RXF15EIDH_EID15_POSN 0x7 #define _RXF15EIDH_EID15_POSITION 0x7 #define _RXF15EIDH_EID15_SIZE 0x1 #define _RXF15EIDH_EID15_LENGTH 0x1 #define _RXF15EIDH_EID15_MASK 0x80 #define _RXF15EIDH_RXF15EID8_POSN 0x0 #define _RXF15EIDH_RXF15EID8_POSITION 0x0 #define _RXF15EIDH_RXF15EID8_SIZE 0x1 #define _RXF15EIDH_RXF15EID8_LENGTH 0x1 #define _RXF15EIDH_RXF15EID8_MASK 0x1 #define _RXF15EIDH_RXF15EID9_POSN 0x1 #define _RXF15EIDH_RXF15EID9_POSITION 0x1 #define _RXF15EIDH_RXF15EID9_SIZE 0x1 #define _RXF15EIDH_RXF15EID9_LENGTH 0x1 #define _RXF15EIDH_RXF15EID9_MASK 0x2 #define _RXF15EIDH_RXF15EID10_POSN 0x2 #define _RXF15EIDH_RXF15EID10_POSITION 0x2 #define _RXF15EIDH_RXF15EID10_SIZE 0x1 #define _RXF15EIDH_RXF15EID10_LENGTH 0x1 #define _RXF15EIDH_RXF15EID10_MASK 0x4 #define _RXF15EIDH_RXF15EID11_POSN 0x3 #define _RXF15EIDH_RXF15EID11_POSITION 0x3 #define _RXF15EIDH_RXF15EID11_SIZE 0x1 #define _RXF15EIDH_RXF15EID11_LENGTH 0x1 #define _RXF15EIDH_RXF15EID11_MASK 0x8 #define _RXF15EIDH_RXF15EID12_POSN 0x4 #define _RXF15EIDH_RXF15EID12_POSITION 0x4 #define _RXF15EIDH_RXF15EID12_SIZE 0x1 #define _RXF15EIDH_RXF15EID12_LENGTH 0x1 #define _RXF15EIDH_RXF15EID12_MASK 0x10 #define _RXF15EIDH_RXF15EID13_POSN 0x5 #define _RXF15EIDH_RXF15EID13_POSITION 0x5 #define _RXF15EIDH_RXF15EID13_SIZE 0x1 #define _RXF15EIDH_RXF15EID13_LENGTH 0x1 #define _RXF15EIDH_RXF15EID13_MASK 0x20 #define _RXF15EIDH_RXF15EID14_POSN 0x6 #define _RXF15EIDH_RXF15EID14_POSITION 0x6 #define _RXF15EIDH_RXF15EID14_SIZE 0x1 #define _RXF15EIDH_RXF15EID14_LENGTH 0x1 #define _RXF15EIDH_RXF15EID14_MASK 0x40 #define _RXF15EIDH_RXF15EID15_POSN 0x7 #define _RXF15EIDH_RXF15EID15_POSITION 0x7 #define _RXF15EIDH_RXF15EID15_SIZE 0x1 #define _RXF15EIDH_RXF15EID15_LENGTH 0x1 #define _RXF15EIDH_RXF15EID15_MASK 0x80 // Register: RXF15EIDL #define RXF15EIDL RXF15EIDL extern volatile unsigned char RXF15EIDL @ 0xE6F; #ifndef _LIB_BUILD asm("RXF15EIDL equ 0E6Fh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF15EID0 :1; unsigned RXF15EID1 :1; unsigned RXF15EID2 :1; unsigned RXF15EID3 :1; unsigned RXF15EID4 :1; unsigned RXF15EID5 :1; unsigned RXF15EID6 :1; unsigned RXF15EID7 :1; }; } RXF15EIDLbits_t; extern volatile RXF15EIDLbits_t RXF15EIDLbits @ 0xE6F; // bitfield macros #define _RXF15EIDL_EID_POSN 0x0 #define _RXF15EIDL_EID_POSITION 0x0 #define _RXF15EIDL_EID_SIZE 0x8 #define _RXF15EIDL_EID_LENGTH 0x8 #define _RXF15EIDL_EID_MASK 0xFF #define _RXF15EIDL_EID0_POSN 0x0 #define _RXF15EIDL_EID0_POSITION 0x0 #define _RXF15EIDL_EID0_SIZE 0x1 #define _RXF15EIDL_EID0_LENGTH 0x1 #define _RXF15EIDL_EID0_MASK 0x1 #define _RXF15EIDL_EID1_POSN 0x1 #define _RXF15EIDL_EID1_POSITION 0x1 #define _RXF15EIDL_EID1_SIZE 0x1 #define _RXF15EIDL_EID1_LENGTH 0x1 #define _RXF15EIDL_EID1_MASK 0x2 #define _RXF15EIDL_EID2_POSN 0x2 #define _RXF15EIDL_EID2_POSITION 0x2 #define _RXF15EIDL_EID2_SIZE 0x1 #define _RXF15EIDL_EID2_LENGTH 0x1 #define _RXF15EIDL_EID2_MASK 0x4 #define _RXF15EIDL_EID3_POSN 0x3 #define _RXF15EIDL_EID3_POSITION 0x3 #define _RXF15EIDL_EID3_SIZE 0x1 #define _RXF15EIDL_EID3_LENGTH 0x1 #define _RXF15EIDL_EID3_MASK 0x8 #define _RXF15EIDL_EID4_POSN 0x4 #define _RXF15EIDL_EID4_POSITION 0x4 #define _RXF15EIDL_EID4_SIZE 0x1 #define _RXF15EIDL_EID4_LENGTH 0x1 #define _RXF15EIDL_EID4_MASK 0x10 #define _RXF15EIDL_EID5_POSN 0x5 #define _RXF15EIDL_EID5_POSITION 0x5 #define _RXF15EIDL_EID5_SIZE 0x1 #define _RXF15EIDL_EID5_LENGTH 0x1 #define _RXF15EIDL_EID5_MASK 0x20 #define _RXF15EIDL_EID6_POSN 0x6 #define _RXF15EIDL_EID6_POSITION 0x6 #define _RXF15EIDL_EID6_SIZE 0x1 #define _RXF15EIDL_EID6_LENGTH 0x1 #define _RXF15EIDL_EID6_MASK 0x40 #define _RXF15EIDL_EID7_POSN 0x7 #define _RXF15EIDL_EID7_POSITION 0x7 #define _RXF15EIDL_EID7_SIZE 0x1 #define _RXF15EIDL_EID7_LENGTH 0x1 #define _RXF15EIDL_EID7_MASK 0x80 #define _RXF15EIDL_RXF15EID0_POSN 0x0 #define _RXF15EIDL_RXF15EID0_POSITION 0x0 #define _RXF15EIDL_RXF15EID0_SIZE 0x1 #define _RXF15EIDL_RXF15EID0_LENGTH 0x1 #define _RXF15EIDL_RXF15EID0_MASK 0x1 #define _RXF15EIDL_RXF15EID1_POSN 0x1 #define _RXF15EIDL_RXF15EID1_POSITION 0x1 #define _RXF15EIDL_RXF15EID1_SIZE 0x1 #define _RXF15EIDL_RXF15EID1_LENGTH 0x1 #define _RXF15EIDL_RXF15EID1_MASK 0x2 #define _RXF15EIDL_RXF15EID2_POSN 0x2 #define _RXF15EIDL_RXF15EID2_POSITION 0x2 #define _RXF15EIDL_RXF15EID2_SIZE 0x1 #define _RXF15EIDL_RXF15EID2_LENGTH 0x1 #define _RXF15EIDL_RXF15EID2_MASK 0x4 #define _RXF15EIDL_RXF15EID3_POSN 0x3 #define _RXF15EIDL_RXF15EID3_POSITION 0x3 #define _RXF15EIDL_RXF15EID3_SIZE 0x1 #define _RXF15EIDL_RXF15EID3_LENGTH 0x1 #define _RXF15EIDL_RXF15EID3_MASK 0x8 #define _RXF15EIDL_RXF15EID4_POSN 0x4 #define _RXF15EIDL_RXF15EID4_POSITION 0x4 #define _RXF15EIDL_RXF15EID4_SIZE 0x1 #define _RXF15EIDL_RXF15EID4_LENGTH 0x1 #define _RXF15EIDL_RXF15EID4_MASK 0x10 #define _RXF15EIDL_RXF15EID5_POSN 0x5 #define _RXF15EIDL_RXF15EID5_POSITION 0x5 #define _RXF15EIDL_RXF15EID5_SIZE 0x1 #define _RXF15EIDL_RXF15EID5_LENGTH 0x1 #define _RXF15EIDL_RXF15EID5_MASK 0x20 #define _RXF15EIDL_RXF15EID6_POSN 0x6 #define _RXF15EIDL_RXF15EID6_POSITION 0x6 #define _RXF15EIDL_RXF15EID6_SIZE 0x1 #define _RXF15EIDL_RXF15EID6_LENGTH 0x1 #define _RXF15EIDL_RXF15EID6_MASK 0x40 #define _RXF15EIDL_RXF15EID7_POSN 0x7 #define _RXF15EIDL_RXF15EID7_POSITION 0x7 #define _RXF15EIDL_RXF15EID7_SIZE 0x1 #define _RXF15EIDL_RXF15EID7_LENGTH 0x1 #define _RXF15EIDL_RXF15EID7_MASK 0x80 // Register: SDFLC #define SDFLC SDFLC extern volatile unsigned char SDFLC @ 0xE70; #ifndef _LIB_BUILD asm("SDFLC equ 0E70h"); #endif // bitfield definitions typedef union { struct { unsigned FLC :5; }; struct { unsigned FLC0 :1; unsigned FLC1 :1; unsigned FLC2 :1; unsigned FLC3 :1; unsigned FLC4 :1; }; } SDFLCbits_t; extern volatile SDFLCbits_t SDFLCbits @ 0xE70; // bitfield macros #define _SDFLC_FLC_POSN 0x0 #define _SDFLC_FLC_POSITION 0x0 #define _SDFLC_FLC_SIZE 0x5 #define _SDFLC_FLC_LENGTH 0x5 #define _SDFLC_FLC_MASK 0x1F #define _SDFLC_FLC0_POSN 0x0 #define _SDFLC_FLC0_POSITION 0x0 #define _SDFLC_FLC0_SIZE 0x1 #define _SDFLC_FLC0_LENGTH 0x1 #define _SDFLC_FLC0_MASK 0x1 #define _SDFLC_FLC1_POSN 0x1 #define _SDFLC_FLC1_POSITION 0x1 #define _SDFLC_FLC1_SIZE 0x1 #define _SDFLC_FLC1_LENGTH 0x1 #define _SDFLC_FLC1_MASK 0x2 #define _SDFLC_FLC2_POSN 0x2 #define _SDFLC_FLC2_POSITION 0x2 #define _SDFLC_FLC2_SIZE 0x1 #define _SDFLC_FLC2_LENGTH 0x1 #define _SDFLC_FLC2_MASK 0x4 #define _SDFLC_FLC3_POSN 0x3 #define _SDFLC_FLC3_POSITION 0x3 #define _SDFLC_FLC3_SIZE 0x1 #define _SDFLC_FLC3_LENGTH 0x1 #define _SDFLC_FLC3_MASK 0x8 #define _SDFLC_FLC4_POSN 0x4 #define _SDFLC_FLC4_POSITION 0x4 #define _SDFLC_FLC4_SIZE 0x1 #define _SDFLC_FLC4_LENGTH 0x1 #define _SDFLC_FLC4_MASK 0x10 // Register: RXFBCON0 #define RXFBCON0 RXFBCON0 extern volatile unsigned char RXFBCON0 @ 0xE71; #ifndef _LIB_BUILD asm("RXFBCON0 equ 0E71h"); #endif // bitfield definitions typedef union { struct { unsigned F0BP :4; unsigned F1BP :4; }; struct { unsigned F0BP_0 :1; unsigned F0BP_1 :1; unsigned F0BP_2 :1; unsigned F0BP_3 :1; unsigned F1BP_0 :1; unsigned F1BP_1 :1; unsigned F1BP_2 :1; unsigned F1BP_3 :1; }; struct { unsigned F0BP_01 :1; }; } RXFBCON0bits_t; extern volatile RXFBCON0bits_t RXFBCON0bits @ 0xE71; // bitfield macros #define _RXFBCON0_F0BP_POSN 0x0 #define _RXFBCON0_F0BP_POSITION 0x0 #define _RXFBCON0_F0BP_SIZE 0x4 #define _RXFBCON0_F0BP_LENGTH 0x4 #define _RXFBCON0_F0BP_MASK 0xF #define _RXFBCON0_F1BP_POSN 0x4 #define _RXFBCON0_F1BP_POSITION 0x4 #define _RXFBCON0_F1BP_SIZE 0x4 #define _RXFBCON0_F1BP_LENGTH 0x4 #define _RXFBCON0_F1BP_MASK 0xF0 #define _RXFBCON0_F0BP_0_POSN 0x0 #define _RXFBCON0_F0BP_0_POSITION 0x0 #define _RXFBCON0_F0BP_0_SIZE 0x1 #define _RXFBCON0_F0BP_0_LENGTH 0x1 #define _RXFBCON0_F0BP_0_MASK 0x1 #define _RXFBCON0_F0BP_1_POSN 0x1 #define _RXFBCON0_F0BP_1_POSITION 0x1 #define _RXFBCON0_F0BP_1_SIZE 0x1 #define _RXFBCON0_F0BP_1_LENGTH 0x1 #define _RXFBCON0_F0BP_1_MASK 0x2 #define _RXFBCON0_F0BP_2_POSN 0x2 #define _RXFBCON0_F0BP_2_POSITION 0x2 #define _RXFBCON0_F0BP_2_SIZE 0x1 #define _RXFBCON0_F0BP_2_LENGTH 0x1 #define _RXFBCON0_F0BP_2_MASK 0x4 #define _RXFBCON0_F0BP_3_POSN 0x3 #define _RXFBCON0_F0BP_3_POSITION 0x3 #define _RXFBCON0_F0BP_3_SIZE 0x1 #define _RXFBCON0_F0BP_3_LENGTH 0x1 #define _RXFBCON0_F0BP_3_MASK 0x8 #define _RXFBCON0_F1BP_0_POSN 0x4 #define _RXFBCON0_F1BP_0_POSITION 0x4 #define _RXFBCON0_F1BP_0_SIZE 0x1 #define _RXFBCON0_F1BP_0_LENGTH 0x1 #define _RXFBCON0_F1BP_0_MASK 0x10 #define _RXFBCON0_F1BP_1_POSN 0x5 #define _RXFBCON0_F1BP_1_POSITION 0x5 #define _RXFBCON0_F1BP_1_SIZE 0x1 #define _RXFBCON0_F1BP_1_LENGTH 0x1 #define _RXFBCON0_F1BP_1_MASK 0x20 #define _RXFBCON0_F1BP_2_POSN 0x6 #define _RXFBCON0_F1BP_2_POSITION 0x6 #define _RXFBCON0_F1BP_2_SIZE 0x1 #define _RXFBCON0_F1BP_2_LENGTH 0x1 #define _RXFBCON0_F1BP_2_MASK 0x40 #define _RXFBCON0_F1BP_3_POSN 0x7 #define _RXFBCON0_F1BP_3_POSITION 0x7 #define _RXFBCON0_F1BP_3_SIZE 0x1 #define _RXFBCON0_F1BP_3_LENGTH 0x1 #define _RXFBCON0_F1BP_3_MASK 0x80 #define _RXFBCON0_F0BP_01_POSN 0x0 #define _RXFBCON0_F0BP_01_POSITION 0x0 #define _RXFBCON0_F0BP_01_SIZE 0x1 #define _RXFBCON0_F0BP_01_LENGTH 0x1 #define _RXFBCON0_F0BP_01_MASK 0x1 // Register: RXFBCON1 #define RXFBCON1 RXFBCON1 extern volatile unsigned char RXFBCON1 @ 0xE72; #ifndef _LIB_BUILD asm("RXFBCON1 equ 0E72h"); #endif // bitfield definitions typedef union { struct { unsigned F2BP :4; unsigned F3BP :4; }; struct { unsigned F2BP_0 :1; unsigned F2BP_1 :1; unsigned F2BP_2 :1; unsigned F2BP_3 :1; unsigned F3BP_0 :1; unsigned F3BP_1 :1; unsigned F3BP_2 :1; unsigned F3BP_3 :1; }; struct { unsigned F2BP_01 :1; }; } RXFBCON1bits_t; extern volatile RXFBCON1bits_t RXFBCON1bits @ 0xE72; // bitfield macros #define _RXFBCON1_F2BP_POSN 0x0 #define _RXFBCON1_F2BP_POSITION 0x0 #define _RXFBCON1_F2BP_SIZE 0x4 #define _RXFBCON1_F2BP_LENGTH 0x4 #define _RXFBCON1_F2BP_MASK 0xF #define _RXFBCON1_F3BP_POSN 0x4 #define _RXFBCON1_F3BP_POSITION 0x4 #define _RXFBCON1_F3BP_SIZE 0x4 #define _RXFBCON1_F3BP_LENGTH 0x4 #define _RXFBCON1_F3BP_MASK 0xF0 #define _RXFBCON1_F2BP_0_POSN 0x0 #define _RXFBCON1_F2BP_0_POSITION 0x0 #define _RXFBCON1_F2BP_0_SIZE 0x1 #define _RXFBCON1_F2BP_0_LENGTH 0x1 #define _RXFBCON1_F2BP_0_MASK 0x1 #define _RXFBCON1_F2BP_1_POSN 0x1 #define _RXFBCON1_F2BP_1_POSITION 0x1 #define _RXFBCON1_F2BP_1_SIZE 0x1 #define _RXFBCON1_F2BP_1_LENGTH 0x1 #define _RXFBCON1_F2BP_1_MASK 0x2 #define _RXFBCON1_F2BP_2_POSN 0x2 #define _RXFBCON1_F2BP_2_POSITION 0x2 #define _RXFBCON1_F2BP_2_SIZE 0x1 #define _RXFBCON1_F2BP_2_LENGTH 0x1 #define _RXFBCON1_F2BP_2_MASK 0x4 #define _RXFBCON1_F2BP_3_POSN 0x3 #define _RXFBCON1_F2BP_3_POSITION 0x3 #define _RXFBCON1_F2BP_3_SIZE 0x1 #define _RXFBCON1_F2BP_3_LENGTH 0x1 #define _RXFBCON1_F2BP_3_MASK 0x8 #define _RXFBCON1_F3BP_0_POSN 0x4 #define _RXFBCON1_F3BP_0_POSITION 0x4 #define _RXFBCON1_F3BP_0_SIZE 0x1 #define _RXFBCON1_F3BP_0_LENGTH 0x1 #define _RXFBCON1_F3BP_0_MASK 0x10 #define _RXFBCON1_F3BP_1_POSN 0x5 #define _RXFBCON1_F3BP_1_POSITION 0x5 #define _RXFBCON1_F3BP_1_SIZE 0x1 #define _RXFBCON1_F3BP_1_LENGTH 0x1 #define _RXFBCON1_F3BP_1_MASK 0x20 #define _RXFBCON1_F3BP_2_POSN 0x6 #define _RXFBCON1_F3BP_2_POSITION 0x6 #define _RXFBCON1_F3BP_2_SIZE 0x1 #define _RXFBCON1_F3BP_2_LENGTH 0x1 #define _RXFBCON1_F3BP_2_MASK 0x40 #define _RXFBCON1_F3BP_3_POSN 0x7 #define _RXFBCON1_F3BP_3_POSITION 0x7 #define _RXFBCON1_F3BP_3_SIZE 0x1 #define _RXFBCON1_F3BP_3_LENGTH 0x1 #define _RXFBCON1_F3BP_3_MASK 0x80 #define _RXFBCON1_F2BP_01_POSN 0x0 #define _RXFBCON1_F2BP_01_POSITION 0x0 #define _RXFBCON1_F2BP_01_SIZE 0x1 #define _RXFBCON1_F2BP_01_LENGTH 0x1 #define _RXFBCON1_F2BP_01_MASK 0x1 // Register: RXFBCON2 #define RXFBCON2 RXFBCON2 extern volatile unsigned char RXFBCON2 @ 0xE73; #ifndef _LIB_BUILD asm("RXFBCON2 equ 0E73h"); #endif // bitfield definitions typedef union { struct { unsigned F4BP :4; unsigned F5BP :4; }; struct { unsigned F4BP_0 :1; unsigned F4BP_1 :1; unsigned F4BP_2 :1; unsigned F4BP_3 :1; unsigned F5BP_0 :1; unsigned F5BP_1 :1; unsigned F5BP_2 :1; unsigned F5BP_3 :1; }; struct { unsigned F4BP_01 :1; }; } RXFBCON2bits_t; extern volatile RXFBCON2bits_t RXFBCON2bits @ 0xE73; // bitfield macros #define _RXFBCON2_F4BP_POSN 0x0 #define _RXFBCON2_F4BP_POSITION 0x0 #define _RXFBCON2_F4BP_SIZE 0x4 #define _RXFBCON2_F4BP_LENGTH 0x4 #define _RXFBCON2_F4BP_MASK 0xF #define _RXFBCON2_F5BP_POSN 0x4 #define _RXFBCON2_F5BP_POSITION 0x4 #define _RXFBCON2_F5BP_SIZE 0x4 #define _RXFBCON2_F5BP_LENGTH 0x4 #define _RXFBCON2_F5BP_MASK 0xF0 #define _RXFBCON2_F4BP_0_POSN 0x0 #define _RXFBCON2_F4BP_0_POSITION 0x0 #define _RXFBCON2_F4BP_0_SIZE 0x1 #define _RXFBCON2_F4BP_0_LENGTH 0x1 #define _RXFBCON2_F4BP_0_MASK 0x1 #define _RXFBCON2_F4BP_1_POSN 0x1 #define _RXFBCON2_F4BP_1_POSITION 0x1 #define _RXFBCON2_F4BP_1_SIZE 0x1 #define _RXFBCON2_F4BP_1_LENGTH 0x1 #define _RXFBCON2_F4BP_1_MASK 0x2 #define _RXFBCON2_F4BP_2_POSN 0x2 #define _RXFBCON2_F4BP_2_POSITION 0x2 #define _RXFBCON2_F4BP_2_SIZE 0x1 #define _RXFBCON2_F4BP_2_LENGTH 0x1 #define _RXFBCON2_F4BP_2_MASK 0x4 #define _RXFBCON2_F4BP_3_POSN 0x3 #define _RXFBCON2_F4BP_3_POSITION 0x3 #define _RXFBCON2_F4BP_3_SIZE 0x1 #define _RXFBCON2_F4BP_3_LENGTH 0x1 #define _RXFBCON2_F4BP_3_MASK 0x8 #define _RXFBCON2_F5BP_0_POSN 0x4 #define _RXFBCON2_F5BP_0_POSITION 0x4 #define _RXFBCON2_F5BP_0_SIZE 0x1 #define _RXFBCON2_F5BP_0_LENGTH 0x1 #define _RXFBCON2_F5BP_0_MASK 0x10 #define _RXFBCON2_F5BP_1_POSN 0x5 #define _RXFBCON2_F5BP_1_POSITION 0x5 #define _RXFBCON2_F5BP_1_SIZE 0x1 #define _RXFBCON2_F5BP_1_LENGTH 0x1 #define _RXFBCON2_F5BP_1_MASK 0x20 #define _RXFBCON2_F5BP_2_POSN 0x6 #define _RXFBCON2_F5BP_2_POSITION 0x6 #define _RXFBCON2_F5BP_2_SIZE 0x1 #define _RXFBCON2_F5BP_2_LENGTH 0x1 #define _RXFBCON2_F5BP_2_MASK 0x40 #define _RXFBCON2_F5BP_3_POSN 0x7 #define _RXFBCON2_F5BP_3_POSITION 0x7 #define _RXFBCON2_F5BP_3_SIZE 0x1 #define _RXFBCON2_F5BP_3_LENGTH 0x1 #define _RXFBCON2_F5BP_3_MASK 0x80 #define _RXFBCON2_F4BP_01_POSN 0x0 #define _RXFBCON2_F4BP_01_POSITION 0x0 #define _RXFBCON2_F4BP_01_SIZE 0x1 #define _RXFBCON2_F4BP_01_LENGTH 0x1 #define _RXFBCON2_F4BP_01_MASK 0x1 // Register: RXFBCON3 #define RXFBCON3 RXFBCON3 extern volatile unsigned char RXFBCON3 @ 0xE74; #ifndef _LIB_BUILD asm("RXFBCON3 equ 0E74h"); #endif // bitfield definitions typedef union { struct { unsigned F6BP :4; unsigned F7BP :4; }; struct { unsigned F6BP_0 :1; unsigned F6BP_1 :1; unsigned F6BP_2 :1; unsigned F6BP_3 :1; unsigned F7BP_0 :1; unsigned F7BP_1 :1; unsigned F7BP_2 :1; unsigned F7BP_3 :1; }; struct { unsigned F6BP_01 :1; }; } RXFBCON3bits_t; extern volatile RXFBCON3bits_t RXFBCON3bits @ 0xE74; // bitfield macros #define _RXFBCON3_F6BP_POSN 0x0 #define _RXFBCON3_F6BP_POSITION 0x0 #define _RXFBCON3_F6BP_SIZE 0x4 #define _RXFBCON3_F6BP_LENGTH 0x4 #define _RXFBCON3_F6BP_MASK 0xF #define _RXFBCON3_F7BP_POSN 0x4 #define _RXFBCON3_F7BP_POSITION 0x4 #define _RXFBCON3_F7BP_SIZE 0x4 #define _RXFBCON3_F7BP_LENGTH 0x4 #define _RXFBCON3_F7BP_MASK 0xF0 #define _RXFBCON3_F6BP_0_POSN 0x0 #define _RXFBCON3_F6BP_0_POSITION 0x0 #define _RXFBCON3_F6BP_0_SIZE 0x1 #define _RXFBCON3_F6BP_0_LENGTH 0x1 #define _RXFBCON3_F6BP_0_MASK 0x1 #define _RXFBCON3_F6BP_1_POSN 0x1 #define _RXFBCON3_F6BP_1_POSITION 0x1 #define _RXFBCON3_F6BP_1_SIZE 0x1 #define _RXFBCON3_F6BP_1_LENGTH 0x1 #define _RXFBCON3_F6BP_1_MASK 0x2 #define _RXFBCON3_F6BP_2_POSN 0x2 #define _RXFBCON3_F6BP_2_POSITION 0x2 #define _RXFBCON3_F6BP_2_SIZE 0x1 #define _RXFBCON3_F6BP_2_LENGTH 0x1 #define _RXFBCON3_F6BP_2_MASK 0x4 #define _RXFBCON3_F6BP_3_POSN 0x3 #define _RXFBCON3_F6BP_3_POSITION 0x3 #define _RXFBCON3_F6BP_3_SIZE 0x1 #define _RXFBCON3_F6BP_3_LENGTH 0x1 #define _RXFBCON3_F6BP_3_MASK 0x8 #define _RXFBCON3_F7BP_0_POSN 0x4 #define _RXFBCON3_F7BP_0_POSITION 0x4 #define _RXFBCON3_F7BP_0_SIZE 0x1 #define _RXFBCON3_F7BP_0_LENGTH 0x1 #define _RXFBCON3_F7BP_0_MASK 0x10 #define _RXFBCON3_F7BP_1_POSN 0x5 #define _RXFBCON3_F7BP_1_POSITION 0x5 #define _RXFBCON3_F7BP_1_SIZE 0x1 #define _RXFBCON3_F7BP_1_LENGTH 0x1 #define _RXFBCON3_F7BP_1_MASK 0x20 #define _RXFBCON3_F7BP_2_POSN 0x6 #define _RXFBCON3_F7BP_2_POSITION 0x6 #define _RXFBCON3_F7BP_2_SIZE 0x1 #define _RXFBCON3_F7BP_2_LENGTH 0x1 #define _RXFBCON3_F7BP_2_MASK 0x40 #define _RXFBCON3_F7BP_3_POSN 0x7 #define _RXFBCON3_F7BP_3_POSITION 0x7 #define _RXFBCON3_F7BP_3_SIZE 0x1 #define _RXFBCON3_F7BP_3_LENGTH 0x1 #define _RXFBCON3_F7BP_3_MASK 0x80 #define _RXFBCON3_F6BP_01_POSN 0x0 #define _RXFBCON3_F6BP_01_POSITION 0x0 #define _RXFBCON3_F6BP_01_SIZE 0x1 #define _RXFBCON3_F6BP_01_LENGTH 0x1 #define _RXFBCON3_F6BP_01_MASK 0x1 // Register: RXFBCON4 #define RXFBCON4 RXFBCON4 extern volatile unsigned char RXFBCON4 @ 0xE75; #ifndef _LIB_BUILD asm("RXFBCON4 equ 0E75h"); #endif // bitfield definitions typedef union { struct { unsigned F8BP :4; unsigned F9BP :4; }; struct { unsigned F8BP_0 :1; unsigned F8BP_1 :1; unsigned F8BP_2 :1; unsigned F8BP_3 :1; unsigned F9BP_0 :1; unsigned F9BP_1 :1; unsigned F9BP_2 :1; unsigned F9BP_3 :1; }; struct { unsigned F8BP_01 :1; }; } RXFBCON4bits_t; extern volatile RXFBCON4bits_t RXFBCON4bits @ 0xE75; // bitfield macros #define _RXFBCON4_F8BP_POSN 0x0 #define _RXFBCON4_F8BP_POSITION 0x0 #define _RXFBCON4_F8BP_SIZE 0x4 #define _RXFBCON4_F8BP_LENGTH 0x4 #define _RXFBCON4_F8BP_MASK 0xF #define _RXFBCON4_F9BP_POSN 0x4 #define _RXFBCON4_F9BP_POSITION 0x4 #define _RXFBCON4_F9BP_SIZE 0x4 #define _RXFBCON4_F9BP_LENGTH 0x4 #define _RXFBCON4_F9BP_MASK 0xF0 #define _RXFBCON4_F8BP_0_POSN 0x0 #define _RXFBCON4_F8BP_0_POSITION 0x0 #define _RXFBCON4_F8BP_0_SIZE 0x1 #define _RXFBCON4_F8BP_0_LENGTH 0x1 #define _RXFBCON4_F8BP_0_MASK 0x1 #define _RXFBCON4_F8BP_1_POSN 0x1 #define _RXFBCON4_F8BP_1_POSITION 0x1 #define _RXFBCON4_F8BP_1_SIZE 0x1 #define _RXFBCON4_F8BP_1_LENGTH 0x1 #define _RXFBCON4_F8BP_1_MASK 0x2 #define _RXFBCON4_F8BP_2_POSN 0x2 #define _RXFBCON4_F8BP_2_POSITION 0x2 #define _RXFBCON4_F8BP_2_SIZE 0x1 #define _RXFBCON4_F8BP_2_LENGTH 0x1 #define _RXFBCON4_F8BP_2_MASK 0x4 #define _RXFBCON4_F8BP_3_POSN 0x3 #define _RXFBCON4_F8BP_3_POSITION 0x3 #define _RXFBCON4_F8BP_3_SIZE 0x1 #define _RXFBCON4_F8BP_3_LENGTH 0x1 #define _RXFBCON4_F8BP_3_MASK 0x8 #define _RXFBCON4_F9BP_0_POSN 0x4 #define _RXFBCON4_F9BP_0_POSITION 0x4 #define _RXFBCON4_F9BP_0_SIZE 0x1 #define _RXFBCON4_F9BP_0_LENGTH 0x1 #define _RXFBCON4_F9BP_0_MASK 0x10 #define _RXFBCON4_F9BP_1_POSN 0x5 #define _RXFBCON4_F9BP_1_POSITION 0x5 #define _RXFBCON4_F9BP_1_SIZE 0x1 #define _RXFBCON4_F9BP_1_LENGTH 0x1 #define _RXFBCON4_F9BP_1_MASK 0x20 #define _RXFBCON4_F9BP_2_POSN 0x6 #define _RXFBCON4_F9BP_2_POSITION 0x6 #define _RXFBCON4_F9BP_2_SIZE 0x1 #define _RXFBCON4_F9BP_2_LENGTH 0x1 #define _RXFBCON4_F9BP_2_MASK 0x40 #define _RXFBCON4_F9BP_3_POSN 0x7 #define _RXFBCON4_F9BP_3_POSITION 0x7 #define _RXFBCON4_F9BP_3_SIZE 0x1 #define _RXFBCON4_F9BP_3_LENGTH 0x1 #define _RXFBCON4_F9BP_3_MASK 0x80 #define _RXFBCON4_F8BP_01_POSN 0x0 #define _RXFBCON4_F8BP_01_POSITION 0x0 #define _RXFBCON4_F8BP_01_SIZE 0x1 #define _RXFBCON4_F8BP_01_LENGTH 0x1 #define _RXFBCON4_F8BP_01_MASK 0x1 // Register: RXFBCON5 #define RXFBCON5 RXFBCON5 extern volatile unsigned char RXFBCON5 @ 0xE76; #ifndef _LIB_BUILD asm("RXFBCON5 equ 0E76h"); #endif // bitfield definitions typedef union { struct { unsigned F10BP :4; unsigned F11BP :4; }; struct { unsigned F10BP_0 :1; unsigned F10BP_1 :1; unsigned F10BP_2 :1; unsigned F10BP_3 :1; unsigned F11BP_0 :1; unsigned F11BP_1 :1; unsigned F11BP_2 :1; unsigned F11BP_3 :1; }; struct { unsigned F10BP_01 :1; }; } RXFBCON5bits_t; extern volatile RXFBCON5bits_t RXFBCON5bits @ 0xE76; // bitfield macros #define _RXFBCON5_F10BP_POSN 0x0 #define _RXFBCON5_F10BP_POSITION 0x0 #define _RXFBCON5_F10BP_SIZE 0x4 #define _RXFBCON5_F10BP_LENGTH 0x4 #define _RXFBCON5_F10BP_MASK 0xF #define _RXFBCON5_F11BP_POSN 0x4 #define _RXFBCON5_F11BP_POSITION 0x4 #define _RXFBCON5_F11BP_SIZE 0x4 #define _RXFBCON5_F11BP_LENGTH 0x4 #define _RXFBCON5_F11BP_MASK 0xF0 #define _RXFBCON5_F10BP_0_POSN 0x0 #define _RXFBCON5_F10BP_0_POSITION 0x0 #define _RXFBCON5_F10BP_0_SIZE 0x1 #define _RXFBCON5_F10BP_0_LENGTH 0x1 #define _RXFBCON5_F10BP_0_MASK 0x1 #define _RXFBCON5_F10BP_1_POSN 0x1 #define _RXFBCON5_F10BP_1_POSITION 0x1 #define _RXFBCON5_F10BP_1_SIZE 0x1 #define _RXFBCON5_F10BP_1_LENGTH 0x1 #define _RXFBCON5_F10BP_1_MASK 0x2 #define _RXFBCON5_F10BP_2_POSN 0x2 #define _RXFBCON5_F10BP_2_POSITION 0x2 #define _RXFBCON5_F10BP_2_SIZE 0x1 #define _RXFBCON5_F10BP_2_LENGTH 0x1 #define _RXFBCON5_F10BP_2_MASK 0x4 #define _RXFBCON5_F10BP_3_POSN 0x3 #define _RXFBCON5_F10BP_3_POSITION 0x3 #define _RXFBCON5_F10BP_3_SIZE 0x1 #define _RXFBCON5_F10BP_3_LENGTH 0x1 #define _RXFBCON5_F10BP_3_MASK 0x8 #define _RXFBCON5_F11BP_0_POSN 0x4 #define _RXFBCON5_F11BP_0_POSITION 0x4 #define _RXFBCON5_F11BP_0_SIZE 0x1 #define _RXFBCON5_F11BP_0_LENGTH 0x1 #define _RXFBCON5_F11BP_0_MASK 0x10 #define _RXFBCON5_F11BP_1_POSN 0x5 #define _RXFBCON5_F11BP_1_POSITION 0x5 #define _RXFBCON5_F11BP_1_SIZE 0x1 #define _RXFBCON5_F11BP_1_LENGTH 0x1 #define _RXFBCON5_F11BP_1_MASK 0x20 #define _RXFBCON5_F11BP_2_POSN 0x6 #define _RXFBCON5_F11BP_2_POSITION 0x6 #define _RXFBCON5_F11BP_2_SIZE 0x1 #define _RXFBCON5_F11BP_2_LENGTH 0x1 #define _RXFBCON5_F11BP_2_MASK 0x40 #define _RXFBCON5_F11BP_3_POSN 0x7 #define _RXFBCON5_F11BP_3_POSITION 0x7 #define _RXFBCON5_F11BP_3_SIZE 0x1 #define _RXFBCON5_F11BP_3_LENGTH 0x1 #define _RXFBCON5_F11BP_3_MASK 0x80 #define _RXFBCON5_F10BP_01_POSN 0x0 #define _RXFBCON5_F10BP_01_POSITION 0x0 #define _RXFBCON5_F10BP_01_SIZE 0x1 #define _RXFBCON5_F10BP_01_LENGTH 0x1 #define _RXFBCON5_F10BP_01_MASK 0x1 // Register: RXFBCON6 #define RXFBCON6 RXFBCON6 extern volatile unsigned char RXFBCON6 @ 0xE77; #ifndef _LIB_BUILD asm("RXFBCON6 equ 0E77h"); #endif // bitfield definitions typedef union { struct { unsigned F12BP :4; unsigned F13BP :4; }; struct { unsigned F12BP_0 :1; unsigned F12BP_1 :1; unsigned F12BP_2 :1; unsigned F12BP_3 :1; unsigned F13BP_0 :1; unsigned F13BP_1 :1; unsigned F13BP_2 :1; unsigned F13BP_3 :1; }; struct { unsigned F12BP_01 :1; }; } RXFBCON6bits_t; extern volatile RXFBCON6bits_t RXFBCON6bits @ 0xE77; // bitfield macros #define _RXFBCON6_F12BP_POSN 0x0 #define _RXFBCON6_F12BP_POSITION 0x0 #define _RXFBCON6_F12BP_SIZE 0x4 #define _RXFBCON6_F12BP_LENGTH 0x4 #define _RXFBCON6_F12BP_MASK 0xF #define _RXFBCON6_F13BP_POSN 0x4 #define _RXFBCON6_F13BP_POSITION 0x4 #define _RXFBCON6_F13BP_SIZE 0x4 #define _RXFBCON6_F13BP_LENGTH 0x4 #define _RXFBCON6_F13BP_MASK 0xF0 #define _RXFBCON6_F12BP_0_POSN 0x0 #define _RXFBCON6_F12BP_0_POSITION 0x0 #define _RXFBCON6_F12BP_0_SIZE 0x1 #define _RXFBCON6_F12BP_0_LENGTH 0x1 #define _RXFBCON6_F12BP_0_MASK 0x1 #define _RXFBCON6_F12BP_1_POSN 0x1 #define _RXFBCON6_F12BP_1_POSITION 0x1 #define _RXFBCON6_F12BP_1_SIZE 0x1 #define _RXFBCON6_F12BP_1_LENGTH 0x1 #define _RXFBCON6_F12BP_1_MASK 0x2 #define _RXFBCON6_F12BP_2_POSN 0x2 #define _RXFBCON6_F12BP_2_POSITION 0x2 #define _RXFBCON6_F12BP_2_SIZE 0x1 #define _RXFBCON6_F12BP_2_LENGTH 0x1 #define _RXFBCON6_F12BP_2_MASK 0x4 #define _RXFBCON6_F12BP_3_POSN 0x3 #define _RXFBCON6_F12BP_3_POSITION 0x3 #define _RXFBCON6_F12BP_3_SIZE 0x1 #define _RXFBCON6_F12BP_3_LENGTH 0x1 #define _RXFBCON6_F12BP_3_MASK 0x8 #define _RXFBCON6_F13BP_0_POSN 0x4 #define _RXFBCON6_F13BP_0_POSITION 0x4 #define _RXFBCON6_F13BP_0_SIZE 0x1 #define _RXFBCON6_F13BP_0_LENGTH 0x1 #define _RXFBCON6_F13BP_0_MASK 0x10 #define _RXFBCON6_F13BP_1_POSN 0x5 #define _RXFBCON6_F13BP_1_POSITION 0x5 #define _RXFBCON6_F13BP_1_SIZE 0x1 #define _RXFBCON6_F13BP_1_LENGTH 0x1 #define _RXFBCON6_F13BP_1_MASK 0x20 #define _RXFBCON6_F13BP_2_POSN 0x6 #define _RXFBCON6_F13BP_2_POSITION 0x6 #define _RXFBCON6_F13BP_2_SIZE 0x1 #define _RXFBCON6_F13BP_2_LENGTH 0x1 #define _RXFBCON6_F13BP_2_MASK 0x40 #define _RXFBCON6_F13BP_3_POSN 0x7 #define _RXFBCON6_F13BP_3_POSITION 0x7 #define _RXFBCON6_F13BP_3_SIZE 0x1 #define _RXFBCON6_F13BP_3_LENGTH 0x1 #define _RXFBCON6_F13BP_3_MASK 0x80 #define _RXFBCON6_F12BP_01_POSN 0x0 #define _RXFBCON6_F12BP_01_POSITION 0x0 #define _RXFBCON6_F12BP_01_SIZE 0x1 #define _RXFBCON6_F12BP_01_LENGTH 0x1 #define _RXFBCON6_F12BP_01_MASK 0x1 // Register: RXFBCON7 #define RXFBCON7 RXFBCON7 extern volatile unsigned char RXFBCON7 @ 0xE78; #ifndef _LIB_BUILD asm("RXFBCON7 equ 0E78h"); #endif // bitfield definitions typedef union { struct { unsigned F14BP :4; unsigned F15BP :4; }; struct { unsigned F14BP_0 :1; unsigned F14BP_1 :1; unsigned F14BP_2 :1; unsigned F14BP_3 :1; unsigned F15BP_0 :1; unsigned F15BP_1 :1; unsigned F15BP_2 :1; unsigned F15BP_3 :1; }; struct { unsigned F14BP_01 :1; }; } RXFBCON7bits_t; extern volatile RXFBCON7bits_t RXFBCON7bits @ 0xE78; // bitfield macros #define _RXFBCON7_F14BP_POSN 0x0 #define _RXFBCON7_F14BP_POSITION 0x0 #define _RXFBCON7_F14BP_SIZE 0x4 #define _RXFBCON7_F14BP_LENGTH 0x4 #define _RXFBCON7_F14BP_MASK 0xF #define _RXFBCON7_F15BP_POSN 0x4 #define _RXFBCON7_F15BP_POSITION 0x4 #define _RXFBCON7_F15BP_SIZE 0x4 #define _RXFBCON7_F15BP_LENGTH 0x4 #define _RXFBCON7_F15BP_MASK 0xF0 #define _RXFBCON7_F14BP_0_POSN 0x0 #define _RXFBCON7_F14BP_0_POSITION 0x0 #define _RXFBCON7_F14BP_0_SIZE 0x1 #define _RXFBCON7_F14BP_0_LENGTH 0x1 #define _RXFBCON7_F14BP_0_MASK 0x1 #define _RXFBCON7_F14BP_1_POSN 0x1 #define _RXFBCON7_F14BP_1_POSITION 0x1 #define _RXFBCON7_F14BP_1_SIZE 0x1 #define _RXFBCON7_F14BP_1_LENGTH 0x1 #define _RXFBCON7_F14BP_1_MASK 0x2 #define _RXFBCON7_F14BP_2_POSN 0x2 #define _RXFBCON7_F14BP_2_POSITION 0x2 #define _RXFBCON7_F14BP_2_SIZE 0x1 #define _RXFBCON7_F14BP_2_LENGTH 0x1 #define _RXFBCON7_F14BP_2_MASK 0x4 #define _RXFBCON7_F14BP_3_POSN 0x3 #define _RXFBCON7_F14BP_3_POSITION 0x3 #define _RXFBCON7_F14BP_3_SIZE 0x1 #define _RXFBCON7_F14BP_3_LENGTH 0x1 #define _RXFBCON7_F14BP_3_MASK 0x8 #define _RXFBCON7_F15BP_0_POSN 0x4 #define _RXFBCON7_F15BP_0_POSITION 0x4 #define _RXFBCON7_F15BP_0_SIZE 0x1 #define _RXFBCON7_F15BP_0_LENGTH 0x1 #define _RXFBCON7_F15BP_0_MASK 0x10 #define _RXFBCON7_F15BP_1_POSN 0x5 #define _RXFBCON7_F15BP_1_POSITION 0x5 #define _RXFBCON7_F15BP_1_SIZE 0x1 #define _RXFBCON7_F15BP_1_LENGTH 0x1 #define _RXFBCON7_F15BP_1_MASK 0x20 #define _RXFBCON7_F15BP_2_POSN 0x6 #define _RXFBCON7_F15BP_2_POSITION 0x6 #define _RXFBCON7_F15BP_2_SIZE 0x1 #define _RXFBCON7_F15BP_2_LENGTH 0x1 #define _RXFBCON7_F15BP_2_MASK 0x40 #define _RXFBCON7_F15BP_3_POSN 0x7 #define _RXFBCON7_F15BP_3_POSITION 0x7 #define _RXFBCON7_F15BP_3_SIZE 0x1 #define _RXFBCON7_F15BP_3_LENGTH 0x1 #define _RXFBCON7_F15BP_3_MASK 0x80 #define _RXFBCON7_F14BP_01_POSN 0x0 #define _RXFBCON7_F14BP_01_POSITION 0x0 #define _RXFBCON7_F14BP_01_SIZE 0x1 #define _RXFBCON7_F14BP_01_LENGTH 0x1 #define _RXFBCON7_F14BP_01_MASK 0x1 // Register: MSEL0 #define MSEL0 MSEL0 extern volatile unsigned char MSEL0 @ 0xE79; #ifndef _LIB_BUILD asm("MSEL0 equ 0E79h"); #endif // bitfield definitions typedef union { struct { unsigned FIL0 :2; unsigned FIL1 :2; unsigned FIL2 :2; unsigned FIL3 :2; }; struct { unsigned FIL0_0 :1; unsigned FIL0_1 :1; unsigned FIL1_0 :1; unsigned FIL1_1 :1; unsigned FIL2_0 :1; unsigned FIL2_1 :1; unsigned FIL3_0 :1; unsigned FIL3_1 :1; }; } MSEL0bits_t; extern volatile MSEL0bits_t MSEL0bits @ 0xE79; // bitfield macros #define _MSEL0_FIL0_POSN 0x0 #define _MSEL0_FIL0_POSITION 0x0 #define _MSEL0_FIL0_SIZE 0x2 #define _MSEL0_FIL0_LENGTH 0x2 #define _MSEL0_FIL0_MASK 0x3 #define _MSEL0_FIL1_POSN 0x2 #define _MSEL0_FIL1_POSITION 0x2 #define _MSEL0_FIL1_SIZE 0x2 #define _MSEL0_FIL1_LENGTH 0x2 #define _MSEL0_FIL1_MASK 0xC #define _MSEL0_FIL2_POSN 0x4 #define _MSEL0_FIL2_POSITION 0x4 #define _MSEL0_FIL2_SIZE 0x2 #define _MSEL0_FIL2_LENGTH 0x2 #define _MSEL0_FIL2_MASK 0x30 #define _MSEL0_FIL3_POSN 0x6 #define _MSEL0_FIL3_POSITION 0x6 #define _MSEL0_FIL3_SIZE 0x2 #define _MSEL0_FIL3_LENGTH 0x2 #define _MSEL0_FIL3_MASK 0xC0 #define _MSEL0_FIL0_0_POSN 0x0 #define _MSEL0_FIL0_0_POSITION 0x0 #define _MSEL0_FIL0_0_SIZE 0x1 #define _MSEL0_FIL0_0_LENGTH 0x1 #define _MSEL0_FIL0_0_MASK 0x1 #define _MSEL0_FIL0_1_POSN 0x1 #define _MSEL0_FIL0_1_POSITION 0x1 #define _MSEL0_FIL0_1_SIZE 0x1 #define _MSEL0_FIL0_1_LENGTH 0x1 #define _MSEL0_FIL0_1_MASK 0x2 #define _MSEL0_FIL1_0_POSN 0x2 #define _MSEL0_FIL1_0_POSITION 0x2 #define _MSEL0_FIL1_0_SIZE 0x1 #define _MSEL0_FIL1_0_LENGTH 0x1 #define _MSEL0_FIL1_0_MASK 0x4 #define _MSEL0_FIL1_1_POSN 0x3 #define _MSEL0_FIL1_1_POSITION 0x3 #define _MSEL0_FIL1_1_SIZE 0x1 #define _MSEL0_FIL1_1_LENGTH 0x1 #define _MSEL0_FIL1_1_MASK 0x8 #define _MSEL0_FIL2_0_POSN 0x4 #define _MSEL0_FIL2_0_POSITION 0x4 #define _MSEL0_FIL2_0_SIZE 0x1 #define _MSEL0_FIL2_0_LENGTH 0x1 #define _MSEL0_FIL2_0_MASK 0x10 #define _MSEL0_FIL2_1_POSN 0x5 #define _MSEL0_FIL2_1_POSITION 0x5 #define _MSEL0_FIL2_1_SIZE 0x1 #define _MSEL0_FIL2_1_LENGTH 0x1 #define _MSEL0_FIL2_1_MASK 0x20 #define _MSEL0_FIL3_0_POSN 0x6 #define _MSEL0_FIL3_0_POSITION 0x6 #define _MSEL0_FIL3_0_SIZE 0x1 #define _MSEL0_FIL3_0_LENGTH 0x1 #define _MSEL0_FIL3_0_MASK 0x40 #define _MSEL0_FIL3_1_POSN 0x7 #define _MSEL0_FIL3_1_POSITION 0x7 #define _MSEL0_FIL3_1_SIZE 0x1 #define _MSEL0_FIL3_1_LENGTH 0x1 #define _MSEL0_FIL3_1_MASK 0x80 // Register: MSEL1 #define MSEL1 MSEL1 extern volatile unsigned char MSEL1 @ 0xE7A; #ifndef _LIB_BUILD asm("MSEL1 equ 0E7Ah"); #endif // bitfield definitions typedef union { struct { unsigned FIL4 :2; unsigned FIL5 :2; unsigned FIL6 :2; unsigned FIL7 :2; }; struct { unsigned FIL4_0 :1; unsigned FIL4_1 :1; unsigned FIL5_0 :1; unsigned FIL5_1 :1; unsigned FIL6_0 :1; unsigned FIL6_1 :1; unsigned FIL7_0 :1; unsigned FIL7_1 :1; }; } MSEL1bits_t; extern volatile MSEL1bits_t MSEL1bits @ 0xE7A; // bitfield macros #define _MSEL1_FIL4_POSN 0x0 #define _MSEL1_FIL4_POSITION 0x0 #define _MSEL1_FIL4_SIZE 0x2 #define _MSEL1_FIL4_LENGTH 0x2 #define _MSEL1_FIL4_MASK 0x3 #define _MSEL1_FIL5_POSN 0x2 #define _MSEL1_FIL5_POSITION 0x2 #define _MSEL1_FIL5_SIZE 0x2 #define _MSEL1_FIL5_LENGTH 0x2 #define _MSEL1_FIL5_MASK 0xC #define _MSEL1_FIL6_POSN 0x4 #define _MSEL1_FIL6_POSITION 0x4 #define _MSEL1_FIL6_SIZE 0x2 #define _MSEL1_FIL6_LENGTH 0x2 #define _MSEL1_FIL6_MASK 0x30 #define _MSEL1_FIL7_POSN 0x6 #define _MSEL1_FIL7_POSITION 0x6 #define _MSEL1_FIL7_SIZE 0x2 #define _MSEL1_FIL7_LENGTH 0x2 #define _MSEL1_FIL7_MASK 0xC0 #define _MSEL1_FIL4_0_POSN 0x0 #define _MSEL1_FIL4_0_POSITION 0x0 #define _MSEL1_FIL4_0_SIZE 0x1 #define _MSEL1_FIL4_0_LENGTH 0x1 #define _MSEL1_FIL4_0_MASK 0x1 #define _MSEL1_FIL4_1_POSN 0x1 #define _MSEL1_FIL4_1_POSITION 0x1 #define _MSEL1_FIL4_1_SIZE 0x1 #define _MSEL1_FIL4_1_LENGTH 0x1 #define _MSEL1_FIL4_1_MASK 0x2 #define _MSEL1_FIL5_0_POSN 0x2 #define _MSEL1_FIL5_0_POSITION 0x2 #define _MSEL1_FIL5_0_SIZE 0x1 #define _MSEL1_FIL5_0_LENGTH 0x1 #define _MSEL1_FIL5_0_MASK 0x4 #define _MSEL1_FIL5_1_POSN 0x3 #define _MSEL1_FIL5_1_POSITION 0x3 #define _MSEL1_FIL5_1_SIZE 0x1 #define _MSEL1_FIL5_1_LENGTH 0x1 #define _MSEL1_FIL5_1_MASK 0x8 #define _MSEL1_FIL6_0_POSN 0x4 #define _MSEL1_FIL6_0_POSITION 0x4 #define _MSEL1_FIL6_0_SIZE 0x1 #define _MSEL1_FIL6_0_LENGTH 0x1 #define _MSEL1_FIL6_0_MASK 0x10 #define _MSEL1_FIL6_1_POSN 0x5 #define _MSEL1_FIL6_1_POSITION 0x5 #define _MSEL1_FIL6_1_SIZE 0x1 #define _MSEL1_FIL6_1_LENGTH 0x1 #define _MSEL1_FIL6_1_MASK 0x20 #define _MSEL1_FIL7_0_POSN 0x6 #define _MSEL1_FIL7_0_POSITION 0x6 #define _MSEL1_FIL7_0_SIZE 0x1 #define _MSEL1_FIL7_0_LENGTH 0x1 #define _MSEL1_FIL7_0_MASK 0x40 #define _MSEL1_FIL7_1_POSN 0x7 #define _MSEL1_FIL7_1_POSITION 0x7 #define _MSEL1_FIL7_1_SIZE 0x1 #define _MSEL1_FIL7_1_LENGTH 0x1 #define _MSEL1_FIL7_1_MASK 0x80 // Register: MSEL2 #define MSEL2 MSEL2 extern volatile unsigned char MSEL2 @ 0xE7B; #ifndef _LIB_BUILD asm("MSEL2 equ 0E7Bh"); #endif // bitfield definitions typedef union { struct { unsigned FIL8 :2; unsigned FIL9 :2; unsigned FIL10 :2; unsigned FIL11 :2; }; struct { unsigned FIL8_0 :1; unsigned FIL8_1 :1; unsigned FIL9_0 :1; unsigned FIL9_1 :1; unsigned FIL10_0 :1; unsigned FIL10_1 :1; unsigned FIL11_0 :1; unsigned FIL11_1 :1; }; } MSEL2bits_t; extern volatile MSEL2bits_t MSEL2bits @ 0xE7B; // bitfield macros #define _MSEL2_FIL8_POSN 0x0 #define _MSEL2_FIL8_POSITION 0x0 #define _MSEL2_FIL8_SIZE 0x2 #define _MSEL2_FIL8_LENGTH 0x2 #define _MSEL2_FIL8_MASK 0x3 #define _MSEL2_FIL9_POSN 0x2 #define _MSEL2_FIL9_POSITION 0x2 #define _MSEL2_FIL9_SIZE 0x2 #define _MSEL2_FIL9_LENGTH 0x2 #define _MSEL2_FIL9_MASK 0xC #define _MSEL2_FIL10_POSN 0x4 #define _MSEL2_FIL10_POSITION 0x4 #define _MSEL2_FIL10_SIZE 0x2 #define _MSEL2_FIL10_LENGTH 0x2 #define _MSEL2_FIL10_MASK 0x30 #define _MSEL2_FIL11_POSN 0x6 #define _MSEL2_FIL11_POSITION 0x6 #define _MSEL2_FIL11_SIZE 0x2 #define _MSEL2_FIL11_LENGTH 0x2 #define _MSEL2_FIL11_MASK 0xC0 #define _MSEL2_FIL8_0_POSN 0x0 #define _MSEL2_FIL8_0_POSITION 0x0 #define _MSEL2_FIL8_0_SIZE 0x1 #define _MSEL2_FIL8_0_LENGTH 0x1 #define _MSEL2_FIL8_0_MASK 0x1 #define _MSEL2_FIL8_1_POSN 0x1 #define _MSEL2_FIL8_1_POSITION 0x1 #define _MSEL2_FIL8_1_SIZE 0x1 #define _MSEL2_FIL8_1_LENGTH 0x1 #define _MSEL2_FIL8_1_MASK 0x2 #define _MSEL2_FIL9_0_POSN 0x2 #define _MSEL2_FIL9_0_POSITION 0x2 #define _MSEL2_FIL9_0_SIZE 0x1 #define _MSEL2_FIL9_0_LENGTH 0x1 #define _MSEL2_FIL9_0_MASK 0x4 #define _MSEL2_FIL9_1_POSN 0x3 #define _MSEL2_FIL9_1_POSITION 0x3 #define _MSEL2_FIL9_1_SIZE 0x1 #define _MSEL2_FIL9_1_LENGTH 0x1 #define _MSEL2_FIL9_1_MASK 0x8 #define _MSEL2_FIL10_0_POSN 0x4 #define _MSEL2_FIL10_0_POSITION 0x4 #define _MSEL2_FIL10_0_SIZE 0x1 #define _MSEL2_FIL10_0_LENGTH 0x1 #define _MSEL2_FIL10_0_MASK 0x10 #define _MSEL2_FIL10_1_POSN 0x5 #define _MSEL2_FIL10_1_POSITION 0x5 #define _MSEL2_FIL10_1_SIZE 0x1 #define _MSEL2_FIL10_1_LENGTH 0x1 #define _MSEL2_FIL10_1_MASK 0x20 #define _MSEL2_FIL11_0_POSN 0x6 #define _MSEL2_FIL11_0_POSITION 0x6 #define _MSEL2_FIL11_0_SIZE 0x1 #define _MSEL2_FIL11_0_LENGTH 0x1 #define _MSEL2_FIL11_0_MASK 0x40 #define _MSEL2_FIL11_1_POSN 0x7 #define _MSEL2_FIL11_1_POSITION 0x7 #define _MSEL2_FIL11_1_SIZE 0x1 #define _MSEL2_FIL11_1_LENGTH 0x1 #define _MSEL2_FIL11_1_MASK 0x80 // Register: MSEL3 #define MSEL3 MSEL3 extern volatile unsigned char MSEL3 @ 0xE7C; #ifndef _LIB_BUILD asm("MSEL3 equ 0E7Ch"); #endif // bitfield definitions typedef union { struct { unsigned FIL12 :2; unsigned FIL13 :2; unsigned FIL14 :2; unsigned FIL15 :2; }; struct { unsigned FIL12_0 :1; unsigned FIL12_1 :1; unsigned FIL13_0 :1; unsigned FIL13_1 :1; unsigned FIL14_0 :1; unsigned FIL14_1 :1; unsigned FIL15_0 :1; unsigned FIL15_1 :1; }; } MSEL3bits_t; extern volatile MSEL3bits_t MSEL3bits @ 0xE7C; // bitfield macros #define _MSEL3_FIL12_POSN 0x0 #define _MSEL3_FIL12_POSITION 0x0 #define _MSEL3_FIL12_SIZE 0x2 #define _MSEL3_FIL12_LENGTH 0x2 #define _MSEL3_FIL12_MASK 0x3 #define _MSEL3_FIL13_POSN 0x2 #define _MSEL3_FIL13_POSITION 0x2 #define _MSEL3_FIL13_SIZE 0x2 #define _MSEL3_FIL13_LENGTH 0x2 #define _MSEL3_FIL13_MASK 0xC #define _MSEL3_FIL14_POSN 0x4 #define _MSEL3_FIL14_POSITION 0x4 #define _MSEL3_FIL14_SIZE 0x2 #define _MSEL3_FIL14_LENGTH 0x2 #define _MSEL3_FIL14_MASK 0x30 #define _MSEL3_FIL15_POSN 0x6 #define _MSEL3_FIL15_POSITION 0x6 #define _MSEL3_FIL15_SIZE 0x2 #define _MSEL3_FIL15_LENGTH 0x2 #define _MSEL3_FIL15_MASK 0xC0 #define _MSEL3_FIL12_0_POSN 0x0 #define _MSEL3_FIL12_0_POSITION 0x0 #define _MSEL3_FIL12_0_SIZE 0x1 #define _MSEL3_FIL12_0_LENGTH 0x1 #define _MSEL3_FIL12_0_MASK 0x1 #define _MSEL3_FIL12_1_POSN 0x1 #define _MSEL3_FIL12_1_POSITION 0x1 #define _MSEL3_FIL12_1_SIZE 0x1 #define _MSEL3_FIL12_1_LENGTH 0x1 #define _MSEL3_FIL12_1_MASK 0x2 #define _MSEL3_FIL13_0_POSN 0x2 #define _MSEL3_FIL13_0_POSITION 0x2 #define _MSEL3_FIL13_0_SIZE 0x1 #define _MSEL3_FIL13_0_LENGTH 0x1 #define _MSEL3_FIL13_0_MASK 0x4 #define _MSEL3_FIL13_1_POSN 0x3 #define _MSEL3_FIL13_1_POSITION 0x3 #define _MSEL3_FIL13_1_SIZE 0x1 #define _MSEL3_FIL13_1_LENGTH 0x1 #define _MSEL3_FIL13_1_MASK 0x8 #define _MSEL3_FIL14_0_POSN 0x4 #define _MSEL3_FIL14_0_POSITION 0x4 #define _MSEL3_FIL14_0_SIZE 0x1 #define _MSEL3_FIL14_0_LENGTH 0x1 #define _MSEL3_FIL14_0_MASK 0x10 #define _MSEL3_FIL14_1_POSN 0x5 #define _MSEL3_FIL14_1_POSITION 0x5 #define _MSEL3_FIL14_1_SIZE 0x1 #define _MSEL3_FIL14_1_LENGTH 0x1 #define _MSEL3_FIL14_1_MASK 0x20 #define _MSEL3_FIL15_0_POSN 0x6 #define _MSEL3_FIL15_0_POSITION 0x6 #define _MSEL3_FIL15_0_SIZE 0x1 #define _MSEL3_FIL15_0_LENGTH 0x1 #define _MSEL3_FIL15_0_MASK 0x40 #define _MSEL3_FIL15_1_POSN 0x7 #define _MSEL3_FIL15_1_POSITION 0x7 #define _MSEL3_FIL15_1_SIZE 0x1 #define _MSEL3_FIL15_1_LENGTH 0x1 #define _MSEL3_FIL15_1_MASK 0x80 // Register: BSEL0 #define BSEL0 BSEL0 extern volatile unsigned char BSEL0 @ 0xE7D; #ifndef _LIB_BUILD asm("BSEL0 equ 0E7Dh"); #endif // bitfield definitions typedef union { struct { unsigned :2; unsigned B0TXEN :1; unsigned B1TXEN :1; unsigned B2TXEN :1; unsigned B3TXEN :1; unsigned B4TXEN :1; unsigned B5TXEN :1; }; } BSEL0bits_t; extern volatile BSEL0bits_t BSEL0bits @ 0xE7D; // bitfield macros #define _BSEL0_B0TXEN_POSN 0x2 #define _BSEL0_B0TXEN_POSITION 0x2 #define _BSEL0_B0TXEN_SIZE 0x1 #define _BSEL0_B0TXEN_LENGTH 0x1 #define _BSEL0_B0TXEN_MASK 0x4 #define _BSEL0_B1TXEN_POSN 0x3 #define _BSEL0_B1TXEN_POSITION 0x3 #define _BSEL0_B1TXEN_SIZE 0x1 #define _BSEL0_B1TXEN_LENGTH 0x1 #define _BSEL0_B1TXEN_MASK 0x8 #define _BSEL0_B2TXEN_POSN 0x4 #define _BSEL0_B2TXEN_POSITION 0x4 #define _BSEL0_B2TXEN_SIZE 0x1 #define _BSEL0_B2TXEN_LENGTH 0x1 #define _BSEL0_B2TXEN_MASK 0x10 #define _BSEL0_B3TXEN_POSN 0x5 #define _BSEL0_B3TXEN_POSITION 0x5 #define _BSEL0_B3TXEN_SIZE 0x1 #define _BSEL0_B3TXEN_LENGTH 0x1 #define _BSEL0_B3TXEN_MASK 0x20 #define _BSEL0_B4TXEN_POSN 0x6 #define _BSEL0_B4TXEN_POSITION 0x6 #define _BSEL0_B4TXEN_SIZE 0x1 #define _BSEL0_B4TXEN_LENGTH 0x1 #define _BSEL0_B4TXEN_MASK 0x40 #define _BSEL0_B5TXEN_POSN 0x7 #define _BSEL0_B5TXEN_POSITION 0x7 #define _BSEL0_B5TXEN_SIZE 0x1 #define _BSEL0_B5TXEN_LENGTH 0x1 #define _BSEL0_B5TXEN_MASK 0x80 // Register: BIE0 #define BIE0 BIE0 extern volatile unsigned char BIE0 @ 0xE7E; #ifndef _LIB_BUILD asm("BIE0 equ 0E7Eh"); #endif // bitfield definitions typedef union { struct { unsigned RXB0IE :1; unsigned RXB1IE :1; unsigned B0IE :1; unsigned B1IE :1; unsigned B2IE :1; unsigned B3IE :1; unsigned B4IE :1; unsigned B5IE :1; }; struct { unsigned DRXB0IE :1; unsigned DRXB1IE :1; }; } BIE0bits_t; extern volatile BIE0bits_t BIE0bits @ 0xE7E; // bitfield macros #define _BIE0_RXB0IE_POSN 0x0 #define _BIE0_RXB0IE_POSITION 0x0 #define _BIE0_RXB0IE_SIZE 0x1 #define _BIE0_RXB0IE_LENGTH 0x1 #define _BIE0_RXB0IE_MASK 0x1 #define _BIE0_RXB1IE_POSN 0x1 #define _BIE0_RXB1IE_POSITION 0x1 #define _BIE0_RXB1IE_SIZE 0x1 #define _BIE0_RXB1IE_LENGTH 0x1 #define _BIE0_RXB1IE_MASK 0x2 #define _BIE0_B0IE_POSN 0x2 #define _BIE0_B0IE_POSITION 0x2 #define _BIE0_B0IE_SIZE 0x1 #define _BIE0_B0IE_LENGTH 0x1 #define _BIE0_B0IE_MASK 0x4 #define _BIE0_B1IE_POSN 0x3 #define _BIE0_B1IE_POSITION 0x3 #define _BIE0_B1IE_SIZE 0x1 #define _BIE0_B1IE_LENGTH 0x1 #define _BIE0_B1IE_MASK 0x8 #define _BIE0_B2IE_POSN 0x4 #define _BIE0_B2IE_POSITION 0x4 #define _BIE0_B2IE_SIZE 0x1 #define _BIE0_B2IE_LENGTH 0x1 #define _BIE0_B2IE_MASK 0x10 #define _BIE0_B3IE_POSN 0x5 #define _BIE0_B3IE_POSITION 0x5 #define _BIE0_B3IE_SIZE 0x1 #define _BIE0_B3IE_LENGTH 0x1 #define _BIE0_B3IE_MASK 0x20 #define _BIE0_B4IE_POSN 0x6 #define _BIE0_B4IE_POSITION 0x6 #define _BIE0_B4IE_SIZE 0x1 #define _BIE0_B4IE_LENGTH 0x1 #define _BIE0_B4IE_MASK 0x40 #define _BIE0_B5IE_POSN 0x7 #define _BIE0_B5IE_POSITION 0x7 #define _BIE0_B5IE_SIZE 0x1 #define _BIE0_B5IE_LENGTH 0x1 #define _BIE0_B5IE_MASK 0x80 #define _BIE0_DRXB0IE_POSN 0x0 #define _BIE0_DRXB0IE_POSITION 0x0 #define _BIE0_DRXB0IE_SIZE 0x1 #define _BIE0_DRXB0IE_LENGTH 0x1 #define _BIE0_DRXB0IE_MASK 0x1 #define _BIE0_DRXB1IE_POSN 0x1 #define _BIE0_DRXB1IE_POSITION 0x1 #define _BIE0_DRXB1IE_SIZE 0x1 #define _BIE0_DRXB1IE_LENGTH 0x1 #define _BIE0_DRXB1IE_MASK 0x2 // Register: TXBIE #define TXBIE TXBIE extern volatile unsigned char TXBIE @ 0xE7F; #ifndef _LIB_BUILD asm("TXBIE equ 0E7Fh"); #endif // bitfield definitions typedef union { struct { unsigned :2; unsigned TXB0IE :1; unsigned TXB1IE :1; unsigned TXB2IE :1; }; struct { unsigned :2; unsigned TX0IE :1; unsigned TX1IE :1; unsigned TX2IE :1; }; } TXBIEbits_t; extern volatile TXBIEbits_t TXBIEbits @ 0xE7F; // bitfield macros #define _TXBIE_TXB0IE_POSN 0x2 #define _TXBIE_TXB0IE_POSITION 0x2 #define _TXBIE_TXB0IE_SIZE 0x1 #define _TXBIE_TXB0IE_LENGTH 0x1 #define _TXBIE_TXB0IE_MASK 0x4 #define _TXBIE_TXB1IE_POSN 0x3 #define _TXBIE_TXB1IE_POSITION 0x3 #define _TXBIE_TXB1IE_SIZE 0x1 #define _TXBIE_TXB1IE_LENGTH 0x1 #define _TXBIE_TXB1IE_MASK 0x8 #define _TXBIE_TXB2IE_POSN 0x4 #define _TXBIE_TXB2IE_POSITION 0x4 #define _TXBIE_TXB2IE_SIZE 0x1 #define _TXBIE_TXB2IE_LENGTH 0x1 #define _TXBIE_TXB2IE_MASK 0x10 #define _TXBIE_TX0IE_POSN 0x2 #define _TXBIE_TX0IE_POSITION 0x2 #define _TXBIE_TX0IE_SIZE 0x1 #define _TXBIE_TX0IE_LENGTH 0x1 #define _TXBIE_TX0IE_MASK 0x4 #define _TXBIE_TX1IE_POSN 0x3 #define _TXBIE_TX1IE_POSITION 0x3 #define _TXBIE_TX1IE_SIZE 0x1 #define _TXBIE_TX1IE_LENGTH 0x1 #define _TXBIE_TX1IE_MASK 0x8 #define _TXBIE_TX2IE_POSN 0x4 #define _TXBIE_TX2IE_POSITION 0x4 #define _TXBIE_TX2IE_SIZE 0x1 #define _TXBIE_TX2IE_LENGTH 0x1 #define _TXBIE_TX2IE_MASK 0x10 // Register: B0CON #define B0CON B0CON extern volatile unsigned char B0CON @ 0xE80; #ifndef _LIB_BUILD asm("B0CON equ 0E80h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B0FILHIT0 :1; unsigned B0FILHIT1 :1; unsigned B0FILHIT2 :1; unsigned B0FILHIT3 :1; unsigned B0FILHIT4 :1; unsigned B0RTRRO :1; unsigned B0RXM1 :1; unsigned B0RXFUL :1; }; struct { unsigned B0TXPRI0 :1; unsigned B0TXPRI1 :1; unsigned B0RTREN :1; unsigned B0TXREQ :1; unsigned B0TXERR :1; unsigned B0TXLARB :1; unsigned B0TXABT :1; unsigned B0TXB3IF :1; }; } B0CONbits_t; extern volatile B0CONbits_t B0CONbits @ 0xE80; // bitfield macros #define _B0CON_FILHIT0_TXPRI0_POSN 0x0 #define _B0CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B0CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B0CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B0CON_FILHIT0_TXPRI0_MASK 0x1 #define _B0CON_FILHIT1_TXPRI1_POSN 0x1 #define _B0CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B0CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B0CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B0CON_FILHIT1_TXPRI1_MASK 0x2 #define _B0CON_FILHIT2_RTREN_POSN 0x2 #define _B0CON_FILHIT2_RTREN_POSITION 0x2 #define _B0CON_FILHIT2_RTREN_SIZE 0x1 #define _B0CON_FILHIT2_RTREN_LENGTH 0x1 #define _B0CON_FILHIT2_RTREN_MASK 0x4 #define _B0CON_FILHIT3_TXREQ_POSN 0x3 #define _B0CON_FILHIT3_TXREQ_POSITION 0x3 #define _B0CON_FILHIT3_TXREQ_SIZE 0x1 #define _B0CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B0CON_FILHIT3_TXREQ_MASK 0x8 #define _B0CON_FILHIT4_TXERR_POSN 0x4 #define _B0CON_FILHIT4_TXERR_POSITION 0x4 #define _B0CON_FILHIT4_TXERR_SIZE 0x1 #define _B0CON_FILHIT4_TXERR_LENGTH 0x1 #define _B0CON_FILHIT4_TXERR_MASK 0x10 #define _B0CON_RXRTRRO_TXLARB_POSN 0x5 #define _B0CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B0CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B0CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B0CON_RXRTRRO_TXLARB_MASK 0x20 #define _B0CON_RXM1_TXABT_POSN 0x6 #define _B0CON_RXM1_TXABT_POSITION 0x6 #define _B0CON_RXM1_TXABT_SIZE 0x1 #define _B0CON_RXM1_TXABT_LENGTH 0x1 #define _B0CON_RXM1_TXABT_MASK 0x40 #define _B0CON_RXFUL_TXBIF_POSN 0x7 #define _B0CON_RXFUL_TXBIF_POSITION 0x7 #define _B0CON_RXFUL_TXBIF_SIZE 0x1 #define _B0CON_RXFUL_TXBIF_LENGTH 0x1 #define _B0CON_RXFUL_TXBIF_MASK 0x80 #define _B0CON_FILHIT0_POSN 0x0 #define _B0CON_FILHIT0_POSITION 0x0 #define _B0CON_FILHIT0_SIZE 0x1 #define _B0CON_FILHIT0_LENGTH 0x1 #define _B0CON_FILHIT0_MASK 0x1 #define _B0CON_FILHIT1_POSN 0x1 #define _B0CON_FILHIT1_POSITION 0x1 #define _B0CON_FILHIT1_SIZE 0x1 #define _B0CON_FILHIT1_LENGTH 0x1 #define _B0CON_FILHIT1_MASK 0x2 #define _B0CON_FILHIT2_POSN 0x2 #define _B0CON_FILHIT2_POSITION 0x2 #define _B0CON_FILHIT2_SIZE 0x1 #define _B0CON_FILHIT2_LENGTH 0x1 #define _B0CON_FILHIT2_MASK 0x4 #define _B0CON_FILHIT3_POSN 0x3 #define _B0CON_FILHIT3_POSITION 0x3 #define _B0CON_FILHIT3_SIZE 0x1 #define _B0CON_FILHIT3_LENGTH 0x1 #define _B0CON_FILHIT3_MASK 0x8 #define _B0CON_FILHIT4_POSN 0x4 #define _B0CON_FILHIT4_POSITION 0x4 #define _B0CON_FILHIT4_SIZE 0x1 #define _B0CON_FILHIT4_LENGTH 0x1 #define _B0CON_FILHIT4_MASK 0x10 #define _B0CON_RXRTRRO_POSN 0x5 #define _B0CON_RXRTRRO_POSITION 0x5 #define _B0CON_RXRTRRO_SIZE 0x1 #define _B0CON_RXRTRRO_LENGTH 0x1 #define _B0CON_RXRTRRO_MASK 0x20 #define _B0CON_RXM1_POSN 0x6 #define _B0CON_RXM1_POSITION 0x6 #define _B0CON_RXM1_SIZE 0x1 #define _B0CON_RXM1_LENGTH 0x1 #define _B0CON_RXM1_MASK 0x40 #define _B0CON_RXFUL_POSN 0x7 #define _B0CON_RXFUL_POSITION 0x7 #define _B0CON_RXFUL_SIZE 0x1 #define _B0CON_RXFUL_LENGTH 0x1 #define _B0CON_RXFUL_MASK 0x80 #define _B0CON_TXPRI0_POSN 0x0 #define _B0CON_TXPRI0_POSITION 0x0 #define _B0CON_TXPRI0_SIZE 0x1 #define _B0CON_TXPRI0_LENGTH 0x1 #define _B0CON_TXPRI0_MASK 0x1 #define _B0CON_TXPRI1_POSN 0x1 #define _B0CON_TXPRI1_POSITION 0x1 #define _B0CON_TXPRI1_SIZE 0x1 #define _B0CON_TXPRI1_LENGTH 0x1 #define _B0CON_TXPRI1_MASK 0x2 #define _B0CON_RTREN_POSN 0x2 #define _B0CON_RTREN_POSITION 0x2 #define _B0CON_RTREN_SIZE 0x1 #define _B0CON_RTREN_LENGTH 0x1 #define _B0CON_RTREN_MASK 0x4 #define _B0CON_TXREQ_POSN 0x3 #define _B0CON_TXREQ_POSITION 0x3 #define _B0CON_TXREQ_SIZE 0x1 #define _B0CON_TXREQ_LENGTH 0x1 #define _B0CON_TXREQ_MASK 0x8 #define _B0CON_TXERR_POSN 0x4 #define _B0CON_TXERR_POSITION 0x4 #define _B0CON_TXERR_SIZE 0x1 #define _B0CON_TXERR_LENGTH 0x1 #define _B0CON_TXERR_MASK 0x10 #define _B0CON_TXLARB_POSN 0x5 #define _B0CON_TXLARB_POSITION 0x5 #define _B0CON_TXLARB_SIZE 0x1 #define _B0CON_TXLARB_LENGTH 0x1 #define _B0CON_TXLARB_MASK 0x20 #define _B0CON_TXABT_POSN 0x6 #define _B0CON_TXABT_POSITION 0x6 #define _B0CON_TXABT_SIZE 0x1 #define _B0CON_TXABT_LENGTH 0x1 #define _B0CON_TXABT_MASK 0x40 #define _B0CON_TXBIF_POSN 0x7 #define _B0CON_TXBIF_POSITION 0x7 #define _B0CON_TXBIF_SIZE 0x1 #define _B0CON_TXBIF_LENGTH 0x1 #define _B0CON_TXBIF_MASK 0x80 #define _B0CON_B0FILHIT0_POSN 0x0 #define _B0CON_B0FILHIT0_POSITION 0x0 #define _B0CON_B0FILHIT0_SIZE 0x1 #define _B0CON_B0FILHIT0_LENGTH 0x1 #define _B0CON_B0FILHIT0_MASK 0x1 #define _B0CON_B0FILHIT1_POSN 0x1 #define _B0CON_B0FILHIT1_POSITION 0x1 #define _B0CON_B0FILHIT1_SIZE 0x1 #define _B0CON_B0FILHIT1_LENGTH 0x1 #define _B0CON_B0FILHIT1_MASK 0x2 #define _B0CON_B0FILHIT2_POSN 0x2 #define _B0CON_B0FILHIT2_POSITION 0x2 #define _B0CON_B0FILHIT2_SIZE 0x1 #define _B0CON_B0FILHIT2_LENGTH 0x1 #define _B0CON_B0FILHIT2_MASK 0x4 #define _B0CON_B0FILHIT3_POSN 0x3 #define _B0CON_B0FILHIT3_POSITION 0x3 #define _B0CON_B0FILHIT3_SIZE 0x1 #define _B0CON_B0FILHIT3_LENGTH 0x1 #define _B0CON_B0FILHIT3_MASK 0x8 #define _B0CON_B0FILHIT4_POSN 0x4 #define _B0CON_B0FILHIT4_POSITION 0x4 #define _B0CON_B0FILHIT4_SIZE 0x1 #define _B0CON_B0FILHIT4_LENGTH 0x1 #define _B0CON_B0FILHIT4_MASK 0x10 #define _B0CON_B0RTRRO_POSN 0x5 #define _B0CON_B0RTRRO_POSITION 0x5 #define _B0CON_B0RTRRO_SIZE 0x1 #define _B0CON_B0RTRRO_LENGTH 0x1 #define _B0CON_B0RTRRO_MASK 0x20 #define _B0CON_B0RXM1_POSN 0x6 #define _B0CON_B0RXM1_POSITION 0x6 #define _B0CON_B0RXM1_SIZE 0x1 #define _B0CON_B0RXM1_LENGTH 0x1 #define _B0CON_B0RXM1_MASK 0x40 #define _B0CON_B0RXFUL_POSN 0x7 #define _B0CON_B0RXFUL_POSITION 0x7 #define _B0CON_B0RXFUL_SIZE 0x1 #define _B0CON_B0RXFUL_LENGTH 0x1 #define _B0CON_B0RXFUL_MASK 0x80 #define _B0CON_B0TXPRI0_POSN 0x0 #define _B0CON_B0TXPRI0_POSITION 0x0 #define _B0CON_B0TXPRI0_SIZE 0x1 #define _B0CON_B0TXPRI0_LENGTH 0x1 #define _B0CON_B0TXPRI0_MASK 0x1 #define _B0CON_B0TXPRI1_POSN 0x1 #define _B0CON_B0TXPRI1_POSITION 0x1 #define _B0CON_B0TXPRI1_SIZE 0x1 #define _B0CON_B0TXPRI1_LENGTH 0x1 #define _B0CON_B0TXPRI1_MASK 0x2 #define _B0CON_B0RTREN_POSN 0x2 #define _B0CON_B0RTREN_POSITION 0x2 #define _B0CON_B0RTREN_SIZE 0x1 #define _B0CON_B0RTREN_LENGTH 0x1 #define _B0CON_B0RTREN_MASK 0x4 #define _B0CON_B0TXREQ_POSN 0x3 #define _B0CON_B0TXREQ_POSITION 0x3 #define _B0CON_B0TXREQ_SIZE 0x1 #define _B0CON_B0TXREQ_LENGTH 0x1 #define _B0CON_B0TXREQ_MASK 0x8 #define _B0CON_B0TXERR_POSN 0x4 #define _B0CON_B0TXERR_POSITION 0x4 #define _B0CON_B0TXERR_SIZE 0x1 #define _B0CON_B0TXERR_LENGTH 0x1 #define _B0CON_B0TXERR_MASK 0x10 #define _B0CON_B0TXLARB_POSN 0x5 #define _B0CON_B0TXLARB_POSITION 0x5 #define _B0CON_B0TXLARB_SIZE 0x1 #define _B0CON_B0TXLARB_LENGTH 0x1 #define _B0CON_B0TXLARB_MASK 0x20 #define _B0CON_B0TXABT_POSN 0x6 #define _B0CON_B0TXABT_POSITION 0x6 #define _B0CON_B0TXABT_SIZE 0x1 #define _B0CON_B0TXABT_LENGTH 0x1 #define _B0CON_B0TXABT_MASK 0x40 #define _B0CON_B0TXB3IF_POSN 0x7 #define _B0CON_B0TXB3IF_POSITION 0x7 #define _B0CON_B0TXB3IF_SIZE 0x1 #define _B0CON_B0TXB3IF_LENGTH 0x1 #define _B0CON_B0TXB3IF_MASK 0x80 // Register: B0SIDH #define B0SIDH B0SIDH extern volatile unsigned char B0SIDH @ 0xE81; #ifndef _LIB_BUILD asm("B0SIDH equ 0E81h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B0SID3 :1; unsigned B0SID4 :1; unsigned B0SID5 :1; unsigned B0SID6 :1; unsigned B0SID7 :1; unsigned B0SID8 :1; unsigned B0SID9 :1; unsigned B0SID10 :1; }; } B0SIDHbits_t; extern volatile B0SIDHbits_t B0SIDHbits @ 0xE81; // bitfield macros #define _B0SIDH_SID_POSN 0x0 #define _B0SIDH_SID_POSITION 0x0 #define _B0SIDH_SID_SIZE 0x8 #define _B0SIDH_SID_LENGTH 0x8 #define _B0SIDH_SID_MASK 0xFF #define _B0SIDH_SID3_POSN 0x0 #define _B0SIDH_SID3_POSITION 0x0 #define _B0SIDH_SID3_SIZE 0x1 #define _B0SIDH_SID3_LENGTH 0x1 #define _B0SIDH_SID3_MASK 0x1 #define _B0SIDH_SID4_POSN 0x1 #define _B0SIDH_SID4_POSITION 0x1 #define _B0SIDH_SID4_SIZE 0x1 #define _B0SIDH_SID4_LENGTH 0x1 #define _B0SIDH_SID4_MASK 0x2 #define _B0SIDH_SID5_POSN 0x2 #define _B0SIDH_SID5_POSITION 0x2 #define _B0SIDH_SID5_SIZE 0x1 #define _B0SIDH_SID5_LENGTH 0x1 #define _B0SIDH_SID5_MASK 0x4 #define _B0SIDH_SID6_POSN 0x3 #define _B0SIDH_SID6_POSITION 0x3 #define _B0SIDH_SID6_SIZE 0x1 #define _B0SIDH_SID6_LENGTH 0x1 #define _B0SIDH_SID6_MASK 0x8 #define _B0SIDH_SID7_POSN 0x4 #define _B0SIDH_SID7_POSITION 0x4 #define _B0SIDH_SID7_SIZE 0x1 #define _B0SIDH_SID7_LENGTH 0x1 #define _B0SIDH_SID7_MASK 0x10 #define _B0SIDH_SID8_POSN 0x5 #define _B0SIDH_SID8_POSITION 0x5 #define _B0SIDH_SID8_SIZE 0x1 #define _B0SIDH_SID8_LENGTH 0x1 #define _B0SIDH_SID8_MASK 0x20 #define _B0SIDH_SID9_POSN 0x6 #define _B0SIDH_SID9_POSITION 0x6 #define _B0SIDH_SID9_SIZE 0x1 #define _B0SIDH_SID9_LENGTH 0x1 #define _B0SIDH_SID9_MASK 0x40 #define _B0SIDH_SID10_POSN 0x7 #define _B0SIDH_SID10_POSITION 0x7 #define _B0SIDH_SID10_SIZE 0x1 #define _B0SIDH_SID10_LENGTH 0x1 #define _B0SIDH_SID10_MASK 0x80 #define _B0SIDH_B0SID3_POSN 0x0 #define _B0SIDH_B0SID3_POSITION 0x0 #define _B0SIDH_B0SID3_SIZE 0x1 #define _B0SIDH_B0SID3_LENGTH 0x1 #define _B0SIDH_B0SID3_MASK 0x1 #define _B0SIDH_B0SID4_POSN 0x1 #define _B0SIDH_B0SID4_POSITION 0x1 #define _B0SIDH_B0SID4_SIZE 0x1 #define _B0SIDH_B0SID4_LENGTH 0x1 #define _B0SIDH_B0SID4_MASK 0x2 #define _B0SIDH_B0SID5_POSN 0x2 #define _B0SIDH_B0SID5_POSITION 0x2 #define _B0SIDH_B0SID5_SIZE 0x1 #define _B0SIDH_B0SID5_LENGTH 0x1 #define _B0SIDH_B0SID5_MASK 0x4 #define _B0SIDH_B0SID6_POSN 0x3 #define _B0SIDH_B0SID6_POSITION 0x3 #define _B0SIDH_B0SID6_SIZE 0x1 #define _B0SIDH_B0SID6_LENGTH 0x1 #define _B0SIDH_B0SID6_MASK 0x8 #define _B0SIDH_B0SID7_POSN 0x4 #define _B0SIDH_B0SID7_POSITION 0x4 #define _B0SIDH_B0SID7_SIZE 0x1 #define _B0SIDH_B0SID7_LENGTH 0x1 #define _B0SIDH_B0SID7_MASK 0x10 #define _B0SIDH_B0SID8_POSN 0x5 #define _B0SIDH_B0SID8_POSITION 0x5 #define _B0SIDH_B0SID8_SIZE 0x1 #define _B0SIDH_B0SID8_LENGTH 0x1 #define _B0SIDH_B0SID8_MASK 0x20 #define _B0SIDH_B0SID9_POSN 0x6 #define _B0SIDH_B0SID9_POSITION 0x6 #define _B0SIDH_B0SID9_SIZE 0x1 #define _B0SIDH_B0SID9_LENGTH 0x1 #define _B0SIDH_B0SID9_MASK 0x40 #define _B0SIDH_B0SID10_POSN 0x7 #define _B0SIDH_B0SID10_POSITION 0x7 #define _B0SIDH_B0SID10_SIZE 0x1 #define _B0SIDH_B0SID10_LENGTH 0x1 #define _B0SIDH_B0SID10_MASK 0x80 // Register: B0SIDL #define B0SIDL B0SIDL extern volatile unsigned char B0SIDL @ 0xE82; #ifndef _LIB_BUILD asm("B0SIDL equ 0E82h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B0EID16 :1; unsigned B0EID17 :1; unsigned :1; unsigned B0EXID :1; unsigned B0SRR :1; unsigned B0SID0 :1; unsigned B0SID1 :1; unsigned B0SID2 :1; }; } B0SIDLbits_t; extern volatile B0SIDLbits_t B0SIDLbits @ 0xE82; // bitfield macros #define _B0SIDL_EID_POSN 0x0 #define _B0SIDL_EID_POSITION 0x0 #define _B0SIDL_EID_SIZE 0x2 #define _B0SIDL_EID_LENGTH 0x2 #define _B0SIDL_EID_MASK 0x3 #define _B0SIDL_EXIDE_POSN 0x3 #define _B0SIDL_EXIDE_POSITION 0x3 #define _B0SIDL_EXIDE_SIZE 0x1 #define _B0SIDL_EXIDE_LENGTH 0x1 #define _B0SIDL_EXIDE_MASK 0x8 #define _B0SIDL_SRR_POSN 0x4 #define _B0SIDL_SRR_POSITION 0x4 #define _B0SIDL_SRR_SIZE 0x1 #define _B0SIDL_SRR_LENGTH 0x1 #define _B0SIDL_SRR_MASK 0x10 #define _B0SIDL_SID_POSN 0x5 #define _B0SIDL_SID_POSITION 0x5 #define _B0SIDL_SID_SIZE 0x3 #define _B0SIDL_SID_LENGTH 0x3 #define _B0SIDL_SID_MASK 0xE0 #define _B0SIDL_EID16_POSN 0x0 #define _B0SIDL_EID16_POSITION 0x0 #define _B0SIDL_EID16_SIZE 0x1 #define _B0SIDL_EID16_LENGTH 0x1 #define _B0SIDL_EID16_MASK 0x1 #define _B0SIDL_EID17_POSN 0x1 #define _B0SIDL_EID17_POSITION 0x1 #define _B0SIDL_EID17_SIZE 0x1 #define _B0SIDL_EID17_LENGTH 0x1 #define _B0SIDL_EID17_MASK 0x2 #define _B0SIDL_SID0_POSN 0x5 #define _B0SIDL_SID0_POSITION 0x5 #define _B0SIDL_SID0_SIZE 0x1 #define _B0SIDL_SID0_LENGTH 0x1 #define _B0SIDL_SID0_MASK 0x20 #define _B0SIDL_SID1_POSN 0x6 #define _B0SIDL_SID1_POSITION 0x6 #define _B0SIDL_SID1_SIZE 0x1 #define _B0SIDL_SID1_LENGTH 0x1 #define _B0SIDL_SID1_MASK 0x40 #define _B0SIDL_SID2_POSN 0x7 #define _B0SIDL_SID2_POSITION 0x7 #define _B0SIDL_SID2_SIZE 0x1 #define _B0SIDL_SID2_LENGTH 0x1 #define _B0SIDL_SID2_MASK 0x80 #define _B0SIDL_B0EID16_POSN 0x0 #define _B0SIDL_B0EID16_POSITION 0x0 #define _B0SIDL_B0EID16_SIZE 0x1 #define _B0SIDL_B0EID16_LENGTH 0x1 #define _B0SIDL_B0EID16_MASK 0x1 #define _B0SIDL_B0EID17_POSN 0x1 #define _B0SIDL_B0EID17_POSITION 0x1 #define _B0SIDL_B0EID17_SIZE 0x1 #define _B0SIDL_B0EID17_LENGTH 0x1 #define _B0SIDL_B0EID17_MASK 0x2 #define _B0SIDL_B0EXID_POSN 0x3 #define _B0SIDL_B0EXID_POSITION 0x3 #define _B0SIDL_B0EXID_SIZE 0x1 #define _B0SIDL_B0EXID_LENGTH 0x1 #define _B0SIDL_B0EXID_MASK 0x8 #define _B0SIDL_B0SRR_POSN 0x4 #define _B0SIDL_B0SRR_POSITION 0x4 #define _B0SIDL_B0SRR_SIZE 0x1 #define _B0SIDL_B0SRR_LENGTH 0x1 #define _B0SIDL_B0SRR_MASK 0x10 #define _B0SIDL_B0SID0_POSN 0x5 #define _B0SIDL_B0SID0_POSITION 0x5 #define _B0SIDL_B0SID0_SIZE 0x1 #define _B0SIDL_B0SID0_LENGTH 0x1 #define _B0SIDL_B0SID0_MASK 0x20 #define _B0SIDL_B0SID1_POSN 0x6 #define _B0SIDL_B0SID1_POSITION 0x6 #define _B0SIDL_B0SID1_SIZE 0x1 #define _B0SIDL_B0SID1_LENGTH 0x1 #define _B0SIDL_B0SID1_MASK 0x40 #define _B0SIDL_B0SID2_POSN 0x7 #define _B0SIDL_B0SID2_POSITION 0x7 #define _B0SIDL_B0SID2_SIZE 0x1 #define _B0SIDL_B0SID2_LENGTH 0x1 #define _B0SIDL_B0SID2_MASK 0x80 // Register: B0EIDH #define B0EIDH B0EIDH extern volatile unsigned char B0EIDH @ 0xE83; #ifndef _LIB_BUILD asm("B0EIDH equ 0E83h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B0EID8 :1; unsigned B0EID9 :1; unsigned B0EID10 :1; unsigned B0EID11 :1; unsigned B0EID12 :1; unsigned B0EID13 :1; unsigned B0EID14 :1; unsigned B0EID15 :1; }; } B0EIDHbits_t; extern volatile B0EIDHbits_t B0EIDHbits @ 0xE83; // bitfield macros #define _B0EIDH_EID_POSN 0x0 #define _B0EIDH_EID_POSITION 0x0 #define _B0EIDH_EID_SIZE 0x8 #define _B0EIDH_EID_LENGTH 0x8 #define _B0EIDH_EID_MASK 0xFF #define _B0EIDH_EID8_POSN 0x0 #define _B0EIDH_EID8_POSITION 0x0 #define _B0EIDH_EID8_SIZE 0x1 #define _B0EIDH_EID8_LENGTH 0x1 #define _B0EIDH_EID8_MASK 0x1 #define _B0EIDH_EID9_POSN 0x1 #define _B0EIDH_EID9_POSITION 0x1 #define _B0EIDH_EID9_SIZE 0x1 #define _B0EIDH_EID9_LENGTH 0x1 #define _B0EIDH_EID9_MASK 0x2 #define _B0EIDH_EID10_POSN 0x2 #define _B0EIDH_EID10_POSITION 0x2 #define _B0EIDH_EID10_SIZE 0x1 #define _B0EIDH_EID10_LENGTH 0x1 #define _B0EIDH_EID10_MASK 0x4 #define _B0EIDH_EID11_POSN 0x3 #define _B0EIDH_EID11_POSITION 0x3 #define _B0EIDH_EID11_SIZE 0x1 #define _B0EIDH_EID11_LENGTH 0x1 #define _B0EIDH_EID11_MASK 0x8 #define _B0EIDH_EID12_POSN 0x4 #define _B0EIDH_EID12_POSITION 0x4 #define _B0EIDH_EID12_SIZE 0x1 #define _B0EIDH_EID12_LENGTH 0x1 #define _B0EIDH_EID12_MASK 0x10 #define _B0EIDH_EID13_POSN 0x5 #define _B0EIDH_EID13_POSITION 0x5 #define _B0EIDH_EID13_SIZE 0x1 #define _B0EIDH_EID13_LENGTH 0x1 #define _B0EIDH_EID13_MASK 0x20 #define _B0EIDH_EID14_POSN 0x6 #define _B0EIDH_EID14_POSITION 0x6 #define _B0EIDH_EID14_SIZE 0x1 #define _B0EIDH_EID14_LENGTH 0x1 #define _B0EIDH_EID14_MASK 0x40 #define _B0EIDH_EID15_POSN 0x7 #define _B0EIDH_EID15_POSITION 0x7 #define _B0EIDH_EID15_SIZE 0x1 #define _B0EIDH_EID15_LENGTH 0x1 #define _B0EIDH_EID15_MASK 0x80 #define _B0EIDH_B0EID8_POSN 0x0 #define _B0EIDH_B0EID8_POSITION 0x0 #define _B0EIDH_B0EID8_SIZE 0x1 #define _B0EIDH_B0EID8_LENGTH 0x1 #define _B0EIDH_B0EID8_MASK 0x1 #define _B0EIDH_B0EID9_POSN 0x1 #define _B0EIDH_B0EID9_POSITION 0x1 #define _B0EIDH_B0EID9_SIZE 0x1 #define _B0EIDH_B0EID9_LENGTH 0x1 #define _B0EIDH_B0EID9_MASK 0x2 #define _B0EIDH_B0EID10_POSN 0x2 #define _B0EIDH_B0EID10_POSITION 0x2 #define _B0EIDH_B0EID10_SIZE 0x1 #define _B0EIDH_B0EID10_LENGTH 0x1 #define _B0EIDH_B0EID10_MASK 0x4 #define _B0EIDH_B0EID11_POSN 0x3 #define _B0EIDH_B0EID11_POSITION 0x3 #define _B0EIDH_B0EID11_SIZE 0x1 #define _B0EIDH_B0EID11_LENGTH 0x1 #define _B0EIDH_B0EID11_MASK 0x8 #define _B0EIDH_B0EID12_POSN 0x4 #define _B0EIDH_B0EID12_POSITION 0x4 #define _B0EIDH_B0EID12_SIZE 0x1 #define _B0EIDH_B0EID12_LENGTH 0x1 #define _B0EIDH_B0EID12_MASK 0x10 #define _B0EIDH_B0EID13_POSN 0x5 #define _B0EIDH_B0EID13_POSITION 0x5 #define _B0EIDH_B0EID13_SIZE 0x1 #define _B0EIDH_B0EID13_LENGTH 0x1 #define _B0EIDH_B0EID13_MASK 0x20 #define _B0EIDH_B0EID14_POSN 0x6 #define _B0EIDH_B0EID14_POSITION 0x6 #define _B0EIDH_B0EID14_SIZE 0x1 #define _B0EIDH_B0EID14_LENGTH 0x1 #define _B0EIDH_B0EID14_MASK 0x40 #define _B0EIDH_B0EID15_POSN 0x7 #define _B0EIDH_B0EID15_POSITION 0x7 #define _B0EIDH_B0EID15_SIZE 0x1 #define _B0EIDH_B0EID15_LENGTH 0x1 #define _B0EIDH_B0EID15_MASK 0x80 // Register: B0EIDL #define B0EIDL B0EIDL extern volatile unsigned char B0EIDL @ 0xE84; #ifndef _LIB_BUILD asm("B0EIDL equ 0E84h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B0EID0 :1; unsigned B0EID1 :1; unsigned B0EID2 :1; unsigned B0EID3 :1; unsigned B0EID4 :1; unsigned B0EID5 :1; unsigned B0EID6 :1; unsigned B0EID7 :1; }; } B0EIDLbits_t; extern volatile B0EIDLbits_t B0EIDLbits @ 0xE84; // bitfield macros #define _B0EIDL_EID_POSN 0x0 #define _B0EIDL_EID_POSITION 0x0 #define _B0EIDL_EID_SIZE 0x8 #define _B0EIDL_EID_LENGTH 0x8 #define _B0EIDL_EID_MASK 0xFF #define _B0EIDL_EID0_POSN 0x0 #define _B0EIDL_EID0_POSITION 0x0 #define _B0EIDL_EID0_SIZE 0x1 #define _B0EIDL_EID0_LENGTH 0x1 #define _B0EIDL_EID0_MASK 0x1 #define _B0EIDL_EID1_POSN 0x1 #define _B0EIDL_EID1_POSITION 0x1 #define _B0EIDL_EID1_SIZE 0x1 #define _B0EIDL_EID1_LENGTH 0x1 #define _B0EIDL_EID1_MASK 0x2 #define _B0EIDL_EID2_POSN 0x2 #define _B0EIDL_EID2_POSITION 0x2 #define _B0EIDL_EID2_SIZE 0x1 #define _B0EIDL_EID2_LENGTH 0x1 #define _B0EIDL_EID2_MASK 0x4 #define _B0EIDL_EID3_POSN 0x3 #define _B0EIDL_EID3_POSITION 0x3 #define _B0EIDL_EID3_SIZE 0x1 #define _B0EIDL_EID3_LENGTH 0x1 #define _B0EIDL_EID3_MASK 0x8 #define _B0EIDL_EID4_POSN 0x4 #define _B0EIDL_EID4_POSITION 0x4 #define _B0EIDL_EID4_SIZE 0x1 #define _B0EIDL_EID4_LENGTH 0x1 #define _B0EIDL_EID4_MASK 0x10 #define _B0EIDL_EID5_POSN 0x5 #define _B0EIDL_EID5_POSITION 0x5 #define _B0EIDL_EID5_SIZE 0x1 #define _B0EIDL_EID5_LENGTH 0x1 #define _B0EIDL_EID5_MASK 0x20 #define _B0EIDL_EID6_POSN 0x6 #define _B0EIDL_EID6_POSITION 0x6 #define _B0EIDL_EID6_SIZE 0x1 #define _B0EIDL_EID6_LENGTH 0x1 #define _B0EIDL_EID6_MASK 0x40 #define _B0EIDL_EID7_POSN 0x7 #define _B0EIDL_EID7_POSITION 0x7 #define _B0EIDL_EID7_SIZE 0x1 #define _B0EIDL_EID7_LENGTH 0x1 #define _B0EIDL_EID7_MASK 0x80 #define _B0EIDL_B0EID0_POSN 0x0 #define _B0EIDL_B0EID0_POSITION 0x0 #define _B0EIDL_B0EID0_SIZE 0x1 #define _B0EIDL_B0EID0_LENGTH 0x1 #define _B0EIDL_B0EID0_MASK 0x1 #define _B0EIDL_B0EID1_POSN 0x1 #define _B0EIDL_B0EID1_POSITION 0x1 #define _B0EIDL_B0EID1_SIZE 0x1 #define _B0EIDL_B0EID1_LENGTH 0x1 #define _B0EIDL_B0EID1_MASK 0x2 #define _B0EIDL_B0EID2_POSN 0x2 #define _B0EIDL_B0EID2_POSITION 0x2 #define _B0EIDL_B0EID2_SIZE 0x1 #define _B0EIDL_B0EID2_LENGTH 0x1 #define _B0EIDL_B0EID2_MASK 0x4 #define _B0EIDL_B0EID3_POSN 0x3 #define _B0EIDL_B0EID3_POSITION 0x3 #define _B0EIDL_B0EID3_SIZE 0x1 #define _B0EIDL_B0EID3_LENGTH 0x1 #define _B0EIDL_B0EID3_MASK 0x8 #define _B0EIDL_B0EID4_POSN 0x4 #define _B0EIDL_B0EID4_POSITION 0x4 #define _B0EIDL_B0EID4_SIZE 0x1 #define _B0EIDL_B0EID4_LENGTH 0x1 #define _B0EIDL_B0EID4_MASK 0x10 #define _B0EIDL_B0EID5_POSN 0x5 #define _B0EIDL_B0EID5_POSITION 0x5 #define _B0EIDL_B0EID5_SIZE 0x1 #define _B0EIDL_B0EID5_LENGTH 0x1 #define _B0EIDL_B0EID5_MASK 0x20 #define _B0EIDL_B0EID6_POSN 0x6 #define _B0EIDL_B0EID6_POSITION 0x6 #define _B0EIDL_B0EID6_SIZE 0x1 #define _B0EIDL_B0EID6_LENGTH 0x1 #define _B0EIDL_B0EID6_MASK 0x40 #define _B0EIDL_B0EID7_POSN 0x7 #define _B0EIDL_B0EID7_POSITION 0x7 #define _B0EIDL_B0EID7_SIZE 0x1 #define _B0EIDL_B0EID7_LENGTH 0x1 #define _B0EIDL_B0EID7_MASK 0x80 // Register: B0DLC #define B0DLC B0DLC extern volatile unsigned char B0DLC @ 0xE85; #ifndef _LIB_BUILD asm("B0DLC equ 0E85h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B0DLC0 :1; unsigned B0DLC1 :1; unsigned B0DLC2 :1; unsigned B0DLC3 :1; unsigned B0RB0 :1; unsigned B0RB1 :1; unsigned B0RXRTR :1; }; } B0DLCbits_t; extern volatile B0DLCbits_t B0DLCbits @ 0xE85; // bitfield macros #define _B0DLC_DLC_POSN 0x0 #define _B0DLC_DLC_POSITION 0x0 #define _B0DLC_DLC_SIZE 0x4 #define _B0DLC_DLC_LENGTH 0x4 #define _B0DLC_DLC_MASK 0xF #define _B0DLC_RB_POSN 0x4 #define _B0DLC_RB_POSITION 0x4 #define _B0DLC_RB_SIZE 0x2 #define _B0DLC_RB_LENGTH 0x2 #define _B0DLC_RB_MASK 0x30 #define _B0DLC_RXRTR_TXRTR_POSN 0x6 #define _B0DLC_RXRTR_TXRTR_POSITION 0x6 #define _B0DLC_RXRTR_TXRTR_SIZE 0x1 #define _B0DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B0DLC_RXRTR_TXRTR_MASK 0x40 #define _B0DLC_DLC0_POSN 0x0 #define _B0DLC_DLC0_POSITION 0x0 #define _B0DLC_DLC0_SIZE 0x1 #define _B0DLC_DLC0_LENGTH 0x1 #define _B0DLC_DLC0_MASK 0x1 #define _B0DLC_DLC1_POSN 0x1 #define _B0DLC_DLC1_POSITION 0x1 #define _B0DLC_DLC1_SIZE 0x1 #define _B0DLC_DLC1_LENGTH 0x1 #define _B0DLC_DLC1_MASK 0x2 #define _B0DLC_DLC2_POSN 0x2 #define _B0DLC_DLC2_POSITION 0x2 #define _B0DLC_DLC2_SIZE 0x1 #define _B0DLC_DLC2_LENGTH 0x1 #define _B0DLC_DLC2_MASK 0x4 #define _B0DLC_DLC3_POSN 0x3 #define _B0DLC_DLC3_POSITION 0x3 #define _B0DLC_DLC3_SIZE 0x1 #define _B0DLC_DLC3_LENGTH 0x1 #define _B0DLC_DLC3_MASK 0x8 #define _B0DLC_RB0_POSN 0x4 #define _B0DLC_RB0_POSITION 0x4 #define _B0DLC_RB0_SIZE 0x1 #define _B0DLC_RB0_LENGTH 0x1 #define _B0DLC_RB0_MASK 0x10 #define _B0DLC_RB1_POSN 0x5 #define _B0DLC_RB1_POSITION 0x5 #define _B0DLC_RB1_SIZE 0x1 #define _B0DLC_RB1_LENGTH 0x1 #define _B0DLC_RB1_MASK 0x20 #define _B0DLC_RXRTR_POSN 0x6 #define _B0DLC_RXRTR_POSITION 0x6 #define _B0DLC_RXRTR_SIZE 0x1 #define _B0DLC_RXRTR_LENGTH 0x1 #define _B0DLC_RXRTR_MASK 0x40 #define _B0DLC_TXRTR_POSN 0x6 #define _B0DLC_TXRTR_POSITION 0x6 #define _B0DLC_TXRTR_SIZE 0x1 #define _B0DLC_TXRTR_LENGTH 0x1 #define _B0DLC_TXRTR_MASK 0x40 #define _B0DLC_B0DLC0_POSN 0x0 #define _B0DLC_B0DLC0_POSITION 0x0 #define _B0DLC_B0DLC0_SIZE 0x1 #define _B0DLC_B0DLC0_LENGTH 0x1 #define _B0DLC_B0DLC0_MASK 0x1 #define _B0DLC_B0DLC1_POSN 0x1 #define _B0DLC_B0DLC1_POSITION 0x1 #define _B0DLC_B0DLC1_SIZE 0x1 #define _B0DLC_B0DLC1_LENGTH 0x1 #define _B0DLC_B0DLC1_MASK 0x2 #define _B0DLC_B0DLC2_POSN 0x2 #define _B0DLC_B0DLC2_POSITION 0x2 #define _B0DLC_B0DLC2_SIZE 0x1 #define _B0DLC_B0DLC2_LENGTH 0x1 #define _B0DLC_B0DLC2_MASK 0x4 #define _B0DLC_B0DLC3_POSN 0x3 #define _B0DLC_B0DLC3_POSITION 0x3 #define _B0DLC_B0DLC3_SIZE 0x1 #define _B0DLC_B0DLC3_LENGTH 0x1 #define _B0DLC_B0DLC3_MASK 0x8 #define _B0DLC_B0RB0_POSN 0x4 #define _B0DLC_B0RB0_POSITION 0x4 #define _B0DLC_B0RB0_SIZE 0x1 #define _B0DLC_B0RB0_LENGTH 0x1 #define _B0DLC_B0RB0_MASK 0x10 #define _B0DLC_B0RB1_POSN 0x5 #define _B0DLC_B0RB1_POSITION 0x5 #define _B0DLC_B0RB1_SIZE 0x1 #define _B0DLC_B0RB1_LENGTH 0x1 #define _B0DLC_B0RB1_MASK 0x20 #define _B0DLC_B0RXRTR_POSN 0x6 #define _B0DLC_B0RXRTR_POSITION 0x6 #define _B0DLC_B0RXRTR_SIZE 0x1 #define _B0DLC_B0RXRTR_LENGTH 0x1 #define _B0DLC_B0RXRTR_MASK 0x40 // Register: B0D0 #define B0D0 B0D0 extern volatile unsigned char B0D0 @ 0xE86; #ifndef _LIB_BUILD asm("B0D0 equ 0E86h"); #endif // bitfield definitions typedef union { struct { unsigned B0D0 :8; }; struct { unsigned B0D00 :1; unsigned B0D01 :1; unsigned B0D02 :1; unsigned B0D03 :1; unsigned B0D04 :1; unsigned B0D05 :1; unsigned B0D06 :1; unsigned B0D07 :1; }; } B0D0bits_t; extern volatile B0D0bits_t B0D0bits @ 0xE86; // bitfield macros #define _B0D0_B0D0_POSN 0x0 #define _B0D0_B0D0_POSITION 0x0 #define _B0D0_B0D0_SIZE 0x8 #define _B0D0_B0D0_LENGTH 0x8 #define _B0D0_B0D0_MASK 0xFF #define _B0D0_B0D00_POSN 0x0 #define _B0D0_B0D00_POSITION 0x0 #define _B0D0_B0D00_SIZE 0x1 #define _B0D0_B0D00_LENGTH 0x1 #define _B0D0_B0D00_MASK 0x1 #define _B0D0_B0D01_POSN 0x1 #define _B0D0_B0D01_POSITION 0x1 #define _B0D0_B0D01_SIZE 0x1 #define _B0D0_B0D01_LENGTH 0x1 #define _B0D0_B0D01_MASK 0x2 #define _B0D0_B0D02_POSN 0x2 #define _B0D0_B0D02_POSITION 0x2 #define _B0D0_B0D02_SIZE 0x1 #define _B0D0_B0D02_LENGTH 0x1 #define _B0D0_B0D02_MASK 0x4 #define _B0D0_B0D03_POSN 0x3 #define _B0D0_B0D03_POSITION 0x3 #define _B0D0_B0D03_SIZE 0x1 #define _B0D0_B0D03_LENGTH 0x1 #define _B0D0_B0D03_MASK 0x8 #define _B0D0_B0D04_POSN 0x4 #define _B0D0_B0D04_POSITION 0x4 #define _B0D0_B0D04_SIZE 0x1 #define _B0D0_B0D04_LENGTH 0x1 #define _B0D0_B0D04_MASK 0x10 #define _B0D0_B0D05_POSN 0x5 #define _B0D0_B0D05_POSITION 0x5 #define _B0D0_B0D05_SIZE 0x1 #define _B0D0_B0D05_LENGTH 0x1 #define _B0D0_B0D05_MASK 0x20 #define _B0D0_B0D06_POSN 0x6 #define _B0D0_B0D06_POSITION 0x6 #define _B0D0_B0D06_SIZE 0x1 #define _B0D0_B0D06_LENGTH 0x1 #define _B0D0_B0D06_MASK 0x40 #define _B0D0_B0D07_POSN 0x7 #define _B0D0_B0D07_POSITION 0x7 #define _B0D0_B0D07_SIZE 0x1 #define _B0D0_B0D07_LENGTH 0x1 #define _B0D0_B0D07_MASK 0x80 // Register: B0D1 #define B0D1 B0D1 extern volatile unsigned char B0D1 @ 0xE87; #ifndef _LIB_BUILD asm("B0D1 equ 0E87h"); #endif // bitfield definitions typedef union { struct { unsigned B0D1 :8; }; struct { unsigned B0D10 :1; unsigned B0D11 :1; unsigned B0D12 :1; unsigned B0D13 :1; unsigned B0D14 :1; unsigned B0D15 :1; unsigned B0D16 :1; unsigned B0D17 :1; }; } B0D1bits_t; extern volatile B0D1bits_t B0D1bits @ 0xE87; // bitfield macros #define _B0D1_B0D1_POSN 0x0 #define _B0D1_B0D1_POSITION 0x0 #define _B0D1_B0D1_SIZE 0x8 #define _B0D1_B0D1_LENGTH 0x8 #define _B0D1_B0D1_MASK 0xFF #define _B0D1_B0D10_POSN 0x0 #define _B0D1_B0D10_POSITION 0x0 #define _B0D1_B0D10_SIZE 0x1 #define _B0D1_B0D10_LENGTH 0x1 #define _B0D1_B0D10_MASK 0x1 #define _B0D1_B0D11_POSN 0x1 #define _B0D1_B0D11_POSITION 0x1 #define _B0D1_B0D11_SIZE 0x1 #define _B0D1_B0D11_LENGTH 0x1 #define _B0D1_B0D11_MASK 0x2 #define _B0D1_B0D12_POSN 0x2 #define _B0D1_B0D12_POSITION 0x2 #define _B0D1_B0D12_SIZE 0x1 #define _B0D1_B0D12_LENGTH 0x1 #define _B0D1_B0D12_MASK 0x4 #define _B0D1_B0D13_POSN 0x3 #define _B0D1_B0D13_POSITION 0x3 #define _B0D1_B0D13_SIZE 0x1 #define _B0D1_B0D13_LENGTH 0x1 #define _B0D1_B0D13_MASK 0x8 #define _B0D1_B0D14_POSN 0x4 #define _B0D1_B0D14_POSITION 0x4 #define _B0D1_B0D14_SIZE 0x1 #define _B0D1_B0D14_LENGTH 0x1 #define _B0D1_B0D14_MASK 0x10 #define _B0D1_B0D15_POSN 0x5 #define _B0D1_B0D15_POSITION 0x5 #define _B0D1_B0D15_SIZE 0x1 #define _B0D1_B0D15_LENGTH 0x1 #define _B0D1_B0D15_MASK 0x20 #define _B0D1_B0D16_POSN 0x6 #define _B0D1_B0D16_POSITION 0x6 #define _B0D1_B0D16_SIZE 0x1 #define _B0D1_B0D16_LENGTH 0x1 #define _B0D1_B0D16_MASK 0x40 #define _B0D1_B0D17_POSN 0x7 #define _B0D1_B0D17_POSITION 0x7 #define _B0D1_B0D17_SIZE 0x1 #define _B0D1_B0D17_LENGTH 0x1 #define _B0D1_B0D17_MASK 0x80 // Register: B0D2 #define B0D2 B0D2 extern volatile unsigned char B0D2 @ 0xE88; #ifndef _LIB_BUILD asm("B0D2 equ 0E88h"); #endif // bitfield definitions typedef union { struct { unsigned B0D2 :8; }; struct { unsigned B0D20 :1; unsigned B0D21 :1; unsigned B0D22 :1; unsigned B0D23 :1; unsigned B0D24 :1; unsigned B0D25 :1; unsigned B0D26 :1; unsigned B0D27 :1; }; } B0D2bits_t; extern volatile B0D2bits_t B0D2bits @ 0xE88; // bitfield macros #define _B0D2_B0D2_POSN 0x0 #define _B0D2_B0D2_POSITION 0x0 #define _B0D2_B0D2_SIZE 0x8 #define _B0D2_B0D2_LENGTH 0x8 #define _B0D2_B0D2_MASK 0xFF #define _B0D2_B0D20_POSN 0x0 #define _B0D2_B0D20_POSITION 0x0 #define _B0D2_B0D20_SIZE 0x1 #define _B0D2_B0D20_LENGTH 0x1 #define _B0D2_B0D20_MASK 0x1 #define _B0D2_B0D21_POSN 0x1 #define _B0D2_B0D21_POSITION 0x1 #define _B0D2_B0D21_SIZE 0x1 #define _B0D2_B0D21_LENGTH 0x1 #define _B0D2_B0D21_MASK 0x2 #define _B0D2_B0D22_POSN 0x2 #define _B0D2_B0D22_POSITION 0x2 #define _B0D2_B0D22_SIZE 0x1 #define _B0D2_B0D22_LENGTH 0x1 #define _B0D2_B0D22_MASK 0x4 #define _B0D2_B0D23_POSN 0x3 #define _B0D2_B0D23_POSITION 0x3 #define _B0D2_B0D23_SIZE 0x1 #define _B0D2_B0D23_LENGTH 0x1 #define _B0D2_B0D23_MASK 0x8 #define _B0D2_B0D24_POSN 0x4 #define _B0D2_B0D24_POSITION 0x4 #define _B0D2_B0D24_SIZE 0x1 #define _B0D2_B0D24_LENGTH 0x1 #define _B0D2_B0D24_MASK 0x10 #define _B0D2_B0D25_POSN 0x5 #define _B0D2_B0D25_POSITION 0x5 #define _B0D2_B0D25_SIZE 0x1 #define _B0D2_B0D25_LENGTH 0x1 #define _B0D2_B0D25_MASK 0x20 #define _B0D2_B0D26_POSN 0x6 #define _B0D2_B0D26_POSITION 0x6 #define _B0D2_B0D26_SIZE 0x1 #define _B0D2_B0D26_LENGTH 0x1 #define _B0D2_B0D26_MASK 0x40 #define _B0D2_B0D27_POSN 0x7 #define _B0D2_B0D27_POSITION 0x7 #define _B0D2_B0D27_SIZE 0x1 #define _B0D2_B0D27_LENGTH 0x1 #define _B0D2_B0D27_MASK 0x80 // Register: B0D3 #define B0D3 B0D3 extern volatile unsigned char B0D3 @ 0xE89; #ifndef _LIB_BUILD asm("B0D3 equ 0E89h"); #endif // bitfield definitions typedef union { struct { unsigned B0D3 :8; }; struct { unsigned B0D30 :1; unsigned B0D31 :1; unsigned B0D32 :1; unsigned B0D33 :1; unsigned B0D34 :1; unsigned B0D35 :1; unsigned B0D36 :1; unsigned B0D37 :1; }; } B0D3bits_t; extern volatile B0D3bits_t B0D3bits @ 0xE89; // bitfield macros #define _B0D3_B0D3_POSN 0x0 #define _B0D3_B0D3_POSITION 0x0 #define _B0D3_B0D3_SIZE 0x8 #define _B0D3_B0D3_LENGTH 0x8 #define _B0D3_B0D3_MASK 0xFF #define _B0D3_B0D30_POSN 0x0 #define _B0D3_B0D30_POSITION 0x0 #define _B0D3_B0D30_SIZE 0x1 #define _B0D3_B0D30_LENGTH 0x1 #define _B0D3_B0D30_MASK 0x1 #define _B0D3_B0D31_POSN 0x1 #define _B0D3_B0D31_POSITION 0x1 #define _B0D3_B0D31_SIZE 0x1 #define _B0D3_B0D31_LENGTH 0x1 #define _B0D3_B0D31_MASK 0x2 #define _B0D3_B0D32_POSN 0x2 #define _B0D3_B0D32_POSITION 0x2 #define _B0D3_B0D32_SIZE 0x1 #define _B0D3_B0D32_LENGTH 0x1 #define _B0D3_B0D32_MASK 0x4 #define _B0D3_B0D33_POSN 0x3 #define _B0D3_B0D33_POSITION 0x3 #define _B0D3_B0D33_SIZE 0x1 #define _B0D3_B0D33_LENGTH 0x1 #define _B0D3_B0D33_MASK 0x8 #define _B0D3_B0D34_POSN 0x4 #define _B0D3_B0D34_POSITION 0x4 #define _B0D3_B0D34_SIZE 0x1 #define _B0D3_B0D34_LENGTH 0x1 #define _B0D3_B0D34_MASK 0x10 #define _B0D3_B0D35_POSN 0x5 #define _B0D3_B0D35_POSITION 0x5 #define _B0D3_B0D35_SIZE 0x1 #define _B0D3_B0D35_LENGTH 0x1 #define _B0D3_B0D35_MASK 0x20 #define _B0D3_B0D36_POSN 0x6 #define _B0D3_B0D36_POSITION 0x6 #define _B0D3_B0D36_SIZE 0x1 #define _B0D3_B0D36_LENGTH 0x1 #define _B0D3_B0D36_MASK 0x40 #define _B0D3_B0D37_POSN 0x7 #define _B0D3_B0D37_POSITION 0x7 #define _B0D3_B0D37_SIZE 0x1 #define _B0D3_B0D37_LENGTH 0x1 #define _B0D3_B0D37_MASK 0x80 // Register: B0D4 #define B0D4 B0D4 extern volatile unsigned char B0D4 @ 0xE8A; #ifndef _LIB_BUILD asm("B0D4 equ 0E8Ah"); #endif // bitfield definitions typedef union { struct { unsigned B0D4 :8; }; struct { unsigned B0D40 :1; unsigned B0D41 :1; unsigned B0D42 :1; unsigned B0D43 :1; unsigned B0D44 :1; unsigned B0D45 :1; unsigned B0D46 :1; unsigned B0D47 :1; }; } B0D4bits_t; extern volatile B0D4bits_t B0D4bits @ 0xE8A; // bitfield macros #define _B0D4_B0D4_POSN 0x0 #define _B0D4_B0D4_POSITION 0x0 #define _B0D4_B0D4_SIZE 0x8 #define _B0D4_B0D4_LENGTH 0x8 #define _B0D4_B0D4_MASK 0xFF #define _B0D4_B0D40_POSN 0x0 #define _B0D4_B0D40_POSITION 0x0 #define _B0D4_B0D40_SIZE 0x1 #define _B0D4_B0D40_LENGTH 0x1 #define _B0D4_B0D40_MASK 0x1 #define _B0D4_B0D41_POSN 0x1 #define _B0D4_B0D41_POSITION 0x1 #define _B0D4_B0D41_SIZE 0x1 #define _B0D4_B0D41_LENGTH 0x1 #define _B0D4_B0D41_MASK 0x2 #define _B0D4_B0D42_POSN 0x2 #define _B0D4_B0D42_POSITION 0x2 #define _B0D4_B0D42_SIZE 0x1 #define _B0D4_B0D42_LENGTH 0x1 #define _B0D4_B0D42_MASK 0x4 #define _B0D4_B0D43_POSN 0x3 #define _B0D4_B0D43_POSITION 0x3 #define _B0D4_B0D43_SIZE 0x1 #define _B0D4_B0D43_LENGTH 0x1 #define _B0D4_B0D43_MASK 0x8 #define _B0D4_B0D44_POSN 0x4 #define _B0D4_B0D44_POSITION 0x4 #define _B0D4_B0D44_SIZE 0x1 #define _B0D4_B0D44_LENGTH 0x1 #define _B0D4_B0D44_MASK 0x10 #define _B0D4_B0D45_POSN 0x5 #define _B0D4_B0D45_POSITION 0x5 #define _B0D4_B0D45_SIZE 0x1 #define _B0D4_B0D45_LENGTH 0x1 #define _B0D4_B0D45_MASK 0x20 #define _B0D4_B0D46_POSN 0x6 #define _B0D4_B0D46_POSITION 0x6 #define _B0D4_B0D46_SIZE 0x1 #define _B0D4_B0D46_LENGTH 0x1 #define _B0D4_B0D46_MASK 0x40 #define _B0D4_B0D47_POSN 0x7 #define _B0D4_B0D47_POSITION 0x7 #define _B0D4_B0D47_SIZE 0x1 #define _B0D4_B0D47_LENGTH 0x1 #define _B0D4_B0D47_MASK 0x80 // Register: B0D5 #define B0D5 B0D5 extern volatile unsigned char B0D5 @ 0xE8B; #ifndef _LIB_BUILD asm("B0D5 equ 0E8Bh"); #endif // bitfield definitions typedef union { struct { unsigned B0D5 :8; }; struct { unsigned B0D50 :1; unsigned B0D51 :1; unsigned B0D52 :1; unsigned B0D53 :1; unsigned B0D54 :1; unsigned B0D55 :1; unsigned B0D56 :1; unsigned B0D57 :1; }; } B0D5bits_t; extern volatile B0D5bits_t B0D5bits @ 0xE8B; // bitfield macros #define _B0D5_B0D5_POSN 0x0 #define _B0D5_B0D5_POSITION 0x0 #define _B0D5_B0D5_SIZE 0x8 #define _B0D5_B0D5_LENGTH 0x8 #define _B0D5_B0D5_MASK 0xFF #define _B0D5_B0D50_POSN 0x0 #define _B0D5_B0D50_POSITION 0x0 #define _B0D5_B0D50_SIZE 0x1 #define _B0D5_B0D50_LENGTH 0x1 #define _B0D5_B0D50_MASK 0x1 #define _B0D5_B0D51_POSN 0x1 #define _B0D5_B0D51_POSITION 0x1 #define _B0D5_B0D51_SIZE 0x1 #define _B0D5_B0D51_LENGTH 0x1 #define _B0D5_B0D51_MASK 0x2 #define _B0D5_B0D52_POSN 0x2 #define _B0D5_B0D52_POSITION 0x2 #define _B0D5_B0D52_SIZE 0x1 #define _B0D5_B0D52_LENGTH 0x1 #define _B0D5_B0D52_MASK 0x4 #define _B0D5_B0D53_POSN 0x3 #define _B0D5_B0D53_POSITION 0x3 #define _B0D5_B0D53_SIZE 0x1 #define _B0D5_B0D53_LENGTH 0x1 #define _B0D5_B0D53_MASK 0x8 #define _B0D5_B0D54_POSN 0x4 #define _B0D5_B0D54_POSITION 0x4 #define _B0D5_B0D54_SIZE 0x1 #define _B0D5_B0D54_LENGTH 0x1 #define _B0D5_B0D54_MASK 0x10 #define _B0D5_B0D55_POSN 0x5 #define _B0D5_B0D55_POSITION 0x5 #define _B0D5_B0D55_SIZE 0x1 #define _B0D5_B0D55_LENGTH 0x1 #define _B0D5_B0D55_MASK 0x20 #define _B0D5_B0D56_POSN 0x6 #define _B0D5_B0D56_POSITION 0x6 #define _B0D5_B0D56_SIZE 0x1 #define _B0D5_B0D56_LENGTH 0x1 #define _B0D5_B0D56_MASK 0x40 #define _B0D5_B0D57_POSN 0x7 #define _B0D5_B0D57_POSITION 0x7 #define _B0D5_B0D57_SIZE 0x1 #define _B0D5_B0D57_LENGTH 0x1 #define _B0D5_B0D57_MASK 0x80 // Register: B0D6 #define B0D6 B0D6 extern volatile unsigned char B0D6 @ 0xE8C; #ifndef _LIB_BUILD asm("B0D6 equ 0E8Ch"); #endif // bitfield definitions typedef union { struct { unsigned B0D6 :8; }; struct { unsigned B0D60 :1; unsigned B0D61 :1; unsigned B0D62 :1; unsigned B0D63 :1; unsigned B0D64 :1; unsigned B0D65 :1; unsigned B0D66 :1; unsigned B0D67 :1; }; } B0D6bits_t; extern volatile B0D6bits_t B0D6bits @ 0xE8C; // bitfield macros #define _B0D6_B0D6_POSN 0x0 #define _B0D6_B0D6_POSITION 0x0 #define _B0D6_B0D6_SIZE 0x8 #define _B0D6_B0D6_LENGTH 0x8 #define _B0D6_B0D6_MASK 0xFF #define _B0D6_B0D60_POSN 0x0 #define _B0D6_B0D60_POSITION 0x0 #define _B0D6_B0D60_SIZE 0x1 #define _B0D6_B0D60_LENGTH 0x1 #define _B0D6_B0D60_MASK 0x1 #define _B0D6_B0D61_POSN 0x1 #define _B0D6_B0D61_POSITION 0x1 #define _B0D6_B0D61_SIZE 0x1 #define _B0D6_B0D61_LENGTH 0x1 #define _B0D6_B0D61_MASK 0x2 #define _B0D6_B0D62_POSN 0x2 #define _B0D6_B0D62_POSITION 0x2 #define _B0D6_B0D62_SIZE 0x1 #define _B0D6_B0D62_LENGTH 0x1 #define _B0D6_B0D62_MASK 0x4 #define _B0D6_B0D63_POSN 0x3 #define _B0D6_B0D63_POSITION 0x3 #define _B0D6_B0D63_SIZE 0x1 #define _B0D6_B0D63_LENGTH 0x1 #define _B0D6_B0D63_MASK 0x8 #define _B0D6_B0D64_POSN 0x4 #define _B0D6_B0D64_POSITION 0x4 #define _B0D6_B0D64_SIZE 0x1 #define _B0D6_B0D64_LENGTH 0x1 #define _B0D6_B0D64_MASK 0x10 #define _B0D6_B0D65_POSN 0x5 #define _B0D6_B0D65_POSITION 0x5 #define _B0D6_B0D65_SIZE 0x1 #define _B0D6_B0D65_LENGTH 0x1 #define _B0D6_B0D65_MASK 0x20 #define _B0D6_B0D66_POSN 0x6 #define _B0D6_B0D66_POSITION 0x6 #define _B0D6_B0D66_SIZE 0x1 #define _B0D6_B0D66_LENGTH 0x1 #define _B0D6_B0D66_MASK 0x40 #define _B0D6_B0D67_POSN 0x7 #define _B0D6_B0D67_POSITION 0x7 #define _B0D6_B0D67_SIZE 0x1 #define _B0D6_B0D67_LENGTH 0x1 #define _B0D6_B0D67_MASK 0x80 // Register: B0D7 #define B0D7 B0D7 extern volatile unsigned char B0D7 @ 0xE8D; #ifndef _LIB_BUILD asm("B0D7 equ 0E8Dh"); #endif // bitfield definitions typedef union { struct { unsigned B0D7 :8; }; struct { unsigned B0D70 :1; unsigned B0D71 :1; unsigned B0D72 :1; unsigned B0D73 :1; unsigned B0D74 :1; unsigned B0D75 :1; unsigned B0D76 :1; unsigned B0D77 :1; }; } B0D7bits_t; extern volatile B0D7bits_t B0D7bits @ 0xE8D; // bitfield macros #define _B0D7_B0D7_POSN 0x0 #define _B0D7_B0D7_POSITION 0x0 #define _B0D7_B0D7_SIZE 0x8 #define _B0D7_B0D7_LENGTH 0x8 #define _B0D7_B0D7_MASK 0xFF #define _B0D7_B0D70_POSN 0x0 #define _B0D7_B0D70_POSITION 0x0 #define _B0D7_B0D70_SIZE 0x1 #define _B0D7_B0D70_LENGTH 0x1 #define _B0D7_B0D70_MASK 0x1 #define _B0D7_B0D71_POSN 0x1 #define _B0D7_B0D71_POSITION 0x1 #define _B0D7_B0D71_SIZE 0x1 #define _B0D7_B0D71_LENGTH 0x1 #define _B0D7_B0D71_MASK 0x2 #define _B0D7_B0D72_POSN 0x2 #define _B0D7_B0D72_POSITION 0x2 #define _B0D7_B0D72_SIZE 0x1 #define _B0D7_B0D72_LENGTH 0x1 #define _B0D7_B0D72_MASK 0x4 #define _B0D7_B0D73_POSN 0x3 #define _B0D7_B0D73_POSITION 0x3 #define _B0D7_B0D73_SIZE 0x1 #define _B0D7_B0D73_LENGTH 0x1 #define _B0D7_B0D73_MASK 0x8 #define _B0D7_B0D74_POSN 0x4 #define _B0D7_B0D74_POSITION 0x4 #define _B0D7_B0D74_SIZE 0x1 #define _B0D7_B0D74_LENGTH 0x1 #define _B0D7_B0D74_MASK 0x10 #define _B0D7_B0D75_POSN 0x5 #define _B0D7_B0D75_POSITION 0x5 #define _B0D7_B0D75_SIZE 0x1 #define _B0D7_B0D75_LENGTH 0x1 #define _B0D7_B0D75_MASK 0x20 #define _B0D7_B0D76_POSN 0x6 #define _B0D7_B0D76_POSITION 0x6 #define _B0D7_B0D76_SIZE 0x1 #define _B0D7_B0D76_LENGTH 0x1 #define _B0D7_B0D76_MASK 0x40 #define _B0D7_B0D77_POSN 0x7 #define _B0D7_B0D77_POSITION 0x7 #define _B0D7_B0D77_SIZE 0x1 #define _B0D7_B0D77_LENGTH 0x1 #define _B0D7_B0D77_MASK 0x80 // Register: CANSTAT_RO9 #define CANSTAT_RO9 CANSTAT_RO9 extern volatile unsigned char CANSTAT_RO9 @ 0xE8E; #ifndef _LIB_BUILD asm("CANSTAT_RO9 equ 0E8Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO9bits_t; extern volatile CANSTAT_RO9bits_t CANSTAT_RO9bits @ 0xE8E; // bitfield macros #define _CANSTAT_RO9_EICODE0_POSN 0x0 #define _CANSTAT_RO9_EICODE0_POSITION 0x0 #define _CANSTAT_RO9_EICODE0_SIZE 0x1 #define _CANSTAT_RO9_EICODE0_LENGTH 0x1 #define _CANSTAT_RO9_EICODE0_MASK 0x1 #define _CANSTAT_RO9_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO9_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO9_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO9_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO9_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO9_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO9_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO9_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO9_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO9_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO9_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO9_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO9_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO9_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO9_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO9_EICODE4_POSN 0x4 #define _CANSTAT_RO9_EICODE4_POSITION 0x4 #define _CANSTAT_RO9_EICODE4_SIZE 0x1 #define _CANSTAT_RO9_EICODE4_LENGTH 0x1 #define _CANSTAT_RO9_EICODE4_MASK 0x10 #define _CANSTAT_RO9_OPMODE_POSN 0x5 #define _CANSTAT_RO9_OPMODE_POSITION 0x5 #define _CANSTAT_RO9_OPMODE_SIZE 0x3 #define _CANSTAT_RO9_OPMODE_LENGTH 0x3 #define _CANSTAT_RO9_OPMODE_MASK 0xE0 #define _CANSTAT_RO9_EICODE1_POSN 0x1 #define _CANSTAT_RO9_EICODE1_POSITION 0x1 #define _CANSTAT_RO9_EICODE1_SIZE 0x1 #define _CANSTAT_RO9_EICODE1_LENGTH 0x1 #define _CANSTAT_RO9_EICODE1_MASK 0x2 #define _CANSTAT_RO9_EICODE2_POSN 0x2 #define _CANSTAT_RO9_EICODE2_POSITION 0x2 #define _CANSTAT_RO9_EICODE2_SIZE 0x1 #define _CANSTAT_RO9_EICODE2_LENGTH 0x1 #define _CANSTAT_RO9_EICODE2_MASK 0x4 #define _CANSTAT_RO9_EICODE3_POSN 0x3 #define _CANSTAT_RO9_EICODE3_POSITION 0x3 #define _CANSTAT_RO9_EICODE3_SIZE 0x1 #define _CANSTAT_RO9_EICODE3_LENGTH 0x1 #define _CANSTAT_RO9_EICODE3_MASK 0x8 #define _CANSTAT_RO9_OPMODE0_POSN 0x5 #define _CANSTAT_RO9_OPMODE0_POSITION 0x5 #define _CANSTAT_RO9_OPMODE0_SIZE 0x1 #define _CANSTAT_RO9_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO9_OPMODE0_MASK 0x20 #define _CANSTAT_RO9_OPMODE1_POSN 0x6 #define _CANSTAT_RO9_OPMODE1_POSITION 0x6 #define _CANSTAT_RO9_OPMODE1_SIZE 0x1 #define _CANSTAT_RO9_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO9_OPMODE1_MASK 0x40 #define _CANSTAT_RO9_OPMODE2_POSN 0x7 #define _CANSTAT_RO9_OPMODE2_POSITION 0x7 #define _CANSTAT_RO9_OPMODE2_SIZE 0x1 #define _CANSTAT_RO9_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO9_OPMODE2_MASK 0x80 #define _CANSTAT_RO9_ICODE0_POSN 0x1 #define _CANSTAT_RO9_ICODE0_POSITION 0x1 #define _CANSTAT_RO9_ICODE0_SIZE 0x1 #define _CANSTAT_RO9_ICODE0_LENGTH 0x1 #define _CANSTAT_RO9_ICODE0_MASK 0x2 #define _CANSTAT_RO9_ICODE1_POSN 0x2 #define _CANSTAT_RO9_ICODE1_POSITION 0x2 #define _CANSTAT_RO9_ICODE1_SIZE 0x1 #define _CANSTAT_RO9_ICODE1_LENGTH 0x1 #define _CANSTAT_RO9_ICODE1_MASK 0x4 #define _CANSTAT_RO9_ICODE2_POSN 0x3 #define _CANSTAT_RO9_ICODE2_POSITION 0x3 #define _CANSTAT_RO9_ICODE2_SIZE 0x1 #define _CANSTAT_RO9_ICODE2_LENGTH 0x1 #define _CANSTAT_RO9_ICODE2_MASK 0x8 // Register: CANCON_RO9 #define CANCON_RO9 CANCON_RO9 extern volatile unsigned char CANCON_RO9 @ 0xE8F; #ifndef _LIB_BUILD asm("CANCON_RO9 equ 0E8Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO9bits_t; extern volatile CANCON_RO9bits_t CANCON_RO9bits @ 0xE8F; // bitfield macros #define _CANCON_RO9_FP0_POSN 0x0 #define _CANCON_RO9_FP0_POSITION 0x0 #define _CANCON_RO9_FP0_SIZE 0x1 #define _CANCON_RO9_FP0_LENGTH 0x1 #define _CANCON_RO9_FP0_MASK 0x1 #define _CANCON_RO9_WIN0_FP1_POSN 0x1 #define _CANCON_RO9_WIN0_FP1_POSITION 0x1 #define _CANCON_RO9_WIN0_FP1_SIZE 0x1 #define _CANCON_RO9_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO9_WIN0_FP1_MASK 0x2 #define _CANCON_RO9_WIN1_FP2_POSN 0x2 #define _CANCON_RO9_WIN1_FP2_POSITION 0x2 #define _CANCON_RO9_WIN1_FP2_SIZE 0x1 #define _CANCON_RO9_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO9_WIN1_FP2_MASK 0x4 #define _CANCON_RO9_WIN2_FP3_POSN 0x3 #define _CANCON_RO9_WIN2_FP3_POSITION 0x3 #define _CANCON_RO9_WIN2_FP3_SIZE 0x1 #define _CANCON_RO9_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO9_WIN2_FP3_MASK 0x8 #define _CANCON_RO9_ABAT_POSN 0x4 #define _CANCON_RO9_ABAT_POSITION 0x4 #define _CANCON_RO9_ABAT_SIZE 0x1 #define _CANCON_RO9_ABAT_LENGTH 0x1 #define _CANCON_RO9_ABAT_MASK 0x10 #define _CANCON_RO9_REQOP_POSN 0x5 #define _CANCON_RO9_REQOP_POSITION 0x5 #define _CANCON_RO9_REQOP_SIZE 0x3 #define _CANCON_RO9_REQOP_LENGTH 0x3 #define _CANCON_RO9_REQOP_MASK 0xE0 #define _CANCON_RO9_WIN0_POSN 0x1 #define _CANCON_RO9_WIN0_POSITION 0x1 #define _CANCON_RO9_WIN0_SIZE 0x1 #define _CANCON_RO9_WIN0_LENGTH 0x1 #define _CANCON_RO9_WIN0_MASK 0x2 #define _CANCON_RO9_WIN1_POSN 0x2 #define _CANCON_RO9_WIN1_POSITION 0x2 #define _CANCON_RO9_WIN1_SIZE 0x1 #define _CANCON_RO9_WIN1_LENGTH 0x1 #define _CANCON_RO9_WIN1_MASK 0x4 #define _CANCON_RO9_WIN2_POSN 0x3 #define _CANCON_RO9_WIN2_POSITION 0x3 #define _CANCON_RO9_WIN2_SIZE 0x1 #define _CANCON_RO9_WIN2_LENGTH 0x1 #define _CANCON_RO9_WIN2_MASK 0x8 #define _CANCON_RO9_FP1_POSN 0x1 #define _CANCON_RO9_FP1_POSITION 0x1 #define _CANCON_RO9_FP1_SIZE 0x1 #define _CANCON_RO9_FP1_LENGTH 0x1 #define _CANCON_RO9_FP1_MASK 0x2 #define _CANCON_RO9_FP2_POSN 0x2 #define _CANCON_RO9_FP2_POSITION 0x2 #define _CANCON_RO9_FP2_SIZE 0x1 #define _CANCON_RO9_FP2_LENGTH 0x1 #define _CANCON_RO9_FP2_MASK 0x4 #define _CANCON_RO9_FP3_POSN 0x3 #define _CANCON_RO9_FP3_POSITION 0x3 #define _CANCON_RO9_FP3_SIZE 0x1 #define _CANCON_RO9_FP3_LENGTH 0x1 #define _CANCON_RO9_FP3_MASK 0x8 // Register: B1CON #define B1CON B1CON extern volatile unsigned char B1CON @ 0xE90; #ifndef _LIB_BUILD asm("B1CON equ 0E90h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B1FILHIT0 :1; unsigned B1FILHIT1 :1; unsigned B1FILHIT2 :1; unsigned B1FILHIT3 :1; unsigned B1FILHIT4 :1; unsigned B1RTRRO :1; unsigned B1RXM1 :1; unsigned B1RXFUL :1; }; struct { unsigned B1TXPRI0 :1; unsigned B1TXPRI1 :1; unsigned B1RTREN :1; unsigned B1TXREQ :1; unsigned B1TXERR :1; unsigned B1TXLARB :1; unsigned B1TXABT :1; unsigned B1TXB3IF :1; }; } B1CONbits_t; extern volatile B1CONbits_t B1CONbits @ 0xE90; // bitfield macros #define _B1CON_FILHIT0_TXPRI0_POSN 0x0 #define _B1CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B1CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B1CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B1CON_FILHIT0_TXPRI0_MASK 0x1 #define _B1CON_FILHIT1_TXPRI1_POSN 0x1 #define _B1CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B1CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B1CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B1CON_FILHIT1_TXPRI1_MASK 0x2 #define _B1CON_FILHIT2_RTREN_POSN 0x2 #define _B1CON_FILHIT2_RTREN_POSITION 0x2 #define _B1CON_FILHIT2_RTREN_SIZE 0x1 #define _B1CON_FILHIT2_RTREN_LENGTH 0x1 #define _B1CON_FILHIT2_RTREN_MASK 0x4 #define _B1CON_FILHIT3_TXREQ_POSN 0x3 #define _B1CON_FILHIT3_TXREQ_POSITION 0x3 #define _B1CON_FILHIT3_TXREQ_SIZE 0x1 #define _B1CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B1CON_FILHIT3_TXREQ_MASK 0x8 #define _B1CON_FILHIT4_TXERR_POSN 0x4 #define _B1CON_FILHIT4_TXERR_POSITION 0x4 #define _B1CON_FILHIT4_TXERR_SIZE 0x1 #define _B1CON_FILHIT4_TXERR_LENGTH 0x1 #define _B1CON_FILHIT4_TXERR_MASK 0x10 #define _B1CON_RXRTRRO_TXLARB_POSN 0x5 #define _B1CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B1CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B1CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B1CON_RXRTRRO_TXLARB_MASK 0x20 #define _B1CON_RXM1_TXABT_POSN 0x6 #define _B1CON_RXM1_TXABT_POSITION 0x6 #define _B1CON_RXM1_TXABT_SIZE 0x1 #define _B1CON_RXM1_TXABT_LENGTH 0x1 #define _B1CON_RXM1_TXABT_MASK 0x40 #define _B1CON_RXFUL_TXBIF_POSN 0x7 #define _B1CON_RXFUL_TXBIF_POSITION 0x7 #define _B1CON_RXFUL_TXBIF_SIZE 0x1 #define _B1CON_RXFUL_TXBIF_LENGTH 0x1 #define _B1CON_RXFUL_TXBIF_MASK 0x80 #define _B1CON_FILHIT0_POSN 0x0 #define _B1CON_FILHIT0_POSITION 0x0 #define _B1CON_FILHIT0_SIZE 0x1 #define _B1CON_FILHIT0_LENGTH 0x1 #define _B1CON_FILHIT0_MASK 0x1 #define _B1CON_FILHIT1_POSN 0x1 #define _B1CON_FILHIT1_POSITION 0x1 #define _B1CON_FILHIT1_SIZE 0x1 #define _B1CON_FILHIT1_LENGTH 0x1 #define _B1CON_FILHIT1_MASK 0x2 #define _B1CON_FILHIT2_POSN 0x2 #define _B1CON_FILHIT2_POSITION 0x2 #define _B1CON_FILHIT2_SIZE 0x1 #define _B1CON_FILHIT2_LENGTH 0x1 #define _B1CON_FILHIT2_MASK 0x4 #define _B1CON_FILHIT3_POSN 0x3 #define _B1CON_FILHIT3_POSITION 0x3 #define _B1CON_FILHIT3_SIZE 0x1 #define _B1CON_FILHIT3_LENGTH 0x1 #define _B1CON_FILHIT3_MASK 0x8 #define _B1CON_FILHIT4_POSN 0x4 #define _B1CON_FILHIT4_POSITION 0x4 #define _B1CON_FILHIT4_SIZE 0x1 #define _B1CON_FILHIT4_LENGTH 0x1 #define _B1CON_FILHIT4_MASK 0x10 #define _B1CON_RXRTRRO_POSN 0x5 #define _B1CON_RXRTRRO_POSITION 0x5 #define _B1CON_RXRTRRO_SIZE 0x1 #define _B1CON_RXRTRRO_LENGTH 0x1 #define _B1CON_RXRTRRO_MASK 0x20 #define _B1CON_RXM1_POSN 0x6 #define _B1CON_RXM1_POSITION 0x6 #define _B1CON_RXM1_SIZE 0x1 #define _B1CON_RXM1_LENGTH 0x1 #define _B1CON_RXM1_MASK 0x40 #define _B1CON_RXFUL_POSN 0x7 #define _B1CON_RXFUL_POSITION 0x7 #define _B1CON_RXFUL_SIZE 0x1 #define _B1CON_RXFUL_LENGTH 0x1 #define _B1CON_RXFUL_MASK 0x80 #define _B1CON_TXPRI0_POSN 0x0 #define _B1CON_TXPRI0_POSITION 0x0 #define _B1CON_TXPRI0_SIZE 0x1 #define _B1CON_TXPRI0_LENGTH 0x1 #define _B1CON_TXPRI0_MASK 0x1 #define _B1CON_TXPRI1_POSN 0x1 #define _B1CON_TXPRI1_POSITION 0x1 #define _B1CON_TXPRI1_SIZE 0x1 #define _B1CON_TXPRI1_LENGTH 0x1 #define _B1CON_TXPRI1_MASK 0x2 #define _B1CON_RTREN_POSN 0x2 #define _B1CON_RTREN_POSITION 0x2 #define _B1CON_RTREN_SIZE 0x1 #define _B1CON_RTREN_LENGTH 0x1 #define _B1CON_RTREN_MASK 0x4 #define _B1CON_TXREQ_POSN 0x3 #define _B1CON_TXREQ_POSITION 0x3 #define _B1CON_TXREQ_SIZE 0x1 #define _B1CON_TXREQ_LENGTH 0x1 #define _B1CON_TXREQ_MASK 0x8 #define _B1CON_TXERR_POSN 0x4 #define _B1CON_TXERR_POSITION 0x4 #define _B1CON_TXERR_SIZE 0x1 #define _B1CON_TXERR_LENGTH 0x1 #define _B1CON_TXERR_MASK 0x10 #define _B1CON_TXLARB_POSN 0x5 #define _B1CON_TXLARB_POSITION 0x5 #define _B1CON_TXLARB_SIZE 0x1 #define _B1CON_TXLARB_LENGTH 0x1 #define _B1CON_TXLARB_MASK 0x20 #define _B1CON_TXABT_POSN 0x6 #define _B1CON_TXABT_POSITION 0x6 #define _B1CON_TXABT_SIZE 0x1 #define _B1CON_TXABT_LENGTH 0x1 #define _B1CON_TXABT_MASK 0x40 #define _B1CON_TXBIF_POSN 0x7 #define _B1CON_TXBIF_POSITION 0x7 #define _B1CON_TXBIF_SIZE 0x1 #define _B1CON_TXBIF_LENGTH 0x1 #define _B1CON_TXBIF_MASK 0x80 #define _B1CON_B1FILHIT0_POSN 0x0 #define _B1CON_B1FILHIT0_POSITION 0x0 #define _B1CON_B1FILHIT0_SIZE 0x1 #define _B1CON_B1FILHIT0_LENGTH 0x1 #define _B1CON_B1FILHIT0_MASK 0x1 #define _B1CON_B1FILHIT1_POSN 0x1 #define _B1CON_B1FILHIT1_POSITION 0x1 #define _B1CON_B1FILHIT1_SIZE 0x1 #define _B1CON_B1FILHIT1_LENGTH 0x1 #define _B1CON_B1FILHIT1_MASK 0x2 #define _B1CON_B1FILHIT2_POSN 0x2 #define _B1CON_B1FILHIT2_POSITION 0x2 #define _B1CON_B1FILHIT2_SIZE 0x1 #define _B1CON_B1FILHIT2_LENGTH 0x1 #define _B1CON_B1FILHIT2_MASK 0x4 #define _B1CON_B1FILHIT3_POSN 0x3 #define _B1CON_B1FILHIT3_POSITION 0x3 #define _B1CON_B1FILHIT3_SIZE 0x1 #define _B1CON_B1FILHIT3_LENGTH 0x1 #define _B1CON_B1FILHIT3_MASK 0x8 #define _B1CON_B1FILHIT4_POSN 0x4 #define _B1CON_B1FILHIT4_POSITION 0x4 #define _B1CON_B1FILHIT4_SIZE 0x1 #define _B1CON_B1FILHIT4_LENGTH 0x1 #define _B1CON_B1FILHIT4_MASK 0x10 #define _B1CON_B1RTRRO_POSN 0x5 #define _B1CON_B1RTRRO_POSITION 0x5 #define _B1CON_B1RTRRO_SIZE 0x1 #define _B1CON_B1RTRRO_LENGTH 0x1 #define _B1CON_B1RTRRO_MASK 0x20 #define _B1CON_B1RXM1_POSN 0x6 #define _B1CON_B1RXM1_POSITION 0x6 #define _B1CON_B1RXM1_SIZE 0x1 #define _B1CON_B1RXM1_LENGTH 0x1 #define _B1CON_B1RXM1_MASK 0x40 #define _B1CON_B1RXFUL_POSN 0x7 #define _B1CON_B1RXFUL_POSITION 0x7 #define _B1CON_B1RXFUL_SIZE 0x1 #define _B1CON_B1RXFUL_LENGTH 0x1 #define _B1CON_B1RXFUL_MASK 0x80 #define _B1CON_B1TXPRI0_POSN 0x0 #define _B1CON_B1TXPRI0_POSITION 0x0 #define _B1CON_B1TXPRI0_SIZE 0x1 #define _B1CON_B1TXPRI0_LENGTH 0x1 #define _B1CON_B1TXPRI0_MASK 0x1 #define _B1CON_B1TXPRI1_POSN 0x1 #define _B1CON_B1TXPRI1_POSITION 0x1 #define _B1CON_B1TXPRI1_SIZE 0x1 #define _B1CON_B1TXPRI1_LENGTH 0x1 #define _B1CON_B1TXPRI1_MASK 0x2 #define _B1CON_B1RTREN_POSN 0x2 #define _B1CON_B1RTREN_POSITION 0x2 #define _B1CON_B1RTREN_SIZE 0x1 #define _B1CON_B1RTREN_LENGTH 0x1 #define _B1CON_B1RTREN_MASK 0x4 #define _B1CON_B1TXREQ_POSN 0x3 #define _B1CON_B1TXREQ_POSITION 0x3 #define _B1CON_B1TXREQ_SIZE 0x1 #define _B1CON_B1TXREQ_LENGTH 0x1 #define _B1CON_B1TXREQ_MASK 0x8 #define _B1CON_B1TXERR_POSN 0x4 #define _B1CON_B1TXERR_POSITION 0x4 #define _B1CON_B1TXERR_SIZE 0x1 #define _B1CON_B1TXERR_LENGTH 0x1 #define _B1CON_B1TXERR_MASK 0x10 #define _B1CON_B1TXLARB_POSN 0x5 #define _B1CON_B1TXLARB_POSITION 0x5 #define _B1CON_B1TXLARB_SIZE 0x1 #define _B1CON_B1TXLARB_LENGTH 0x1 #define _B1CON_B1TXLARB_MASK 0x20 #define _B1CON_B1TXABT_POSN 0x6 #define _B1CON_B1TXABT_POSITION 0x6 #define _B1CON_B1TXABT_SIZE 0x1 #define _B1CON_B1TXABT_LENGTH 0x1 #define _B1CON_B1TXABT_MASK 0x40 #define _B1CON_B1TXB3IF_POSN 0x7 #define _B1CON_B1TXB3IF_POSITION 0x7 #define _B1CON_B1TXB3IF_SIZE 0x1 #define _B1CON_B1TXB3IF_LENGTH 0x1 #define _B1CON_B1TXB3IF_MASK 0x80 // Register: B1SIDH #define B1SIDH B1SIDH extern volatile unsigned char B1SIDH @ 0xE91; #ifndef _LIB_BUILD asm("B1SIDH equ 0E91h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B1SID3 :1; unsigned B1SID4 :1; unsigned B1SID5 :1; unsigned B1SID6 :1; unsigned B1SID7 :1; unsigned B1SID8 :1; unsigned B1SID9 :1; unsigned B1SID10 :1; }; } B1SIDHbits_t; extern volatile B1SIDHbits_t B1SIDHbits @ 0xE91; // bitfield macros #define _B1SIDH_SID_POSN 0x0 #define _B1SIDH_SID_POSITION 0x0 #define _B1SIDH_SID_SIZE 0x8 #define _B1SIDH_SID_LENGTH 0x8 #define _B1SIDH_SID_MASK 0xFF #define _B1SIDH_SID3_POSN 0x0 #define _B1SIDH_SID3_POSITION 0x0 #define _B1SIDH_SID3_SIZE 0x1 #define _B1SIDH_SID3_LENGTH 0x1 #define _B1SIDH_SID3_MASK 0x1 #define _B1SIDH_SID4_POSN 0x1 #define _B1SIDH_SID4_POSITION 0x1 #define _B1SIDH_SID4_SIZE 0x1 #define _B1SIDH_SID4_LENGTH 0x1 #define _B1SIDH_SID4_MASK 0x2 #define _B1SIDH_SID5_POSN 0x2 #define _B1SIDH_SID5_POSITION 0x2 #define _B1SIDH_SID5_SIZE 0x1 #define _B1SIDH_SID5_LENGTH 0x1 #define _B1SIDH_SID5_MASK 0x4 #define _B1SIDH_SID6_POSN 0x3 #define _B1SIDH_SID6_POSITION 0x3 #define _B1SIDH_SID6_SIZE 0x1 #define _B1SIDH_SID6_LENGTH 0x1 #define _B1SIDH_SID6_MASK 0x8 #define _B1SIDH_SID7_POSN 0x4 #define _B1SIDH_SID7_POSITION 0x4 #define _B1SIDH_SID7_SIZE 0x1 #define _B1SIDH_SID7_LENGTH 0x1 #define _B1SIDH_SID7_MASK 0x10 #define _B1SIDH_SID8_POSN 0x5 #define _B1SIDH_SID8_POSITION 0x5 #define _B1SIDH_SID8_SIZE 0x1 #define _B1SIDH_SID8_LENGTH 0x1 #define _B1SIDH_SID8_MASK 0x20 #define _B1SIDH_SID9_POSN 0x6 #define _B1SIDH_SID9_POSITION 0x6 #define _B1SIDH_SID9_SIZE 0x1 #define _B1SIDH_SID9_LENGTH 0x1 #define _B1SIDH_SID9_MASK 0x40 #define _B1SIDH_SID10_POSN 0x7 #define _B1SIDH_SID10_POSITION 0x7 #define _B1SIDH_SID10_SIZE 0x1 #define _B1SIDH_SID10_LENGTH 0x1 #define _B1SIDH_SID10_MASK 0x80 #define _B1SIDH_B1SID3_POSN 0x0 #define _B1SIDH_B1SID3_POSITION 0x0 #define _B1SIDH_B1SID3_SIZE 0x1 #define _B1SIDH_B1SID3_LENGTH 0x1 #define _B1SIDH_B1SID3_MASK 0x1 #define _B1SIDH_B1SID4_POSN 0x1 #define _B1SIDH_B1SID4_POSITION 0x1 #define _B1SIDH_B1SID4_SIZE 0x1 #define _B1SIDH_B1SID4_LENGTH 0x1 #define _B1SIDH_B1SID4_MASK 0x2 #define _B1SIDH_B1SID5_POSN 0x2 #define _B1SIDH_B1SID5_POSITION 0x2 #define _B1SIDH_B1SID5_SIZE 0x1 #define _B1SIDH_B1SID5_LENGTH 0x1 #define _B1SIDH_B1SID5_MASK 0x4 #define _B1SIDH_B1SID6_POSN 0x3 #define _B1SIDH_B1SID6_POSITION 0x3 #define _B1SIDH_B1SID6_SIZE 0x1 #define _B1SIDH_B1SID6_LENGTH 0x1 #define _B1SIDH_B1SID6_MASK 0x8 #define _B1SIDH_B1SID7_POSN 0x4 #define _B1SIDH_B1SID7_POSITION 0x4 #define _B1SIDH_B1SID7_SIZE 0x1 #define _B1SIDH_B1SID7_LENGTH 0x1 #define _B1SIDH_B1SID7_MASK 0x10 #define _B1SIDH_B1SID8_POSN 0x5 #define _B1SIDH_B1SID8_POSITION 0x5 #define _B1SIDH_B1SID8_SIZE 0x1 #define _B1SIDH_B1SID8_LENGTH 0x1 #define _B1SIDH_B1SID8_MASK 0x20 #define _B1SIDH_B1SID9_POSN 0x6 #define _B1SIDH_B1SID9_POSITION 0x6 #define _B1SIDH_B1SID9_SIZE 0x1 #define _B1SIDH_B1SID9_LENGTH 0x1 #define _B1SIDH_B1SID9_MASK 0x40 #define _B1SIDH_B1SID10_POSN 0x7 #define _B1SIDH_B1SID10_POSITION 0x7 #define _B1SIDH_B1SID10_SIZE 0x1 #define _B1SIDH_B1SID10_LENGTH 0x1 #define _B1SIDH_B1SID10_MASK 0x80 // Register: B1SIDL #define B1SIDL B1SIDL extern volatile unsigned char B1SIDL @ 0xE92; #ifndef _LIB_BUILD asm("B1SIDL equ 0E92h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B1EID16 :1; unsigned B1EID17 :1; unsigned :1; unsigned B1EXID :1; unsigned B1SRR :1; unsigned B1SID0 :1; unsigned B1SID1 :1; unsigned B1SID2 :1; }; } B1SIDLbits_t; extern volatile B1SIDLbits_t B1SIDLbits @ 0xE92; // bitfield macros #define _B1SIDL_EID_POSN 0x0 #define _B1SIDL_EID_POSITION 0x0 #define _B1SIDL_EID_SIZE 0x2 #define _B1SIDL_EID_LENGTH 0x2 #define _B1SIDL_EID_MASK 0x3 #define _B1SIDL_EXIDE_POSN 0x3 #define _B1SIDL_EXIDE_POSITION 0x3 #define _B1SIDL_EXIDE_SIZE 0x1 #define _B1SIDL_EXIDE_LENGTH 0x1 #define _B1SIDL_EXIDE_MASK 0x8 #define _B1SIDL_SRR_POSN 0x4 #define _B1SIDL_SRR_POSITION 0x4 #define _B1SIDL_SRR_SIZE 0x1 #define _B1SIDL_SRR_LENGTH 0x1 #define _B1SIDL_SRR_MASK 0x10 #define _B1SIDL_SID_POSN 0x5 #define _B1SIDL_SID_POSITION 0x5 #define _B1SIDL_SID_SIZE 0x3 #define _B1SIDL_SID_LENGTH 0x3 #define _B1SIDL_SID_MASK 0xE0 #define _B1SIDL_EID16_POSN 0x0 #define _B1SIDL_EID16_POSITION 0x0 #define _B1SIDL_EID16_SIZE 0x1 #define _B1SIDL_EID16_LENGTH 0x1 #define _B1SIDL_EID16_MASK 0x1 #define _B1SIDL_EID17_POSN 0x1 #define _B1SIDL_EID17_POSITION 0x1 #define _B1SIDL_EID17_SIZE 0x1 #define _B1SIDL_EID17_LENGTH 0x1 #define _B1SIDL_EID17_MASK 0x2 #define _B1SIDL_SID0_POSN 0x5 #define _B1SIDL_SID0_POSITION 0x5 #define _B1SIDL_SID0_SIZE 0x1 #define _B1SIDL_SID0_LENGTH 0x1 #define _B1SIDL_SID0_MASK 0x20 #define _B1SIDL_SID1_POSN 0x6 #define _B1SIDL_SID1_POSITION 0x6 #define _B1SIDL_SID1_SIZE 0x1 #define _B1SIDL_SID1_LENGTH 0x1 #define _B1SIDL_SID1_MASK 0x40 #define _B1SIDL_SID2_POSN 0x7 #define _B1SIDL_SID2_POSITION 0x7 #define _B1SIDL_SID2_SIZE 0x1 #define _B1SIDL_SID2_LENGTH 0x1 #define _B1SIDL_SID2_MASK 0x80 #define _B1SIDL_B1EID16_POSN 0x0 #define _B1SIDL_B1EID16_POSITION 0x0 #define _B1SIDL_B1EID16_SIZE 0x1 #define _B1SIDL_B1EID16_LENGTH 0x1 #define _B1SIDL_B1EID16_MASK 0x1 #define _B1SIDL_B1EID17_POSN 0x1 #define _B1SIDL_B1EID17_POSITION 0x1 #define _B1SIDL_B1EID17_SIZE 0x1 #define _B1SIDL_B1EID17_LENGTH 0x1 #define _B1SIDL_B1EID17_MASK 0x2 #define _B1SIDL_B1EXID_POSN 0x3 #define _B1SIDL_B1EXID_POSITION 0x3 #define _B1SIDL_B1EXID_SIZE 0x1 #define _B1SIDL_B1EXID_LENGTH 0x1 #define _B1SIDL_B1EXID_MASK 0x8 #define _B1SIDL_B1SRR_POSN 0x4 #define _B1SIDL_B1SRR_POSITION 0x4 #define _B1SIDL_B1SRR_SIZE 0x1 #define _B1SIDL_B1SRR_LENGTH 0x1 #define _B1SIDL_B1SRR_MASK 0x10 #define _B1SIDL_B1SID0_POSN 0x5 #define _B1SIDL_B1SID0_POSITION 0x5 #define _B1SIDL_B1SID0_SIZE 0x1 #define _B1SIDL_B1SID0_LENGTH 0x1 #define _B1SIDL_B1SID0_MASK 0x20 #define _B1SIDL_B1SID1_POSN 0x6 #define _B1SIDL_B1SID1_POSITION 0x6 #define _B1SIDL_B1SID1_SIZE 0x1 #define _B1SIDL_B1SID1_LENGTH 0x1 #define _B1SIDL_B1SID1_MASK 0x40 #define _B1SIDL_B1SID2_POSN 0x7 #define _B1SIDL_B1SID2_POSITION 0x7 #define _B1SIDL_B1SID2_SIZE 0x1 #define _B1SIDL_B1SID2_LENGTH 0x1 #define _B1SIDL_B1SID2_MASK 0x80 // Register: B1EIDH #define B1EIDH B1EIDH extern volatile unsigned char B1EIDH @ 0xE93; #ifndef _LIB_BUILD asm("B1EIDH equ 0E93h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B1EID8 :1; unsigned B1EID9 :1; unsigned B1EID10 :1; unsigned B1EID11 :1; unsigned B1EID12 :1; unsigned B1EID13 :1; unsigned B1EID14 :1; unsigned B1EID15 :1; }; } B1EIDHbits_t; extern volatile B1EIDHbits_t B1EIDHbits @ 0xE93; // bitfield macros #define _B1EIDH_EID_POSN 0x0 #define _B1EIDH_EID_POSITION 0x0 #define _B1EIDH_EID_SIZE 0x8 #define _B1EIDH_EID_LENGTH 0x8 #define _B1EIDH_EID_MASK 0xFF #define _B1EIDH_EID8_POSN 0x0 #define _B1EIDH_EID8_POSITION 0x0 #define _B1EIDH_EID8_SIZE 0x1 #define _B1EIDH_EID8_LENGTH 0x1 #define _B1EIDH_EID8_MASK 0x1 #define _B1EIDH_EID9_POSN 0x1 #define _B1EIDH_EID9_POSITION 0x1 #define _B1EIDH_EID9_SIZE 0x1 #define _B1EIDH_EID9_LENGTH 0x1 #define _B1EIDH_EID9_MASK 0x2 #define _B1EIDH_EID10_POSN 0x2 #define _B1EIDH_EID10_POSITION 0x2 #define _B1EIDH_EID10_SIZE 0x1 #define _B1EIDH_EID10_LENGTH 0x1 #define _B1EIDH_EID10_MASK 0x4 #define _B1EIDH_EID11_POSN 0x3 #define _B1EIDH_EID11_POSITION 0x3 #define _B1EIDH_EID11_SIZE 0x1 #define _B1EIDH_EID11_LENGTH 0x1 #define _B1EIDH_EID11_MASK 0x8 #define _B1EIDH_EID12_POSN 0x4 #define _B1EIDH_EID12_POSITION 0x4 #define _B1EIDH_EID12_SIZE 0x1 #define _B1EIDH_EID12_LENGTH 0x1 #define _B1EIDH_EID12_MASK 0x10 #define _B1EIDH_EID13_POSN 0x5 #define _B1EIDH_EID13_POSITION 0x5 #define _B1EIDH_EID13_SIZE 0x1 #define _B1EIDH_EID13_LENGTH 0x1 #define _B1EIDH_EID13_MASK 0x20 #define _B1EIDH_EID14_POSN 0x6 #define _B1EIDH_EID14_POSITION 0x6 #define _B1EIDH_EID14_SIZE 0x1 #define _B1EIDH_EID14_LENGTH 0x1 #define _B1EIDH_EID14_MASK 0x40 #define _B1EIDH_EID15_POSN 0x7 #define _B1EIDH_EID15_POSITION 0x7 #define _B1EIDH_EID15_SIZE 0x1 #define _B1EIDH_EID15_LENGTH 0x1 #define _B1EIDH_EID15_MASK 0x80 #define _B1EIDH_B1EID8_POSN 0x0 #define _B1EIDH_B1EID8_POSITION 0x0 #define _B1EIDH_B1EID8_SIZE 0x1 #define _B1EIDH_B1EID8_LENGTH 0x1 #define _B1EIDH_B1EID8_MASK 0x1 #define _B1EIDH_B1EID9_POSN 0x1 #define _B1EIDH_B1EID9_POSITION 0x1 #define _B1EIDH_B1EID9_SIZE 0x1 #define _B1EIDH_B1EID9_LENGTH 0x1 #define _B1EIDH_B1EID9_MASK 0x2 #define _B1EIDH_B1EID10_POSN 0x2 #define _B1EIDH_B1EID10_POSITION 0x2 #define _B1EIDH_B1EID10_SIZE 0x1 #define _B1EIDH_B1EID10_LENGTH 0x1 #define _B1EIDH_B1EID10_MASK 0x4 #define _B1EIDH_B1EID11_POSN 0x3 #define _B1EIDH_B1EID11_POSITION 0x3 #define _B1EIDH_B1EID11_SIZE 0x1 #define _B1EIDH_B1EID11_LENGTH 0x1 #define _B1EIDH_B1EID11_MASK 0x8 #define _B1EIDH_B1EID12_POSN 0x4 #define _B1EIDH_B1EID12_POSITION 0x4 #define _B1EIDH_B1EID12_SIZE 0x1 #define _B1EIDH_B1EID12_LENGTH 0x1 #define _B1EIDH_B1EID12_MASK 0x10 #define _B1EIDH_B1EID13_POSN 0x5 #define _B1EIDH_B1EID13_POSITION 0x5 #define _B1EIDH_B1EID13_SIZE 0x1 #define _B1EIDH_B1EID13_LENGTH 0x1 #define _B1EIDH_B1EID13_MASK 0x20 #define _B1EIDH_B1EID14_POSN 0x6 #define _B1EIDH_B1EID14_POSITION 0x6 #define _B1EIDH_B1EID14_SIZE 0x1 #define _B1EIDH_B1EID14_LENGTH 0x1 #define _B1EIDH_B1EID14_MASK 0x40 #define _B1EIDH_B1EID15_POSN 0x7 #define _B1EIDH_B1EID15_POSITION 0x7 #define _B1EIDH_B1EID15_SIZE 0x1 #define _B1EIDH_B1EID15_LENGTH 0x1 #define _B1EIDH_B1EID15_MASK 0x80 // Register: B1EIDL #define B1EIDL B1EIDL extern volatile unsigned char B1EIDL @ 0xE94; #ifndef _LIB_BUILD asm("B1EIDL equ 0E94h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B1EID0 :1; unsigned B1EID1 :1; unsigned B1EID2 :1; unsigned B1EID3 :1; unsigned B1EID4 :1; unsigned B1EID5 :1; unsigned B1EID6 :1; unsigned B1EID7 :1; }; } B1EIDLbits_t; extern volatile B1EIDLbits_t B1EIDLbits @ 0xE94; // bitfield macros #define _B1EIDL_EID_POSN 0x0 #define _B1EIDL_EID_POSITION 0x0 #define _B1EIDL_EID_SIZE 0x8 #define _B1EIDL_EID_LENGTH 0x8 #define _B1EIDL_EID_MASK 0xFF #define _B1EIDL_EID0_POSN 0x0 #define _B1EIDL_EID0_POSITION 0x0 #define _B1EIDL_EID0_SIZE 0x1 #define _B1EIDL_EID0_LENGTH 0x1 #define _B1EIDL_EID0_MASK 0x1 #define _B1EIDL_EID1_POSN 0x1 #define _B1EIDL_EID1_POSITION 0x1 #define _B1EIDL_EID1_SIZE 0x1 #define _B1EIDL_EID1_LENGTH 0x1 #define _B1EIDL_EID1_MASK 0x2 #define _B1EIDL_EID2_POSN 0x2 #define _B1EIDL_EID2_POSITION 0x2 #define _B1EIDL_EID2_SIZE 0x1 #define _B1EIDL_EID2_LENGTH 0x1 #define _B1EIDL_EID2_MASK 0x4 #define _B1EIDL_EID3_POSN 0x3 #define _B1EIDL_EID3_POSITION 0x3 #define _B1EIDL_EID3_SIZE 0x1 #define _B1EIDL_EID3_LENGTH 0x1 #define _B1EIDL_EID3_MASK 0x8 #define _B1EIDL_EID4_POSN 0x4 #define _B1EIDL_EID4_POSITION 0x4 #define _B1EIDL_EID4_SIZE 0x1 #define _B1EIDL_EID4_LENGTH 0x1 #define _B1EIDL_EID4_MASK 0x10 #define _B1EIDL_EID5_POSN 0x5 #define _B1EIDL_EID5_POSITION 0x5 #define _B1EIDL_EID5_SIZE 0x1 #define _B1EIDL_EID5_LENGTH 0x1 #define _B1EIDL_EID5_MASK 0x20 #define _B1EIDL_EID6_POSN 0x6 #define _B1EIDL_EID6_POSITION 0x6 #define _B1EIDL_EID6_SIZE 0x1 #define _B1EIDL_EID6_LENGTH 0x1 #define _B1EIDL_EID6_MASK 0x40 #define _B1EIDL_EID7_POSN 0x7 #define _B1EIDL_EID7_POSITION 0x7 #define _B1EIDL_EID7_SIZE 0x1 #define _B1EIDL_EID7_LENGTH 0x1 #define _B1EIDL_EID7_MASK 0x80 #define _B1EIDL_B1EID0_POSN 0x0 #define _B1EIDL_B1EID0_POSITION 0x0 #define _B1EIDL_B1EID0_SIZE 0x1 #define _B1EIDL_B1EID0_LENGTH 0x1 #define _B1EIDL_B1EID0_MASK 0x1 #define _B1EIDL_B1EID1_POSN 0x1 #define _B1EIDL_B1EID1_POSITION 0x1 #define _B1EIDL_B1EID1_SIZE 0x1 #define _B1EIDL_B1EID1_LENGTH 0x1 #define _B1EIDL_B1EID1_MASK 0x2 #define _B1EIDL_B1EID2_POSN 0x2 #define _B1EIDL_B1EID2_POSITION 0x2 #define _B1EIDL_B1EID2_SIZE 0x1 #define _B1EIDL_B1EID2_LENGTH 0x1 #define _B1EIDL_B1EID2_MASK 0x4 #define _B1EIDL_B1EID3_POSN 0x3 #define _B1EIDL_B1EID3_POSITION 0x3 #define _B1EIDL_B1EID3_SIZE 0x1 #define _B1EIDL_B1EID3_LENGTH 0x1 #define _B1EIDL_B1EID3_MASK 0x8 #define _B1EIDL_B1EID4_POSN 0x4 #define _B1EIDL_B1EID4_POSITION 0x4 #define _B1EIDL_B1EID4_SIZE 0x1 #define _B1EIDL_B1EID4_LENGTH 0x1 #define _B1EIDL_B1EID4_MASK 0x10 #define _B1EIDL_B1EID5_POSN 0x5 #define _B1EIDL_B1EID5_POSITION 0x5 #define _B1EIDL_B1EID5_SIZE 0x1 #define _B1EIDL_B1EID5_LENGTH 0x1 #define _B1EIDL_B1EID5_MASK 0x20 #define _B1EIDL_B1EID6_POSN 0x6 #define _B1EIDL_B1EID6_POSITION 0x6 #define _B1EIDL_B1EID6_SIZE 0x1 #define _B1EIDL_B1EID6_LENGTH 0x1 #define _B1EIDL_B1EID6_MASK 0x40 #define _B1EIDL_B1EID7_POSN 0x7 #define _B1EIDL_B1EID7_POSITION 0x7 #define _B1EIDL_B1EID7_SIZE 0x1 #define _B1EIDL_B1EID7_LENGTH 0x1 #define _B1EIDL_B1EID7_MASK 0x80 // Register: B1DLC #define B1DLC B1DLC extern volatile unsigned char B1DLC @ 0xE95; #ifndef _LIB_BUILD asm("B1DLC equ 0E95h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B1DLC0 :1; unsigned B1DLC1 :1; unsigned B1DLC2 :1; unsigned B1DLC3 :1; unsigned B1RB0 :1; unsigned B1RB1 :1; unsigned B1RXRTR :1; }; } B1DLCbits_t; extern volatile B1DLCbits_t B1DLCbits @ 0xE95; // bitfield macros #define _B1DLC_DLC_POSN 0x0 #define _B1DLC_DLC_POSITION 0x0 #define _B1DLC_DLC_SIZE 0x4 #define _B1DLC_DLC_LENGTH 0x4 #define _B1DLC_DLC_MASK 0xF #define _B1DLC_RB_POSN 0x4 #define _B1DLC_RB_POSITION 0x4 #define _B1DLC_RB_SIZE 0x2 #define _B1DLC_RB_LENGTH 0x2 #define _B1DLC_RB_MASK 0x30 #define _B1DLC_RXRTR_TXRTR_POSN 0x6 #define _B1DLC_RXRTR_TXRTR_POSITION 0x6 #define _B1DLC_RXRTR_TXRTR_SIZE 0x1 #define _B1DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B1DLC_RXRTR_TXRTR_MASK 0x40 #define _B1DLC_DLC0_POSN 0x0 #define _B1DLC_DLC0_POSITION 0x0 #define _B1DLC_DLC0_SIZE 0x1 #define _B1DLC_DLC0_LENGTH 0x1 #define _B1DLC_DLC0_MASK 0x1 #define _B1DLC_DLC1_POSN 0x1 #define _B1DLC_DLC1_POSITION 0x1 #define _B1DLC_DLC1_SIZE 0x1 #define _B1DLC_DLC1_LENGTH 0x1 #define _B1DLC_DLC1_MASK 0x2 #define _B1DLC_DLC2_POSN 0x2 #define _B1DLC_DLC2_POSITION 0x2 #define _B1DLC_DLC2_SIZE 0x1 #define _B1DLC_DLC2_LENGTH 0x1 #define _B1DLC_DLC2_MASK 0x4 #define _B1DLC_DLC3_POSN 0x3 #define _B1DLC_DLC3_POSITION 0x3 #define _B1DLC_DLC3_SIZE 0x1 #define _B1DLC_DLC3_LENGTH 0x1 #define _B1DLC_DLC3_MASK 0x8 #define _B1DLC_RB0_POSN 0x4 #define _B1DLC_RB0_POSITION 0x4 #define _B1DLC_RB0_SIZE 0x1 #define _B1DLC_RB0_LENGTH 0x1 #define _B1DLC_RB0_MASK 0x10 #define _B1DLC_RB1_POSN 0x5 #define _B1DLC_RB1_POSITION 0x5 #define _B1DLC_RB1_SIZE 0x1 #define _B1DLC_RB1_LENGTH 0x1 #define _B1DLC_RB1_MASK 0x20 #define _B1DLC_RXRTR_POSN 0x6 #define _B1DLC_RXRTR_POSITION 0x6 #define _B1DLC_RXRTR_SIZE 0x1 #define _B1DLC_RXRTR_LENGTH 0x1 #define _B1DLC_RXRTR_MASK 0x40 #define _B1DLC_TXRTR_POSN 0x6 #define _B1DLC_TXRTR_POSITION 0x6 #define _B1DLC_TXRTR_SIZE 0x1 #define _B1DLC_TXRTR_LENGTH 0x1 #define _B1DLC_TXRTR_MASK 0x40 #define _B1DLC_B1DLC0_POSN 0x0 #define _B1DLC_B1DLC0_POSITION 0x0 #define _B1DLC_B1DLC0_SIZE 0x1 #define _B1DLC_B1DLC0_LENGTH 0x1 #define _B1DLC_B1DLC0_MASK 0x1 #define _B1DLC_B1DLC1_POSN 0x1 #define _B1DLC_B1DLC1_POSITION 0x1 #define _B1DLC_B1DLC1_SIZE 0x1 #define _B1DLC_B1DLC1_LENGTH 0x1 #define _B1DLC_B1DLC1_MASK 0x2 #define _B1DLC_B1DLC2_POSN 0x2 #define _B1DLC_B1DLC2_POSITION 0x2 #define _B1DLC_B1DLC2_SIZE 0x1 #define _B1DLC_B1DLC2_LENGTH 0x1 #define _B1DLC_B1DLC2_MASK 0x4 #define _B1DLC_B1DLC3_POSN 0x3 #define _B1DLC_B1DLC3_POSITION 0x3 #define _B1DLC_B1DLC3_SIZE 0x1 #define _B1DLC_B1DLC3_LENGTH 0x1 #define _B1DLC_B1DLC3_MASK 0x8 #define _B1DLC_B1RB0_POSN 0x4 #define _B1DLC_B1RB0_POSITION 0x4 #define _B1DLC_B1RB0_SIZE 0x1 #define _B1DLC_B1RB0_LENGTH 0x1 #define _B1DLC_B1RB0_MASK 0x10 #define _B1DLC_B1RB1_POSN 0x5 #define _B1DLC_B1RB1_POSITION 0x5 #define _B1DLC_B1RB1_SIZE 0x1 #define _B1DLC_B1RB1_LENGTH 0x1 #define _B1DLC_B1RB1_MASK 0x20 #define _B1DLC_B1RXRTR_POSN 0x6 #define _B1DLC_B1RXRTR_POSITION 0x6 #define _B1DLC_B1RXRTR_SIZE 0x1 #define _B1DLC_B1RXRTR_LENGTH 0x1 #define _B1DLC_B1RXRTR_MASK 0x40 // Register: B1D0 #define B1D0 B1D0 extern volatile unsigned char B1D0 @ 0xE96; #ifndef _LIB_BUILD asm("B1D0 equ 0E96h"); #endif // bitfield definitions typedef union { struct { unsigned B1D0 :8; }; struct { unsigned B1D00 :1; unsigned B1D01 :1; unsigned B1D02 :1; unsigned B1D03 :1; unsigned B1D04 :1; unsigned B1D05 :1; unsigned B1D06 :1; unsigned B1D07 :1; }; } B1D0bits_t; extern volatile B1D0bits_t B1D0bits @ 0xE96; // bitfield macros #define _B1D0_B1D0_POSN 0x0 #define _B1D0_B1D0_POSITION 0x0 #define _B1D0_B1D0_SIZE 0x8 #define _B1D0_B1D0_LENGTH 0x8 #define _B1D0_B1D0_MASK 0xFF #define _B1D0_B1D00_POSN 0x0 #define _B1D0_B1D00_POSITION 0x0 #define _B1D0_B1D00_SIZE 0x1 #define _B1D0_B1D00_LENGTH 0x1 #define _B1D0_B1D00_MASK 0x1 #define _B1D0_B1D01_POSN 0x1 #define _B1D0_B1D01_POSITION 0x1 #define _B1D0_B1D01_SIZE 0x1 #define _B1D0_B1D01_LENGTH 0x1 #define _B1D0_B1D01_MASK 0x2 #define _B1D0_B1D02_POSN 0x2 #define _B1D0_B1D02_POSITION 0x2 #define _B1D0_B1D02_SIZE 0x1 #define _B1D0_B1D02_LENGTH 0x1 #define _B1D0_B1D02_MASK 0x4 #define _B1D0_B1D03_POSN 0x3 #define _B1D0_B1D03_POSITION 0x3 #define _B1D0_B1D03_SIZE 0x1 #define _B1D0_B1D03_LENGTH 0x1 #define _B1D0_B1D03_MASK 0x8 #define _B1D0_B1D04_POSN 0x4 #define _B1D0_B1D04_POSITION 0x4 #define _B1D0_B1D04_SIZE 0x1 #define _B1D0_B1D04_LENGTH 0x1 #define _B1D0_B1D04_MASK 0x10 #define _B1D0_B1D05_POSN 0x5 #define _B1D0_B1D05_POSITION 0x5 #define _B1D0_B1D05_SIZE 0x1 #define _B1D0_B1D05_LENGTH 0x1 #define _B1D0_B1D05_MASK 0x20 #define _B1D0_B1D06_POSN 0x6 #define _B1D0_B1D06_POSITION 0x6 #define _B1D0_B1D06_SIZE 0x1 #define _B1D0_B1D06_LENGTH 0x1 #define _B1D0_B1D06_MASK 0x40 #define _B1D0_B1D07_POSN 0x7 #define _B1D0_B1D07_POSITION 0x7 #define _B1D0_B1D07_SIZE 0x1 #define _B1D0_B1D07_LENGTH 0x1 #define _B1D0_B1D07_MASK 0x80 // Register: B1D1 #define B1D1 B1D1 extern volatile unsigned char B1D1 @ 0xE97; #ifndef _LIB_BUILD asm("B1D1 equ 0E97h"); #endif // bitfield definitions typedef union { struct { unsigned B1D1 :8; }; struct { unsigned B1D10 :1; unsigned B1D11 :1; unsigned B1D12 :1; unsigned B1D13 :1; unsigned B1D14 :1; unsigned B1D15 :1; unsigned B1D16 :1; unsigned B1D17 :1; }; } B1D1bits_t; extern volatile B1D1bits_t B1D1bits @ 0xE97; // bitfield macros #define _B1D1_B1D1_POSN 0x0 #define _B1D1_B1D1_POSITION 0x0 #define _B1D1_B1D1_SIZE 0x8 #define _B1D1_B1D1_LENGTH 0x8 #define _B1D1_B1D1_MASK 0xFF #define _B1D1_B1D10_POSN 0x0 #define _B1D1_B1D10_POSITION 0x0 #define _B1D1_B1D10_SIZE 0x1 #define _B1D1_B1D10_LENGTH 0x1 #define _B1D1_B1D10_MASK 0x1 #define _B1D1_B1D11_POSN 0x1 #define _B1D1_B1D11_POSITION 0x1 #define _B1D1_B1D11_SIZE 0x1 #define _B1D1_B1D11_LENGTH 0x1 #define _B1D1_B1D11_MASK 0x2 #define _B1D1_B1D12_POSN 0x2 #define _B1D1_B1D12_POSITION 0x2 #define _B1D1_B1D12_SIZE 0x1 #define _B1D1_B1D12_LENGTH 0x1 #define _B1D1_B1D12_MASK 0x4 #define _B1D1_B1D13_POSN 0x3 #define _B1D1_B1D13_POSITION 0x3 #define _B1D1_B1D13_SIZE 0x1 #define _B1D1_B1D13_LENGTH 0x1 #define _B1D1_B1D13_MASK 0x8 #define _B1D1_B1D14_POSN 0x4 #define _B1D1_B1D14_POSITION 0x4 #define _B1D1_B1D14_SIZE 0x1 #define _B1D1_B1D14_LENGTH 0x1 #define _B1D1_B1D14_MASK 0x10 #define _B1D1_B1D15_POSN 0x5 #define _B1D1_B1D15_POSITION 0x5 #define _B1D1_B1D15_SIZE 0x1 #define _B1D1_B1D15_LENGTH 0x1 #define _B1D1_B1D15_MASK 0x20 #define _B1D1_B1D16_POSN 0x6 #define _B1D1_B1D16_POSITION 0x6 #define _B1D1_B1D16_SIZE 0x1 #define _B1D1_B1D16_LENGTH 0x1 #define _B1D1_B1D16_MASK 0x40 #define _B1D1_B1D17_POSN 0x7 #define _B1D1_B1D17_POSITION 0x7 #define _B1D1_B1D17_SIZE 0x1 #define _B1D1_B1D17_LENGTH 0x1 #define _B1D1_B1D17_MASK 0x80 // Register: B1D2 #define B1D2 B1D2 extern volatile unsigned char B1D2 @ 0xE98; #ifndef _LIB_BUILD asm("B1D2 equ 0E98h"); #endif // bitfield definitions typedef union { struct { unsigned B1D2 :8; }; struct { unsigned B1D20 :1; unsigned B1D21 :1; unsigned B1D22 :1; unsigned B1D23 :1; unsigned B1D24 :1; unsigned B1D25 :1; unsigned B1D26 :1; unsigned B1D27 :1; }; } B1D2bits_t; extern volatile B1D2bits_t B1D2bits @ 0xE98; // bitfield macros #define _B1D2_B1D2_POSN 0x0 #define _B1D2_B1D2_POSITION 0x0 #define _B1D2_B1D2_SIZE 0x8 #define _B1D2_B1D2_LENGTH 0x8 #define _B1D2_B1D2_MASK 0xFF #define _B1D2_B1D20_POSN 0x0 #define _B1D2_B1D20_POSITION 0x0 #define _B1D2_B1D20_SIZE 0x1 #define _B1D2_B1D20_LENGTH 0x1 #define _B1D2_B1D20_MASK 0x1 #define _B1D2_B1D21_POSN 0x1 #define _B1D2_B1D21_POSITION 0x1 #define _B1D2_B1D21_SIZE 0x1 #define _B1D2_B1D21_LENGTH 0x1 #define _B1D2_B1D21_MASK 0x2 #define _B1D2_B1D22_POSN 0x2 #define _B1D2_B1D22_POSITION 0x2 #define _B1D2_B1D22_SIZE 0x1 #define _B1D2_B1D22_LENGTH 0x1 #define _B1D2_B1D22_MASK 0x4 #define _B1D2_B1D23_POSN 0x3 #define _B1D2_B1D23_POSITION 0x3 #define _B1D2_B1D23_SIZE 0x1 #define _B1D2_B1D23_LENGTH 0x1 #define _B1D2_B1D23_MASK 0x8 #define _B1D2_B1D24_POSN 0x4 #define _B1D2_B1D24_POSITION 0x4 #define _B1D2_B1D24_SIZE 0x1 #define _B1D2_B1D24_LENGTH 0x1 #define _B1D2_B1D24_MASK 0x10 #define _B1D2_B1D25_POSN 0x5 #define _B1D2_B1D25_POSITION 0x5 #define _B1D2_B1D25_SIZE 0x1 #define _B1D2_B1D25_LENGTH 0x1 #define _B1D2_B1D25_MASK 0x20 #define _B1D2_B1D26_POSN 0x6 #define _B1D2_B1D26_POSITION 0x6 #define _B1D2_B1D26_SIZE 0x1 #define _B1D2_B1D26_LENGTH 0x1 #define _B1D2_B1D26_MASK 0x40 #define _B1D2_B1D27_POSN 0x7 #define _B1D2_B1D27_POSITION 0x7 #define _B1D2_B1D27_SIZE 0x1 #define _B1D2_B1D27_LENGTH 0x1 #define _B1D2_B1D27_MASK 0x80 // Register: B1D3 #define B1D3 B1D3 extern volatile unsigned char B1D3 @ 0xE99; #ifndef _LIB_BUILD asm("B1D3 equ 0E99h"); #endif // bitfield definitions typedef union { struct { unsigned B1D3 :8; }; struct { unsigned B1D30 :1; unsigned B1D31 :1; unsigned B1D32 :1; unsigned B1D33 :1; unsigned B1D34 :1; unsigned B1D35 :1; unsigned B1D36 :1; unsigned B1D37 :1; }; } B1D3bits_t; extern volatile B1D3bits_t B1D3bits @ 0xE99; // bitfield macros #define _B1D3_B1D3_POSN 0x0 #define _B1D3_B1D3_POSITION 0x0 #define _B1D3_B1D3_SIZE 0x8 #define _B1D3_B1D3_LENGTH 0x8 #define _B1D3_B1D3_MASK 0xFF #define _B1D3_B1D30_POSN 0x0 #define _B1D3_B1D30_POSITION 0x0 #define _B1D3_B1D30_SIZE 0x1 #define _B1D3_B1D30_LENGTH 0x1 #define _B1D3_B1D30_MASK 0x1 #define _B1D3_B1D31_POSN 0x1 #define _B1D3_B1D31_POSITION 0x1 #define _B1D3_B1D31_SIZE 0x1 #define _B1D3_B1D31_LENGTH 0x1 #define _B1D3_B1D31_MASK 0x2 #define _B1D3_B1D32_POSN 0x2 #define _B1D3_B1D32_POSITION 0x2 #define _B1D3_B1D32_SIZE 0x1 #define _B1D3_B1D32_LENGTH 0x1 #define _B1D3_B1D32_MASK 0x4 #define _B1D3_B1D33_POSN 0x3 #define _B1D3_B1D33_POSITION 0x3 #define _B1D3_B1D33_SIZE 0x1 #define _B1D3_B1D33_LENGTH 0x1 #define _B1D3_B1D33_MASK 0x8 #define _B1D3_B1D34_POSN 0x4 #define _B1D3_B1D34_POSITION 0x4 #define _B1D3_B1D34_SIZE 0x1 #define _B1D3_B1D34_LENGTH 0x1 #define _B1D3_B1D34_MASK 0x10 #define _B1D3_B1D35_POSN 0x5 #define _B1D3_B1D35_POSITION 0x5 #define _B1D3_B1D35_SIZE 0x1 #define _B1D3_B1D35_LENGTH 0x1 #define _B1D3_B1D35_MASK 0x20 #define _B1D3_B1D36_POSN 0x6 #define _B1D3_B1D36_POSITION 0x6 #define _B1D3_B1D36_SIZE 0x1 #define _B1D3_B1D36_LENGTH 0x1 #define _B1D3_B1D36_MASK 0x40 #define _B1D3_B1D37_POSN 0x7 #define _B1D3_B1D37_POSITION 0x7 #define _B1D3_B1D37_SIZE 0x1 #define _B1D3_B1D37_LENGTH 0x1 #define _B1D3_B1D37_MASK 0x80 // Register: B1D4 #define B1D4 B1D4 extern volatile unsigned char B1D4 @ 0xE9A; #ifndef _LIB_BUILD asm("B1D4 equ 0E9Ah"); #endif // bitfield definitions typedef union { struct { unsigned B1D4 :8; }; struct { unsigned B1D40 :1; unsigned B1D41 :1; unsigned B1D42 :1; unsigned B1D43 :1; unsigned B1D44 :1; unsigned B1D45 :1; unsigned B1D46 :1; unsigned B1D47 :1; }; } B1D4bits_t; extern volatile B1D4bits_t B1D4bits @ 0xE9A; // bitfield macros #define _B1D4_B1D4_POSN 0x0 #define _B1D4_B1D4_POSITION 0x0 #define _B1D4_B1D4_SIZE 0x8 #define _B1D4_B1D4_LENGTH 0x8 #define _B1D4_B1D4_MASK 0xFF #define _B1D4_B1D40_POSN 0x0 #define _B1D4_B1D40_POSITION 0x0 #define _B1D4_B1D40_SIZE 0x1 #define _B1D4_B1D40_LENGTH 0x1 #define _B1D4_B1D40_MASK 0x1 #define _B1D4_B1D41_POSN 0x1 #define _B1D4_B1D41_POSITION 0x1 #define _B1D4_B1D41_SIZE 0x1 #define _B1D4_B1D41_LENGTH 0x1 #define _B1D4_B1D41_MASK 0x2 #define _B1D4_B1D42_POSN 0x2 #define _B1D4_B1D42_POSITION 0x2 #define _B1D4_B1D42_SIZE 0x1 #define _B1D4_B1D42_LENGTH 0x1 #define _B1D4_B1D42_MASK 0x4 #define _B1D4_B1D43_POSN 0x3 #define _B1D4_B1D43_POSITION 0x3 #define _B1D4_B1D43_SIZE 0x1 #define _B1D4_B1D43_LENGTH 0x1 #define _B1D4_B1D43_MASK 0x8 #define _B1D4_B1D44_POSN 0x4 #define _B1D4_B1D44_POSITION 0x4 #define _B1D4_B1D44_SIZE 0x1 #define _B1D4_B1D44_LENGTH 0x1 #define _B1D4_B1D44_MASK 0x10 #define _B1D4_B1D45_POSN 0x5 #define _B1D4_B1D45_POSITION 0x5 #define _B1D4_B1D45_SIZE 0x1 #define _B1D4_B1D45_LENGTH 0x1 #define _B1D4_B1D45_MASK 0x20 #define _B1D4_B1D46_POSN 0x6 #define _B1D4_B1D46_POSITION 0x6 #define _B1D4_B1D46_SIZE 0x1 #define _B1D4_B1D46_LENGTH 0x1 #define _B1D4_B1D46_MASK 0x40 #define _B1D4_B1D47_POSN 0x7 #define _B1D4_B1D47_POSITION 0x7 #define _B1D4_B1D47_SIZE 0x1 #define _B1D4_B1D47_LENGTH 0x1 #define _B1D4_B1D47_MASK 0x80 // Register: B1D5 #define B1D5 B1D5 extern volatile unsigned char B1D5 @ 0xE9B; #ifndef _LIB_BUILD asm("B1D5 equ 0E9Bh"); #endif // bitfield definitions typedef union { struct { unsigned B1D5 :8; }; struct { unsigned B1D50 :1; unsigned B1D51 :1; unsigned B1D52 :1; unsigned B1D53 :1; unsigned B1D54 :1; unsigned B1D55 :1; unsigned B1D56 :1; unsigned B1D57 :1; }; } B1D5bits_t; extern volatile B1D5bits_t B1D5bits @ 0xE9B; // bitfield macros #define _B1D5_B1D5_POSN 0x0 #define _B1D5_B1D5_POSITION 0x0 #define _B1D5_B1D5_SIZE 0x8 #define _B1D5_B1D5_LENGTH 0x8 #define _B1D5_B1D5_MASK 0xFF #define _B1D5_B1D50_POSN 0x0 #define _B1D5_B1D50_POSITION 0x0 #define _B1D5_B1D50_SIZE 0x1 #define _B1D5_B1D50_LENGTH 0x1 #define _B1D5_B1D50_MASK 0x1 #define _B1D5_B1D51_POSN 0x1 #define _B1D5_B1D51_POSITION 0x1 #define _B1D5_B1D51_SIZE 0x1 #define _B1D5_B1D51_LENGTH 0x1 #define _B1D5_B1D51_MASK 0x2 #define _B1D5_B1D52_POSN 0x2 #define _B1D5_B1D52_POSITION 0x2 #define _B1D5_B1D52_SIZE 0x1 #define _B1D5_B1D52_LENGTH 0x1 #define _B1D5_B1D52_MASK 0x4 #define _B1D5_B1D53_POSN 0x3 #define _B1D5_B1D53_POSITION 0x3 #define _B1D5_B1D53_SIZE 0x1 #define _B1D5_B1D53_LENGTH 0x1 #define _B1D5_B1D53_MASK 0x8 #define _B1D5_B1D54_POSN 0x4 #define _B1D5_B1D54_POSITION 0x4 #define _B1D5_B1D54_SIZE 0x1 #define _B1D5_B1D54_LENGTH 0x1 #define _B1D5_B1D54_MASK 0x10 #define _B1D5_B1D55_POSN 0x5 #define _B1D5_B1D55_POSITION 0x5 #define _B1D5_B1D55_SIZE 0x1 #define _B1D5_B1D55_LENGTH 0x1 #define _B1D5_B1D55_MASK 0x20 #define _B1D5_B1D56_POSN 0x6 #define _B1D5_B1D56_POSITION 0x6 #define _B1D5_B1D56_SIZE 0x1 #define _B1D5_B1D56_LENGTH 0x1 #define _B1D5_B1D56_MASK 0x40 #define _B1D5_B1D57_POSN 0x7 #define _B1D5_B1D57_POSITION 0x7 #define _B1D5_B1D57_SIZE 0x1 #define _B1D5_B1D57_LENGTH 0x1 #define _B1D5_B1D57_MASK 0x80 // Register: B1D6 #define B1D6 B1D6 extern volatile unsigned char B1D6 @ 0xE9C; #ifndef _LIB_BUILD asm("B1D6 equ 0E9Ch"); #endif // bitfield definitions typedef union { struct { unsigned B1D6 :8; }; struct { unsigned B1D60 :1; unsigned B1D61 :1; unsigned B1D62 :1; unsigned B1D63 :1; unsigned B1D64 :1; unsigned B1D65 :1; unsigned B1D66 :1; unsigned B1D67 :1; }; } B1D6bits_t; extern volatile B1D6bits_t B1D6bits @ 0xE9C; // bitfield macros #define _B1D6_B1D6_POSN 0x0 #define _B1D6_B1D6_POSITION 0x0 #define _B1D6_B1D6_SIZE 0x8 #define _B1D6_B1D6_LENGTH 0x8 #define _B1D6_B1D6_MASK 0xFF #define _B1D6_B1D60_POSN 0x0 #define _B1D6_B1D60_POSITION 0x0 #define _B1D6_B1D60_SIZE 0x1 #define _B1D6_B1D60_LENGTH 0x1 #define _B1D6_B1D60_MASK 0x1 #define _B1D6_B1D61_POSN 0x1 #define _B1D6_B1D61_POSITION 0x1 #define _B1D6_B1D61_SIZE 0x1 #define _B1D6_B1D61_LENGTH 0x1 #define _B1D6_B1D61_MASK 0x2 #define _B1D6_B1D62_POSN 0x2 #define _B1D6_B1D62_POSITION 0x2 #define _B1D6_B1D62_SIZE 0x1 #define _B1D6_B1D62_LENGTH 0x1 #define _B1D6_B1D62_MASK 0x4 #define _B1D6_B1D63_POSN 0x3 #define _B1D6_B1D63_POSITION 0x3 #define _B1D6_B1D63_SIZE 0x1 #define _B1D6_B1D63_LENGTH 0x1 #define _B1D6_B1D63_MASK 0x8 #define _B1D6_B1D64_POSN 0x4 #define _B1D6_B1D64_POSITION 0x4 #define _B1D6_B1D64_SIZE 0x1 #define _B1D6_B1D64_LENGTH 0x1 #define _B1D6_B1D64_MASK 0x10 #define _B1D6_B1D65_POSN 0x5 #define _B1D6_B1D65_POSITION 0x5 #define _B1D6_B1D65_SIZE 0x1 #define _B1D6_B1D65_LENGTH 0x1 #define _B1D6_B1D65_MASK 0x20 #define _B1D6_B1D66_POSN 0x6 #define _B1D6_B1D66_POSITION 0x6 #define _B1D6_B1D66_SIZE 0x1 #define _B1D6_B1D66_LENGTH 0x1 #define _B1D6_B1D66_MASK 0x40 #define _B1D6_B1D67_POSN 0x7 #define _B1D6_B1D67_POSITION 0x7 #define _B1D6_B1D67_SIZE 0x1 #define _B1D6_B1D67_LENGTH 0x1 #define _B1D6_B1D67_MASK 0x80 // Register: B1D7 #define B1D7 B1D7 extern volatile unsigned char B1D7 @ 0xE9D; #ifndef _LIB_BUILD asm("B1D7 equ 0E9Dh"); #endif // bitfield definitions typedef union { struct { unsigned B1D7 :8; }; struct { unsigned B1D70 :1; unsigned B1D71 :1; unsigned B1D72 :1; unsigned B1D73 :1; unsigned B1D74 :1; unsigned B1D75 :1; unsigned B1D76 :1; unsigned B1D77 :1; }; } B1D7bits_t; extern volatile B1D7bits_t B1D7bits @ 0xE9D; // bitfield macros #define _B1D7_B1D7_POSN 0x0 #define _B1D7_B1D7_POSITION 0x0 #define _B1D7_B1D7_SIZE 0x8 #define _B1D7_B1D7_LENGTH 0x8 #define _B1D7_B1D7_MASK 0xFF #define _B1D7_B1D70_POSN 0x0 #define _B1D7_B1D70_POSITION 0x0 #define _B1D7_B1D70_SIZE 0x1 #define _B1D7_B1D70_LENGTH 0x1 #define _B1D7_B1D70_MASK 0x1 #define _B1D7_B1D71_POSN 0x1 #define _B1D7_B1D71_POSITION 0x1 #define _B1D7_B1D71_SIZE 0x1 #define _B1D7_B1D71_LENGTH 0x1 #define _B1D7_B1D71_MASK 0x2 #define _B1D7_B1D72_POSN 0x2 #define _B1D7_B1D72_POSITION 0x2 #define _B1D7_B1D72_SIZE 0x1 #define _B1D7_B1D72_LENGTH 0x1 #define _B1D7_B1D72_MASK 0x4 #define _B1D7_B1D73_POSN 0x3 #define _B1D7_B1D73_POSITION 0x3 #define _B1D7_B1D73_SIZE 0x1 #define _B1D7_B1D73_LENGTH 0x1 #define _B1D7_B1D73_MASK 0x8 #define _B1D7_B1D74_POSN 0x4 #define _B1D7_B1D74_POSITION 0x4 #define _B1D7_B1D74_SIZE 0x1 #define _B1D7_B1D74_LENGTH 0x1 #define _B1D7_B1D74_MASK 0x10 #define _B1D7_B1D75_POSN 0x5 #define _B1D7_B1D75_POSITION 0x5 #define _B1D7_B1D75_SIZE 0x1 #define _B1D7_B1D75_LENGTH 0x1 #define _B1D7_B1D75_MASK 0x20 #define _B1D7_B1D76_POSN 0x6 #define _B1D7_B1D76_POSITION 0x6 #define _B1D7_B1D76_SIZE 0x1 #define _B1D7_B1D76_LENGTH 0x1 #define _B1D7_B1D76_MASK 0x40 #define _B1D7_B1D77_POSN 0x7 #define _B1D7_B1D77_POSITION 0x7 #define _B1D7_B1D77_SIZE 0x1 #define _B1D7_B1D77_LENGTH 0x1 #define _B1D7_B1D77_MASK 0x80 // Register: CANSTAT_RO8 #define CANSTAT_RO8 CANSTAT_RO8 extern volatile unsigned char CANSTAT_RO8 @ 0xE9E; #ifndef _LIB_BUILD asm("CANSTAT_RO8 equ 0E9Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO8bits_t; extern volatile CANSTAT_RO8bits_t CANSTAT_RO8bits @ 0xE9E; // bitfield macros #define _CANSTAT_RO8_EICODE0_POSN 0x0 #define _CANSTAT_RO8_EICODE0_POSITION 0x0 #define _CANSTAT_RO8_EICODE0_SIZE 0x1 #define _CANSTAT_RO8_EICODE0_LENGTH 0x1 #define _CANSTAT_RO8_EICODE0_MASK 0x1 #define _CANSTAT_RO8_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO8_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO8_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO8_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO8_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO8_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO8_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO8_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO8_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO8_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO8_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO8_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO8_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO8_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO8_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO8_EICODE4_POSN 0x4 #define _CANSTAT_RO8_EICODE4_POSITION 0x4 #define _CANSTAT_RO8_EICODE4_SIZE 0x1 #define _CANSTAT_RO8_EICODE4_LENGTH 0x1 #define _CANSTAT_RO8_EICODE4_MASK 0x10 #define _CANSTAT_RO8_OPMODE_POSN 0x5 #define _CANSTAT_RO8_OPMODE_POSITION 0x5 #define _CANSTAT_RO8_OPMODE_SIZE 0x3 #define _CANSTAT_RO8_OPMODE_LENGTH 0x3 #define _CANSTAT_RO8_OPMODE_MASK 0xE0 #define _CANSTAT_RO8_EICODE1_POSN 0x1 #define _CANSTAT_RO8_EICODE1_POSITION 0x1 #define _CANSTAT_RO8_EICODE1_SIZE 0x1 #define _CANSTAT_RO8_EICODE1_LENGTH 0x1 #define _CANSTAT_RO8_EICODE1_MASK 0x2 #define _CANSTAT_RO8_EICODE2_POSN 0x2 #define _CANSTAT_RO8_EICODE2_POSITION 0x2 #define _CANSTAT_RO8_EICODE2_SIZE 0x1 #define _CANSTAT_RO8_EICODE2_LENGTH 0x1 #define _CANSTAT_RO8_EICODE2_MASK 0x4 #define _CANSTAT_RO8_EICODE3_POSN 0x3 #define _CANSTAT_RO8_EICODE3_POSITION 0x3 #define _CANSTAT_RO8_EICODE3_SIZE 0x1 #define _CANSTAT_RO8_EICODE3_LENGTH 0x1 #define _CANSTAT_RO8_EICODE3_MASK 0x8 #define _CANSTAT_RO8_OPMODE0_POSN 0x5 #define _CANSTAT_RO8_OPMODE0_POSITION 0x5 #define _CANSTAT_RO8_OPMODE0_SIZE 0x1 #define _CANSTAT_RO8_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO8_OPMODE0_MASK 0x20 #define _CANSTAT_RO8_OPMODE1_POSN 0x6 #define _CANSTAT_RO8_OPMODE1_POSITION 0x6 #define _CANSTAT_RO8_OPMODE1_SIZE 0x1 #define _CANSTAT_RO8_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO8_OPMODE1_MASK 0x40 #define _CANSTAT_RO8_OPMODE2_POSN 0x7 #define _CANSTAT_RO8_OPMODE2_POSITION 0x7 #define _CANSTAT_RO8_OPMODE2_SIZE 0x1 #define _CANSTAT_RO8_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO8_OPMODE2_MASK 0x80 #define _CANSTAT_RO8_ICODE0_POSN 0x1 #define _CANSTAT_RO8_ICODE0_POSITION 0x1 #define _CANSTAT_RO8_ICODE0_SIZE 0x1 #define _CANSTAT_RO8_ICODE0_LENGTH 0x1 #define _CANSTAT_RO8_ICODE0_MASK 0x2 #define _CANSTAT_RO8_ICODE1_POSN 0x2 #define _CANSTAT_RO8_ICODE1_POSITION 0x2 #define _CANSTAT_RO8_ICODE1_SIZE 0x1 #define _CANSTAT_RO8_ICODE1_LENGTH 0x1 #define _CANSTAT_RO8_ICODE1_MASK 0x4 #define _CANSTAT_RO8_ICODE2_POSN 0x3 #define _CANSTAT_RO8_ICODE2_POSITION 0x3 #define _CANSTAT_RO8_ICODE2_SIZE 0x1 #define _CANSTAT_RO8_ICODE2_LENGTH 0x1 #define _CANSTAT_RO8_ICODE2_MASK 0x8 // Register: CANCON_RO8 #define CANCON_RO8 CANCON_RO8 extern volatile unsigned char CANCON_RO8 @ 0xE9F; #ifndef _LIB_BUILD asm("CANCON_RO8 equ 0E9Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO8bits_t; extern volatile CANCON_RO8bits_t CANCON_RO8bits @ 0xE9F; // bitfield macros #define _CANCON_RO8_FP0_POSN 0x0 #define _CANCON_RO8_FP0_POSITION 0x0 #define _CANCON_RO8_FP0_SIZE 0x1 #define _CANCON_RO8_FP0_LENGTH 0x1 #define _CANCON_RO8_FP0_MASK 0x1 #define _CANCON_RO8_WIN0_FP1_POSN 0x1 #define _CANCON_RO8_WIN0_FP1_POSITION 0x1 #define _CANCON_RO8_WIN0_FP1_SIZE 0x1 #define _CANCON_RO8_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO8_WIN0_FP1_MASK 0x2 #define _CANCON_RO8_WIN1_FP2_POSN 0x2 #define _CANCON_RO8_WIN1_FP2_POSITION 0x2 #define _CANCON_RO8_WIN1_FP2_SIZE 0x1 #define _CANCON_RO8_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO8_WIN1_FP2_MASK 0x4 #define _CANCON_RO8_WIN2_FP3_POSN 0x3 #define _CANCON_RO8_WIN2_FP3_POSITION 0x3 #define _CANCON_RO8_WIN2_FP3_SIZE 0x1 #define _CANCON_RO8_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO8_WIN2_FP3_MASK 0x8 #define _CANCON_RO8_ABAT_POSN 0x4 #define _CANCON_RO8_ABAT_POSITION 0x4 #define _CANCON_RO8_ABAT_SIZE 0x1 #define _CANCON_RO8_ABAT_LENGTH 0x1 #define _CANCON_RO8_ABAT_MASK 0x10 #define _CANCON_RO8_REQOP_POSN 0x5 #define _CANCON_RO8_REQOP_POSITION 0x5 #define _CANCON_RO8_REQOP_SIZE 0x3 #define _CANCON_RO8_REQOP_LENGTH 0x3 #define _CANCON_RO8_REQOP_MASK 0xE0 #define _CANCON_RO8_WIN0_POSN 0x1 #define _CANCON_RO8_WIN0_POSITION 0x1 #define _CANCON_RO8_WIN0_SIZE 0x1 #define _CANCON_RO8_WIN0_LENGTH 0x1 #define _CANCON_RO8_WIN0_MASK 0x2 #define _CANCON_RO8_WIN1_POSN 0x2 #define _CANCON_RO8_WIN1_POSITION 0x2 #define _CANCON_RO8_WIN1_SIZE 0x1 #define _CANCON_RO8_WIN1_LENGTH 0x1 #define _CANCON_RO8_WIN1_MASK 0x4 #define _CANCON_RO8_WIN2_POSN 0x3 #define _CANCON_RO8_WIN2_POSITION 0x3 #define _CANCON_RO8_WIN2_SIZE 0x1 #define _CANCON_RO8_WIN2_LENGTH 0x1 #define _CANCON_RO8_WIN2_MASK 0x8 #define _CANCON_RO8_FP1_POSN 0x1 #define _CANCON_RO8_FP1_POSITION 0x1 #define _CANCON_RO8_FP1_SIZE 0x1 #define _CANCON_RO8_FP1_LENGTH 0x1 #define _CANCON_RO8_FP1_MASK 0x2 #define _CANCON_RO8_FP2_POSN 0x2 #define _CANCON_RO8_FP2_POSITION 0x2 #define _CANCON_RO8_FP2_SIZE 0x1 #define _CANCON_RO8_FP2_LENGTH 0x1 #define _CANCON_RO8_FP2_MASK 0x4 #define _CANCON_RO8_FP3_POSN 0x3 #define _CANCON_RO8_FP3_POSITION 0x3 #define _CANCON_RO8_FP3_SIZE 0x1 #define _CANCON_RO8_FP3_LENGTH 0x1 #define _CANCON_RO8_FP3_MASK 0x8 // Register: B2CON #define B2CON B2CON extern volatile unsigned char B2CON @ 0xEA0; #ifndef _LIB_BUILD asm("B2CON equ 0EA0h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B2FILHIT0 :1; unsigned B2FILHIT1 :1; unsigned B2FILHIT2 :1; unsigned B2FILHIT3 :1; unsigned B2FILHIT4 :1; unsigned B2RTRRO :1; unsigned B2RXM1 :1; unsigned B2RXFUL :1; }; struct { unsigned B2TXPRI0 :1; unsigned B2TXPRI1 :1; unsigned B2RTREN :1; unsigned B2TXREQ :1; unsigned B2TXERR :1; unsigned B2TXLARB :1; unsigned B2TXABT :1; unsigned B2TXB3IF :1; }; } B2CONbits_t; extern volatile B2CONbits_t B2CONbits @ 0xEA0; // bitfield macros #define _B2CON_FILHIT0_TXPRI0_POSN 0x0 #define _B2CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B2CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B2CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B2CON_FILHIT0_TXPRI0_MASK 0x1 #define _B2CON_FILHIT1_TXPRI1_POSN 0x1 #define _B2CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B2CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B2CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B2CON_FILHIT1_TXPRI1_MASK 0x2 #define _B2CON_FILHIT2_RTREN_POSN 0x2 #define _B2CON_FILHIT2_RTREN_POSITION 0x2 #define _B2CON_FILHIT2_RTREN_SIZE 0x1 #define _B2CON_FILHIT2_RTREN_LENGTH 0x1 #define _B2CON_FILHIT2_RTREN_MASK 0x4 #define _B2CON_FILHIT3_TXREQ_POSN 0x3 #define _B2CON_FILHIT3_TXREQ_POSITION 0x3 #define _B2CON_FILHIT3_TXREQ_SIZE 0x1 #define _B2CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B2CON_FILHIT3_TXREQ_MASK 0x8 #define _B2CON_FILHIT4_TXERR_POSN 0x4 #define _B2CON_FILHIT4_TXERR_POSITION 0x4 #define _B2CON_FILHIT4_TXERR_SIZE 0x1 #define _B2CON_FILHIT4_TXERR_LENGTH 0x1 #define _B2CON_FILHIT4_TXERR_MASK 0x10 #define _B2CON_RXRTRRO_TXLARB_POSN 0x5 #define _B2CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B2CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B2CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B2CON_RXRTRRO_TXLARB_MASK 0x20 #define _B2CON_RXM1_TXABT_POSN 0x6 #define _B2CON_RXM1_TXABT_POSITION 0x6 #define _B2CON_RXM1_TXABT_SIZE 0x1 #define _B2CON_RXM1_TXABT_LENGTH 0x1 #define _B2CON_RXM1_TXABT_MASK 0x40 #define _B2CON_RXFUL_TXBIF_POSN 0x7 #define _B2CON_RXFUL_TXBIF_POSITION 0x7 #define _B2CON_RXFUL_TXBIF_SIZE 0x1 #define _B2CON_RXFUL_TXBIF_LENGTH 0x1 #define _B2CON_RXFUL_TXBIF_MASK 0x80 #define _B2CON_FILHIT0_POSN 0x0 #define _B2CON_FILHIT0_POSITION 0x0 #define _B2CON_FILHIT0_SIZE 0x1 #define _B2CON_FILHIT0_LENGTH 0x1 #define _B2CON_FILHIT0_MASK 0x1 #define _B2CON_FILHIT1_POSN 0x1 #define _B2CON_FILHIT1_POSITION 0x1 #define _B2CON_FILHIT1_SIZE 0x1 #define _B2CON_FILHIT1_LENGTH 0x1 #define _B2CON_FILHIT1_MASK 0x2 #define _B2CON_FILHIT2_POSN 0x2 #define _B2CON_FILHIT2_POSITION 0x2 #define _B2CON_FILHIT2_SIZE 0x1 #define _B2CON_FILHIT2_LENGTH 0x1 #define _B2CON_FILHIT2_MASK 0x4 #define _B2CON_FILHIT3_POSN 0x3 #define _B2CON_FILHIT3_POSITION 0x3 #define _B2CON_FILHIT3_SIZE 0x1 #define _B2CON_FILHIT3_LENGTH 0x1 #define _B2CON_FILHIT3_MASK 0x8 #define _B2CON_FILHIT4_POSN 0x4 #define _B2CON_FILHIT4_POSITION 0x4 #define _B2CON_FILHIT4_SIZE 0x1 #define _B2CON_FILHIT4_LENGTH 0x1 #define _B2CON_FILHIT4_MASK 0x10 #define _B2CON_RXRTRRO_POSN 0x5 #define _B2CON_RXRTRRO_POSITION 0x5 #define _B2CON_RXRTRRO_SIZE 0x1 #define _B2CON_RXRTRRO_LENGTH 0x1 #define _B2CON_RXRTRRO_MASK 0x20 #define _B2CON_RXM1_POSN 0x6 #define _B2CON_RXM1_POSITION 0x6 #define _B2CON_RXM1_SIZE 0x1 #define _B2CON_RXM1_LENGTH 0x1 #define _B2CON_RXM1_MASK 0x40 #define _B2CON_RXFUL_POSN 0x7 #define _B2CON_RXFUL_POSITION 0x7 #define _B2CON_RXFUL_SIZE 0x1 #define _B2CON_RXFUL_LENGTH 0x1 #define _B2CON_RXFUL_MASK 0x80 #define _B2CON_TXPRI0_POSN 0x0 #define _B2CON_TXPRI0_POSITION 0x0 #define _B2CON_TXPRI0_SIZE 0x1 #define _B2CON_TXPRI0_LENGTH 0x1 #define _B2CON_TXPRI0_MASK 0x1 #define _B2CON_TXPRI1_POSN 0x1 #define _B2CON_TXPRI1_POSITION 0x1 #define _B2CON_TXPRI1_SIZE 0x1 #define _B2CON_TXPRI1_LENGTH 0x1 #define _B2CON_TXPRI1_MASK 0x2 #define _B2CON_RTREN_POSN 0x2 #define _B2CON_RTREN_POSITION 0x2 #define _B2CON_RTREN_SIZE 0x1 #define _B2CON_RTREN_LENGTH 0x1 #define _B2CON_RTREN_MASK 0x4 #define _B2CON_TXREQ_POSN 0x3 #define _B2CON_TXREQ_POSITION 0x3 #define _B2CON_TXREQ_SIZE 0x1 #define _B2CON_TXREQ_LENGTH 0x1 #define _B2CON_TXREQ_MASK 0x8 #define _B2CON_TXERR_POSN 0x4 #define _B2CON_TXERR_POSITION 0x4 #define _B2CON_TXERR_SIZE 0x1 #define _B2CON_TXERR_LENGTH 0x1 #define _B2CON_TXERR_MASK 0x10 #define _B2CON_TXLARB_POSN 0x5 #define _B2CON_TXLARB_POSITION 0x5 #define _B2CON_TXLARB_SIZE 0x1 #define _B2CON_TXLARB_LENGTH 0x1 #define _B2CON_TXLARB_MASK 0x20 #define _B2CON_TXABT_POSN 0x6 #define _B2CON_TXABT_POSITION 0x6 #define _B2CON_TXABT_SIZE 0x1 #define _B2CON_TXABT_LENGTH 0x1 #define _B2CON_TXABT_MASK 0x40 #define _B2CON_TXBIF_POSN 0x7 #define _B2CON_TXBIF_POSITION 0x7 #define _B2CON_TXBIF_SIZE 0x1 #define _B2CON_TXBIF_LENGTH 0x1 #define _B2CON_TXBIF_MASK 0x80 #define _B2CON_B2FILHIT0_POSN 0x0 #define _B2CON_B2FILHIT0_POSITION 0x0 #define _B2CON_B2FILHIT0_SIZE 0x1 #define _B2CON_B2FILHIT0_LENGTH 0x1 #define _B2CON_B2FILHIT0_MASK 0x1 #define _B2CON_B2FILHIT1_POSN 0x1 #define _B2CON_B2FILHIT1_POSITION 0x1 #define _B2CON_B2FILHIT1_SIZE 0x1 #define _B2CON_B2FILHIT1_LENGTH 0x1 #define _B2CON_B2FILHIT1_MASK 0x2 #define _B2CON_B2FILHIT2_POSN 0x2 #define _B2CON_B2FILHIT2_POSITION 0x2 #define _B2CON_B2FILHIT2_SIZE 0x1 #define _B2CON_B2FILHIT2_LENGTH 0x1 #define _B2CON_B2FILHIT2_MASK 0x4 #define _B2CON_B2FILHIT3_POSN 0x3 #define _B2CON_B2FILHIT3_POSITION 0x3 #define _B2CON_B2FILHIT3_SIZE 0x1 #define _B2CON_B2FILHIT3_LENGTH 0x1 #define _B2CON_B2FILHIT3_MASK 0x8 #define _B2CON_B2FILHIT4_POSN 0x4 #define _B2CON_B2FILHIT4_POSITION 0x4 #define _B2CON_B2FILHIT4_SIZE 0x1 #define _B2CON_B2FILHIT4_LENGTH 0x1 #define _B2CON_B2FILHIT4_MASK 0x10 #define _B2CON_B2RTRRO_POSN 0x5 #define _B2CON_B2RTRRO_POSITION 0x5 #define _B2CON_B2RTRRO_SIZE 0x1 #define _B2CON_B2RTRRO_LENGTH 0x1 #define _B2CON_B2RTRRO_MASK 0x20 #define _B2CON_B2RXM1_POSN 0x6 #define _B2CON_B2RXM1_POSITION 0x6 #define _B2CON_B2RXM1_SIZE 0x1 #define _B2CON_B2RXM1_LENGTH 0x1 #define _B2CON_B2RXM1_MASK 0x40 #define _B2CON_B2RXFUL_POSN 0x7 #define _B2CON_B2RXFUL_POSITION 0x7 #define _B2CON_B2RXFUL_SIZE 0x1 #define _B2CON_B2RXFUL_LENGTH 0x1 #define _B2CON_B2RXFUL_MASK 0x80 #define _B2CON_B2TXPRI0_POSN 0x0 #define _B2CON_B2TXPRI0_POSITION 0x0 #define _B2CON_B2TXPRI0_SIZE 0x1 #define _B2CON_B2TXPRI0_LENGTH 0x1 #define _B2CON_B2TXPRI0_MASK 0x1 #define _B2CON_B2TXPRI1_POSN 0x1 #define _B2CON_B2TXPRI1_POSITION 0x1 #define _B2CON_B2TXPRI1_SIZE 0x1 #define _B2CON_B2TXPRI1_LENGTH 0x1 #define _B2CON_B2TXPRI1_MASK 0x2 #define _B2CON_B2RTREN_POSN 0x2 #define _B2CON_B2RTREN_POSITION 0x2 #define _B2CON_B2RTREN_SIZE 0x1 #define _B2CON_B2RTREN_LENGTH 0x1 #define _B2CON_B2RTREN_MASK 0x4 #define _B2CON_B2TXREQ_POSN 0x3 #define _B2CON_B2TXREQ_POSITION 0x3 #define _B2CON_B2TXREQ_SIZE 0x1 #define _B2CON_B2TXREQ_LENGTH 0x1 #define _B2CON_B2TXREQ_MASK 0x8 #define _B2CON_B2TXERR_POSN 0x4 #define _B2CON_B2TXERR_POSITION 0x4 #define _B2CON_B2TXERR_SIZE 0x1 #define _B2CON_B2TXERR_LENGTH 0x1 #define _B2CON_B2TXERR_MASK 0x10 #define _B2CON_B2TXLARB_POSN 0x5 #define _B2CON_B2TXLARB_POSITION 0x5 #define _B2CON_B2TXLARB_SIZE 0x1 #define _B2CON_B2TXLARB_LENGTH 0x1 #define _B2CON_B2TXLARB_MASK 0x20 #define _B2CON_B2TXABT_POSN 0x6 #define _B2CON_B2TXABT_POSITION 0x6 #define _B2CON_B2TXABT_SIZE 0x1 #define _B2CON_B2TXABT_LENGTH 0x1 #define _B2CON_B2TXABT_MASK 0x40 #define _B2CON_B2TXB3IF_POSN 0x7 #define _B2CON_B2TXB3IF_POSITION 0x7 #define _B2CON_B2TXB3IF_SIZE 0x1 #define _B2CON_B2TXB3IF_LENGTH 0x1 #define _B2CON_B2TXB3IF_MASK 0x80 // Register: B2SIDH #define B2SIDH B2SIDH extern volatile unsigned char B2SIDH @ 0xEA1; #ifndef _LIB_BUILD asm("B2SIDH equ 0EA1h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B2SID3 :1; unsigned B2SID4 :1; unsigned B2SID5 :1; unsigned B2SID6 :1; unsigned B2SID7 :1; unsigned B2SID8 :1; unsigned B2SID9 :1; unsigned B2SID10 :1; }; } B2SIDHbits_t; extern volatile B2SIDHbits_t B2SIDHbits @ 0xEA1; // bitfield macros #define _B2SIDH_SID_POSN 0x0 #define _B2SIDH_SID_POSITION 0x0 #define _B2SIDH_SID_SIZE 0x8 #define _B2SIDH_SID_LENGTH 0x8 #define _B2SIDH_SID_MASK 0xFF #define _B2SIDH_SID3_POSN 0x0 #define _B2SIDH_SID3_POSITION 0x0 #define _B2SIDH_SID3_SIZE 0x1 #define _B2SIDH_SID3_LENGTH 0x1 #define _B2SIDH_SID3_MASK 0x1 #define _B2SIDH_SID4_POSN 0x1 #define _B2SIDH_SID4_POSITION 0x1 #define _B2SIDH_SID4_SIZE 0x1 #define _B2SIDH_SID4_LENGTH 0x1 #define _B2SIDH_SID4_MASK 0x2 #define _B2SIDH_SID5_POSN 0x2 #define _B2SIDH_SID5_POSITION 0x2 #define _B2SIDH_SID5_SIZE 0x1 #define _B2SIDH_SID5_LENGTH 0x1 #define _B2SIDH_SID5_MASK 0x4 #define _B2SIDH_SID6_POSN 0x3 #define _B2SIDH_SID6_POSITION 0x3 #define _B2SIDH_SID6_SIZE 0x1 #define _B2SIDH_SID6_LENGTH 0x1 #define _B2SIDH_SID6_MASK 0x8 #define _B2SIDH_SID7_POSN 0x4 #define _B2SIDH_SID7_POSITION 0x4 #define _B2SIDH_SID7_SIZE 0x1 #define _B2SIDH_SID7_LENGTH 0x1 #define _B2SIDH_SID7_MASK 0x10 #define _B2SIDH_SID8_POSN 0x5 #define _B2SIDH_SID8_POSITION 0x5 #define _B2SIDH_SID8_SIZE 0x1 #define _B2SIDH_SID8_LENGTH 0x1 #define _B2SIDH_SID8_MASK 0x20 #define _B2SIDH_SID9_POSN 0x6 #define _B2SIDH_SID9_POSITION 0x6 #define _B2SIDH_SID9_SIZE 0x1 #define _B2SIDH_SID9_LENGTH 0x1 #define _B2SIDH_SID9_MASK 0x40 #define _B2SIDH_SID10_POSN 0x7 #define _B2SIDH_SID10_POSITION 0x7 #define _B2SIDH_SID10_SIZE 0x1 #define _B2SIDH_SID10_LENGTH 0x1 #define _B2SIDH_SID10_MASK 0x80 #define _B2SIDH_B2SID3_POSN 0x0 #define _B2SIDH_B2SID3_POSITION 0x0 #define _B2SIDH_B2SID3_SIZE 0x1 #define _B2SIDH_B2SID3_LENGTH 0x1 #define _B2SIDH_B2SID3_MASK 0x1 #define _B2SIDH_B2SID4_POSN 0x1 #define _B2SIDH_B2SID4_POSITION 0x1 #define _B2SIDH_B2SID4_SIZE 0x1 #define _B2SIDH_B2SID4_LENGTH 0x1 #define _B2SIDH_B2SID4_MASK 0x2 #define _B2SIDH_B2SID5_POSN 0x2 #define _B2SIDH_B2SID5_POSITION 0x2 #define _B2SIDH_B2SID5_SIZE 0x1 #define _B2SIDH_B2SID5_LENGTH 0x1 #define _B2SIDH_B2SID5_MASK 0x4 #define _B2SIDH_B2SID6_POSN 0x3 #define _B2SIDH_B2SID6_POSITION 0x3 #define _B2SIDH_B2SID6_SIZE 0x1 #define _B2SIDH_B2SID6_LENGTH 0x1 #define _B2SIDH_B2SID6_MASK 0x8 #define _B2SIDH_B2SID7_POSN 0x4 #define _B2SIDH_B2SID7_POSITION 0x4 #define _B2SIDH_B2SID7_SIZE 0x1 #define _B2SIDH_B2SID7_LENGTH 0x1 #define _B2SIDH_B2SID7_MASK 0x10 #define _B2SIDH_B2SID8_POSN 0x5 #define _B2SIDH_B2SID8_POSITION 0x5 #define _B2SIDH_B2SID8_SIZE 0x1 #define _B2SIDH_B2SID8_LENGTH 0x1 #define _B2SIDH_B2SID8_MASK 0x20 #define _B2SIDH_B2SID9_POSN 0x6 #define _B2SIDH_B2SID9_POSITION 0x6 #define _B2SIDH_B2SID9_SIZE 0x1 #define _B2SIDH_B2SID9_LENGTH 0x1 #define _B2SIDH_B2SID9_MASK 0x40 #define _B2SIDH_B2SID10_POSN 0x7 #define _B2SIDH_B2SID10_POSITION 0x7 #define _B2SIDH_B2SID10_SIZE 0x1 #define _B2SIDH_B2SID10_LENGTH 0x1 #define _B2SIDH_B2SID10_MASK 0x80 // Register: B2SIDL #define B2SIDL B2SIDL extern volatile unsigned char B2SIDL @ 0xEA2; #ifndef _LIB_BUILD asm("B2SIDL equ 0EA2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B2EID16 :1; unsigned B2EID17 :1; unsigned :1; unsigned B2EXID :1; unsigned B2SRR :1; unsigned B2SID0 :1; unsigned B2SID1 :1; unsigned B2SID2 :1; }; struct { unsigned :3; unsigned B2EXIDE :1; }; } B2SIDLbits_t; extern volatile B2SIDLbits_t B2SIDLbits @ 0xEA2; // bitfield macros #define _B2SIDL_EID_POSN 0x0 #define _B2SIDL_EID_POSITION 0x0 #define _B2SIDL_EID_SIZE 0x2 #define _B2SIDL_EID_LENGTH 0x2 #define _B2SIDL_EID_MASK 0x3 #define _B2SIDL_EXIDE_POSN 0x3 #define _B2SIDL_EXIDE_POSITION 0x3 #define _B2SIDL_EXIDE_SIZE 0x1 #define _B2SIDL_EXIDE_LENGTH 0x1 #define _B2SIDL_EXIDE_MASK 0x8 #define _B2SIDL_SRR_POSN 0x4 #define _B2SIDL_SRR_POSITION 0x4 #define _B2SIDL_SRR_SIZE 0x1 #define _B2SIDL_SRR_LENGTH 0x1 #define _B2SIDL_SRR_MASK 0x10 #define _B2SIDL_SID_POSN 0x5 #define _B2SIDL_SID_POSITION 0x5 #define _B2SIDL_SID_SIZE 0x3 #define _B2SIDL_SID_LENGTH 0x3 #define _B2SIDL_SID_MASK 0xE0 #define _B2SIDL_EID16_POSN 0x0 #define _B2SIDL_EID16_POSITION 0x0 #define _B2SIDL_EID16_SIZE 0x1 #define _B2SIDL_EID16_LENGTH 0x1 #define _B2SIDL_EID16_MASK 0x1 #define _B2SIDL_EID17_POSN 0x1 #define _B2SIDL_EID17_POSITION 0x1 #define _B2SIDL_EID17_SIZE 0x1 #define _B2SIDL_EID17_LENGTH 0x1 #define _B2SIDL_EID17_MASK 0x2 #define _B2SIDL_SID0_POSN 0x5 #define _B2SIDL_SID0_POSITION 0x5 #define _B2SIDL_SID0_SIZE 0x1 #define _B2SIDL_SID0_LENGTH 0x1 #define _B2SIDL_SID0_MASK 0x20 #define _B2SIDL_SID1_POSN 0x6 #define _B2SIDL_SID1_POSITION 0x6 #define _B2SIDL_SID1_SIZE 0x1 #define _B2SIDL_SID1_LENGTH 0x1 #define _B2SIDL_SID1_MASK 0x40 #define _B2SIDL_SID2_POSN 0x7 #define _B2SIDL_SID2_POSITION 0x7 #define _B2SIDL_SID2_SIZE 0x1 #define _B2SIDL_SID2_LENGTH 0x1 #define _B2SIDL_SID2_MASK 0x80 #define _B2SIDL_B2EID16_POSN 0x0 #define _B2SIDL_B2EID16_POSITION 0x0 #define _B2SIDL_B2EID16_SIZE 0x1 #define _B2SIDL_B2EID16_LENGTH 0x1 #define _B2SIDL_B2EID16_MASK 0x1 #define _B2SIDL_B2EID17_POSN 0x1 #define _B2SIDL_B2EID17_POSITION 0x1 #define _B2SIDL_B2EID17_SIZE 0x1 #define _B2SIDL_B2EID17_LENGTH 0x1 #define _B2SIDL_B2EID17_MASK 0x2 #define _B2SIDL_B2EXID_POSN 0x3 #define _B2SIDL_B2EXID_POSITION 0x3 #define _B2SIDL_B2EXID_SIZE 0x1 #define _B2SIDL_B2EXID_LENGTH 0x1 #define _B2SIDL_B2EXID_MASK 0x8 #define _B2SIDL_B2SRR_POSN 0x4 #define _B2SIDL_B2SRR_POSITION 0x4 #define _B2SIDL_B2SRR_SIZE 0x1 #define _B2SIDL_B2SRR_LENGTH 0x1 #define _B2SIDL_B2SRR_MASK 0x10 #define _B2SIDL_B2SID0_POSN 0x5 #define _B2SIDL_B2SID0_POSITION 0x5 #define _B2SIDL_B2SID0_SIZE 0x1 #define _B2SIDL_B2SID0_LENGTH 0x1 #define _B2SIDL_B2SID0_MASK 0x20 #define _B2SIDL_B2SID1_POSN 0x6 #define _B2SIDL_B2SID1_POSITION 0x6 #define _B2SIDL_B2SID1_SIZE 0x1 #define _B2SIDL_B2SID1_LENGTH 0x1 #define _B2SIDL_B2SID1_MASK 0x40 #define _B2SIDL_B2SID2_POSN 0x7 #define _B2SIDL_B2SID2_POSITION 0x7 #define _B2SIDL_B2SID2_SIZE 0x1 #define _B2SIDL_B2SID2_LENGTH 0x1 #define _B2SIDL_B2SID2_MASK 0x80 #define _B2SIDL_B2EXIDE_POSN 0x3 #define _B2SIDL_B2EXIDE_POSITION 0x3 #define _B2SIDL_B2EXIDE_SIZE 0x1 #define _B2SIDL_B2EXIDE_LENGTH 0x1 #define _B2SIDL_B2EXIDE_MASK 0x8 // Register: B2EIDH #define B2EIDH B2EIDH extern volatile unsigned char B2EIDH @ 0xEA3; #ifndef _LIB_BUILD asm("B2EIDH equ 0EA3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B2EID8 :1; unsigned B2EID9 :1; unsigned B2EID10 :1; unsigned B2EID11 :1; unsigned B2EID12 :1; unsigned B2EID13 :1; unsigned B2EID14 :1; unsigned B2EID15 :1; }; } B2EIDHbits_t; extern volatile B2EIDHbits_t B2EIDHbits @ 0xEA3; // bitfield macros #define _B2EIDH_EID_POSN 0x0 #define _B2EIDH_EID_POSITION 0x0 #define _B2EIDH_EID_SIZE 0x8 #define _B2EIDH_EID_LENGTH 0x8 #define _B2EIDH_EID_MASK 0xFF #define _B2EIDH_EID8_POSN 0x0 #define _B2EIDH_EID8_POSITION 0x0 #define _B2EIDH_EID8_SIZE 0x1 #define _B2EIDH_EID8_LENGTH 0x1 #define _B2EIDH_EID8_MASK 0x1 #define _B2EIDH_EID9_POSN 0x1 #define _B2EIDH_EID9_POSITION 0x1 #define _B2EIDH_EID9_SIZE 0x1 #define _B2EIDH_EID9_LENGTH 0x1 #define _B2EIDH_EID9_MASK 0x2 #define _B2EIDH_EID10_POSN 0x2 #define _B2EIDH_EID10_POSITION 0x2 #define _B2EIDH_EID10_SIZE 0x1 #define _B2EIDH_EID10_LENGTH 0x1 #define _B2EIDH_EID10_MASK 0x4 #define _B2EIDH_EID11_POSN 0x3 #define _B2EIDH_EID11_POSITION 0x3 #define _B2EIDH_EID11_SIZE 0x1 #define _B2EIDH_EID11_LENGTH 0x1 #define _B2EIDH_EID11_MASK 0x8 #define _B2EIDH_EID12_POSN 0x4 #define _B2EIDH_EID12_POSITION 0x4 #define _B2EIDH_EID12_SIZE 0x1 #define _B2EIDH_EID12_LENGTH 0x1 #define _B2EIDH_EID12_MASK 0x10 #define _B2EIDH_EID13_POSN 0x5 #define _B2EIDH_EID13_POSITION 0x5 #define _B2EIDH_EID13_SIZE 0x1 #define _B2EIDH_EID13_LENGTH 0x1 #define _B2EIDH_EID13_MASK 0x20 #define _B2EIDH_EID14_POSN 0x6 #define _B2EIDH_EID14_POSITION 0x6 #define _B2EIDH_EID14_SIZE 0x1 #define _B2EIDH_EID14_LENGTH 0x1 #define _B2EIDH_EID14_MASK 0x40 #define _B2EIDH_EID15_POSN 0x7 #define _B2EIDH_EID15_POSITION 0x7 #define _B2EIDH_EID15_SIZE 0x1 #define _B2EIDH_EID15_LENGTH 0x1 #define _B2EIDH_EID15_MASK 0x80 #define _B2EIDH_B2EID8_POSN 0x0 #define _B2EIDH_B2EID8_POSITION 0x0 #define _B2EIDH_B2EID8_SIZE 0x1 #define _B2EIDH_B2EID8_LENGTH 0x1 #define _B2EIDH_B2EID8_MASK 0x1 #define _B2EIDH_B2EID9_POSN 0x1 #define _B2EIDH_B2EID9_POSITION 0x1 #define _B2EIDH_B2EID9_SIZE 0x1 #define _B2EIDH_B2EID9_LENGTH 0x1 #define _B2EIDH_B2EID9_MASK 0x2 #define _B2EIDH_B2EID10_POSN 0x2 #define _B2EIDH_B2EID10_POSITION 0x2 #define _B2EIDH_B2EID10_SIZE 0x1 #define _B2EIDH_B2EID10_LENGTH 0x1 #define _B2EIDH_B2EID10_MASK 0x4 #define _B2EIDH_B2EID11_POSN 0x3 #define _B2EIDH_B2EID11_POSITION 0x3 #define _B2EIDH_B2EID11_SIZE 0x1 #define _B2EIDH_B2EID11_LENGTH 0x1 #define _B2EIDH_B2EID11_MASK 0x8 #define _B2EIDH_B2EID12_POSN 0x4 #define _B2EIDH_B2EID12_POSITION 0x4 #define _B2EIDH_B2EID12_SIZE 0x1 #define _B2EIDH_B2EID12_LENGTH 0x1 #define _B2EIDH_B2EID12_MASK 0x10 #define _B2EIDH_B2EID13_POSN 0x5 #define _B2EIDH_B2EID13_POSITION 0x5 #define _B2EIDH_B2EID13_SIZE 0x1 #define _B2EIDH_B2EID13_LENGTH 0x1 #define _B2EIDH_B2EID13_MASK 0x20 #define _B2EIDH_B2EID14_POSN 0x6 #define _B2EIDH_B2EID14_POSITION 0x6 #define _B2EIDH_B2EID14_SIZE 0x1 #define _B2EIDH_B2EID14_LENGTH 0x1 #define _B2EIDH_B2EID14_MASK 0x40 #define _B2EIDH_B2EID15_POSN 0x7 #define _B2EIDH_B2EID15_POSITION 0x7 #define _B2EIDH_B2EID15_SIZE 0x1 #define _B2EIDH_B2EID15_LENGTH 0x1 #define _B2EIDH_B2EID15_MASK 0x80 // Register: B2EIDL #define B2EIDL B2EIDL extern volatile unsigned char B2EIDL @ 0xEA4; #ifndef _LIB_BUILD asm("B2EIDL equ 0EA4h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B2EID0 :1; unsigned B2EID1 :1; unsigned B2EID2 :1; unsigned B2EID3 :1; unsigned B2EID4 :1; unsigned B2EID5 :1; unsigned B2EID6 :1; unsigned B2EID7 :1; }; } B2EIDLbits_t; extern volatile B2EIDLbits_t B2EIDLbits @ 0xEA4; // bitfield macros #define _B2EIDL_EID_POSN 0x0 #define _B2EIDL_EID_POSITION 0x0 #define _B2EIDL_EID_SIZE 0x8 #define _B2EIDL_EID_LENGTH 0x8 #define _B2EIDL_EID_MASK 0xFF #define _B2EIDL_EID0_POSN 0x0 #define _B2EIDL_EID0_POSITION 0x0 #define _B2EIDL_EID0_SIZE 0x1 #define _B2EIDL_EID0_LENGTH 0x1 #define _B2EIDL_EID0_MASK 0x1 #define _B2EIDL_EID1_POSN 0x1 #define _B2EIDL_EID1_POSITION 0x1 #define _B2EIDL_EID1_SIZE 0x1 #define _B2EIDL_EID1_LENGTH 0x1 #define _B2EIDL_EID1_MASK 0x2 #define _B2EIDL_EID2_POSN 0x2 #define _B2EIDL_EID2_POSITION 0x2 #define _B2EIDL_EID2_SIZE 0x1 #define _B2EIDL_EID2_LENGTH 0x1 #define _B2EIDL_EID2_MASK 0x4 #define _B2EIDL_EID3_POSN 0x3 #define _B2EIDL_EID3_POSITION 0x3 #define _B2EIDL_EID3_SIZE 0x1 #define _B2EIDL_EID3_LENGTH 0x1 #define _B2EIDL_EID3_MASK 0x8 #define _B2EIDL_EID4_POSN 0x4 #define _B2EIDL_EID4_POSITION 0x4 #define _B2EIDL_EID4_SIZE 0x1 #define _B2EIDL_EID4_LENGTH 0x1 #define _B2EIDL_EID4_MASK 0x10 #define _B2EIDL_EID5_POSN 0x5 #define _B2EIDL_EID5_POSITION 0x5 #define _B2EIDL_EID5_SIZE 0x1 #define _B2EIDL_EID5_LENGTH 0x1 #define _B2EIDL_EID5_MASK 0x20 #define _B2EIDL_EID6_POSN 0x6 #define _B2EIDL_EID6_POSITION 0x6 #define _B2EIDL_EID6_SIZE 0x1 #define _B2EIDL_EID6_LENGTH 0x1 #define _B2EIDL_EID6_MASK 0x40 #define _B2EIDL_EID7_POSN 0x7 #define _B2EIDL_EID7_POSITION 0x7 #define _B2EIDL_EID7_SIZE 0x1 #define _B2EIDL_EID7_LENGTH 0x1 #define _B2EIDL_EID7_MASK 0x80 #define _B2EIDL_B2EID0_POSN 0x0 #define _B2EIDL_B2EID0_POSITION 0x0 #define _B2EIDL_B2EID0_SIZE 0x1 #define _B2EIDL_B2EID0_LENGTH 0x1 #define _B2EIDL_B2EID0_MASK 0x1 #define _B2EIDL_B2EID1_POSN 0x1 #define _B2EIDL_B2EID1_POSITION 0x1 #define _B2EIDL_B2EID1_SIZE 0x1 #define _B2EIDL_B2EID1_LENGTH 0x1 #define _B2EIDL_B2EID1_MASK 0x2 #define _B2EIDL_B2EID2_POSN 0x2 #define _B2EIDL_B2EID2_POSITION 0x2 #define _B2EIDL_B2EID2_SIZE 0x1 #define _B2EIDL_B2EID2_LENGTH 0x1 #define _B2EIDL_B2EID2_MASK 0x4 #define _B2EIDL_B2EID3_POSN 0x3 #define _B2EIDL_B2EID3_POSITION 0x3 #define _B2EIDL_B2EID3_SIZE 0x1 #define _B2EIDL_B2EID3_LENGTH 0x1 #define _B2EIDL_B2EID3_MASK 0x8 #define _B2EIDL_B2EID4_POSN 0x4 #define _B2EIDL_B2EID4_POSITION 0x4 #define _B2EIDL_B2EID4_SIZE 0x1 #define _B2EIDL_B2EID4_LENGTH 0x1 #define _B2EIDL_B2EID4_MASK 0x10 #define _B2EIDL_B2EID5_POSN 0x5 #define _B2EIDL_B2EID5_POSITION 0x5 #define _B2EIDL_B2EID5_SIZE 0x1 #define _B2EIDL_B2EID5_LENGTH 0x1 #define _B2EIDL_B2EID5_MASK 0x20 #define _B2EIDL_B2EID6_POSN 0x6 #define _B2EIDL_B2EID6_POSITION 0x6 #define _B2EIDL_B2EID6_SIZE 0x1 #define _B2EIDL_B2EID6_LENGTH 0x1 #define _B2EIDL_B2EID6_MASK 0x40 #define _B2EIDL_B2EID7_POSN 0x7 #define _B2EIDL_B2EID7_POSITION 0x7 #define _B2EIDL_B2EID7_SIZE 0x1 #define _B2EIDL_B2EID7_LENGTH 0x1 #define _B2EIDL_B2EID7_MASK 0x80 // Register: B2DLC #define B2DLC B2DLC extern volatile unsigned char B2DLC @ 0xEA5; #ifndef _LIB_BUILD asm("B2DLC equ 0EA5h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B2DLC0 :1; unsigned B2DLC1 :1; unsigned B2DLC2 :1; unsigned B2DLC3 :1; unsigned B2RB0 :1; unsigned B2RB1 :1; unsigned B2RXRTR :1; }; } B2DLCbits_t; extern volatile B2DLCbits_t B2DLCbits @ 0xEA5; // bitfield macros #define _B2DLC_DLC_POSN 0x0 #define _B2DLC_DLC_POSITION 0x0 #define _B2DLC_DLC_SIZE 0x4 #define _B2DLC_DLC_LENGTH 0x4 #define _B2DLC_DLC_MASK 0xF #define _B2DLC_RB_POSN 0x4 #define _B2DLC_RB_POSITION 0x4 #define _B2DLC_RB_SIZE 0x2 #define _B2DLC_RB_LENGTH 0x2 #define _B2DLC_RB_MASK 0x30 #define _B2DLC_RXRTR_TXRTR_POSN 0x6 #define _B2DLC_RXRTR_TXRTR_POSITION 0x6 #define _B2DLC_RXRTR_TXRTR_SIZE 0x1 #define _B2DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B2DLC_RXRTR_TXRTR_MASK 0x40 #define _B2DLC_DLC0_POSN 0x0 #define _B2DLC_DLC0_POSITION 0x0 #define _B2DLC_DLC0_SIZE 0x1 #define _B2DLC_DLC0_LENGTH 0x1 #define _B2DLC_DLC0_MASK 0x1 #define _B2DLC_DLC1_POSN 0x1 #define _B2DLC_DLC1_POSITION 0x1 #define _B2DLC_DLC1_SIZE 0x1 #define _B2DLC_DLC1_LENGTH 0x1 #define _B2DLC_DLC1_MASK 0x2 #define _B2DLC_DLC2_POSN 0x2 #define _B2DLC_DLC2_POSITION 0x2 #define _B2DLC_DLC2_SIZE 0x1 #define _B2DLC_DLC2_LENGTH 0x1 #define _B2DLC_DLC2_MASK 0x4 #define _B2DLC_DLC3_POSN 0x3 #define _B2DLC_DLC3_POSITION 0x3 #define _B2DLC_DLC3_SIZE 0x1 #define _B2DLC_DLC3_LENGTH 0x1 #define _B2DLC_DLC3_MASK 0x8 #define _B2DLC_RB0_POSN 0x4 #define _B2DLC_RB0_POSITION 0x4 #define _B2DLC_RB0_SIZE 0x1 #define _B2DLC_RB0_LENGTH 0x1 #define _B2DLC_RB0_MASK 0x10 #define _B2DLC_RB1_POSN 0x5 #define _B2DLC_RB1_POSITION 0x5 #define _B2DLC_RB1_SIZE 0x1 #define _B2DLC_RB1_LENGTH 0x1 #define _B2DLC_RB1_MASK 0x20 #define _B2DLC_RXRTR_POSN 0x6 #define _B2DLC_RXRTR_POSITION 0x6 #define _B2DLC_RXRTR_SIZE 0x1 #define _B2DLC_RXRTR_LENGTH 0x1 #define _B2DLC_RXRTR_MASK 0x40 #define _B2DLC_TXRTR_POSN 0x6 #define _B2DLC_TXRTR_POSITION 0x6 #define _B2DLC_TXRTR_SIZE 0x1 #define _B2DLC_TXRTR_LENGTH 0x1 #define _B2DLC_TXRTR_MASK 0x40 #define _B2DLC_B2DLC0_POSN 0x0 #define _B2DLC_B2DLC0_POSITION 0x0 #define _B2DLC_B2DLC0_SIZE 0x1 #define _B2DLC_B2DLC0_LENGTH 0x1 #define _B2DLC_B2DLC0_MASK 0x1 #define _B2DLC_B2DLC1_POSN 0x1 #define _B2DLC_B2DLC1_POSITION 0x1 #define _B2DLC_B2DLC1_SIZE 0x1 #define _B2DLC_B2DLC1_LENGTH 0x1 #define _B2DLC_B2DLC1_MASK 0x2 #define _B2DLC_B2DLC2_POSN 0x2 #define _B2DLC_B2DLC2_POSITION 0x2 #define _B2DLC_B2DLC2_SIZE 0x1 #define _B2DLC_B2DLC2_LENGTH 0x1 #define _B2DLC_B2DLC2_MASK 0x4 #define _B2DLC_B2DLC3_POSN 0x3 #define _B2DLC_B2DLC3_POSITION 0x3 #define _B2DLC_B2DLC3_SIZE 0x1 #define _B2DLC_B2DLC3_LENGTH 0x1 #define _B2DLC_B2DLC3_MASK 0x8 #define _B2DLC_B2RB0_POSN 0x4 #define _B2DLC_B2RB0_POSITION 0x4 #define _B2DLC_B2RB0_SIZE 0x1 #define _B2DLC_B2RB0_LENGTH 0x1 #define _B2DLC_B2RB0_MASK 0x10 #define _B2DLC_B2RB1_POSN 0x5 #define _B2DLC_B2RB1_POSITION 0x5 #define _B2DLC_B2RB1_SIZE 0x1 #define _B2DLC_B2RB1_LENGTH 0x1 #define _B2DLC_B2RB1_MASK 0x20 #define _B2DLC_B2RXRTR_POSN 0x6 #define _B2DLC_B2RXRTR_POSITION 0x6 #define _B2DLC_B2RXRTR_SIZE 0x1 #define _B2DLC_B2RXRTR_LENGTH 0x1 #define _B2DLC_B2RXRTR_MASK 0x40 // Register: B2D0 #define B2D0 B2D0 extern volatile unsigned char B2D0 @ 0xEA6; #ifndef _LIB_BUILD asm("B2D0 equ 0EA6h"); #endif // bitfield definitions typedef union { struct { unsigned B2D0 :8; }; struct { unsigned B2D00 :1; unsigned B2D01 :1; unsigned B2D02 :1; unsigned B2D03 :1; unsigned B2D04 :1; unsigned B2D05 :1; unsigned B2D06 :1; unsigned B2D07 :1; }; } B2D0bits_t; extern volatile B2D0bits_t B2D0bits @ 0xEA6; // bitfield macros #define _B2D0_B2D0_POSN 0x0 #define _B2D0_B2D0_POSITION 0x0 #define _B2D0_B2D0_SIZE 0x8 #define _B2D0_B2D0_LENGTH 0x8 #define _B2D0_B2D0_MASK 0xFF #define _B2D0_B2D00_POSN 0x0 #define _B2D0_B2D00_POSITION 0x0 #define _B2D0_B2D00_SIZE 0x1 #define _B2D0_B2D00_LENGTH 0x1 #define _B2D0_B2D00_MASK 0x1 #define _B2D0_B2D01_POSN 0x1 #define _B2D0_B2D01_POSITION 0x1 #define _B2D0_B2D01_SIZE 0x1 #define _B2D0_B2D01_LENGTH 0x1 #define _B2D0_B2D01_MASK 0x2 #define _B2D0_B2D02_POSN 0x2 #define _B2D0_B2D02_POSITION 0x2 #define _B2D0_B2D02_SIZE 0x1 #define _B2D0_B2D02_LENGTH 0x1 #define _B2D0_B2D02_MASK 0x4 #define _B2D0_B2D03_POSN 0x3 #define _B2D0_B2D03_POSITION 0x3 #define _B2D0_B2D03_SIZE 0x1 #define _B2D0_B2D03_LENGTH 0x1 #define _B2D0_B2D03_MASK 0x8 #define _B2D0_B2D04_POSN 0x4 #define _B2D0_B2D04_POSITION 0x4 #define _B2D0_B2D04_SIZE 0x1 #define _B2D0_B2D04_LENGTH 0x1 #define _B2D0_B2D04_MASK 0x10 #define _B2D0_B2D05_POSN 0x5 #define _B2D0_B2D05_POSITION 0x5 #define _B2D0_B2D05_SIZE 0x1 #define _B2D0_B2D05_LENGTH 0x1 #define _B2D0_B2D05_MASK 0x20 #define _B2D0_B2D06_POSN 0x6 #define _B2D0_B2D06_POSITION 0x6 #define _B2D0_B2D06_SIZE 0x1 #define _B2D0_B2D06_LENGTH 0x1 #define _B2D0_B2D06_MASK 0x40 #define _B2D0_B2D07_POSN 0x7 #define _B2D0_B2D07_POSITION 0x7 #define _B2D0_B2D07_SIZE 0x1 #define _B2D0_B2D07_LENGTH 0x1 #define _B2D0_B2D07_MASK 0x80 // Register: B2D1 #define B2D1 B2D1 extern volatile unsigned char B2D1 @ 0xEA7; #ifndef _LIB_BUILD asm("B2D1 equ 0EA7h"); #endif // bitfield definitions typedef union { struct { unsigned B2D1 :8; }; struct { unsigned B2D10 :1; unsigned B2D11 :1; unsigned B2D12 :1; unsigned B2D13 :1; unsigned B2D14 :1; unsigned B2D15 :1; unsigned B2D16 :1; unsigned B2D17 :1; }; } B2D1bits_t; extern volatile B2D1bits_t B2D1bits @ 0xEA7; // bitfield macros #define _B2D1_B2D1_POSN 0x0 #define _B2D1_B2D1_POSITION 0x0 #define _B2D1_B2D1_SIZE 0x8 #define _B2D1_B2D1_LENGTH 0x8 #define _B2D1_B2D1_MASK 0xFF #define _B2D1_B2D10_POSN 0x0 #define _B2D1_B2D10_POSITION 0x0 #define _B2D1_B2D10_SIZE 0x1 #define _B2D1_B2D10_LENGTH 0x1 #define _B2D1_B2D10_MASK 0x1 #define _B2D1_B2D11_POSN 0x1 #define _B2D1_B2D11_POSITION 0x1 #define _B2D1_B2D11_SIZE 0x1 #define _B2D1_B2D11_LENGTH 0x1 #define _B2D1_B2D11_MASK 0x2 #define _B2D1_B2D12_POSN 0x2 #define _B2D1_B2D12_POSITION 0x2 #define _B2D1_B2D12_SIZE 0x1 #define _B2D1_B2D12_LENGTH 0x1 #define _B2D1_B2D12_MASK 0x4 #define _B2D1_B2D13_POSN 0x3 #define _B2D1_B2D13_POSITION 0x3 #define _B2D1_B2D13_SIZE 0x1 #define _B2D1_B2D13_LENGTH 0x1 #define _B2D1_B2D13_MASK 0x8 #define _B2D1_B2D14_POSN 0x4 #define _B2D1_B2D14_POSITION 0x4 #define _B2D1_B2D14_SIZE 0x1 #define _B2D1_B2D14_LENGTH 0x1 #define _B2D1_B2D14_MASK 0x10 #define _B2D1_B2D15_POSN 0x5 #define _B2D1_B2D15_POSITION 0x5 #define _B2D1_B2D15_SIZE 0x1 #define _B2D1_B2D15_LENGTH 0x1 #define _B2D1_B2D15_MASK 0x20 #define _B2D1_B2D16_POSN 0x6 #define _B2D1_B2D16_POSITION 0x6 #define _B2D1_B2D16_SIZE 0x1 #define _B2D1_B2D16_LENGTH 0x1 #define _B2D1_B2D16_MASK 0x40 #define _B2D1_B2D17_POSN 0x7 #define _B2D1_B2D17_POSITION 0x7 #define _B2D1_B2D17_SIZE 0x1 #define _B2D1_B2D17_LENGTH 0x1 #define _B2D1_B2D17_MASK 0x80 // Register: B2D2 #define B2D2 B2D2 extern volatile unsigned char B2D2 @ 0xEA8; #ifndef _LIB_BUILD asm("B2D2 equ 0EA8h"); #endif // bitfield definitions typedef union { struct { unsigned B2D2 :8; }; struct { unsigned B2D20 :1; unsigned B2D21 :1; unsigned B2D22 :1; unsigned B2D23 :1; unsigned B2D24 :1; unsigned B2D25 :1; unsigned B2D26 :1; unsigned B2D27 :1; }; } B2D2bits_t; extern volatile B2D2bits_t B2D2bits @ 0xEA8; // bitfield macros #define _B2D2_B2D2_POSN 0x0 #define _B2D2_B2D2_POSITION 0x0 #define _B2D2_B2D2_SIZE 0x8 #define _B2D2_B2D2_LENGTH 0x8 #define _B2D2_B2D2_MASK 0xFF #define _B2D2_B2D20_POSN 0x0 #define _B2D2_B2D20_POSITION 0x0 #define _B2D2_B2D20_SIZE 0x1 #define _B2D2_B2D20_LENGTH 0x1 #define _B2D2_B2D20_MASK 0x1 #define _B2D2_B2D21_POSN 0x1 #define _B2D2_B2D21_POSITION 0x1 #define _B2D2_B2D21_SIZE 0x1 #define _B2D2_B2D21_LENGTH 0x1 #define _B2D2_B2D21_MASK 0x2 #define _B2D2_B2D22_POSN 0x2 #define _B2D2_B2D22_POSITION 0x2 #define _B2D2_B2D22_SIZE 0x1 #define _B2D2_B2D22_LENGTH 0x1 #define _B2D2_B2D22_MASK 0x4 #define _B2D2_B2D23_POSN 0x3 #define _B2D2_B2D23_POSITION 0x3 #define _B2D2_B2D23_SIZE 0x1 #define _B2D2_B2D23_LENGTH 0x1 #define _B2D2_B2D23_MASK 0x8 #define _B2D2_B2D24_POSN 0x4 #define _B2D2_B2D24_POSITION 0x4 #define _B2D2_B2D24_SIZE 0x1 #define _B2D2_B2D24_LENGTH 0x1 #define _B2D2_B2D24_MASK 0x10 #define _B2D2_B2D25_POSN 0x5 #define _B2D2_B2D25_POSITION 0x5 #define _B2D2_B2D25_SIZE 0x1 #define _B2D2_B2D25_LENGTH 0x1 #define _B2D2_B2D25_MASK 0x20 #define _B2D2_B2D26_POSN 0x6 #define _B2D2_B2D26_POSITION 0x6 #define _B2D2_B2D26_SIZE 0x1 #define _B2D2_B2D26_LENGTH 0x1 #define _B2D2_B2D26_MASK 0x40 #define _B2D2_B2D27_POSN 0x7 #define _B2D2_B2D27_POSITION 0x7 #define _B2D2_B2D27_SIZE 0x1 #define _B2D2_B2D27_LENGTH 0x1 #define _B2D2_B2D27_MASK 0x80 // Register: B2D3 #define B2D3 B2D3 extern volatile unsigned char B2D3 @ 0xEA9; #ifndef _LIB_BUILD asm("B2D3 equ 0EA9h"); #endif // bitfield definitions typedef union { struct { unsigned B2D3 :8; }; struct { unsigned B2D30 :1; unsigned B2D31 :1; unsigned B2D32 :1; unsigned B2D33 :1; unsigned B2D34 :1; unsigned B2D35 :1; unsigned B2D36 :1; unsigned B2D37 :1; }; } B2D3bits_t; extern volatile B2D3bits_t B2D3bits @ 0xEA9; // bitfield macros #define _B2D3_B2D3_POSN 0x0 #define _B2D3_B2D3_POSITION 0x0 #define _B2D3_B2D3_SIZE 0x8 #define _B2D3_B2D3_LENGTH 0x8 #define _B2D3_B2D3_MASK 0xFF #define _B2D3_B2D30_POSN 0x0 #define _B2D3_B2D30_POSITION 0x0 #define _B2D3_B2D30_SIZE 0x1 #define _B2D3_B2D30_LENGTH 0x1 #define _B2D3_B2D30_MASK 0x1 #define _B2D3_B2D31_POSN 0x1 #define _B2D3_B2D31_POSITION 0x1 #define _B2D3_B2D31_SIZE 0x1 #define _B2D3_B2D31_LENGTH 0x1 #define _B2D3_B2D31_MASK 0x2 #define _B2D3_B2D32_POSN 0x2 #define _B2D3_B2D32_POSITION 0x2 #define _B2D3_B2D32_SIZE 0x1 #define _B2D3_B2D32_LENGTH 0x1 #define _B2D3_B2D32_MASK 0x4 #define _B2D3_B2D33_POSN 0x3 #define _B2D3_B2D33_POSITION 0x3 #define _B2D3_B2D33_SIZE 0x1 #define _B2D3_B2D33_LENGTH 0x1 #define _B2D3_B2D33_MASK 0x8 #define _B2D3_B2D34_POSN 0x4 #define _B2D3_B2D34_POSITION 0x4 #define _B2D3_B2D34_SIZE 0x1 #define _B2D3_B2D34_LENGTH 0x1 #define _B2D3_B2D34_MASK 0x10 #define _B2D3_B2D35_POSN 0x5 #define _B2D3_B2D35_POSITION 0x5 #define _B2D3_B2D35_SIZE 0x1 #define _B2D3_B2D35_LENGTH 0x1 #define _B2D3_B2D35_MASK 0x20 #define _B2D3_B2D36_POSN 0x6 #define _B2D3_B2D36_POSITION 0x6 #define _B2D3_B2D36_SIZE 0x1 #define _B2D3_B2D36_LENGTH 0x1 #define _B2D3_B2D36_MASK 0x40 #define _B2D3_B2D37_POSN 0x7 #define _B2D3_B2D37_POSITION 0x7 #define _B2D3_B2D37_SIZE 0x1 #define _B2D3_B2D37_LENGTH 0x1 #define _B2D3_B2D37_MASK 0x80 // Register: B2D4 #define B2D4 B2D4 extern volatile unsigned char B2D4 @ 0xEAA; #ifndef _LIB_BUILD asm("B2D4 equ 0EAAh"); #endif // bitfield definitions typedef union { struct { unsigned B2D4 :8; }; struct { unsigned B2D40 :1; unsigned B2D41 :1; unsigned B2D42 :1; unsigned B2D43 :1; unsigned B2D44 :1; unsigned B2D45 :1; unsigned B2D46 :1; unsigned B2D47 :1; }; } B2D4bits_t; extern volatile B2D4bits_t B2D4bits @ 0xEAA; // bitfield macros #define _B2D4_B2D4_POSN 0x0 #define _B2D4_B2D4_POSITION 0x0 #define _B2D4_B2D4_SIZE 0x8 #define _B2D4_B2D4_LENGTH 0x8 #define _B2D4_B2D4_MASK 0xFF #define _B2D4_B2D40_POSN 0x0 #define _B2D4_B2D40_POSITION 0x0 #define _B2D4_B2D40_SIZE 0x1 #define _B2D4_B2D40_LENGTH 0x1 #define _B2D4_B2D40_MASK 0x1 #define _B2D4_B2D41_POSN 0x1 #define _B2D4_B2D41_POSITION 0x1 #define _B2D4_B2D41_SIZE 0x1 #define _B2D4_B2D41_LENGTH 0x1 #define _B2D4_B2D41_MASK 0x2 #define _B2D4_B2D42_POSN 0x2 #define _B2D4_B2D42_POSITION 0x2 #define _B2D4_B2D42_SIZE 0x1 #define _B2D4_B2D42_LENGTH 0x1 #define _B2D4_B2D42_MASK 0x4 #define _B2D4_B2D43_POSN 0x3 #define _B2D4_B2D43_POSITION 0x3 #define _B2D4_B2D43_SIZE 0x1 #define _B2D4_B2D43_LENGTH 0x1 #define _B2D4_B2D43_MASK 0x8 #define _B2D4_B2D44_POSN 0x4 #define _B2D4_B2D44_POSITION 0x4 #define _B2D4_B2D44_SIZE 0x1 #define _B2D4_B2D44_LENGTH 0x1 #define _B2D4_B2D44_MASK 0x10 #define _B2D4_B2D45_POSN 0x5 #define _B2D4_B2D45_POSITION 0x5 #define _B2D4_B2D45_SIZE 0x1 #define _B2D4_B2D45_LENGTH 0x1 #define _B2D4_B2D45_MASK 0x20 #define _B2D4_B2D46_POSN 0x6 #define _B2D4_B2D46_POSITION 0x6 #define _B2D4_B2D46_SIZE 0x1 #define _B2D4_B2D46_LENGTH 0x1 #define _B2D4_B2D46_MASK 0x40 #define _B2D4_B2D47_POSN 0x7 #define _B2D4_B2D47_POSITION 0x7 #define _B2D4_B2D47_SIZE 0x1 #define _B2D4_B2D47_LENGTH 0x1 #define _B2D4_B2D47_MASK 0x80 // Register: B2D5 #define B2D5 B2D5 extern volatile unsigned char B2D5 @ 0xEAB; #ifndef _LIB_BUILD asm("B2D5 equ 0EABh"); #endif // bitfield definitions typedef union { struct { unsigned B2D5 :8; }; struct { unsigned B2D50 :1; unsigned B2D51 :1; unsigned B2D52 :1; unsigned B2D53 :1; unsigned B2D54 :1; unsigned B2D55 :1; unsigned B2D56 :1; unsigned B2D57 :1; }; } B2D5bits_t; extern volatile B2D5bits_t B2D5bits @ 0xEAB; // bitfield macros #define _B2D5_B2D5_POSN 0x0 #define _B2D5_B2D5_POSITION 0x0 #define _B2D5_B2D5_SIZE 0x8 #define _B2D5_B2D5_LENGTH 0x8 #define _B2D5_B2D5_MASK 0xFF #define _B2D5_B2D50_POSN 0x0 #define _B2D5_B2D50_POSITION 0x0 #define _B2D5_B2D50_SIZE 0x1 #define _B2D5_B2D50_LENGTH 0x1 #define _B2D5_B2D50_MASK 0x1 #define _B2D5_B2D51_POSN 0x1 #define _B2D5_B2D51_POSITION 0x1 #define _B2D5_B2D51_SIZE 0x1 #define _B2D5_B2D51_LENGTH 0x1 #define _B2D5_B2D51_MASK 0x2 #define _B2D5_B2D52_POSN 0x2 #define _B2D5_B2D52_POSITION 0x2 #define _B2D5_B2D52_SIZE 0x1 #define _B2D5_B2D52_LENGTH 0x1 #define _B2D5_B2D52_MASK 0x4 #define _B2D5_B2D53_POSN 0x3 #define _B2D5_B2D53_POSITION 0x3 #define _B2D5_B2D53_SIZE 0x1 #define _B2D5_B2D53_LENGTH 0x1 #define _B2D5_B2D53_MASK 0x8 #define _B2D5_B2D54_POSN 0x4 #define _B2D5_B2D54_POSITION 0x4 #define _B2D5_B2D54_SIZE 0x1 #define _B2D5_B2D54_LENGTH 0x1 #define _B2D5_B2D54_MASK 0x10 #define _B2D5_B2D55_POSN 0x5 #define _B2D5_B2D55_POSITION 0x5 #define _B2D5_B2D55_SIZE 0x1 #define _B2D5_B2D55_LENGTH 0x1 #define _B2D5_B2D55_MASK 0x20 #define _B2D5_B2D56_POSN 0x6 #define _B2D5_B2D56_POSITION 0x6 #define _B2D5_B2D56_SIZE 0x1 #define _B2D5_B2D56_LENGTH 0x1 #define _B2D5_B2D56_MASK 0x40 #define _B2D5_B2D57_POSN 0x7 #define _B2D5_B2D57_POSITION 0x7 #define _B2D5_B2D57_SIZE 0x1 #define _B2D5_B2D57_LENGTH 0x1 #define _B2D5_B2D57_MASK 0x80 // Register: B2D6 #define B2D6 B2D6 extern volatile unsigned char B2D6 @ 0xEAC; #ifndef _LIB_BUILD asm("B2D6 equ 0EACh"); #endif // bitfield definitions typedef union { struct { unsigned B2D6 :8; }; struct { unsigned B2D60 :1; unsigned B2D61 :1; unsigned B2D62 :1; unsigned B2D63 :1; unsigned B2D64 :1; unsigned B2D65 :1; unsigned B2D66 :1; unsigned B2D67 :1; }; } B2D6bits_t; extern volatile B2D6bits_t B2D6bits @ 0xEAC; // bitfield macros #define _B2D6_B2D6_POSN 0x0 #define _B2D6_B2D6_POSITION 0x0 #define _B2D6_B2D6_SIZE 0x8 #define _B2D6_B2D6_LENGTH 0x8 #define _B2D6_B2D6_MASK 0xFF #define _B2D6_B2D60_POSN 0x0 #define _B2D6_B2D60_POSITION 0x0 #define _B2D6_B2D60_SIZE 0x1 #define _B2D6_B2D60_LENGTH 0x1 #define _B2D6_B2D60_MASK 0x1 #define _B2D6_B2D61_POSN 0x1 #define _B2D6_B2D61_POSITION 0x1 #define _B2D6_B2D61_SIZE 0x1 #define _B2D6_B2D61_LENGTH 0x1 #define _B2D6_B2D61_MASK 0x2 #define _B2D6_B2D62_POSN 0x2 #define _B2D6_B2D62_POSITION 0x2 #define _B2D6_B2D62_SIZE 0x1 #define _B2D6_B2D62_LENGTH 0x1 #define _B2D6_B2D62_MASK 0x4 #define _B2D6_B2D63_POSN 0x3 #define _B2D6_B2D63_POSITION 0x3 #define _B2D6_B2D63_SIZE 0x1 #define _B2D6_B2D63_LENGTH 0x1 #define _B2D6_B2D63_MASK 0x8 #define _B2D6_B2D64_POSN 0x4 #define _B2D6_B2D64_POSITION 0x4 #define _B2D6_B2D64_SIZE 0x1 #define _B2D6_B2D64_LENGTH 0x1 #define _B2D6_B2D64_MASK 0x10 #define _B2D6_B2D65_POSN 0x5 #define _B2D6_B2D65_POSITION 0x5 #define _B2D6_B2D65_SIZE 0x1 #define _B2D6_B2D65_LENGTH 0x1 #define _B2D6_B2D65_MASK 0x20 #define _B2D6_B2D66_POSN 0x6 #define _B2D6_B2D66_POSITION 0x6 #define _B2D6_B2D66_SIZE 0x1 #define _B2D6_B2D66_LENGTH 0x1 #define _B2D6_B2D66_MASK 0x40 #define _B2D6_B2D67_POSN 0x7 #define _B2D6_B2D67_POSITION 0x7 #define _B2D6_B2D67_SIZE 0x1 #define _B2D6_B2D67_LENGTH 0x1 #define _B2D6_B2D67_MASK 0x80 // Register: B2D7 #define B2D7 B2D7 extern volatile unsigned char B2D7 @ 0xEAD; #ifndef _LIB_BUILD asm("B2D7 equ 0EADh"); #endif // bitfield definitions typedef union { struct { unsigned B2D7 :8; }; struct { unsigned B2D70 :1; unsigned B2D71 :1; unsigned B2D72 :1; unsigned B2D73 :1; unsigned B2D74 :1; unsigned B2D75 :1; unsigned B2D76 :1; unsigned B2D77 :1; }; } B2D7bits_t; extern volatile B2D7bits_t B2D7bits @ 0xEAD; // bitfield macros #define _B2D7_B2D7_POSN 0x0 #define _B2D7_B2D7_POSITION 0x0 #define _B2D7_B2D7_SIZE 0x8 #define _B2D7_B2D7_LENGTH 0x8 #define _B2D7_B2D7_MASK 0xFF #define _B2D7_B2D70_POSN 0x0 #define _B2D7_B2D70_POSITION 0x0 #define _B2D7_B2D70_SIZE 0x1 #define _B2D7_B2D70_LENGTH 0x1 #define _B2D7_B2D70_MASK 0x1 #define _B2D7_B2D71_POSN 0x1 #define _B2D7_B2D71_POSITION 0x1 #define _B2D7_B2D71_SIZE 0x1 #define _B2D7_B2D71_LENGTH 0x1 #define _B2D7_B2D71_MASK 0x2 #define _B2D7_B2D72_POSN 0x2 #define _B2D7_B2D72_POSITION 0x2 #define _B2D7_B2D72_SIZE 0x1 #define _B2D7_B2D72_LENGTH 0x1 #define _B2D7_B2D72_MASK 0x4 #define _B2D7_B2D73_POSN 0x3 #define _B2D7_B2D73_POSITION 0x3 #define _B2D7_B2D73_SIZE 0x1 #define _B2D7_B2D73_LENGTH 0x1 #define _B2D7_B2D73_MASK 0x8 #define _B2D7_B2D74_POSN 0x4 #define _B2D7_B2D74_POSITION 0x4 #define _B2D7_B2D74_SIZE 0x1 #define _B2D7_B2D74_LENGTH 0x1 #define _B2D7_B2D74_MASK 0x10 #define _B2D7_B2D75_POSN 0x5 #define _B2D7_B2D75_POSITION 0x5 #define _B2D7_B2D75_SIZE 0x1 #define _B2D7_B2D75_LENGTH 0x1 #define _B2D7_B2D75_MASK 0x20 #define _B2D7_B2D76_POSN 0x6 #define _B2D7_B2D76_POSITION 0x6 #define _B2D7_B2D76_SIZE 0x1 #define _B2D7_B2D76_LENGTH 0x1 #define _B2D7_B2D76_MASK 0x40 #define _B2D7_B2D77_POSN 0x7 #define _B2D7_B2D77_POSITION 0x7 #define _B2D7_B2D77_SIZE 0x1 #define _B2D7_B2D77_LENGTH 0x1 #define _B2D7_B2D77_MASK 0x80 // Register: CANSTAT_RO7 #define CANSTAT_RO7 CANSTAT_RO7 extern volatile unsigned char CANSTAT_RO7 @ 0xEAE; #ifndef _LIB_BUILD asm("CANSTAT_RO7 equ 0EAEh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO7bits_t; extern volatile CANSTAT_RO7bits_t CANSTAT_RO7bits @ 0xEAE; // bitfield macros #define _CANSTAT_RO7_EICODE0_POSN 0x0 #define _CANSTAT_RO7_EICODE0_POSITION 0x0 #define _CANSTAT_RO7_EICODE0_SIZE 0x1 #define _CANSTAT_RO7_EICODE0_LENGTH 0x1 #define _CANSTAT_RO7_EICODE0_MASK 0x1 #define _CANSTAT_RO7_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO7_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO7_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO7_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO7_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO7_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO7_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO7_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO7_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO7_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO7_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO7_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO7_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO7_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO7_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO7_EICODE4_POSN 0x4 #define _CANSTAT_RO7_EICODE4_POSITION 0x4 #define _CANSTAT_RO7_EICODE4_SIZE 0x1 #define _CANSTAT_RO7_EICODE4_LENGTH 0x1 #define _CANSTAT_RO7_EICODE4_MASK 0x10 #define _CANSTAT_RO7_OPMODE_POSN 0x5 #define _CANSTAT_RO7_OPMODE_POSITION 0x5 #define _CANSTAT_RO7_OPMODE_SIZE 0x3 #define _CANSTAT_RO7_OPMODE_LENGTH 0x3 #define _CANSTAT_RO7_OPMODE_MASK 0xE0 #define _CANSTAT_RO7_EICODE1_POSN 0x1 #define _CANSTAT_RO7_EICODE1_POSITION 0x1 #define _CANSTAT_RO7_EICODE1_SIZE 0x1 #define _CANSTAT_RO7_EICODE1_LENGTH 0x1 #define _CANSTAT_RO7_EICODE1_MASK 0x2 #define _CANSTAT_RO7_EICODE2_POSN 0x2 #define _CANSTAT_RO7_EICODE2_POSITION 0x2 #define _CANSTAT_RO7_EICODE2_SIZE 0x1 #define _CANSTAT_RO7_EICODE2_LENGTH 0x1 #define _CANSTAT_RO7_EICODE2_MASK 0x4 #define _CANSTAT_RO7_EICODE3_POSN 0x3 #define _CANSTAT_RO7_EICODE3_POSITION 0x3 #define _CANSTAT_RO7_EICODE3_SIZE 0x1 #define _CANSTAT_RO7_EICODE3_LENGTH 0x1 #define _CANSTAT_RO7_EICODE3_MASK 0x8 #define _CANSTAT_RO7_OPMODE0_POSN 0x5 #define _CANSTAT_RO7_OPMODE0_POSITION 0x5 #define _CANSTAT_RO7_OPMODE0_SIZE 0x1 #define _CANSTAT_RO7_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO7_OPMODE0_MASK 0x20 #define _CANSTAT_RO7_OPMODE1_POSN 0x6 #define _CANSTAT_RO7_OPMODE1_POSITION 0x6 #define _CANSTAT_RO7_OPMODE1_SIZE 0x1 #define _CANSTAT_RO7_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO7_OPMODE1_MASK 0x40 #define _CANSTAT_RO7_OPMODE2_POSN 0x7 #define _CANSTAT_RO7_OPMODE2_POSITION 0x7 #define _CANSTAT_RO7_OPMODE2_SIZE 0x1 #define _CANSTAT_RO7_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO7_OPMODE2_MASK 0x80 #define _CANSTAT_RO7_ICODE0_POSN 0x1 #define _CANSTAT_RO7_ICODE0_POSITION 0x1 #define _CANSTAT_RO7_ICODE0_SIZE 0x1 #define _CANSTAT_RO7_ICODE0_LENGTH 0x1 #define _CANSTAT_RO7_ICODE0_MASK 0x2 #define _CANSTAT_RO7_ICODE1_POSN 0x2 #define _CANSTAT_RO7_ICODE1_POSITION 0x2 #define _CANSTAT_RO7_ICODE1_SIZE 0x1 #define _CANSTAT_RO7_ICODE1_LENGTH 0x1 #define _CANSTAT_RO7_ICODE1_MASK 0x4 #define _CANSTAT_RO7_ICODE2_POSN 0x3 #define _CANSTAT_RO7_ICODE2_POSITION 0x3 #define _CANSTAT_RO7_ICODE2_SIZE 0x1 #define _CANSTAT_RO7_ICODE2_LENGTH 0x1 #define _CANSTAT_RO7_ICODE2_MASK 0x8 // Register: CANCON_RO7 #define CANCON_RO7 CANCON_RO7 extern volatile unsigned char CANCON_RO7 @ 0xEAF; #ifndef _LIB_BUILD asm("CANCON_RO7 equ 0EAFh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO7bits_t; extern volatile CANCON_RO7bits_t CANCON_RO7bits @ 0xEAF; // bitfield macros #define _CANCON_RO7_FP0_POSN 0x0 #define _CANCON_RO7_FP0_POSITION 0x0 #define _CANCON_RO7_FP0_SIZE 0x1 #define _CANCON_RO7_FP0_LENGTH 0x1 #define _CANCON_RO7_FP0_MASK 0x1 #define _CANCON_RO7_WIN0_FP1_POSN 0x1 #define _CANCON_RO7_WIN0_FP1_POSITION 0x1 #define _CANCON_RO7_WIN0_FP1_SIZE 0x1 #define _CANCON_RO7_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO7_WIN0_FP1_MASK 0x2 #define _CANCON_RO7_WIN1_FP2_POSN 0x2 #define _CANCON_RO7_WIN1_FP2_POSITION 0x2 #define _CANCON_RO7_WIN1_FP2_SIZE 0x1 #define _CANCON_RO7_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO7_WIN1_FP2_MASK 0x4 #define _CANCON_RO7_WIN2_FP3_POSN 0x3 #define _CANCON_RO7_WIN2_FP3_POSITION 0x3 #define _CANCON_RO7_WIN2_FP3_SIZE 0x1 #define _CANCON_RO7_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO7_WIN2_FP3_MASK 0x8 #define _CANCON_RO7_ABAT_POSN 0x4 #define _CANCON_RO7_ABAT_POSITION 0x4 #define _CANCON_RO7_ABAT_SIZE 0x1 #define _CANCON_RO7_ABAT_LENGTH 0x1 #define _CANCON_RO7_ABAT_MASK 0x10 #define _CANCON_RO7_REQOP_POSN 0x5 #define _CANCON_RO7_REQOP_POSITION 0x5 #define _CANCON_RO7_REQOP_SIZE 0x3 #define _CANCON_RO7_REQOP_LENGTH 0x3 #define _CANCON_RO7_REQOP_MASK 0xE0 #define _CANCON_RO7_WIN0_POSN 0x1 #define _CANCON_RO7_WIN0_POSITION 0x1 #define _CANCON_RO7_WIN0_SIZE 0x1 #define _CANCON_RO7_WIN0_LENGTH 0x1 #define _CANCON_RO7_WIN0_MASK 0x2 #define _CANCON_RO7_WIN1_POSN 0x2 #define _CANCON_RO7_WIN1_POSITION 0x2 #define _CANCON_RO7_WIN1_SIZE 0x1 #define _CANCON_RO7_WIN1_LENGTH 0x1 #define _CANCON_RO7_WIN1_MASK 0x4 #define _CANCON_RO7_WIN2_POSN 0x3 #define _CANCON_RO7_WIN2_POSITION 0x3 #define _CANCON_RO7_WIN2_SIZE 0x1 #define _CANCON_RO7_WIN2_LENGTH 0x1 #define _CANCON_RO7_WIN2_MASK 0x8 #define _CANCON_RO7_FP1_POSN 0x1 #define _CANCON_RO7_FP1_POSITION 0x1 #define _CANCON_RO7_FP1_SIZE 0x1 #define _CANCON_RO7_FP1_LENGTH 0x1 #define _CANCON_RO7_FP1_MASK 0x2 #define _CANCON_RO7_FP2_POSN 0x2 #define _CANCON_RO7_FP2_POSITION 0x2 #define _CANCON_RO7_FP2_SIZE 0x1 #define _CANCON_RO7_FP2_LENGTH 0x1 #define _CANCON_RO7_FP2_MASK 0x4 #define _CANCON_RO7_FP3_POSN 0x3 #define _CANCON_RO7_FP3_POSITION 0x3 #define _CANCON_RO7_FP3_SIZE 0x1 #define _CANCON_RO7_FP3_LENGTH 0x1 #define _CANCON_RO7_FP3_MASK 0x8 // Register: B3CON #define B3CON B3CON extern volatile unsigned char B3CON @ 0xEB0; #ifndef _LIB_BUILD asm("B3CON equ 0EB0h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B3FILHIT0 :1; unsigned B3FILHIT1 :1; unsigned B3FILHIT2 :1; unsigned B3FILHIT3 :1; unsigned B3FILHIT4 :1; unsigned B3RTRRO :1; unsigned B3RXM1 :1; unsigned B3RXFUL :1; }; struct { unsigned B3TXPRI0 :1; unsigned B3TXPRI1 :1; unsigned B3RTREN :1; unsigned B3TXREQ :1; unsigned B3TXERR :1; unsigned B3TXLARB :1; unsigned B3TXABT :1; unsigned B3TXB3IF :1; }; } B3CONbits_t; extern volatile B3CONbits_t B3CONbits @ 0xEB0; // bitfield macros #define _B3CON_FILHIT0_TXPRI0_POSN 0x0 #define _B3CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B3CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B3CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B3CON_FILHIT0_TXPRI0_MASK 0x1 #define _B3CON_FILHIT1_TXPRI1_POSN 0x1 #define _B3CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B3CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B3CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B3CON_FILHIT1_TXPRI1_MASK 0x2 #define _B3CON_FILHIT2_RTREN_POSN 0x2 #define _B3CON_FILHIT2_RTREN_POSITION 0x2 #define _B3CON_FILHIT2_RTREN_SIZE 0x1 #define _B3CON_FILHIT2_RTREN_LENGTH 0x1 #define _B3CON_FILHIT2_RTREN_MASK 0x4 #define _B3CON_FILHIT3_TXREQ_POSN 0x3 #define _B3CON_FILHIT3_TXREQ_POSITION 0x3 #define _B3CON_FILHIT3_TXREQ_SIZE 0x1 #define _B3CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B3CON_FILHIT3_TXREQ_MASK 0x8 #define _B3CON_FILHIT4_TXERR_POSN 0x4 #define _B3CON_FILHIT4_TXERR_POSITION 0x4 #define _B3CON_FILHIT4_TXERR_SIZE 0x1 #define _B3CON_FILHIT4_TXERR_LENGTH 0x1 #define _B3CON_FILHIT4_TXERR_MASK 0x10 #define _B3CON_RXRTRRO_TXLARB_POSN 0x5 #define _B3CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B3CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B3CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B3CON_RXRTRRO_TXLARB_MASK 0x20 #define _B3CON_RXM1_TXABT_POSN 0x6 #define _B3CON_RXM1_TXABT_POSITION 0x6 #define _B3CON_RXM1_TXABT_SIZE 0x1 #define _B3CON_RXM1_TXABT_LENGTH 0x1 #define _B3CON_RXM1_TXABT_MASK 0x40 #define _B3CON_RXFUL_TXBIF_POSN 0x7 #define _B3CON_RXFUL_TXBIF_POSITION 0x7 #define _B3CON_RXFUL_TXBIF_SIZE 0x1 #define _B3CON_RXFUL_TXBIF_LENGTH 0x1 #define _B3CON_RXFUL_TXBIF_MASK 0x80 #define _B3CON_FILHIT0_POSN 0x0 #define _B3CON_FILHIT0_POSITION 0x0 #define _B3CON_FILHIT0_SIZE 0x1 #define _B3CON_FILHIT0_LENGTH 0x1 #define _B3CON_FILHIT0_MASK 0x1 #define _B3CON_FILHIT1_POSN 0x1 #define _B3CON_FILHIT1_POSITION 0x1 #define _B3CON_FILHIT1_SIZE 0x1 #define _B3CON_FILHIT1_LENGTH 0x1 #define _B3CON_FILHIT1_MASK 0x2 #define _B3CON_FILHIT2_POSN 0x2 #define _B3CON_FILHIT2_POSITION 0x2 #define _B3CON_FILHIT2_SIZE 0x1 #define _B3CON_FILHIT2_LENGTH 0x1 #define _B3CON_FILHIT2_MASK 0x4 #define _B3CON_FILHIT3_POSN 0x3 #define _B3CON_FILHIT3_POSITION 0x3 #define _B3CON_FILHIT3_SIZE 0x1 #define _B3CON_FILHIT3_LENGTH 0x1 #define _B3CON_FILHIT3_MASK 0x8 #define _B3CON_FILHIT4_POSN 0x4 #define _B3CON_FILHIT4_POSITION 0x4 #define _B3CON_FILHIT4_SIZE 0x1 #define _B3CON_FILHIT4_LENGTH 0x1 #define _B3CON_FILHIT4_MASK 0x10 #define _B3CON_RXRTRRO_POSN 0x5 #define _B3CON_RXRTRRO_POSITION 0x5 #define _B3CON_RXRTRRO_SIZE 0x1 #define _B3CON_RXRTRRO_LENGTH 0x1 #define _B3CON_RXRTRRO_MASK 0x20 #define _B3CON_RXM1_POSN 0x6 #define _B3CON_RXM1_POSITION 0x6 #define _B3CON_RXM1_SIZE 0x1 #define _B3CON_RXM1_LENGTH 0x1 #define _B3CON_RXM1_MASK 0x40 #define _B3CON_RXFUL_POSN 0x7 #define _B3CON_RXFUL_POSITION 0x7 #define _B3CON_RXFUL_SIZE 0x1 #define _B3CON_RXFUL_LENGTH 0x1 #define _B3CON_RXFUL_MASK 0x80 #define _B3CON_TXPRI0_POSN 0x0 #define _B3CON_TXPRI0_POSITION 0x0 #define _B3CON_TXPRI0_SIZE 0x1 #define _B3CON_TXPRI0_LENGTH 0x1 #define _B3CON_TXPRI0_MASK 0x1 #define _B3CON_TXPRI1_POSN 0x1 #define _B3CON_TXPRI1_POSITION 0x1 #define _B3CON_TXPRI1_SIZE 0x1 #define _B3CON_TXPRI1_LENGTH 0x1 #define _B3CON_TXPRI1_MASK 0x2 #define _B3CON_RTREN_POSN 0x2 #define _B3CON_RTREN_POSITION 0x2 #define _B3CON_RTREN_SIZE 0x1 #define _B3CON_RTREN_LENGTH 0x1 #define _B3CON_RTREN_MASK 0x4 #define _B3CON_TXREQ_POSN 0x3 #define _B3CON_TXREQ_POSITION 0x3 #define _B3CON_TXREQ_SIZE 0x1 #define _B3CON_TXREQ_LENGTH 0x1 #define _B3CON_TXREQ_MASK 0x8 #define _B3CON_TXERR_POSN 0x4 #define _B3CON_TXERR_POSITION 0x4 #define _B3CON_TXERR_SIZE 0x1 #define _B3CON_TXERR_LENGTH 0x1 #define _B3CON_TXERR_MASK 0x10 #define _B3CON_TXLARB_POSN 0x5 #define _B3CON_TXLARB_POSITION 0x5 #define _B3CON_TXLARB_SIZE 0x1 #define _B3CON_TXLARB_LENGTH 0x1 #define _B3CON_TXLARB_MASK 0x20 #define _B3CON_TXABT_POSN 0x6 #define _B3CON_TXABT_POSITION 0x6 #define _B3CON_TXABT_SIZE 0x1 #define _B3CON_TXABT_LENGTH 0x1 #define _B3CON_TXABT_MASK 0x40 #define _B3CON_TXBIF_POSN 0x7 #define _B3CON_TXBIF_POSITION 0x7 #define _B3CON_TXBIF_SIZE 0x1 #define _B3CON_TXBIF_LENGTH 0x1 #define _B3CON_TXBIF_MASK 0x80 #define _B3CON_B3FILHIT0_POSN 0x0 #define _B3CON_B3FILHIT0_POSITION 0x0 #define _B3CON_B3FILHIT0_SIZE 0x1 #define _B3CON_B3FILHIT0_LENGTH 0x1 #define _B3CON_B3FILHIT0_MASK 0x1 #define _B3CON_B3FILHIT1_POSN 0x1 #define _B3CON_B3FILHIT1_POSITION 0x1 #define _B3CON_B3FILHIT1_SIZE 0x1 #define _B3CON_B3FILHIT1_LENGTH 0x1 #define _B3CON_B3FILHIT1_MASK 0x2 #define _B3CON_B3FILHIT2_POSN 0x2 #define _B3CON_B3FILHIT2_POSITION 0x2 #define _B3CON_B3FILHIT2_SIZE 0x1 #define _B3CON_B3FILHIT2_LENGTH 0x1 #define _B3CON_B3FILHIT2_MASK 0x4 #define _B3CON_B3FILHIT3_POSN 0x3 #define _B3CON_B3FILHIT3_POSITION 0x3 #define _B3CON_B3FILHIT3_SIZE 0x1 #define _B3CON_B3FILHIT3_LENGTH 0x1 #define _B3CON_B3FILHIT3_MASK 0x8 #define _B3CON_B3FILHIT4_POSN 0x4 #define _B3CON_B3FILHIT4_POSITION 0x4 #define _B3CON_B3FILHIT4_SIZE 0x1 #define _B3CON_B3FILHIT4_LENGTH 0x1 #define _B3CON_B3FILHIT4_MASK 0x10 #define _B3CON_B3RTRRO_POSN 0x5 #define _B3CON_B3RTRRO_POSITION 0x5 #define _B3CON_B3RTRRO_SIZE 0x1 #define _B3CON_B3RTRRO_LENGTH 0x1 #define _B3CON_B3RTRRO_MASK 0x20 #define _B3CON_B3RXM1_POSN 0x6 #define _B3CON_B3RXM1_POSITION 0x6 #define _B3CON_B3RXM1_SIZE 0x1 #define _B3CON_B3RXM1_LENGTH 0x1 #define _B3CON_B3RXM1_MASK 0x40 #define _B3CON_B3RXFUL_POSN 0x7 #define _B3CON_B3RXFUL_POSITION 0x7 #define _B3CON_B3RXFUL_SIZE 0x1 #define _B3CON_B3RXFUL_LENGTH 0x1 #define _B3CON_B3RXFUL_MASK 0x80 #define _B3CON_B3TXPRI0_POSN 0x0 #define _B3CON_B3TXPRI0_POSITION 0x0 #define _B3CON_B3TXPRI0_SIZE 0x1 #define _B3CON_B3TXPRI0_LENGTH 0x1 #define _B3CON_B3TXPRI0_MASK 0x1 #define _B3CON_B3TXPRI1_POSN 0x1 #define _B3CON_B3TXPRI1_POSITION 0x1 #define _B3CON_B3TXPRI1_SIZE 0x1 #define _B3CON_B3TXPRI1_LENGTH 0x1 #define _B3CON_B3TXPRI1_MASK 0x2 #define _B3CON_B3RTREN_POSN 0x2 #define _B3CON_B3RTREN_POSITION 0x2 #define _B3CON_B3RTREN_SIZE 0x1 #define _B3CON_B3RTREN_LENGTH 0x1 #define _B3CON_B3RTREN_MASK 0x4 #define _B3CON_B3TXREQ_POSN 0x3 #define _B3CON_B3TXREQ_POSITION 0x3 #define _B3CON_B3TXREQ_SIZE 0x1 #define _B3CON_B3TXREQ_LENGTH 0x1 #define _B3CON_B3TXREQ_MASK 0x8 #define _B3CON_B3TXERR_POSN 0x4 #define _B3CON_B3TXERR_POSITION 0x4 #define _B3CON_B3TXERR_SIZE 0x1 #define _B3CON_B3TXERR_LENGTH 0x1 #define _B3CON_B3TXERR_MASK 0x10 #define _B3CON_B3TXLARB_POSN 0x5 #define _B3CON_B3TXLARB_POSITION 0x5 #define _B3CON_B3TXLARB_SIZE 0x1 #define _B3CON_B3TXLARB_LENGTH 0x1 #define _B3CON_B3TXLARB_MASK 0x20 #define _B3CON_B3TXABT_POSN 0x6 #define _B3CON_B3TXABT_POSITION 0x6 #define _B3CON_B3TXABT_SIZE 0x1 #define _B3CON_B3TXABT_LENGTH 0x1 #define _B3CON_B3TXABT_MASK 0x40 #define _B3CON_B3TXB3IF_POSN 0x7 #define _B3CON_B3TXB3IF_POSITION 0x7 #define _B3CON_B3TXB3IF_SIZE 0x1 #define _B3CON_B3TXB3IF_LENGTH 0x1 #define _B3CON_B3TXB3IF_MASK 0x80 // Register: B3SIDH #define B3SIDH B3SIDH extern volatile unsigned char B3SIDH @ 0xEB1; #ifndef _LIB_BUILD asm("B3SIDH equ 0EB1h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B3SID3 :1; unsigned B3SID4 :1; unsigned B3SID5 :1; unsigned B3SID6 :1; unsigned B3SID7 :1; unsigned B3SID8 :1; unsigned B3SID9 :1; unsigned B3SID10 :1; }; } B3SIDHbits_t; extern volatile B3SIDHbits_t B3SIDHbits @ 0xEB1; // bitfield macros #define _B3SIDH_SID_POSN 0x0 #define _B3SIDH_SID_POSITION 0x0 #define _B3SIDH_SID_SIZE 0x8 #define _B3SIDH_SID_LENGTH 0x8 #define _B3SIDH_SID_MASK 0xFF #define _B3SIDH_SID3_POSN 0x0 #define _B3SIDH_SID3_POSITION 0x0 #define _B3SIDH_SID3_SIZE 0x1 #define _B3SIDH_SID3_LENGTH 0x1 #define _B3SIDH_SID3_MASK 0x1 #define _B3SIDH_SID4_POSN 0x1 #define _B3SIDH_SID4_POSITION 0x1 #define _B3SIDH_SID4_SIZE 0x1 #define _B3SIDH_SID4_LENGTH 0x1 #define _B3SIDH_SID4_MASK 0x2 #define _B3SIDH_SID5_POSN 0x2 #define _B3SIDH_SID5_POSITION 0x2 #define _B3SIDH_SID5_SIZE 0x1 #define _B3SIDH_SID5_LENGTH 0x1 #define _B3SIDH_SID5_MASK 0x4 #define _B3SIDH_SID6_POSN 0x3 #define _B3SIDH_SID6_POSITION 0x3 #define _B3SIDH_SID6_SIZE 0x1 #define _B3SIDH_SID6_LENGTH 0x1 #define _B3SIDH_SID6_MASK 0x8 #define _B3SIDH_SID7_POSN 0x4 #define _B3SIDH_SID7_POSITION 0x4 #define _B3SIDH_SID7_SIZE 0x1 #define _B3SIDH_SID7_LENGTH 0x1 #define _B3SIDH_SID7_MASK 0x10 #define _B3SIDH_SID8_POSN 0x5 #define _B3SIDH_SID8_POSITION 0x5 #define _B3SIDH_SID8_SIZE 0x1 #define _B3SIDH_SID8_LENGTH 0x1 #define _B3SIDH_SID8_MASK 0x20 #define _B3SIDH_SID9_POSN 0x6 #define _B3SIDH_SID9_POSITION 0x6 #define _B3SIDH_SID9_SIZE 0x1 #define _B3SIDH_SID9_LENGTH 0x1 #define _B3SIDH_SID9_MASK 0x40 #define _B3SIDH_SID10_POSN 0x7 #define _B3SIDH_SID10_POSITION 0x7 #define _B3SIDH_SID10_SIZE 0x1 #define _B3SIDH_SID10_LENGTH 0x1 #define _B3SIDH_SID10_MASK 0x80 #define _B3SIDH_B3SID3_POSN 0x0 #define _B3SIDH_B3SID3_POSITION 0x0 #define _B3SIDH_B3SID3_SIZE 0x1 #define _B3SIDH_B3SID3_LENGTH 0x1 #define _B3SIDH_B3SID3_MASK 0x1 #define _B3SIDH_B3SID4_POSN 0x1 #define _B3SIDH_B3SID4_POSITION 0x1 #define _B3SIDH_B3SID4_SIZE 0x1 #define _B3SIDH_B3SID4_LENGTH 0x1 #define _B3SIDH_B3SID4_MASK 0x2 #define _B3SIDH_B3SID5_POSN 0x2 #define _B3SIDH_B3SID5_POSITION 0x2 #define _B3SIDH_B3SID5_SIZE 0x1 #define _B3SIDH_B3SID5_LENGTH 0x1 #define _B3SIDH_B3SID5_MASK 0x4 #define _B3SIDH_B3SID6_POSN 0x3 #define _B3SIDH_B3SID6_POSITION 0x3 #define _B3SIDH_B3SID6_SIZE 0x1 #define _B3SIDH_B3SID6_LENGTH 0x1 #define _B3SIDH_B3SID6_MASK 0x8 #define _B3SIDH_B3SID7_POSN 0x4 #define _B3SIDH_B3SID7_POSITION 0x4 #define _B3SIDH_B3SID7_SIZE 0x1 #define _B3SIDH_B3SID7_LENGTH 0x1 #define _B3SIDH_B3SID7_MASK 0x10 #define _B3SIDH_B3SID8_POSN 0x5 #define _B3SIDH_B3SID8_POSITION 0x5 #define _B3SIDH_B3SID8_SIZE 0x1 #define _B3SIDH_B3SID8_LENGTH 0x1 #define _B3SIDH_B3SID8_MASK 0x20 #define _B3SIDH_B3SID9_POSN 0x6 #define _B3SIDH_B3SID9_POSITION 0x6 #define _B3SIDH_B3SID9_SIZE 0x1 #define _B3SIDH_B3SID9_LENGTH 0x1 #define _B3SIDH_B3SID9_MASK 0x40 #define _B3SIDH_B3SID10_POSN 0x7 #define _B3SIDH_B3SID10_POSITION 0x7 #define _B3SIDH_B3SID10_SIZE 0x1 #define _B3SIDH_B3SID10_LENGTH 0x1 #define _B3SIDH_B3SID10_MASK 0x80 // Register: B3SIDL #define B3SIDL B3SIDL extern volatile unsigned char B3SIDL @ 0xEB2; #ifndef _LIB_BUILD asm("B3SIDL equ 0EB2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B3EID16 :1; unsigned B3EID17 :1; unsigned :1; unsigned B3EXID :1; unsigned B3SRR :1; unsigned B3SID0 :1; unsigned B3SID1 :1; unsigned B3SID2 :1; }; struct { unsigned :3; unsigned B3EXIDE :1; }; } B3SIDLbits_t; extern volatile B3SIDLbits_t B3SIDLbits @ 0xEB2; // bitfield macros #define _B3SIDL_EID_POSN 0x0 #define _B3SIDL_EID_POSITION 0x0 #define _B3SIDL_EID_SIZE 0x2 #define _B3SIDL_EID_LENGTH 0x2 #define _B3SIDL_EID_MASK 0x3 #define _B3SIDL_EXIDE_POSN 0x3 #define _B3SIDL_EXIDE_POSITION 0x3 #define _B3SIDL_EXIDE_SIZE 0x1 #define _B3SIDL_EXIDE_LENGTH 0x1 #define _B3SIDL_EXIDE_MASK 0x8 #define _B3SIDL_SRR_POSN 0x4 #define _B3SIDL_SRR_POSITION 0x4 #define _B3SIDL_SRR_SIZE 0x1 #define _B3SIDL_SRR_LENGTH 0x1 #define _B3SIDL_SRR_MASK 0x10 #define _B3SIDL_SID_POSN 0x5 #define _B3SIDL_SID_POSITION 0x5 #define _B3SIDL_SID_SIZE 0x3 #define _B3SIDL_SID_LENGTH 0x3 #define _B3SIDL_SID_MASK 0xE0 #define _B3SIDL_EID16_POSN 0x0 #define _B3SIDL_EID16_POSITION 0x0 #define _B3SIDL_EID16_SIZE 0x1 #define _B3SIDL_EID16_LENGTH 0x1 #define _B3SIDL_EID16_MASK 0x1 #define _B3SIDL_EID17_POSN 0x1 #define _B3SIDL_EID17_POSITION 0x1 #define _B3SIDL_EID17_SIZE 0x1 #define _B3SIDL_EID17_LENGTH 0x1 #define _B3SIDL_EID17_MASK 0x2 #define _B3SIDL_SID0_POSN 0x5 #define _B3SIDL_SID0_POSITION 0x5 #define _B3SIDL_SID0_SIZE 0x1 #define _B3SIDL_SID0_LENGTH 0x1 #define _B3SIDL_SID0_MASK 0x20 #define _B3SIDL_SID1_POSN 0x6 #define _B3SIDL_SID1_POSITION 0x6 #define _B3SIDL_SID1_SIZE 0x1 #define _B3SIDL_SID1_LENGTH 0x1 #define _B3SIDL_SID1_MASK 0x40 #define _B3SIDL_SID2_POSN 0x7 #define _B3SIDL_SID2_POSITION 0x7 #define _B3SIDL_SID2_SIZE 0x1 #define _B3SIDL_SID2_LENGTH 0x1 #define _B3SIDL_SID2_MASK 0x80 #define _B3SIDL_B3EID16_POSN 0x0 #define _B3SIDL_B3EID16_POSITION 0x0 #define _B3SIDL_B3EID16_SIZE 0x1 #define _B3SIDL_B3EID16_LENGTH 0x1 #define _B3SIDL_B3EID16_MASK 0x1 #define _B3SIDL_B3EID17_POSN 0x1 #define _B3SIDL_B3EID17_POSITION 0x1 #define _B3SIDL_B3EID17_SIZE 0x1 #define _B3SIDL_B3EID17_LENGTH 0x1 #define _B3SIDL_B3EID17_MASK 0x2 #define _B3SIDL_B3EXID_POSN 0x3 #define _B3SIDL_B3EXID_POSITION 0x3 #define _B3SIDL_B3EXID_SIZE 0x1 #define _B3SIDL_B3EXID_LENGTH 0x1 #define _B3SIDL_B3EXID_MASK 0x8 #define _B3SIDL_B3SRR_POSN 0x4 #define _B3SIDL_B3SRR_POSITION 0x4 #define _B3SIDL_B3SRR_SIZE 0x1 #define _B3SIDL_B3SRR_LENGTH 0x1 #define _B3SIDL_B3SRR_MASK 0x10 #define _B3SIDL_B3SID0_POSN 0x5 #define _B3SIDL_B3SID0_POSITION 0x5 #define _B3SIDL_B3SID0_SIZE 0x1 #define _B3SIDL_B3SID0_LENGTH 0x1 #define _B3SIDL_B3SID0_MASK 0x20 #define _B3SIDL_B3SID1_POSN 0x6 #define _B3SIDL_B3SID1_POSITION 0x6 #define _B3SIDL_B3SID1_SIZE 0x1 #define _B3SIDL_B3SID1_LENGTH 0x1 #define _B3SIDL_B3SID1_MASK 0x40 #define _B3SIDL_B3SID2_POSN 0x7 #define _B3SIDL_B3SID2_POSITION 0x7 #define _B3SIDL_B3SID2_SIZE 0x1 #define _B3SIDL_B3SID2_LENGTH 0x1 #define _B3SIDL_B3SID2_MASK 0x80 #define _B3SIDL_B3EXIDE_POSN 0x3 #define _B3SIDL_B3EXIDE_POSITION 0x3 #define _B3SIDL_B3EXIDE_SIZE 0x1 #define _B3SIDL_B3EXIDE_LENGTH 0x1 #define _B3SIDL_B3EXIDE_MASK 0x8 // Register: B3EIDH #define B3EIDH B3EIDH extern volatile unsigned char B3EIDH @ 0xEB3; #ifndef _LIB_BUILD asm("B3EIDH equ 0EB3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B3EID8 :1; unsigned B3EID9 :1; unsigned B3EID10 :1; unsigned B3EID11 :1; unsigned B3EID12 :1; unsigned B3EID13 :1; unsigned B3EID14 :1; unsigned B3EID15 :1; }; } B3EIDHbits_t; extern volatile B3EIDHbits_t B3EIDHbits @ 0xEB3; // bitfield macros #define _B3EIDH_EID_POSN 0x0 #define _B3EIDH_EID_POSITION 0x0 #define _B3EIDH_EID_SIZE 0x8 #define _B3EIDH_EID_LENGTH 0x8 #define _B3EIDH_EID_MASK 0xFF #define _B3EIDH_EID8_POSN 0x0 #define _B3EIDH_EID8_POSITION 0x0 #define _B3EIDH_EID8_SIZE 0x1 #define _B3EIDH_EID8_LENGTH 0x1 #define _B3EIDH_EID8_MASK 0x1 #define _B3EIDH_EID9_POSN 0x1 #define _B3EIDH_EID9_POSITION 0x1 #define _B3EIDH_EID9_SIZE 0x1 #define _B3EIDH_EID9_LENGTH 0x1 #define _B3EIDH_EID9_MASK 0x2 #define _B3EIDH_EID10_POSN 0x2 #define _B3EIDH_EID10_POSITION 0x2 #define _B3EIDH_EID10_SIZE 0x1 #define _B3EIDH_EID10_LENGTH 0x1 #define _B3EIDH_EID10_MASK 0x4 #define _B3EIDH_EID11_POSN 0x3 #define _B3EIDH_EID11_POSITION 0x3 #define _B3EIDH_EID11_SIZE 0x1 #define _B3EIDH_EID11_LENGTH 0x1 #define _B3EIDH_EID11_MASK 0x8 #define _B3EIDH_EID12_POSN 0x4 #define _B3EIDH_EID12_POSITION 0x4 #define _B3EIDH_EID12_SIZE 0x1 #define _B3EIDH_EID12_LENGTH 0x1 #define _B3EIDH_EID12_MASK 0x10 #define _B3EIDH_EID13_POSN 0x5 #define _B3EIDH_EID13_POSITION 0x5 #define _B3EIDH_EID13_SIZE 0x1 #define _B3EIDH_EID13_LENGTH 0x1 #define _B3EIDH_EID13_MASK 0x20 #define _B3EIDH_EID14_POSN 0x6 #define _B3EIDH_EID14_POSITION 0x6 #define _B3EIDH_EID14_SIZE 0x1 #define _B3EIDH_EID14_LENGTH 0x1 #define _B3EIDH_EID14_MASK 0x40 #define _B3EIDH_EID15_POSN 0x7 #define _B3EIDH_EID15_POSITION 0x7 #define _B3EIDH_EID15_SIZE 0x1 #define _B3EIDH_EID15_LENGTH 0x1 #define _B3EIDH_EID15_MASK 0x80 #define _B3EIDH_B3EID8_POSN 0x0 #define _B3EIDH_B3EID8_POSITION 0x0 #define _B3EIDH_B3EID8_SIZE 0x1 #define _B3EIDH_B3EID8_LENGTH 0x1 #define _B3EIDH_B3EID8_MASK 0x1 #define _B3EIDH_B3EID9_POSN 0x1 #define _B3EIDH_B3EID9_POSITION 0x1 #define _B3EIDH_B3EID9_SIZE 0x1 #define _B3EIDH_B3EID9_LENGTH 0x1 #define _B3EIDH_B3EID9_MASK 0x2 #define _B3EIDH_B3EID10_POSN 0x2 #define _B3EIDH_B3EID10_POSITION 0x2 #define _B3EIDH_B3EID10_SIZE 0x1 #define _B3EIDH_B3EID10_LENGTH 0x1 #define _B3EIDH_B3EID10_MASK 0x4 #define _B3EIDH_B3EID11_POSN 0x3 #define _B3EIDH_B3EID11_POSITION 0x3 #define _B3EIDH_B3EID11_SIZE 0x1 #define _B3EIDH_B3EID11_LENGTH 0x1 #define _B3EIDH_B3EID11_MASK 0x8 #define _B3EIDH_B3EID12_POSN 0x4 #define _B3EIDH_B3EID12_POSITION 0x4 #define _B3EIDH_B3EID12_SIZE 0x1 #define _B3EIDH_B3EID12_LENGTH 0x1 #define _B3EIDH_B3EID12_MASK 0x10 #define _B3EIDH_B3EID13_POSN 0x5 #define _B3EIDH_B3EID13_POSITION 0x5 #define _B3EIDH_B3EID13_SIZE 0x1 #define _B3EIDH_B3EID13_LENGTH 0x1 #define _B3EIDH_B3EID13_MASK 0x20 #define _B3EIDH_B3EID14_POSN 0x6 #define _B3EIDH_B3EID14_POSITION 0x6 #define _B3EIDH_B3EID14_SIZE 0x1 #define _B3EIDH_B3EID14_LENGTH 0x1 #define _B3EIDH_B3EID14_MASK 0x40 #define _B3EIDH_B3EID15_POSN 0x7 #define _B3EIDH_B3EID15_POSITION 0x7 #define _B3EIDH_B3EID15_SIZE 0x1 #define _B3EIDH_B3EID15_LENGTH 0x1 #define _B3EIDH_B3EID15_MASK 0x80 // Register: B3EIDL #define B3EIDL B3EIDL extern volatile unsigned char B3EIDL @ 0xEB4; #ifndef _LIB_BUILD asm("B3EIDL equ 0EB4h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B3EID0 :1; unsigned B3EID1 :1; unsigned B3EID2 :1; unsigned B3EID3 :1; unsigned B3EID4 :1; unsigned B3EID5 :1; unsigned B3EID6 :1; unsigned B3EID7 :1; }; } B3EIDLbits_t; extern volatile B3EIDLbits_t B3EIDLbits @ 0xEB4; // bitfield macros #define _B3EIDL_EID_POSN 0x0 #define _B3EIDL_EID_POSITION 0x0 #define _B3EIDL_EID_SIZE 0x8 #define _B3EIDL_EID_LENGTH 0x8 #define _B3EIDL_EID_MASK 0xFF #define _B3EIDL_EID0_POSN 0x0 #define _B3EIDL_EID0_POSITION 0x0 #define _B3EIDL_EID0_SIZE 0x1 #define _B3EIDL_EID0_LENGTH 0x1 #define _B3EIDL_EID0_MASK 0x1 #define _B3EIDL_EID1_POSN 0x1 #define _B3EIDL_EID1_POSITION 0x1 #define _B3EIDL_EID1_SIZE 0x1 #define _B3EIDL_EID1_LENGTH 0x1 #define _B3EIDL_EID1_MASK 0x2 #define _B3EIDL_EID2_POSN 0x2 #define _B3EIDL_EID2_POSITION 0x2 #define _B3EIDL_EID2_SIZE 0x1 #define _B3EIDL_EID2_LENGTH 0x1 #define _B3EIDL_EID2_MASK 0x4 #define _B3EIDL_EID3_POSN 0x3 #define _B3EIDL_EID3_POSITION 0x3 #define _B3EIDL_EID3_SIZE 0x1 #define _B3EIDL_EID3_LENGTH 0x1 #define _B3EIDL_EID3_MASK 0x8 #define _B3EIDL_EID4_POSN 0x4 #define _B3EIDL_EID4_POSITION 0x4 #define _B3EIDL_EID4_SIZE 0x1 #define _B3EIDL_EID4_LENGTH 0x1 #define _B3EIDL_EID4_MASK 0x10 #define _B3EIDL_EID5_POSN 0x5 #define _B3EIDL_EID5_POSITION 0x5 #define _B3EIDL_EID5_SIZE 0x1 #define _B3EIDL_EID5_LENGTH 0x1 #define _B3EIDL_EID5_MASK 0x20 #define _B3EIDL_EID6_POSN 0x6 #define _B3EIDL_EID6_POSITION 0x6 #define _B3EIDL_EID6_SIZE 0x1 #define _B3EIDL_EID6_LENGTH 0x1 #define _B3EIDL_EID6_MASK 0x40 #define _B3EIDL_EID7_POSN 0x7 #define _B3EIDL_EID7_POSITION 0x7 #define _B3EIDL_EID7_SIZE 0x1 #define _B3EIDL_EID7_LENGTH 0x1 #define _B3EIDL_EID7_MASK 0x80 #define _B3EIDL_B3EID0_POSN 0x0 #define _B3EIDL_B3EID0_POSITION 0x0 #define _B3EIDL_B3EID0_SIZE 0x1 #define _B3EIDL_B3EID0_LENGTH 0x1 #define _B3EIDL_B3EID0_MASK 0x1 #define _B3EIDL_B3EID1_POSN 0x1 #define _B3EIDL_B3EID1_POSITION 0x1 #define _B3EIDL_B3EID1_SIZE 0x1 #define _B3EIDL_B3EID1_LENGTH 0x1 #define _B3EIDL_B3EID1_MASK 0x2 #define _B3EIDL_B3EID2_POSN 0x2 #define _B3EIDL_B3EID2_POSITION 0x2 #define _B3EIDL_B3EID2_SIZE 0x1 #define _B3EIDL_B3EID2_LENGTH 0x1 #define _B3EIDL_B3EID2_MASK 0x4 #define _B3EIDL_B3EID3_POSN 0x3 #define _B3EIDL_B3EID3_POSITION 0x3 #define _B3EIDL_B3EID3_SIZE 0x1 #define _B3EIDL_B3EID3_LENGTH 0x1 #define _B3EIDL_B3EID3_MASK 0x8 #define _B3EIDL_B3EID4_POSN 0x4 #define _B3EIDL_B3EID4_POSITION 0x4 #define _B3EIDL_B3EID4_SIZE 0x1 #define _B3EIDL_B3EID4_LENGTH 0x1 #define _B3EIDL_B3EID4_MASK 0x10 #define _B3EIDL_B3EID5_POSN 0x5 #define _B3EIDL_B3EID5_POSITION 0x5 #define _B3EIDL_B3EID5_SIZE 0x1 #define _B3EIDL_B3EID5_LENGTH 0x1 #define _B3EIDL_B3EID5_MASK 0x20 #define _B3EIDL_B3EID6_POSN 0x6 #define _B3EIDL_B3EID6_POSITION 0x6 #define _B3EIDL_B3EID6_SIZE 0x1 #define _B3EIDL_B3EID6_LENGTH 0x1 #define _B3EIDL_B3EID6_MASK 0x40 #define _B3EIDL_B3EID7_POSN 0x7 #define _B3EIDL_B3EID7_POSITION 0x7 #define _B3EIDL_B3EID7_SIZE 0x1 #define _B3EIDL_B3EID7_LENGTH 0x1 #define _B3EIDL_B3EID7_MASK 0x80 // Register: B3DLC #define B3DLC B3DLC extern volatile unsigned char B3DLC @ 0xEB5; #ifndef _LIB_BUILD asm("B3DLC equ 0EB5h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B3DLC0 :1; unsigned B3DLC1 :1; unsigned B3DLC2 :1; unsigned B3DLC3 :1; unsigned B3RB0 :1; unsigned B3RB1 :1; unsigned B3RXRTR :1; }; } B3DLCbits_t; extern volatile B3DLCbits_t B3DLCbits @ 0xEB5; // bitfield macros #define _B3DLC_DLC_POSN 0x0 #define _B3DLC_DLC_POSITION 0x0 #define _B3DLC_DLC_SIZE 0x4 #define _B3DLC_DLC_LENGTH 0x4 #define _B3DLC_DLC_MASK 0xF #define _B3DLC_RB_POSN 0x4 #define _B3DLC_RB_POSITION 0x4 #define _B3DLC_RB_SIZE 0x2 #define _B3DLC_RB_LENGTH 0x2 #define _B3DLC_RB_MASK 0x30 #define _B3DLC_RXRTR_TXRTR_POSN 0x6 #define _B3DLC_RXRTR_TXRTR_POSITION 0x6 #define _B3DLC_RXRTR_TXRTR_SIZE 0x1 #define _B3DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B3DLC_RXRTR_TXRTR_MASK 0x40 #define _B3DLC_DLC0_POSN 0x0 #define _B3DLC_DLC0_POSITION 0x0 #define _B3DLC_DLC0_SIZE 0x1 #define _B3DLC_DLC0_LENGTH 0x1 #define _B3DLC_DLC0_MASK 0x1 #define _B3DLC_DLC1_POSN 0x1 #define _B3DLC_DLC1_POSITION 0x1 #define _B3DLC_DLC1_SIZE 0x1 #define _B3DLC_DLC1_LENGTH 0x1 #define _B3DLC_DLC1_MASK 0x2 #define _B3DLC_DLC2_POSN 0x2 #define _B3DLC_DLC2_POSITION 0x2 #define _B3DLC_DLC2_SIZE 0x1 #define _B3DLC_DLC2_LENGTH 0x1 #define _B3DLC_DLC2_MASK 0x4 #define _B3DLC_DLC3_POSN 0x3 #define _B3DLC_DLC3_POSITION 0x3 #define _B3DLC_DLC3_SIZE 0x1 #define _B3DLC_DLC3_LENGTH 0x1 #define _B3DLC_DLC3_MASK 0x8 #define _B3DLC_RB0_POSN 0x4 #define _B3DLC_RB0_POSITION 0x4 #define _B3DLC_RB0_SIZE 0x1 #define _B3DLC_RB0_LENGTH 0x1 #define _B3DLC_RB0_MASK 0x10 #define _B3DLC_RB1_POSN 0x5 #define _B3DLC_RB1_POSITION 0x5 #define _B3DLC_RB1_SIZE 0x1 #define _B3DLC_RB1_LENGTH 0x1 #define _B3DLC_RB1_MASK 0x20 #define _B3DLC_RXRTR_POSN 0x6 #define _B3DLC_RXRTR_POSITION 0x6 #define _B3DLC_RXRTR_SIZE 0x1 #define _B3DLC_RXRTR_LENGTH 0x1 #define _B3DLC_RXRTR_MASK 0x40 #define _B3DLC_TXRTR_POSN 0x6 #define _B3DLC_TXRTR_POSITION 0x6 #define _B3DLC_TXRTR_SIZE 0x1 #define _B3DLC_TXRTR_LENGTH 0x1 #define _B3DLC_TXRTR_MASK 0x40 #define _B3DLC_B3DLC0_POSN 0x0 #define _B3DLC_B3DLC0_POSITION 0x0 #define _B3DLC_B3DLC0_SIZE 0x1 #define _B3DLC_B3DLC0_LENGTH 0x1 #define _B3DLC_B3DLC0_MASK 0x1 #define _B3DLC_B3DLC1_POSN 0x1 #define _B3DLC_B3DLC1_POSITION 0x1 #define _B3DLC_B3DLC1_SIZE 0x1 #define _B3DLC_B3DLC1_LENGTH 0x1 #define _B3DLC_B3DLC1_MASK 0x2 #define _B3DLC_B3DLC2_POSN 0x2 #define _B3DLC_B3DLC2_POSITION 0x2 #define _B3DLC_B3DLC2_SIZE 0x1 #define _B3DLC_B3DLC2_LENGTH 0x1 #define _B3DLC_B3DLC2_MASK 0x4 #define _B3DLC_B3DLC3_POSN 0x3 #define _B3DLC_B3DLC3_POSITION 0x3 #define _B3DLC_B3DLC3_SIZE 0x1 #define _B3DLC_B3DLC3_LENGTH 0x1 #define _B3DLC_B3DLC3_MASK 0x8 #define _B3DLC_B3RB0_POSN 0x4 #define _B3DLC_B3RB0_POSITION 0x4 #define _B3DLC_B3RB0_SIZE 0x1 #define _B3DLC_B3RB0_LENGTH 0x1 #define _B3DLC_B3RB0_MASK 0x10 #define _B3DLC_B3RB1_POSN 0x5 #define _B3DLC_B3RB1_POSITION 0x5 #define _B3DLC_B3RB1_SIZE 0x1 #define _B3DLC_B3RB1_LENGTH 0x1 #define _B3DLC_B3RB1_MASK 0x20 #define _B3DLC_B3RXRTR_POSN 0x6 #define _B3DLC_B3RXRTR_POSITION 0x6 #define _B3DLC_B3RXRTR_SIZE 0x1 #define _B3DLC_B3RXRTR_LENGTH 0x1 #define _B3DLC_B3RXRTR_MASK 0x40 // Register: B3D0 #define B3D0 B3D0 extern volatile unsigned char B3D0 @ 0xEB6; #ifndef _LIB_BUILD asm("B3D0 equ 0EB6h"); #endif // bitfield definitions typedef union { struct { unsigned B3D0 :8; }; struct { unsigned B3D00 :1; unsigned B3D01 :1; unsigned B3D02 :1; unsigned B3D03 :1; unsigned B3D04 :1; unsigned B3D05 :1; unsigned B3D06 :1; unsigned B3D07 :1; }; } B3D0bits_t; extern volatile B3D0bits_t B3D0bits @ 0xEB6; // bitfield macros #define _B3D0_B3D0_POSN 0x0 #define _B3D0_B3D0_POSITION 0x0 #define _B3D0_B3D0_SIZE 0x8 #define _B3D0_B3D0_LENGTH 0x8 #define _B3D0_B3D0_MASK 0xFF #define _B3D0_B3D00_POSN 0x0 #define _B3D0_B3D00_POSITION 0x0 #define _B3D0_B3D00_SIZE 0x1 #define _B3D0_B3D00_LENGTH 0x1 #define _B3D0_B3D00_MASK 0x1 #define _B3D0_B3D01_POSN 0x1 #define _B3D0_B3D01_POSITION 0x1 #define _B3D0_B3D01_SIZE 0x1 #define _B3D0_B3D01_LENGTH 0x1 #define _B3D0_B3D01_MASK 0x2 #define _B3D0_B3D02_POSN 0x2 #define _B3D0_B3D02_POSITION 0x2 #define _B3D0_B3D02_SIZE 0x1 #define _B3D0_B3D02_LENGTH 0x1 #define _B3D0_B3D02_MASK 0x4 #define _B3D0_B3D03_POSN 0x3 #define _B3D0_B3D03_POSITION 0x3 #define _B3D0_B3D03_SIZE 0x1 #define _B3D0_B3D03_LENGTH 0x1 #define _B3D0_B3D03_MASK 0x8 #define _B3D0_B3D04_POSN 0x4 #define _B3D0_B3D04_POSITION 0x4 #define _B3D0_B3D04_SIZE 0x1 #define _B3D0_B3D04_LENGTH 0x1 #define _B3D0_B3D04_MASK 0x10 #define _B3D0_B3D05_POSN 0x5 #define _B3D0_B3D05_POSITION 0x5 #define _B3D0_B3D05_SIZE 0x1 #define _B3D0_B3D05_LENGTH 0x1 #define _B3D0_B3D05_MASK 0x20 #define _B3D0_B3D06_POSN 0x6 #define _B3D0_B3D06_POSITION 0x6 #define _B3D0_B3D06_SIZE 0x1 #define _B3D0_B3D06_LENGTH 0x1 #define _B3D0_B3D06_MASK 0x40 #define _B3D0_B3D07_POSN 0x7 #define _B3D0_B3D07_POSITION 0x7 #define _B3D0_B3D07_SIZE 0x1 #define _B3D0_B3D07_LENGTH 0x1 #define _B3D0_B3D07_MASK 0x80 // Register: B3D1 #define B3D1 B3D1 extern volatile unsigned char B3D1 @ 0xEB7; #ifndef _LIB_BUILD asm("B3D1 equ 0EB7h"); #endif // bitfield definitions typedef union { struct { unsigned B3D1 :8; }; struct { unsigned B3D10 :1; unsigned B3D11 :1; unsigned B3D12 :1; unsigned B3D13 :1; unsigned B3D14 :1; unsigned B3D15 :1; unsigned B3D16 :1; unsigned B3D17 :1; }; } B3D1bits_t; extern volatile B3D1bits_t B3D1bits @ 0xEB7; // bitfield macros #define _B3D1_B3D1_POSN 0x0 #define _B3D1_B3D1_POSITION 0x0 #define _B3D1_B3D1_SIZE 0x8 #define _B3D1_B3D1_LENGTH 0x8 #define _B3D1_B3D1_MASK 0xFF #define _B3D1_B3D10_POSN 0x0 #define _B3D1_B3D10_POSITION 0x0 #define _B3D1_B3D10_SIZE 0x1 #define _B3D1_B3D10_LENGTH 0x1 #define _B3D1_B3D10_MASK 0x1 #define _B3D1_B3D11_POSN 0x1 #define _B3D1_B3D11_POSITION 0x1 #define _B3D1_B3D11_SIZE 0x1 #define _B3D1_B3D11_LENGTH 0x1 #define _B3D1_B3D11_MASK 0x2 #define _B3D1_B3D12_POSN 0x2 #define _B3D1_B3D12_POSITION 0x2 #define _B3D1_B3D12_SIZE 0x1 #define _B3D1_B3D12_LENGTH 0x1 #define _B3D1_B3D12_MASK 0x4 #define _B3D1_B3D13_POSN 0x3 #define _B3D1_B3D13_POSITION 0x3 #define _B3D1_B3D13_SIZE 0x1 #define _B3D1_B3D13_LENGTH 0x1 #define _B3D1_B3D13_MASK 0x8 #define _B3D1_B3D14_POSN 0x4 #define _B3D1_B3D14_POSITION 0x4 #define _B3D1_B3D14_SIZE 0x1 #define _B3D1_B3D14_LENGTH 0x1 #define _B3D1_B3D14_MASK 0x10 #define _B3D1_B3D15_POSN 0x5 #define _B3D1_B3D15_POSITION 0x5 #define _B3D1_B3D15_SIZE 0x1 #define _B3D1_B3D15_LENGTH 0x1 #define _B3D1_B3D15_MASK 0x20 #define _B3D1_B3D16_POSN 0x6 #define _B3D1_B3D16_POSITION 0x6 #define _B3D1_B3D16_SIZE 0x1 #define _B3D1_B3D16_LENGTH 0x1 #define _B3D1_B3D16_MASK 0x40 #define _B3D1_B3D17_POSN 0x7 #define _B3D1_B3D17_POSITION 0x7 #define _B3D1_B3D17_SIZE 0x1 #define _B3D1_B3D17_LENGTH 0x1 #define _B3D1_B3D17_MASK 0x80 // Register: B3D2 #define B3D2 B3D2 extern volatile unsigned char B3D2 @ 0xEB8; #ifndef _LIB_BUILD asm("B3D2 equ 0EB8h"); #endif // bitfield definitions typedef union { struct { unsigned B3D2 :8; }; struct { unsigned B3D20 :1; unsigned B3D21 :1; unsigned B3D22 :1; unsigned B3D23 :1; unsigned B3D24 :1; unsigned B3D25 :1; unsigned B3D26 :1; unsigned B3D27 :1; }; } B3D2bits_t; extern volatile B3D2bits_t B3D2bits @ 0xEB8; // bitfield macros #define _B3D2_B3D2_POSN 0x0 #define _B3D2_B3D2_POSITION 0x0 #define _B3D2_B3D2_SIZE 0x8 #define _B3D2_B3D2_LENGTH 0x8 #define _B3D2_B3D2_MASK 0xFF #define _B3D2_B3D20_POSN 0x0 #define _B3D2_B3D20_POSITION 0x0 #define _B3D2_B3D20_SIZE 0x1 #define _B3D2_B3D20_LENGTH 0x1 #define _B3D2_B3D20_MASK 0x1 #define _B3D2_B3D21_POSN 0x1 #define _B3D2_B3D21_POSITION 0x1 #define _B3D2_B3D21_SIZE 0x1 #define _B3D2_B3D21_LENGTH 0x1 #define _B3D2_B3D21_MASK 0x2 #define _B3D2_B3D22_POSN 0x2 #define _B3D2_B3D22_POSITION 0x2 #define _B3D2_B3D22_SIZE 0x1 #define _B3D2_B3D22_LENGTH 0x1 #define _B3D2_B3D22_MASK 0x4 #define _B3D2_B3D23_POSN 0x3 #define _B3D2_B3D23_POSITION 0x3 #define _B3D2_B3D23_SIZE 0x1 #define _B3D2_B3D23_LENGTH 0x1 #define _B3D2_B3D23_MASK 0x8 #define _B3D2_B3D24_POSN 0x4 #define _B3D2_B3D24_POSITION 0x4 #define _B3D2_B3D24_SIZE 0x1 #define _B3D2_B3D24_LENGTH 0x1 #define _B3D2_B3D24_MASK 0x10 #define _B3D2_B3D25_POSN 0x5 #define _B3D2_B3D25_POSITION 0x5 #define _B3D2_B3D25_SIZE 0x1 #define _B3D2_B3D25_LENGTH 0x1 #define _B3D2_B3D25_MASK 0x20 #define _B3D2_B3D26_POSN 0x6 #define _B3D2_B3D26_POSITION 0x6 #define _B3D2_B3D26_SIZE 0x1 #define _B3D2_B3D26_LENGTH 0x1 #define _B3D2_B3D26_MASK 0x40 #define _B3D2_B3D27_POSN 0x7 #define _B3D2_B3D27_POSITION 0x7 #define _B3D2_B3D27_SIZE 0x1 #define _B3D2_B3D27_LENGTH 0x1 #define _B3D2_B3D27_MASK 0x80 // Register: B3D3 #define B3D3 B3D3 extern volatile unsigned char B3D3 @ 0xEB9; #ifndef _LIB_BUILD asm("B3D3 equ 0EB9h"); #endif // bitfield definitions typedef union { struct { unsigned B3D3 :8; }; struct { unsigned B3D30 :1; unsigned B3D31 :1; unsigned B3D32 :1; unsigned B3D33 :1; unsigned B3D34 :1; unsigned B3D35 :1; unsigned B3D36 :1; unsigned B3D37 :1; }; } B3D3bits_t; extern volatile B3D3bits_t B3D3bits @ 0xEB9; // bitfield macros #define _B3D3_B3D3_POSN 0x0 #define _B3D3_B3D3_POSITION 0x0 #define _B3D3_B3D3_SIZE 0x8 #define _B3D3_B3D3_LENGTH 0x8 #define _B3D3_B3D3_MASK 0xFF #define _B3D3_B3D30_POSN 0x0 #define _B3D3_B3D30_POSITION 0x0 #define _B3D3_B3D30_SIZE 0x1 #define _B3D3_B3D30_LENGTH 0x1 #define _B3D3_B3D30_MASK 0x1 #define _B3D3_B3D31_POSN 0x1 #define _B3D3_B3D31_POSITION 0x1 #define _B3D3_B3D31_SIZE 0x1 #define _B3D3_B3D31_LENGTH 0x1 #define _B3D3_B3D31_MASK 0x2 #define _B3D3_B3D32_POSN 0x2 #define _B3D3_B3D32_POSITION 0x2 #define _B3D3_B3D32_SIZE 0x1 #define _B3D3_B3D32_LENGTH 0x1 #define _B3D3_B3D32_MASK 0x4 #define _B3D3_B3D33_POSN 0x3 #define _B3D3_B3D33_POSITION 0x3 #define _B3D3_B3D33_SIZE 0x1 #define _B3D3_B3D33_LENGTH 0x1 #define _B3D3_B3D33_MASK 0x8 #define _B3D3_B3D34_POSN 0x4 #define _B3D3_B3D34_POSITION 0x4 #define _B3D3_B3D34_SIZE 0x1 #define _B3D3_B3D34_LENGTH 0x1 #define _B3D3_B3D34_MASK 0x10 #define _B3D3_B3D35_POSN 0x5 #define _B3D3_B3D35_POSITION 0x5 #define _B3D3_B3D35_SIZE 0x1 #define _B3D3_B3D35_LENGTH 0x1 #define _B3D3_B3D35_MASK 0x20 #define _B3D3_B3D36_POSN 0x6 #define _B3D3_B3D36_POSITION 0x6 #define _B3D3_B3D36_SIZE 0x1 #define _B3D3_B3D36_LENGTH 0x1 #define _B3D3_B3D36_MASK 0x40 #define _B3D3_B3D37_POSN 0x7 #define _B3D3_B3D37_POSITION 0x7 #define _B3D3_B3D37_SIZE 0x1 #define _B3D3_B3D37_LENGTH 0x1 #define _B3D3_B3D37_MASK 0x80 // Register: B3D4 #define B3D4 B3D4 extern volatile unsigned char B3D4 @ 0xEBA; #ifndef _LIB_BUILD asm("B3D4 equ 0EBAh"); #endif // bitfield definitions typedef union { struct { unsigned B3D4 :8; }; struct { unsigned B3D40 :1; unsigned B3D41 :1; unsigned B3D42 :1; unsigned B3D43 :1; unsigned B3D44 :1; unsigned B3D45 :1; unsigned B3D46 :1; unsigned B3D47 :1; }; } B3D4bits_t; extern volatile B3D4bits_t B3D4bits @ 0xEBA; // bitfield macros #define _B3D4_B3D4_POSN 0x0 #define _B3D4_B3D4_POSITION 0x0 #define _B3D4_B3D4_SIZE 0x8 #define _B3D4_B3D4_LENGTH 0x8 #define _B3D4_B3D4_MASK 0xFF #define _B3D4_B3D40_POSN 0x0 #define _B3D4_B3D40_POSITION 0x0 #define _B3D4_B3D40_SIZE 0x1 #define _B3D4_B3D40_LENGTH 0x1 #define _B3D4_B3D40_MASK 0x1 #define _B3D4_B3D41_POSN 0x1 #define _B3D4_B3D41_POSITION 0x1 #define _B3D4_B3D41_SIZE 0x1 #define _B3D4_B3D41_LENGTH 0x1 #define _B3D4_B3D41_MASK 0x2 #define _B3D4_B3D42_POSN 0x2 #define _B3D4_B3D42_POSITION 0x2 #define _B3D4_B3D42_SIZE 0x1 #define _B3D4_B3D42_LENGTH 0x1 #define _B3D4_B3D42_MASK 0x4 #define _B3D4_B3D43_POSN 0x3 #define _B3D4_B3D43_POSITION 0x3 #define _B3D4_B3D43_SIZE 0x1 #define _B3D4_B3D43_LENGTH 0x1 #define _B3D4_B3D43_MASK 0x8 #define _B3D4_B3D44_POSN 0x4 #define _B3D4_B3D44_POSITION 0x4 #define _B3D4_B3D44_SIZE 0x1 #define _B3D4_B3D44_LENGTH 0x1 #define _B3D4_B3D44_MASK 0x10 #define _B3D4_B3D45_POSN 0x5 #define _B3D4_B3D45_POSITION 0x5 #define _B3D4_B3D45_SIZE 0x1 #define _B3D4_B3D45_LENGTH 0x1 #define _B3D4_B3D45_MASK 0x20 #define _B3D4_B3D46_POSN 0x6 #define _B3D4_B3D46_POSITION 0x6 #define _B3D4_B3D46_SIZE 0x1 #define _B3D4_B3D46_LENGTH 0x1 #define _B3D4_B3D46_MASK 0x40 #define _B3D4_B3D47_POSN 0x7 #define _B3D4_B3D47_POSITION 0x7 #define _B3D4_B3D47_SIZE 0x1 #define _B3D4_B3D47_LENGTH 0x1 #define _B3D4_B3D47_MASK 0x80 // Register: B3D5 #define B3D5 B3D5 extern volatile unsigned char B3D5 @ 0xEBB; #ifndef _LIB_BUILD asm("B3D5 equ 0EBBh"); #endif // bitfield definitions typedef union { struct { unsigned B3D5 :8; }; struct { unsigned B3D50 :1; unsigned B3D51 :1; unsigned B3D52 :1; unsigned B3D53 :1; unsigned B3D54 :1; unsigned B3D55 :1; unsigned B3D56 :1; unsigned B3D57 :1; }; } B3D5bits_t; extern volatile B3D5bits_t B3D5bits @ 0xEBB; // bitfield macros #define _B3D5_B3D5_POSN 0x0 #define _B3D5_B3D5_POSITION 0x0 #define _B3D5_B3D5_SIZE 0x8 #define _B3D5_B3D5_LENGTH 0x8 #define _B3D5_B3D5_MASK 0xFF #define _B3D5_B3D50_POSN 0x0 #define _B3D5_B3D50_POSITION 0x0 #define _B3D5_B3D50_SIZE 0x1 #define _B3D5_B3D50_LENGTH 0x1 #define _B3D5_B3D50_MASK 0x1 #define _B3D5_B3D51_POSN 0x1 #define _B3D5_B3D51_POSITION 0x1 #define _B3D5_B3D51_SIZE 0x1 #define _B3D5_B3D51_LENGTH 0x1 #define _B3D5_B3D51_MASK 0x2 #define _B3D5_B3D52_POSN 0x2 #define _B3D5_B3D52_POSITION 0x2 #define _B3D5_B3D52_SIZE 0x1 #define _B3D5_B3D52_LENGTH 0x1 #define _B3D5_B3D52_MASK 0x4 #define _B3D5_B3D53_POSN 0x3 #define _B3D5_B3D53_POSITION 0x3 #define _B3D5_B3D53_SIZE 0x1 #define _B3D5_B3D53_LENGTH 0x1 #define _B3D5_B3D53_MASK 0x8 #define _B3D5_B3D54_POSN 0x4 #define _B3D5_B3D54_POSITION 0x4 #define _B3D5_B3D54_SIZE 0x1 #define _B3D5_B3D54_LENGTH 0x1 #define _B3D5_B3D54_MASK 0x10 #define _B3D5_B3D55_POSN 0x5 #define _B3D5_B3D55_POSITION 0x5 #define _B3D5_B3D55_SIZE 0x1 #define _B3D5_B3D55_LENGTH 0x1 #define _B3D5_B3D55_MASK 0x20 #define _B3D5_B3D56_POSN 0x6 #define _B3D5_B3D56_POSITION 0x6 #define _B3D5_B3D56_SIZE 0x1 #define _B3D5_B3D56_LENGTH 0x1 #define _B3D5_B3D56_MASK 0x40 #define _B3D5_B3D57_POSN 0x7 #define _B3D5_B3D57_POSITION 0x7 #define _B3D5_B3D57_SIZE 0x1 #define _B3D5_B3D57_LENGTH 0x1 #define _B3D5_B3D57_MASK 0x80 // Register: B3D6 #define B3D6 B3D6 extern volatile unsigned char B3D6 @ 0xEBC; #ifndef _LIB_BUILD asm("B3D6 equ 0EBCh"); #endif // bitfield definitions typedef union { struct { unsigned B3D6 :8; }; struct { unsigned B3D60 :1; unsigned B3D61 :1; unsigned B3D62 :1; unsigned B3D63 :1; unsigned B3D64 :1; unsigned B3D65 :1; unsigned B3D66 :1; unsigned B3D67 :1; }; } B3D6bits_t; extern volatile B3D6bits_t B3D6bits @ 0xEBC; // bitfield macros #define _B3D6_B3D6_POSN 0x0 #define _B3D6_B3D6_POSITION 0x0 #define _B3D6_B3D6_SIZE 0x8 #define _B3D6_B3D6_LENGTH 0x8 #define _B3D6_B3D6_MASK 0xFF #define _B3D6_B3D60_POSN 0x0 #define _B3D6_B3D60_POSITION 0x0 #define _B3D6_B3D60_SIZE 0x1 #define _B3D6_B3D60_LENGTH 0x1 #define _B3D6_B3D60_MASK 0x1 #define _B3D6_B3D61_POSN 0x1 #define _B3D6_B3D61_POSITION 0x1 #define _B3D6_B3D61_SIZE 0x1 #define _B3D6_B3D61_LENGTH 0x1 #define _B3D6_B3D61_MASK 0x2 #define _B3D6_B3D62_POSN 0x2 #define _B3D6_B3D62_POSITION 0x2 #define _B3D6_B3D62_SIZE 0x1 #define _B3D6_B3D62_LENGTH 0x1 #define _B3D6_B3D62_MASK 0x4 #define _B3D6_B3D63_POSN 0x3 #define _B3D6_B3D63_POSITION 0x3 #define _B3D6_B3D63_SIZE 0x1 #define _B3D6_B3D63_LENGTH 0x1 #define _B3D6_B3D63_MASK 0x8 #define _B3D6_B3D64_POSN 0x4 #define _B3D6_B3D64_POSITION 0x4 #define _B3D6_B3D64_SIZE 0x1 #define _B3D6_B3D64_LENGTH 0x1 #define _B3D6_B3D64_MASK 0x10 #define _B3D6_B3D65_POSN 0x5 #define _B3D6_B3D65_POSITION 0x5 #define _B3D6_B3D65_SIZE 0x1 #define _B3D6_B3D65_LENGTH 0x1 #define _B3D6_B3D65_MASK 0x20 #define _B3D6_B3D66_POSN 0x6 #define _B3D6_B3D66_POSITION 0x6 #define _B3D6_B3D66_SIZE 0x1 #define _B3D6_B3D66_LENGTH 0x1 #define _B3D6_B3D66_MASK 0x40 #define _B3D6_B3D67_POSN 0x7 #define _B3D6_B3D67_POSITION 0x7 #define _B3D6_B3D67_SIZE 0x1 #define _B3D6_B3D67_LENGTH 0x1 #define _B3D6_B3D67_MASK 0x80 // Register: B3D7 #define B3D7 B3D7 extern volatile unsigned char B3D7 @ 0xEBD; #ifndef _LIB_BUILD asm("B3D7 equ 0EBDh"); #endif // bitfield definitions typedef union { struct { unsigned B3D7 :8; }; struct { unsigned B3D70 :1; unsigned B3D71 :1; unsigned B3D72 :1; unsigned B3D73 :1; unsigned B3D74 :1; unsigned B3D75 :1; unsigned B3D76 :1; unsigned B3D77 :1; }; } B3D7bits_t; extern volatile B3D7bits_t B3D7bits @ 0xEBD; // bitfield macros #define _B3D7_B3D7_POSN 0x0 #define _B3D7_B3D7_POSITION 0x0 #define _B3D7_B3D7_SIZE 0x8 #define _B3D7_B3D7_LENGTH 0x8 #define _B3D7_B3D7_MASK 0xFF #define _B3D7_B3D70_POSN 0x0 #define _B3D7_B3D70_POSITION 0x0 #define _B3D7_B3D70_SIZE 0x1 #define _B3D7_B3D70_LENGTH 0x1 #define _B3D7_B3D70_MASK 0x1 #define _B3D7_B3D71_POSN 0x1 #define _B3D7_B3D71_POSITION 0x1 #define _B3D7_B3D71_SIZE 0x1 #define _B3D7_B3D71_LENGTH 0x1 #define _B3D7_B3D71_MASK 0x2 #define _B3D7_B3D72_POSN 0x2 #define _B3D7_B3D72_POSITION 0x2 #define _B3D7_B3D72_SIZE 0x1 #define _B3D7_B3D72_LENGTH 0x1 #define _B3D7_B3D72_MASK 0x4 #define _B3D7_B3D73_POSN 0x3 #define _B3D7_B3D73_POSITION 0x3 #define _B3D7_B3D73_SIZE 0x1 #define _B3D7_B3D73_LENGTH 0x1 #define _B3D7_B3D73_MASK 0x8 #define _B3D7_B3D74_POSN 0x4 #define _B3D7_B3D74_POSITION 0x4 #define _B3D7_B3D74_SIZE 0x1 #define _B3D7_B3D74_LENGTH 0x1 #define _B3D7_B3D74_MASK 0x10 #define _B3D7_B3D75_POSN 0x5 #define _B3D7_B3D75_POSITION 0x5 #define _B3D7_B3D75_SIZE 0x1 #define _B3D7_B3D75_LENGTH 0x1 #define _B3D7_B3D75_MASK 0x20 #define _B3D7_B3D76_POSN 0x6 #define _B3D7_B3D76_POSITION 0x6 #define _B3D7_B3D76_SIZE 0x1 #define _B3D7_B3D76_LENGTH 0x1 #define _B3D7_B3D76_MASK 0x40 #define _B3D7_B3D77_POSN 0x7 #define _B3D7_B3D77_POSITION 0x7 #define _B3D7_B3D77_SIZE 0x1 #define _B3D7_B3D77_LENGTH 0x1 #define _B3D7_B3D77_MASK 0x80 // Register: CANSTAT_RO6 #define CANSTAT_RO6 CANSTAT_RO6 extern volatile unsigned char CANSTAT_RO6 @ 0xEBE; #ifndef _LIB_BUILD asm("CANSTAT_RO6 equ 0EBEh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO6bits_t; extern volatile CANSTAT_RO6bits_t CANSTAT_RO6bits @ 0xEBE; // bitfield macros #define _CANSTAT_RO6_EICODE0_POSN 0x0 #define _CANSTAT_RO6_EICODE0_POSITION 0x0 #define _CANSTAT_RO6_EICODE0_SIZE 0x1 #define _CANSTAT_RO6_EICODE0_LENGTH 0x1 #define _CANSTAT_RO6_EICODE0_MASK 0x1 #define _CANSTAT_RO6_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO6_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO6_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO6_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO6_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO6_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO6_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO6_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO6_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO6_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO6_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO6_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO6_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO6_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO6_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO6_EICODE4_POSN 0x4 #define _CANSTAT_RO6_EICODE4_POSITION 0x4 #define _CANSTAT_RO6_EICODE4_SIZE 0x1 #define _CANSTAT_RO6_EICODE4_LENGTH 0x1 #define _CANSTAT_RO6_EICODE4_MASK 0x10 #define _CANSTAT_RO6_OPMODE_POSN 0x5 #define _CANSTAT_RO6_OPMODE_POSITION 0x5 #define _CANSTAT_RO6_OPMODE_SIZE 0x3 #define _CANSTAT_RO6_OPMODE_LENGTH 0x3 #define _CANSTAT_RO6_OPMODE_MASK 0xE0 #define _CANSTAT_RO6_EICODE1_POSN 0x1 #define _CANSTAT_RO6_EICODE1_POSITION 0x1 #define _CANSTAT_RO6_EICODE1_SIZE 0x1 #define _CANSTAT_RO6_EICODE1_LENGTH 0x1 #define _CANSTAT_RO6_EICODE1_MASK 0x2 #define _CANSTAT_RO6_EICODE2_POSN 0x2 #define _CANSTAT_RO6_EICODE2_POSITION 0x2 #define _CANSTAT_RO6_EICODE2_SIZE 0x1 #define _CANSTAT_RO6_EICODE2_LENGTH 0x1 #define _CANSTAT_RO6_EICODE2_MASK 0x4 #define _CANSTAT_RO6_EICODE3_POSN 0x3 #define _CANSTAT_RO6_EICODE3_POSITION 0x3 #define _CANSTAT_RO6_EICODE3_SIZE 0x1 #define _CANSTAT_RO6_EICODE3_LENGTH 0x1 #define _CANSTAT_RO6_EICODE3_MASK 0x8 #define _CANSTAT_RO6_OPMODE0_POSN 0x5 #define _CANSTAT_RO6_OPMODE0_POSITION 0x5 #define _CANSTAT_RO6_OPMODE0_SIZE 0x1 #define _CANSTAT_RO6_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO6_OPMODE0_MASK 0x20 #define _CANSTAT_RO6_OPMODE1_POSN 0x6 #define _CANSTAT_RO6_OPMODE1_POSITION 0x6 #define _CANSTAT_RO6_OPMODE1_SIZE 0x1 #define _CANSTAT_RO6_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO6_OPMODE1_MASK 0x40 #define _CANSTAT_RO6_OPMODE2_POSN 0x7 #define _CANSTAT_RO6_OPMODE2_POSITION 0x7 #define _CANSTAT_RO6_OPMODE2_SIZE 0x1 #define _CANSTAT_RO6_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO6_OPMODE2_MASK 0x80 #define _CANSTAT_RO6_ICODE0_POSN 0x1 #define _CANSTAT_RO6_ICODE0_POSITION 0x1 #define _CANSTAT_RO6_ICODE0_SIZE 0x1 #define _CANSTAT_RO6_ICODE0_LENGTH 0x1 #define _CANSTAT_RO6_ICODE0_MASK 0x2 #define _CANSTAT_RO6_ICODE1_POSN 0x2 #define _CANSTAT_RO6_ICODE1_POSITION 0x2 #define _CANSTAT_RO6_ICODE1_SIZE 0x1 #define _CANSTAT_RO6_ICODE1_LENGTH 0x1 #define _CANSTAT_RO6_ICODE1_MASK 0x4 #define _CANSTAT_RO6_ICODE2_POSN 0x3 #define _CANSTAT_RO6_ICODE2_POSITION 0x3 #define _CANSTAT_RO6_ICODE2_SIZE 0x1 #define _CANSTAT_RO6_ICODE2_LENGTH 0x1 #define _CANSTAT_RO6_ICODE2_MASK 0x8 // Register: CANCON_RO6 #define CANCON_RO6 CANCON_RO6 extern volatile unsigned char CANCON_RO6 @ 0xEBF; #ifndef _LIB_BUILD asm("CANCON_RO6 equ 0EBFh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO6bits_t; extern volatile CANCON_RO6bits_t CANCON_RO6bits @ 0xEBF; // bitfield macros #define _CANCON_RO6_FP0_POSN 0x0 #define _CANCON_RO6_FP0_POSITION 0x0 #define _CANCON_RO6_FP0_SIZE 0x1 #define _CANCON_RO6_FP0_LENGTH 0x1 #define _CANCON_RO6_FP0_MASK 0x1 #define _CANCON_RO6_WIN0_FP1_POSN 0x1 #define _CANCON_RO6_WIN0_FP1_POSITION 0x1 #define _CANCON_RO6_WIN0_FP1_SIZE 0x1 #define _CANCON_RO6_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO6_WIN0_FP1_MASK 0x2 #define _CANCON_RO6_WIN1_FP2_POSN 0x2 #define _CANCON_RO6_WIN1_FP2_POSITION 0x2 #define _CANCON_RO6_WIN1_FP2_SIZE 0x1 #define _CANCON_RO6_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO6_WIN1_FP2_MASK 0x4 #define _CANCON_RO6_WIN2_FP3_POSN 0x3 #define _CANCON_RO6_WIN2_FP3_POSITION 0x3 #define _CANCON_RO6_WIN2_FP3_SIZE 0x1 #define _CANCON_RO6_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO6_WIN2_FP3_MASK 0x8 #define _CANCON_RO6_ABAT_POSN 0x4 #define _CANCON_RO6_ABAT_POSITION 0x4 #define _CANCON_RO6_ABAT_SIZE 0x1 #define _CANCON_RO6_ABAT_LENGTH 0x1 #define _CANCON_RO6_ABAT_MASK 0x10 #define _CANCON_RO6_REQOP_POSN 0x5 #define _CANCON_RO6_REQOP_POSITION 0x5 #define _CANCON_RO6_REQOP_SIZE 0x3 #define _CANCON_RO6_REQOP_LENGTH 0x3 #define _CANCON_RO6_REQOP_MASK 0xE0 #define _CANCON_RO6_WIN0_POSN 0x1 #define _CANCON_RO6_WIN0_POSITION 0x1 #define _CANCON_RO6_WIN0_SIZE 0x1 #define _CANCON_RO6_WIN0_LENGTH 0x1 #define _CANCON_RO6_WIN0_MASK 0x2 #define _CANCON_RO6_WIN1_POSN 0x2 #define _CANCON_RO6_WIN1_POSITION 0x2 #define _CANCON_RO6_WIN1_SIZE 0x1 #define _CANCON_RO6_WIN1_LENGTH 0x1 #define _CANCON_RO6_WIN1_MASK 0x4 #define _CANCON_RO6_WIN2_POSN 0x3 #define _CANCON_RO6_WIN2_POSITION 0x3 #define _CANCON_RO6_WIN2_SIZE 0x1 #define _CANCON_RO6_WIN2_LENGTH 0x1 #define _CANCON_RO6_WIN2_MASK 0x8 #define _CANCON_RO6_FP1_POSN 0x1 #define _CANCON_RO6_FP1_POSITION 0x1 #define _CANCON_RO6_FP1_SIZE 0x1 #define _CANCON_RO6_FP1_LENGTH 0x1 #define _CANCON_RO6_FP1_MASK 0x2 #define _CANCON_RO6_FP2_POSN 0x2 #define _CANCON_RO6_FP2_POSITION 0x2 #define _CANCON_RO6_FP2_SIZE 0x1 #define _CANCON_RO6_FP2_LENGTH 0x1 #define _CANCON_RO6_FP2_MASK 0x4 #define _CANCON_RO6_FP3_POSN 0x3 #define _CANCON_RO6_FP3_POSITION 0x3 #define _CANCON_RO6_FP3_SIZE 0x1 #define _CANCON_RO6_FP3_LENGTH 0x1 #define _CANCON_RO6_FP3_MASK 0x8 // Register: B4CON #define B4CON B4CON extern volatile unsigned char B4CON @ 0xEC0; #ifndef _LIB_BUILD asm("B4CON equ 0EC0h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B4FILHIT0 :1; unsigned B4FILHIT1 :1; unsigned B4FILHIT2 :1; unsigned B4FILHIT3 :1; unsigned B4FILHIT4 :1; unsigned B4RTRRO :1; unsigned B4RXM1 :1; unsigned B4RXFUL :1; }; struct { unsigned B4TXPRI0 :1; unsigned B4TXPRI1 :1; unsigned B4RTREN :1; unsigned B4TXREQ :1; unsigned B4TXERR :1; unsigned B4TXLARB :1; unsigned B4TXABT :1; unsigned B4TXB3IF :1; }; } B4CONbits_t; extern volatile B4CONbits_t B4CONbits @ 0xEC0; // bitfield macros #define _B4CON_FILHIT0_TXPRI0_POSN 0x0 #define _B4CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B4CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B4CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B4CON_FILHIT0_TXPRI0_MASK 0x1 #define _B4CON_FILHIT1_TXPRI1_POSN 0x1 #define _B4CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B4CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B4CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B4CON_FILHIT1_TXPRI1_MASK 0x2 #define _B4CON_FILHIT2_RTREN_POSN 0x2 #define _B4CON_FILHIT2_RTREN_POSITION 0x2 #define _B4CON_FILHIT2_RTREN_SIZE 0x1 #define _B4CON_FILHIT2_RTREN_LENGTH 0x1 #define _B4CON_FILHIT2_RTREN_MASK 0x4 #define _B4CON_FILHIT3_TXREQ_POSN 0x3 #define _B4CON_FILHIT3_TXREQ_POSITION 0x3 #define _B4CON_FILHIT3_TXREQ_SIZE 0x1 #define _B4CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B4CON_FILHIT3_TXREQ_MASK 0x8 #define _B4CON_FILHIT4_TXERR_POSN 0x4 #define _B4CON_FILHIT4_TXERR_POSITION 0x4 #define _B4CON_FILHIT4_TXERR_SIZE 0x1 #define _B4CON_FILHIT4_TXERR_LENGTH 0x1 #define _B4CON_FILHIT4_TXERR_MASK 0x10 #define _B4CON_RXRTRRO_TXLARB_POSN 0x5 #define _B4CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B4CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B4CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B4CON_RXRTRRO_TXLARB_MASK 0x20 #define _B4CON_RXM1_TXABT_POSN 0x6 #define _B4CON_RXM1_TXABT_POSITION 0x6 #define _B4CON_RXM1_TXABT_SIZE 0x1 #define _B4CON_RXM1_TXABT_LENGTH 0x1 #define _B4CON_RXM1_TXABT_MASK 0x40 #define _B4CON_RXFUL_TXBIF_POSN 0x7 #define _B4CON_RXFUL_TXBIF_POSITION 0x7 #define _B4CON_RXFUL_TXBIF_SIZE 0x1 #define _B4CON_RXFUL_TXBIF_LENGTH 0x1 #define _B4CON_RXFUL_TXBIF_MASK 0x80 #define _B4CON_FILHIT0_POSN 0x0 #define _B4CON_FILHIT0_POSITION 0x0 #define _B4CON_FILHIT0_SIZE 0x1 #define _B4CON_FILHIT0_LENGTH 0x1 #define _B4CON_FILHIT0_MASK 0x1 #define _B4CON_FILHIT1_POSN 0x1 #define _B4CON_FILHIT1_POSITION 0x1 #define _B4CON_FILHIT1_SIZE 0x1 #define _B4CON_FILHIT1_LENGTH 0x1 #define _B4CON_FILHIT1_MASK 0x2 #define _B4CON_FILHIT2_POSN 0x2 #define _B4CON_FILHIT2_POSITION 0x2 #define _B4CON_FILHIT2_SIZE 0x1 #define _B4CON_FILHIT2_LENGTH 0x1 #define _B4CON_FILHIT2_MASK 0x4 #define _B4CON_FILHIT3_POSN 0x3 #define _B4CON_FILHIT3_POSITION 0x3 #define _B4CON_FILHIT3_SIZE 0x1 #define _B4CON_FILHIT3_LENGTH 0x1 #define _B4CON_FILHIT3_MASK 0x8 #define _B4CON_FILHIT4_POSN 0x4 #define _B4CON_FILHIT4_POSITION 0x4 #define _B4CON_FILHIT4_SIZE 0x1 #define _B4CON_FILHIT4_LENGTH 0x1 #define _B4CON_FILHIT4_MASK 0x10 #define _B4CON_RXRTRRO_POSN 0x5 #define _B4CON_RXRTRRO_POSITION 0x5 #define _B4CON_RXRTRRO_SIZE 0x1 #define _B4CON_RXRTRRO_LENGTH 0x1 #define _B4CON_RXRTRRO_MASK 0x20 #define _B4CON_RXM1_POSN 0x6 #define _B4CON_RXM1_POSITION 0x6 #define _B4CON_RXM1_SIZE 0x1 #define _B4CON_RXM1_LENGTH 0x1 #define _B4CON_RXM1_MASK 0x40 #define _B4CON_RXFUL_POSN 0x7 #define _B4CON_RXFUL_POSITION 0x7 #define _B4CON_RXFUL_SIZE 0x1 #define _B4CON_RXFUL_LENGTH 0x1 #define _B4CON_RXFUL_MASK 0x80 #define _B4CON_TXPRI0_POSN 0x0 #define _B4CON_TXPRI0_POSITION 0x0 #define _B4CON_TXPRI0_SIZE 0x1 #define _B4CON_TXPRI0_LENGTH 0x1 #define _B4CON_TXPRI0_MASK 0x1 #define _B4CON_TXPRI1_POSN 0x1 #define _B4CON_TXPRI1_POSITION 0x1 #define _B4CON_TXPRI1_SIZE 0x1 #define _B4CON_TXPRI1_LENGTH 0x1 #define _B4CON_TXPRI1_MASK 0x2 #define _B4CON_RTREN_POSN 0x2 #define _B4CON_RTREN_POSITION 0x2 #define _B4CON_RTREN_SIZE 0x1 #define _B4CON_RTREN_LENGTH 0x1 #define _B4CON_RTREN_MASK 0x4 #define _B4CON_TXREQ_POSN 0x3 #define _B4CON_TXREQ_POSITION 0x3 #define _B4CON_TXREQ_SIZE 0x1 #define _B4CON_TXREQ_LENGTH 0x1 #define _B4CON_TXREQ_MASK 0x8 #define _B4CON_TXERR_POSN 0x4 #define _B4CON_TXERR_POSITION 0x4 #define _B4CON_TXERR_SIZE 0x1 #define _B4CON_TXERR_LENGTH 0x1 #define _B4CON_TXERR_MASK 0x10 #define _B4CON_TXLARB_POSN 0x5 #define _B4CON_TXLARB_POSITION 0x5 #define _B4CON_TXLARB_SIZE 0x1 #define _B4CON_TXLARB_LENGTH 0x1 #define _B4CON_TXLARB_MASK 0x20 #define _B4CON_TXABT_POSN 0x6 #define _B4CON_TXABT_POSITION 0x6 #define _B4CON_TXABT_SIZE 0x1 #define _B4CON_TXABT_LENGTH 0x1 #define _B4CON_TXABT_MASK 0x40 #define _B4CON_TXBIF_POSN 0x7 #define _B4CON_TXBIF_POSITION 0x7 #define _B4CON_TXBIF_SIZE 0x1 #define _B4CON_TXBIF_LENGTH 0x1 #define _B4CON_TXBIF_MASK 0x80 #define _B4CON_B4FILHIT0_POSN 0x0 #define _B4CON_B4FILHIT0_POSITION 0x0 #define _B4CON_B4FILHIT0_SIZE 0x1 #define _B4CON_B4FILHIT0_LENGTH 0x1 #define _B4CON_B4FILHIT0_MASK 0x1 #define _B4CON_B4FILHIT1_POSN 0x1 #define _B4CON_B4FILHIT1_POSITION 0x1 #define _B4CON_B4FILHIT1_SIZE 0x1 #define _B4CON_B4FILHIT1_LENGTH 0x1 #define _B4CON_B4FILHIT1_MASK 0x2 #define _B4CON_B4FILHIT2_POSN 0x2 #define _B4CON_B4FILHIT2_POSITION 0x2 #define _B4CON_B4FILHIT2_SIZE 0x1 #define _B4CON_B4FILHIT2_LENGTH 0x1 #define _B4CON_B4FILHIT2_MASK 0x4 #define _B4CON_B4FILHIT3_POSN 0x3 #define _B4CON_B4FILHIT3_POSITION 0x3 #define _B4CON_B4FILHIT3_SIZE 0x1 #define _B4CON_B4FILHIT3_LENGTH 0x1 #define _B4CON_B4FILHIT3_MASK 0x8 #define _B4CON_B4FILHIT4_POSN 0x4 #define _B4CON_B4FILHIT4_POSITION 0x4 #define _B4CON_B4FILHIT4_SIZE 0x1 #define _B4CON_B4FILHIT4_LENGTH 0x1 #define _B4CON_B4FILHIT4_MASK 0x10 #define _B4CON_B4RTRRO_POSN 0x5 #define _B4CON_B4RTRRO_POSITION 0x5 #define _B4CON_B4RTRRO_SIZE 0x1 #define _B4CON_B4RTRRO_LENGTH 0x1 #define _B4CON_B4RTRRO_MASK 0x20 #define _B4CON_B4RXM1_POSN 0x6 #define _B4CON_B4RXM1_POSITION 0x6 #define _B4CON_B4RXM1_SIZE 0x1 #define _B4CON_B4RXM1_LENGTH 0x1 #define _B4CON_B4RXM1_MASK 0x40 #define _B4CON_B4RXFUL_POSN 0x7 #define _B4CON_B4RXFUL_POSITION 0x7 #define _B4CON_B4RXFUL_SIZE 0x1 #define _B4CON_B4RXFUL_LENGTH 0x1 #define _B4CON_B4RXFUL_MASK 0x80 #define _B4CON_B4TXPRI0_POSN 0x0 #define _B4CON_B4TXPRI0_POSITION 0x0 #define _B4CON_B4TXPRI0_SIZE 0x1 #define _B4CON_B4TXPRI0_LENGTH 0x1 #define _B4CON_B4TXPRI0_MASK 0x1 #define _B4CON_B4TXPRI1_POSN 0x1 #define _B4CON_B4TXPRI1_POSITION 0x1 #define _B4CON_B4TXPRI1_SIZE 0x1 #define _B4CON_B4TXPRI1_LENGTH 0x1 #define _B4CON_B4TXPRI1_MASK 0x2 #define _B4CON_B4RTREN_POSN 0x2 #define _B4CON_B4RTREN_POSITION 0x2 #define _B4CON_B4RTREN_SIZE 0x1 #define _B4CON_B4RTREN_LENGTH 0x1 #define _B4CON_B4RTREN_MASK 0x4 #define _B4CON_B4TXREQ_POSN 0x3 #define _B4CON_B4TXREQ_POSITION 0x3 #define _B4CON_B4TXREQ_SIZE 0x1 #define _B4CON_B4TXREQ_LENGTH 0x1 #define _B4CON_B4TXREQ_MASK 0x8 #define _B4CON_B4TXERR_POSN 0x4 #define _B4CON_B4TXERR_POSITION 0x4 #define _B4CON_B4TXERR_SIZE 0x1 #define _B4CON_B4TXERR_LENGTH 0x1 #define _B4CON_B4TXERR_MASK 0x10 #define _B4CON_B4TXLARB_POSN 0x5 #define _B4CON_B4TXLARB_POSITION 0x5 #define _B4CON_B4TXLARB_SIZE 0x1 #define _B4CON_B4TXLARB_LENGTH 0x1 #define _B4CON_B4TXLARB_MASK 0x20 #define _B4CON_B4TXABT_POSN 0x6 #define _B4CON_B4TXABT_POSITION 0x6 #define _B4CON_B4TXABT_SIZE 0x1 #define _B4CON_B4TXABT_LENGTH 0x1 #define _B4CON_B4TXABT_MASK 0x40 #define _B4CON_B4TXB3IF_POSN 0x7 #define _B4CON_B4TXB3IF_POSITION 0x7 #define _B4CON_B4TXB3IF_SIZE 0x1 #define _B4CON_B4TXB3IF_LENGTH 0x1 #define _B4CON_B4TXB3IF_MASK 0x80 // Register: B4SIDH #define B4SIDH B4SIDH extern volatile unsigned char B4SIDH @ 0xEC1; #ifndef _LIB_BUILD asm("B4SIDH equ 0EC1h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B4SID3 :1; unsigned B4SID4 :1; unsigned B4SID5 :1; unsigned B4SID6 :1; unsigned B4SID7 :1; unsigned B4SID8 :1; unsigned B4SID9 :1; unsigned B4SID10 :1; }; } B4SIDHbits_t; extern volatile B4SIDHbits_t B4SIDHbits @ 0xEC1; // bitfield macros #define _B4SIDH_SID_POSN 0x0 #define _B4SIDH_SID_POSITION 0x0 #define _B4SIDH_SID_SIZE 0x8 #define _B4SIDH_SID_LENGTH 0x8 #define _B4SIDH_SID_MASK 0xFF #define _B4SIDH_SID3_POSN 0x0 #define _B4SIDH_SID3_POSITION 0x0 #define _B4SIDH_SID3_SIZE 0x1 #define _B4SIDH_SID3_LENGTH 0x1 #define _B4SIDH_SID3_MASK 0x1 #define _B4SIDH_SID4_POSN 0x1 #define _B4SIDH_SID4_POSITION 0x1 #define _B4SIDH_SID4_SIZE 0x1 #define _B4SIDH_SID4_LENGTH 0x1 #define _B4SIDH_SID4_MASK 0x2 #define _B4SIDH_SID5_POSN 0x2 #define _B4SIDH_SID5_POSITION 0x2 #define _B4SIDH_SID5_SIZE 0x1 #define _B4SIDH_SID5_LENGTH 0x1 #define _B4SIDH_SID5_MASK 0x4 #define _B4SIDH_SID6_POSN 0x3 #define _B4SIDH_SID6_POSITION 0x3 #define _B4SIDH_SID6_SIZE 0x1 #define _B4SIDH_SID6_LENGTH 0x1 #define _B4SIDH_SID6_MASK 0x8 #define _B4SIDH_SID7_POSN 0x4 #define _B4SIDH_SID7_POSITION 0x4 #define _B4SIDH_SID7_SIZE 0x1 #define _B4SIDH_SID7_LENGTH 0x1 #define _B4SIDH_SID7_MASK 0x10 #define _B4SIDH_SID8_POSN 0x5 #define _B4SIDH_SID8_POSITION 0x5 #define _B4SIDH_SID8_SIZE 0x1 #define _B4SIDH_SID8_LENGTH 0x1 #define _B4SIDH_SID8_MASK 0x20 #define _B4SIDH_SID9_POSN 0x6 #define _B4SIDH_SID9_POSITION 0x6 #define _B4SIDH_SID9_SIZE 0x1 #define _B4SIDH_SID9_LENGTH 0x1 #define _B4SIDH_SID9_MASK 0x40 #define _B4SIDH_SID10_POSN 0x7 #define _B4SIDH_SID10_POSITION 0x7 #define _B4SIDH_SID10_SIZE 0x1 #define _B4SIDH_SID10_LENGTH 0x1 #define _B4SIDH_SID10_MASK 0x80 #define _B4SIDH_B4SID3_POSN 0x0 #define _B4SIDH_B4SID3_POSITION 0x0 #define _B4SIDH_B4SID3_SIZE 0x1 #define _B4SIDH_B4SID3_LENGTH 0x1 #define _B4SIDH_B4SID3_MASK 0x1 #define _B4SIDH_B4SID4_POSN 0x1 #define _B4SIDH_B4SID4_POSITION 0x1 #define _B4SIDH_B4SID4_SIZE 0x1 #define _B4SIDH_B4SID4_LENGTH 0x1 #define _B4SIDH_B4SID4_MASK 0x2 #define _B4SIDH_B4SID5_POSN 0x2 #define _B4SIDH_B4SID5_POSITION 0x2 #define _B4SIDH_B4SID5_SIZE 0x1 #define _B4SIDH_B4SID5_LENGTH 0x1 #define _B4SIDH_B4SID5_MASK 0x4 #define _B4SIDH_B4SID6_POSN 0x3 #define _B4SIDH_B4SID6_POSITION 0x3 #define _B4SIDH_B4SID6_SIZE 0x1 #define _B4SIDH_B4SID6_LENGTH 0x1 #define _B4SIDH_B4SID6_MASK 0x8 #define _B4SIDH_B4SID7_POSN 0x4 #define _B4SIDH_B4SID7_POSITION 0x4 #define _B4SIDH_B4SID7_SIZE 0x1 #define _B4SIDH_B4SID7_LENGTH 0x1 #define _B4SIDH_B4SID7_MASK 0x10 #define _B4SIDH_B4SID8_POSN 0x5 #define _B4SIDH_B4SID8_POSITION 0x5 #define _B4SIDH_B4SID8_SIZE 0x1 #define _B4SIDH_B4SID8_LENGTH 0x1 #define _B4SIDH_B4SID8_MASK 0x20 #define _B4SIDH_B4SID9_POSN 0x6 #define _B4SIDH_B4SID9_POSITION 0x6 #define _B4SIDH_B4SID9_SIZE 0x1 #define _B4SIDH_B4SID9_LENGTH 0x1 #define _B4SIDH_B4SID9_MASK 0x40 #define _B4SIDH_B4SID10_POSN 0x7 #define _B4SIDH_B4SID10_POSITION 0x7 #define _B4SIDH_B4SID10_SIZE 0x1 #define _B4SIDH_B4SID10_LENGTH 0x1 #define _B4SIDH_B4SID10_MASK 0x80 // Register: B4SIDL #define B4SIDL B4SIDL extern volatile unsigned char B4SIDL @ 0xEC2; #ifndef _LIB_BUILD asm("B4SIDL equ 0EC2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B4EID16 :1; unsigned B4EID17 :1; unsigned :1; unsigned B4EXID :1; unsigned B4SRR :1; unsigned B4SID0 :1; unsigned B4SID1 :1; unsigned B4SID2 :1; }; struct { unsigned :3; unsigned B4EXIDE :1; }; } B4SIDLbits_t; extern volatile B4SIDLbits_t B4SIDLbits @ 0xEC2; // bitfield macros #define _B4SIDL_EID_POSN 0x0 #define _B4SIDL_EID_POSITION 0x0 #define _B4SIDL_EID_SIZE 0x2 #define _B4SIDL_EID_LENGTH 0x2 #define _B4SIDL_EID_MASK 0x3 #define _B4SIDL_EXIDE_POSN 0x3 #define _B4SIDL_EXIDE_POSITION 0x3 #define _B4SIDL_EXIDE_SIZE 0x1 #define _B4SIDL_EXIDE_LENGTH 0x1 #define _B4SIDL_EXIDE_MASK 0x8 #define _B4SIDL_SRR_POSN 0x4 #define _B4SIDL_SRR_POSITION 0x4 #define _B4SIDL_SRR_SIZE 0x1 #define _B4SIDL_SRR_LENGTH 0x1 #define _B4SIDL_SRR_MASK 0x10 #define _B4SIDL_SID_POSN 0x5 #define _B4SIDL_SID_POSITION 0x5 #define _B4SIDL_SID_SIZE 0x3 #define _B4SIDL_SID_LENGTH 0x3 #define _B4SIDL_SID_MASK 0xE0 #define _B4SIDL_EID16_POSN 0x0 #define _B4SIDL_EID16_POSITION 0x0 #define _B4SIDL_EID16_SIZE 0x1 #define _B4SIDL_EID16_LENGTH 0x1 #define _B4SIDL_EID16_MASK 0x1 #define _B4SIDL_EID17_POSN 0x1 #define _B4SIDL_EID17_POSITION 0x1 #define _B4SIDL_EID17_SIZE 0x1 #define _B4SIDL_EID17_LENGTH 0x1 #define _B4SIDL_EID17_MASK 0x2 #define _B4SIDL_SID0_POSN 0x5 #define _B4SIDL_SID0_POSITION 0x5 #define _B4SIDL_SID0_SIZE 0x1 #define _B4SIDL_SID0_LENGTH 0x1 #define _B4SIDL_SID0_MASK 0x20 #define _B4SIDL_SID1_POSN 0x6 #define _B4SIDL_SID1_POSITION 0x6 #define _B4SIDL_SID1_SIZE 0x1 #define _B4SIDL_SID1_LENGTH 0x1 #define _B4SIDL_SID1_MASK 0x40 #define _B4SIDL_SID2_POSN 0x7 #define _B4SIDL_SID2_POSITION 0x7 #define _B4SIDL_SID2_SIZE 0x1 #define _B4SIDL_SID2_LENGTH 0x1 #define _B4SIDL_SID2_MASK 0x80 #define _B4SIDL_B4EID16_POSN 0x0 #define _B4SIDL_B4EID16_POSITION 0x0 #define _B4SIDL_B4EID16_SIZE 0x1 #define _B4SIDL_B4EID16_LENGTH 0x1 #define _B4SIDL_B4EID16_MASK 0x1 #define _B4SIDL_B4EID17_POSN 0x1 #define _B4SIDL_B4EID17_POSITION 0x1 #define _B4SIDL_B4EID17_SIZE 0x1 #define _B4SIDL_B4EID17_LENGTH 0x1 #define _B4SIDL_B4EID17_MASK 0x2 #define _B4SIDL_B4EXID_POSN 0x3 #define _B4SIDL_B4EXID_POSITION 0x3 #define _B4SIDL_B4EXID_SIZE 0x1 #define _B4SIDL_B4EXID_LENGTH 0x1 #define _B4SIDL_B4EXID_MASK 0x8 #define _B4SIDL_B4SRR_POSN 0x4 #define _B4SIDL_B4SRR_POSITION 0x4 #define _B4SIDL_B4SRR_SIZE 0x1 #define _B4SIDL_B4SRR_LENGTH 0x1 #define _B4SIDL_B4SRR_MASK 0x10 #define _B4SIDL_B4SID0_POSN 0x5 #define _B4SIDL_B4SID0_POSITION 0x5 #define _B4SIDL_B4SID0_SIZE 0x1 #define _B4SIDL_B4SID0_LENGTH 0x1 #define _B4SIDL_B4SID0_MASK 0x20 #define _B4SIDL_B4SID1_POSN 0x6 #define _B4SIDL_B4SID1_POSITION 0x6 #define _B4SIDL_B4SID1_SIZE 0x1 #define _B4SIDL_B4SID1_LENGTH 0x1 #define _B4SIDL_B4SID1_MASK 0x40 #define _B4SIDL_B4SID2_POSN 0x7 #define _B4SIDL_B4SID2_POSITION 0x7 #define _B4SIDL_B4SID2_SIZE 0x1 #define _B4SIDL_B4SID2_LENGTH 0x1 #define _B4SIDL_B4SID2_MASK 0x80 #define _B4SIDL_B4EXIDE_POSN 0x3 #define _B4SIDL_B4EXIDE_POSITION 0x3 #define _B4SIDL_B4EXIDE_SIZE 0x1 #define _B4SIDL_B4EXIDE_LENGTH 0x1 #define _B4SIDL_B4EXIDE_MASK 0x8 // Register: B4EIDH #define B4EIDH B4EIDH extern volatile unsigned char B4EIDH @ 0xEC3; #ifndef _LIB_BUILD asm("B4EIDH equ 0EC3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B4EID8 :1; unsigned B4EID9 :1; unsigned B4EID10 :1; unsigned B4EID11 :1; unsigned B4EID12 :1; unsigned B4EID13 :1; unsigned B4EID14 :1; unsigned B4EID15 :1; }; } B4EIDHbits_t; extern volatile B4EIDHbits_t B4EIDHbits @ 0xEC3; // bitfield macros #define _B4EIDH_EID_POSN 0x0 #define _B4EIDH_EID_POSITION 0x0 #define _B4EIDH_EID_SIZE 0x8 #define _B4EIDH_EID_LENGTH 0x8 #define _B4EIDH_EID_MASK 0xFF #define _B4EIDH_EID8_POSN 0x0 #define _B4EIDH_EID8_POSITION 0x0 #define _B4EIDH_EID8_SIZE 0x1 #define _B4EIDH_EID8_LENGTH 0x1 #define _B4EIDH_EID8_MASK 0x1 #define _B4EIDH_EID9_POSN 0x1 #define _B4EIDH_EID9_POSITION 0x1 #define _B4EIDH_EID9_SIZE 0x1 #define _B4EIDH_EID9_LENGTH 0x1 #define _B4EIDH_EID9_MASK 0x2 #define _B4EIDH_EID10_POSN 0x2 #define _B4EIDH_EID10_POSITION 0x2 #define _B4EIDH_EID10_SIZE 0x1 #define _B4EIDH_EID10_LENGTH 0x1 #define _B4EIDH_EID10_MASK 0x4 #define _B4EIDH_EID11_POSN 0x3 #define _B4EIDH_EID11_POSITION 0x3 #define _B4EIDH_EID11_SIZE 0x1 #define _B4EIDH_EID11_LENGTH 0x1 #define _B4EIDH_EID11_MASK 0x8 #define _B4EIDH_EID12_POSN 0x4 #define _B4EIDH_EID12_POSITION 0x4 #define _B4EIDH_EID12_SIZE 0x1 #define _B4EIDH_EID12_LENGTH 0x1 #define _B4EIDH_EID12_MASK 0x10 #define _B4EIDH_EID13_POSN 0x5 #define _B4EIDH_EID13_POSITION 0x5 #define _B4EIDH_EID13_SIZE 0x1 #define _B4EIDH_EID13_LENGTH 0x1 #define _B4EIDH_EID13_MASK 0x20 #define _B4EIDH_EID14_POSN 0x6 #define _B4EIDH_EID14_POSITION 0x6 #define _B4EIDH_EID14_SIZE 0x1 #define _B4EIDH_EID14_LENGTH 0x1 #define _B4EIDH_EID14_MASK 0x40 #define _B4EIDH_EID15_POSN 0x7 #define _B4EIDH_EID15_POSITION 0x7 #define _B4EIDH_EID15_SIZE 0x1 #define _B4EIDH_EID15_LENGTH 0x1 #define _B4EIDH_EID15_MASK 0x80 #define _B4EIDH_B4EID8_POSN 0x0 #define _B4EIDH_B4EID8_POSITION 0x0 #define _B4EIDH_B4EID8_SIZE 0x1 #define _B4EIDH_B4EID8_LENGTH 0x1 #define _B4EIDH_B4EID8_MASK 0x1 #define _B4EIDH_B4EID9_POSN 0x1 #define _B4EIDH_B4EID9_POSITION 0x1 #define _B4EIDH_B4EID9_SIZE 0x1 #define _B4EIDH_B4EID9_LENGTH 0x1 #define _B4EIDH_B4EID9_MASK 0x2 #define _B4EIDH_B4EID10_POSN 0x2 #define _B4EIDH_B4EID10_POSITION 0x2 #define _B4EIDH_B4EID10_SIZE 0x1 #define _B4EIDH_B4EID10_LENGTH 0x1 #define _B4EIDH_B4EID10_MASK 0x4 #define _B4EIDH_B4EID11_POSN 0x3 #define _B4EIDH_B4EID11_POSITION 0x3 #define _B4EIDH_B4EID11_SIZE 0x1 #define _B4EIDH_B4EID11_LENGTH 0x1 #define _B4EIDH_B4EID11_MASK 0x8 #define _B4EIDH_B4EID12_POSN 0x4 #define _B4EIDH_B4EID12_POSITION 0x4 #define _B4EIDH_B4EID12_SIZE 0x1 #define _B4EIDH_B4EID12_LENGTH 0x1 #define _B4EIDH_B4EID12_MASK 0x10 #define _B4EIDH_B4EID13_POSN 0x5 #define _B4EIDH_B4EID13_POSITION 0x5 #define _B4EIDH_B4EID13_SIZE 0x1 #define _B4EIDH_B4EID13_LENGTH 0x1 #define _B4EIDH_B4EID13_MASK 0x20 #define _B4EIDH_B4EID14_POSN 0x6 #define _B4EIDH_B4EID14_POSITION 0x6 #define _B4EIDH_B4EID14_SIZE 0x1 #define _B4EIDH_B4EID14_LENGTH 0x1 #define _B4EIDH_B4EID14_MASK 0x40 #define _B4EIDH_B4EID15_POSN 0x7 #define _B4EIDH_B4EID15_POSITION 0x7 #define _B4EIDH_B4EID15_SIZE 0x1 #define _B4EIDH_B4EID15_LENGTH 0x1 #define _B4EIDH_B4EID15_MASK 0x80 // Register: B4EIDL #define B4EIDL B4EIDL extern volatile unsigned char B4EIDL @ 0xEC4; #ifndef _LIB_BUILD asm("B4EIDL equ 0EC4h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B4EID0 :1; unsigned B4EID1 :1; unsigned B4EID2 :1; unsigned B4EID3 :1; unsigned B4EID4 :1; unsigned B4EID5 :1; unsigned B4EID6 :1; unsigned B4EID7 :1; }; } B4EIDLbits_t; extern volatile B4EIDLbits_t B4EIDLbits @ 0xEC4; // bitfield macros #define _B4EIDL_EID_POSN 0x0 #define _B4EIDL_EID_POSITION 0x0 #define _B4EIDL_EID_SIZE 0x8 #define _B4EIDL_EID_LENGTH 0x8 #define _B4EIDL_EID_MASK 0xFF #define _B4EIDL_EID0_POSN 0x0 #define _B4EIDL_EID0_POSITION 0x0 #define _B4EIDL_EID0_SIZE 0x1 #define _B4EIDL_EID0_LENGTH 0x1 #define _B4EIDL_EID0_MASK 0x1 #define _B4EIDL_EID1_POSN 0x1 #define _B4EIDL_EID1_POSITION 0x1 #define _B4EIDL_EID1_SIZE 0x1 #define _B4EIDL_EID1_LENGTH 0x1 #define _B4EIDL_EID1_MASK 0x2 #define _B4EIDL_EID2_POSN 0x2 #define _B4EIDL_EID2_POSITION 0x2 #define _B4EIDL_EID2_SIZE 0x1 #define _B4EIDL_EID2_LENGTH 0x1 #define _B4EIDL_EID2_MASK 0x4 #define _B4EIDL_EID3_POSN 0x3 #define _B4EIDL_EID3_POSITION 0x3 #define _B4EIDL_EID3_SIZE 0x1 #define _B4EIDL_EID3_LENGTH 0x1 #define _B4EIDL_EID3_MASK 0x8 #define _B4EIDL_EID4_POSN 0x4 #define _B4EIDL_EID4_POSITION 0x4 #define _B4EIDL_EID4_SIZE 0x1 #define _B4EIDL_EID4_LENGTH 0x1 #define _B4EIDL_EID4_MASK 0x10 #define _B4EIDL_EID5_POSN 0x5 #define _B4EIDL_EID5_POSITION 0x5 #define _B4EIDL_EID5_SIZE 0x1 #define _B4EIDL_EID5_LENGTH 0x1 #define _B4EIDL_EID5_MASK 0x20 #define _B4EIDL_EID6_POSN 0x6 #define _B4EIDL_EID6_POSITION 0x6 #define _B4EIDL_EID6_SIZE 0x1 #define _B4EIDL_EID6_LENGTH 0x1 #define _B4EIDL_EID6_MASK 0x40 #define _B4EIDL_EID7_POSN 0x7 #define _B4EIDL_EID7_POSITION 0x7 #define _B4EIDL_EID7_SIZE 0x1 #define _B4EIDL_EID7_LENGTH 0x1 #define _B4EIDL_EID7_MASK 0x80 #define _B4EIDL_B4EID0_POSN 0x0 #define _B4EIDL_B4EID0_POSITION 0x0 #define _B4EIDL_B4EID0_SIZE 0x1 #define _B4EIDL_B4EID0_LENGTH 0x1 #define _B4EIDL_B4EID0_MASK 0x1 #define _B4EIDL_B4EID1_POSN 0x1 #define _B4EIDL_B4EID1_POSITION 0x1 #define _B4EIDL_B4EID1_SIZE 0x1 #define _B4EIDL_B4EID1_LENGTH 0x1 #define _B4EIDL_B4EID1_MASK 0x2 #define _B4EIDL_B4EID2_POSN 0x2 #define _B4EIDL_B4EID2_POSITION 0x2 #define _B4EIDL_B4EID2_SIZE 0x1 #define _B4EIDL_B4EID2_LENGTH 0x1 #define _B4EIDL_B4EID2_MASK 0x4 #define _B4EIDL_B4EID3_POSN 0x3 #define _B4EIDL_B4EID3_POSITION 0x3 #define _B4EIDL_B4EID3_SIZE 0x1 #define _B4EIDL_B4EID3_LENGTH 0x1 #define _B4EIDL_B4EID3_MASK 0x8 #define _B4EIDL_B4EID4_POSN 0x4 #define _B4EIDL_B4EID4_POSITION 0x4 #define _B4EIDL_B4EID4_SIZE 0x1 #define _B4EIDL_B4EID4_LENGTH 0x1 #define _B4EIDL_B4EID4_MASK 0x10 #define _B4EIDL_B4EID5_POSN 0x5 #define _B4EIDL_B4EID5_POSITION 0x5 #define _B4EIDL_B4EID5_SIZE 0x1 #define _B4EIDL_B4EID5_LENGTH 0x1 #define _B4EIDL_B4EID5_MASK 0x20 #define _B4EIDL_B4EID6_POSN 0x6 #define _B4EIDL_B4EID6_POSITION 0x6 #define _B4EIDL_B4EID6_SIZE 0x1 #define _B4EIDL_B4EID6_LENGTH 0x1 #define _B4EIDL_B4EID6_MASK 0x40 #define _B4EIDL_B4EID7_POSN 0x7 #define _B4EIDL_B4EID7_POSITION 0x7 #define _B4EIDL_B4EID7_SIZE 0x1 #define _B4EIDL_B4EID7_LENGTH 0x1 #define _B4EIDL_B4EID7_MASK 0x80 // Register: B4DLC #define B4DLC B4DLC extern volatile unsigned char B4DLC @ 0xEC5; #ifndef _LIB_BUILD asm("B4DLC equ 0EC5h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B4DLC0 :1; unsigned B4DLC1 :1; unsigned B4DLC2 :1; unsigned B4DLC3 :1; unsigned B4RB0 :1; unsigned B4RB1 :1; unsigned B4RXRTR :1; }; } B4DLCbits_t; extern volatile B4DLCbits_t B4DLCbits @ 0xEC5; // bitfield macros #define _B4DLC_DLC_POSN 0x0 #define _B4DLC_DLC_POSITION 0x0 #define _B4DLC_DLC_SIZE 0x4 #define _B4DLC_DLC_LENGTH 0x4 #define _B4DLC_DLC_MASK 0xF #define _B4DLC_RB_POSN 0x4 #define _B4DLC_RB_POSITION 0x4 #define _B4DLC_RB_SIZE 0x2 #define _B4DLC_RB_LENGTH 0x2 #define _B4DLC_RB_MASK 0x30 #define _B4DLC_RXRTR_TXRTR_POSN 0x6 #define _B4DLC_RXRTR_TXRTR_POSITION 0x6 #define _B4DLC_RXRTR_TXRTR_SIZE 0x1 #define _B4DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B4DLC_RXRTR_TXRTR_MASK 0x40 #define _B4DLC_DLC0_POSN 0x0 #define _B4DLC_DLC0_POSITION 0x0 #define _B4DLC_DLC0_SIZE 0x1 #define _B4DLC_DLC0_LENGTH 0x1 #define _B4DLC_DLC0_MASK 0x1 #define _B4DLC_DLC1_POSN 0x1 #define _B4DLC_DLC1_POSITION 0x1 #define _B4DLC_DLC1_SIZE 0x1 #define _B4DLC_DLC1_LENGTH 0x1 #define _B4DLC_DLC1_MASK 0x2 #define _B4DLC_DLC2_POSN 0x2 #define _B4DLC_DLC2_POSITION 0x2 #define _B4DLC_DLC2_SIZE 0x1 #define _B4DLC_DLC2_LENGTH 0x1 #define _B4DLC_DLC2_MASK 0x4 #define _B4DLC_DLC3_POSN 0x3 #define _B4DLC_DLC3_POSITION 0x3 #define _B4DLC_DLC3_SIZE 0x1 #define _B4DLC_DLC3_LENGTH 0x1 #define _B4DLC_DLC3_MASK 0x8 #define _B4DLC_RB0_POSN 0x4 #define _B4DLC_RB0_POSITION 0x4 #define _B4DLC_RB0_SIZE 0x1 #define _B4DLC_RB0_LENGTH 0x1 #define _B4DLC_RB0_MASK 0x10 #define _B4DLC_RB1_POSN 0x5 #define _B4DLC_RB1_POSITION 0x5 #define _B4DLC_RB1_SIZE 0x1 #define _B4DLC_RB1_LENGTH 0x1 #define _B4DLC_RB1_MASK 0x20 #define _B4DLC_RXRTR_POSN 0x6 #define _B4DLC_RXRTR_POSITION 0x6 #define _B4DLC_RXRTR_SIZE 0x1 #define _B4DLC_RXRTR_LENGTH 0x1 #define _B4DLC_RXRTR_MASK 0x40 #define _B4DLC_TXRTR_POSN 0x6 #define _B4DLC_TXRTR_POSITION 0x6 #define _B4DLC_TXRTR_SIZE 0x1 #define _B4DLC_TXRTR_LENGTH 0x1 #define _B4DLC_TXRTR_MASK 0x40 #define _B4DLC_B4DLC0_POSN 0x0 #define _B4DLC_B4DLC0_POSITION 0x0 #define _B4DLC_B4DLC0_SIZE 0x1 #define _B4DLC_B4DLC0_LENGTH 0x1 #define _B4DLC_B4DLC0_MASK 0x1 #define _B4DLC_B4DLC1_POSN 0x1 #define _B4DLC_B4DLC1_POSITION 0x1 #define _B4DLC_B4DLC1_SIZE 0x1 #define _B4DLC_B4DLC1_LENGTH 0x1 #define _B4DLC_B4DLC1_MASK 0x2 #define _B4DLC_B4DLC2_POSN 0x2 #define _B4DLC_B4DLC2_POSITION 0x2 #define _B4DLC_B4DLC2_SIZE 0x1 #define _B4DLC_B4DLC2_LENGTH 0x1 #define _B4DLC_B4DLC2_MASK 0x4 #define _B4DLC_B4DLC3_POSN 0x3 #define _B4DLC_B4DLC3_POSITION 0x3 #define _B4DLC_B4DLC3_SIZE 0x1 #define _B4DLC_B4DLC3_LENGTH 0x1 #define _B4DLC_B4DLC3_MASK 0x8 #define _B4DLC_B4RB0_POSN 0x4 #define _B4DLC_B4RB0_POSITION 0x4 #define _B4DLC_B4RB0_SIZE 0x1 #define _B4DLC_B4RB0_LENGTH 0x1 #define _B4DLC_B4RB0_MASK 0x10 #define _B4DLC_B4RB1_POSN 0x5 #define _B4DLC_B4RB1_POSITION 0x5 #define _B4DLC_B4RB1_SIZE 0x1 #define _B4DLC_B4RB1_LENGTH 0x1 #define _B4DLC_B4RB1_MASK 0x20 #define _B4DLC_B4RXRTR_POSN 0x6 #define _B4DLC_B4RXRTR_POSITION 0x6 #define _B4DLC_B4RXRTR_SIZE 0x1 #define _B4DLC_B4RXRTR_LENGTH 0x1 #define _B4DLC_B4RXRTR_MASK 0x40 // Register: B4D0 #define B4D0 B4D0 extern volatile unsigned char B4D0 @ 0xEC6; #ifndef _LIB_BUILD asm("B4D0 equ 0EC6h"); #endif // bitfield definitions typedef union { struct { unsigned B4D0 :8; }; struct { unsigned B4D00 :1; unsigned B4D01 :1; unsigned B4D02 :1; unsigned B4D03 :1; unsigned B4D04 :1; unsigned B4D05 :1; unsigned B4D06 :1; unsigned B4D07 :1; }; } B4D0bits_t; extern volatile B4D0bits_t B4D0bits @ 0xEC6; // bitfield macros #define _B4D0_B4D0_POSN 0x0 #define _B4D0_B4D0_POSITION 0x0 #define _B4D0_B4D0_SIZE 0x8 #define _B4D0_B4D0_LENGTH 0x8 #define _B4D0_B4D0_MASK 0xFF #define _B4D0_B4D00_POSN 0x0 #define _B4D0_B4D00_POSITION 0x0 #define _B4D0_B4D00_SIZE 0x1 #define _B4D0_B4D00_LENGTH 0x1 #define _B4D0_B4D00_MASK 0x1 #define _B4D0_B4D01_POSN 0x1 #define _B4D0_B4D01_POSITION 0x1 #define _B4D0_B4D01_SIZE 0x1 #define _B4D0_B4D01_LENGTH 0x1 #define _B4D0_B4D01_MASK 0x2 #define _B4D0_B4D02_POSN 0x2 #define _B4D0_B4D02_POSITION 0x2 #define _B4D0_B4D02_SIZE 0x1 #define _B4D0_B4D02_LENGTH 0x1 #define _B4D0_B4D02_MASK 0x4 #define _B4D0_B4D03_POSN 0x3 #define _B4D0_B4D03_POSITION 0x3 #define _B4D0_B4D03_SIZE 0x1 #define _B4D0_B4D03_LENGTH 0x1 #define _B4D0_B4D03_MASK 0x8 #define _B4D0_B4D04_POSN 0x4 #define _B4D0_B4D04_POSITION 0x4 #define _B4D0_B4D04_SIZE 0x1 #define _B4D0_B4D04_LENGTH 0x1 #define _B4D0_B4D04_MASK 0x10 #define _B4D0_B4D05_POSN 0x5 #define _B4D0_B4D05_POSITION 0x5 #define _B4D0_B4D05_SIZE 0x1 #define _B4D0_B4D05_LENGTH 0x1 #define _B4D0_B4D05_MASK 0x20 #define _B4D0_B4D06_POSN 0x6 #define _B4D0_B4D06_POSITION 0x6 #define _B4D0_B4D06_SIZE 0x1 #define _B4D0_B4D06_LENGTH 0x1 #define _B4D0_B4D06_MASK 0x40 #define _B4D0_B4D07_POSN 0x7 #define _B4D0_B4D07_POSITION 0x7 #define _B4D0_B4D07_SIZE 0x1 #define _B4D0_B4D07_LENGTH 0x1 #define _B4D0_B4D07_MASK 0x80 // Register: B4D1 #define B4D1 B4D1 extern volatile unsigned char B4D1 @ 0xEC7; #ifndef _LIB_BUILD asm("B4D1 equ 0EC7h"); #endif // bitfield definitions typedef union { struct { unsigned B4D1 :8; }; struct { unsigned B4D10 :1; unsigned B4D11 :1; unsigned B4D12 :1; unsigned B4D13 :1; unsigned B4D14 :1; unsigned B4D15 :1; unsigned B4D16 :1; unsigned B4D17 :1; }; } B4D1bits_t; extern volatile B4D1bits_t B4D1bits @ 0xEC7; // bitfield macros #define _B4D1_B4D1_POSN 0x0 #define _B4D1_B4D1_POSITION 0x0 #define _B4D1_B4D1_SIZE 0x8 #define _B4D1_B4D1_LENGTH 0x8 #define _B4D1_B4D1_MASK 0xFF #define _B4D1_B4D10_POSN 0x0 #define _B4D1_B4D10_POSITION 0x0 #define _B4D1_B4D10_SIZE 0x1 #define _B4D1_B4D10_LENGTH 0x1 #define _B4D1_B4D10_MASK 0x1 #define _B4D1_B4D11_POSN 0x1 #define _B4D1_B4D11_POSITION 0x1 #define _B4D1_B4D11_SIZE 0x1 #define _B4D1_B4D11_LENGTH 0x1 #define _B4D1_B4D11_MASK 0x2 #define _B4D1_B4D12_POSN 0x2 #define _B4D1_B4D12_POSITION 0x2 #define _B4D1_B4D12_SIZE 0x1 #define _B4D1_B4D12_LENGTH 0x1 #define _B4D1_B4D12_MASK 0x4 #define _B4D1_B4D13_POSN 0x3 #define _B4D1_B4D13_POSITION 0x3 #define _B4D1_B4D13_SIZE 0x1 #define _B4D1_B4D13_LENGTH 0x1 #define _B4D1_B4D13_MASK 0x8 #define _B4D1_B4D14_POSN 0x4 #define _B4D1_B4D14_POSITION 0x4 #define _B4D1_B4D14_SIZE 0x1 #define _B4D1_B4D14_LENGTH 0x1 #define _B4D1_B4D14_MASK 0x10 #define _B4D1_B4D15_POSN 0x5 #define _B4D1_B4D15_POSITION 0x5 #define _B4D1_B4D15_SIZE 0x1 #define _B4D1_B4D15_LENGTH 0x1 #define _B4D1_B4D15_MASK 0x20 #define _B4D1_B4D16_POSN 0x6 #define _B4D1_B4D16_POSITION 0x6 #define _B4D1_B4D16_SIZE 0x1 #define _B4D1_B4D16_LENGTH 0x1 #define _B4D1_B4D16_MASK 0x40 #define _B4D1_B4D17_POSN 0x7 #define _B4D1_B4D17_POSITION 0x7 #define _B4D1_B4D17_SIZE 0x1 #define _B4D1_B4D17_LENGTH 0x1 #define _B4D1_B4D17_MASK 0x80 // Register: B4D2 #define B4D2 B4D2 extern volatile unsigned char B4D2 @ 0xEC8; #ifndef _LIB_BUILD asm("B4D2 equ 0EC8h"); #endif // bitfield definitions typedef union { struct { unsigned B4D2 :8; }; struct { unsigned B4D20 :1; unsigned B4D21 :1; unsigned B4D22 :1; unsigned B4D23 :1; unsigned B4D24 :1; unsigned B4D25 :1; unsigned B4D26 :1; unsigned B4D27 :1; }; } B4D2bits_t; extern volatile B4D2bits_t B4D2bits @ 0xEC8; // bitfield macros #define _B4D2_B4D2_POSN 0x0 #define _B4D2_B4D2_POSITION 0x0 #define _B4D2_B4D2_SIZE 0x8 #define _B4D2_B4D2_LENGTH 0x8 #define _B4D2_B4D2_MASK 0xFF #define _B4D2_B4D20_POSN 0x0 #define _B4D2_B4D20_POSITION 0x0 #define _B4D2_B4D20_SIZE 0x1 #define _B4D2_B4D20_LENGTH 0x1 #define _B4D2_B4D20_MASK 0x1 #define _B4D2_B4D21_POSN 0x1 #define _B4D2_B4D21_POSITION 0x1 #define _B4D2_B4D21_SIZE 0x1 #define _B4D2_B4D21_LENGTH 0x1 #define _B4D2_B4D21_MASK 0x2 #define _B4D2_B4D22_POSN 0x2 #define _B4D2_B4D22_POSITION 0x2 #define _B4D2_B4D22_SIZE 0x1 #define _B4D2_B4D22_LENGTH 0x1 #define _B4D2_B4D22_MASK 0x4 #define _B4D2_B4D23_POSN 0x3 #define _B4D2_B4D23_POSITION 0x3 #define _B4D2_B4D23_SIZE 0x1 #define _B4D2_B4D23_LENGTH 0x1 #define _B4D2_B4D23_MASK 0x8 #define _B4D2_B4D24_POSN 0x4 #define _B4D2_B4D24_POSITION 0x4 #define _B4D2_B4D24_SIZE 0x1 #define _B4D2_B4D24_LENGTH 0x1 #define _B4D2_B4D24_MASK 0x10 #define _B4D2_B4D25_POSN 0x5 #define _B4D2_B4D25_POSITION 0x5 #define _B4D2_B4D25_SIZE 0x1 #define _B4D2_B4D25_LENGTH 0x1 #define _B4D2_B4D25_MASK 0x20 #define _B4D2_B4D26_POSN 0x6 #define _B4D2_B4D26_POSITION 0x6 #define _B4D2_B4D26_SIZE 0x1 #define _B4D2_B4D26_LENGTH 0x1 #define _B4D2_B4D26_MASK 0x40 #define _B4D2_B4D27_POSN 0x7 #define _B4D2_B4D27_POSITION 0x7 #define _B4D2_B4D27_SIZE 0x1 #define _B4D2_B4D27_LENGTH 0x1 #define _B4D2_B4D27_MASK 0x80 // Register: B4D3 #define B4D3 B4D3 extern volatile unsigned char B4D3 @ 0xEC9; #ifndef _LIB_BUILD asm("B4D3 equ 0EC9h"); #endif // bitfield definitions typedef union { struct { unsigned B4D3 :8; }; struct { unsigned B4D30 :1; unsigned B4D31 :1; unsigned B4D32 :1; unsigned B4D33 :1; unsigned B4D34 :1; unsigned B4D35 :1; unsigned B4D36 :1; unsigned B4D37 :1; }; } B4D3bits_t; extern volatile B4D3bits_t B4D3bits @ 0xEC9; // bitfield macros #define _B4D3_B4D3_POSN 0x0 #define _B4D3_B4D3_POSITION 0x0 #define _B4D3_B4D3_SIZE 0x8 #define _B4D3_B4D3_LENGTH 0x8 #define _B4D3_B4D3_MASK 0xFF #define _B4D3_B4D30_POSN 0x0 #define _B4D3_B4D30_POSITION 0x0 #define _B4D3_B4D30_SIZE 0x1 #define _B4D3_B4D30_LENGTH 0x1 #define _B4D3_B4D30_MASK 0x1 #define _B4D3_B4D31_POSN 0x1 #define _B4D3_B4D31_POSITION 0x1 #define _B4D3_B4D31_SIZE 0x1 #define _B4D3_B4D31_LENGTH 0x1 #define _B4D3_B4D31_MASK 0x2 #define _B4D3_B4D32_POSN 0x2 #define _B4D3_B4D32_POSITION 0x2 #define _B4D3_B4D32_SIZE 0x1 #define _B4D3_B4D32_LENGTH 0x1 #define _B4D3_B4D32_MASK 0x4 #define _B4D3_B4D33_POSN 0x3 #define _B4D3_B4D33_POSITION 0x3 #define _B4D3_B4D33_SIZE 0x1 #define _B4D3_B4D33_LENGTH 0x1 #define _B4D3_B4D33_MASK 0x8 #define _B4D3_B4D34_POSN 0x4 #define _B4D3_B4D34_POSITION 0x4 #define _B4D3_B4D34_SIZE 0x1 #define _B4D3_B4D34_LENGTH 0x1 #define _B4D3_B4D34_MASK 0x10 #define _B4D3_B4D35_POSN 0x5 #define _B4D3_B4D35_POSITION 0x5 #define _B4D3_B4D35_SIZE 0x1 #define _B4D3_B4D35_LENGTH 0x1 #define _B4D3_B4D35_MASK 0x20 #define _B4D3_B4D36_POSN 0x6 #define _B4D3_B4D36_POSITION 0x6 #define _B4D3_B4D36_SIZE 0x1 #define _B4D3_B4D36_LENGTH 0x1 #define _B4D3_B4D36_MASK 0x40 #define _B4D3_B4D37_POSN 0x7 #define _B4D3_B4D37_POSITION 0x7 #define _B4D3_B4D37_SIZE 0x1 #define _B4D3_B4D37_LENGTH 0x1 #define _B4D3_B4D37_MASK 0x80 // Register: B4D4 #define B4D4 B4D4 extern volatile unsigned char B4D4 @ 0xECA; #ifndef _LIB_BUILD asm("B4D4 equ 0ECAh"); #endif // bitfield definitions typedef union { struct { unsigned B4D4 :8; }; struct { unsigned B4D40 :1; unsigned B4D41 :1; unsigned B4D42 :1; unsigned B4D43 :1; unsigned B4D44 :1; unsigned B4D45 :1; unsigned B4D46 :1; unsigned B4D47 :1; }; } B4D4bits_t; extern volatile B4D4bits_t B4D4bits @ 0xECA; // bitfield macros #define _B4D4_B4D4_POSN 0x0 #define _B4D4_B4D4_POSITION 0x0 #define _B4D4_B4D4_SIZE 0x8 #define _B4D4_B4D4_LENGTH 0x8 #define _B4D4_B4D4_MASK 0xFF #define _B4D4_B4D40_POSN 0x0 #define _B4D4_B4D40_POSITION 0x0 #define _B4D4_B4D40_SIZE 0x1 #define _B4D4_B4D40_LENGTH 0x1 #define _B4D4_B4D40_MASK 0x1 #define _B4D4_B4D41_POSN 0x1 #define _B4D4_B4D41_POSITION 0x1 #define _B4D4_B4D41_SIZE 0x1 #define _B4D4_B4D41_LENGTH 0x1 #define _B4D4_B4D41_MASK 0x2 #define _B4D4_B4D42_POSN 0x2 #define _B4D4_B4D42_POSITION 0x2 #define _B4D4_B4D42_SIZE 0x1 #define _B4D4_B4D42_LENGTH 0x1 #define _B4D4_B4D42_MASK 0x4 #define _B4D4_B4D43_POSN 0x3 #define _B4D4_B4D43_POSITION 0x3 #define _B4D4_B4D43_SIZE 0x1 #define _B4D4_B4D43_LENGTH 0x1 #define _B4D4_B4D43_MASK 0x8 #define _B4D4_B4D44_POSN 0x4 #define _B4D4_B4D44_POSITION 0x4 #define _B4D4_B4D44_SIZE 0x1 #define _B4D4_B4D44_LENGTH 0x1 #define _B4D4_B4D44_MASK 0x10 #define _B4D4_B4D45_POSN 0x5 #define _B4D4_B4D45_POSITION 0x5 #define _B4D4_B4D45_SIZE 0x1 #define _B4D4_B4D45_LENGTH 0x1 #define _B4D4_B4D45_MASK 0x20 #define _B4D4_B4D46_POSN 0x6 #define _B4D4_B4D46_POSITION 0x6 #define _B4D4_B4D46_SIZE 0x1 #define _B4D4_B4D46_LENGTH 0x1 #define _B4D4_B4D46_MASK 0x40 #define _B4D4_B4D47_POSN 0x7 #define _B4D4_B4D47_POSITION 0x7 #define _B4D4_B4D47_SIZE 0x1 #define _B4D4_B4D47_LENGTH 0x1 #define _B4D4_B4D47_MASK 0x80 // Register: B4D5 #define B4D5 B4D5 extern volatile unsigned char B4D5 @ 0xECB; #ifndef _LIB_BUILD asm("B4D5 equ 0ECBh"); #endif // bitfield definitions typedef union { struct { unsigned B4D5 :8; }; struct { unsigned B4D50 :1; unsigned B4D51 :1; unsigned B4D52 :1; unsigned B4D53 :1; unsigned B4D54 :1; unsigned B4D55 :1; unsigned B4D56 :1; unsigned B4D57 :1; }; } B4D5bits_t; extern volatile B4D5bits_t B4D5bits @ 0xECB; // bitfield macros #define _B4D5_B4D5_POSN 0x0 #define _B4D5_B4D5_POSITION 0x0 #define _B4D5_B4D5_SIZE 0x8 #define _B4D5_B4D5_LENGTH 0x8 #define _B4D5_B4D5_MASK 0xFF #define _B4D5_B4D50_POSN 0x0 #define _B4D5_B4D50_POSITION 0x0 #define _B4D5_B4D50_SIZE 0x1 #define _B4D5_B4D50_LENGTH 0x1 #define _B4D5_B4D50_MASK 0x1 #define _B4D5_B4D51_POSN 0x1 #define _B4D5_B4D51_POSITION 0x1 #define _B4D5_B4D51_SIZE 0x1 #define _B4D5_B4D51_LENGTH 0x1 #define _B4D5_B4D51_MASK 0x2 #define _B4D5_B4D52_POSN 0x2 #define _B4D5_B4D52_POSITION 0x2 #define _B4D5_B4D52_SIZE 0x1 #define _B4D5_B4D52_LENGTH 0x1 #define _B4D5_B4D52_MASK 0x4 #define _B4D5_B4D53_POSN 0x3 #define _B4D5_B4D53_POSITION 0x3 #define _B4D5_B4D53_SIZE 0x1 #define _B4D5_B4D53_LENGTH 0x1 #define _B4D5_B4D53_MASK 0x8 #define _B4D5_B4D54_POSN 0x4 #define _B4D5_B4D54_POSITION 0x4 #define _B4D5_B4D54_SIZE 0x1 #define _B4D5_B4D54_LENGTH 0x1 #define _B4D5_B4D54_MASK 0x10 #define _B4D5_B4D55_POSN 0x5 #define _B4D5_B4D55_POSITION 0x5 #define _B4D5_B4D55_SIZE 0x1 #define _B4D5_B4D55_LENGTH 0x1 #define _B4D5_B4D55_MASK 0x20 #define _B4D5_B4D56_POSN 0x6 #define _B4D5_B4D56_POSITION 0x6 #define _B4D5_B4D56_SIZE 0x1 #define _B4D5_B4D56_LENGTH 0x1 #define _B4D5_B4D56_MASK 0x40 #define _B4D5_B4D57_POSN 0x7 #define _B4D5_B4D57_POSITION 0x7 #define _B4D5_B4D57_SIZE 0x1 #define _B4D5_B4D57_LENGTH 0x1 #define _B4D5_B4D57_MASK 0x80 // Register: B4D6 #define B4D6 B4D6 extern volatile unsigned char B4D6 @ 0xECC; #ifndef _LIB_BUILD asm("B4D6 equ 0ECCh"); #endif // bitfield definitions typedef union { struct { unsigned B4D6 :8; }; struct { unsigned B4D60 :1; unsigned B4D61 :1; unsigned B4D62 :1; unsigned B4D63 :1; unsigned B4D64 :1; unsigned B4D65 :1; unsigned B4D66 :1; unsigned B4D67 :1; }; } B4D6bits_t; extern volatile B4D6bits_t B4D6bits @ 0xECC; // bitfield macros #define _B4D6_B4D6_POSN 0x0 #define _B4D6_B4D6_POSITION 0x0 #define _B4D6_B4D6_SIZE 0x8 #define _B4D6_B4D6_LENGTH 0x8 #define _B4D6_B4D6_MASK 0xFF #define _B4D6_B4D60_POSN 0x0 #define _B4D6_B4D60_POSITION 0x0 #define _B4D6_B4D60_SIZE 0x1 #define _B4D6_B4D60_LENGTH 0x1 #define _B4D6_B4D60_MASK 0x1 #define _B4D6_B4D61_POSN 0x1 #define _B4D6_B4D61_POSITION 0x1 #define _B4D6_B4D61_SIZE 0x1 #define _B4D6_B4D61_LENGTH 0x1 #define _B4D6_B4D61_MASK 0x2 #define _B4D6_B4D62_POSN 0x2 #define _B4D6_B4D62_POSITION 0x2 #define _B4D6_B4D62_SIZE 0x1 #define _B4D6_B4D62_LENGTH 0x1 #define _B4D6_B4D62_MASK 0x4 #define _B4D6_B4D63_POSN 0x3 #define _B4D6_B4D63_POSITION 0x3 #define _B4D6_B4D63_SIZE 0x1 #define _B4D6_B4D63_LENGTH 0x1 #define _B4D6_B4D63_MASK 0x8 #define _B4D6_B4D64_POSN 0x4 #define _B4D6_B4D64_POSITION 0x4 #define _B4D6_B4D64_SIZE 0x1 #define _B4D6_B4D64_LENGTH 0x1 #define _B4D6_B4D64_MASK 0x10 #define _B4D6_B4D65_POSN 0x5 #define _B4D6_B4D65_POSITION 0x5 #define _B4D6_B4D65_SIZE 0x1 #define _B4D6_B4D65_LENGTH 0x1 #define _B4D6_B4D65_MASK 0x20 #define _B4D6_B4D66_POSN 0x6 #define _B4D6_B4D66_POSITION 0x6 #define _B4D6_B4D66_SIZE 0x1 #define _B4D6_B4D66_LENGTH 0x1 #define _B4D6_B4D66_MASK 0x40 #define _B4D6_B4D67_POSN 0x7 #define _B4D6_B4D67_POSITION 0x7 #define _B4D6_B4D67_SIZE 0x1 #define _B4D6_B4D67_LENGTH 0x1 #define _B4D6_B4D67_MASK 0x80 // Register: B4D7 #define B4D7 B4D7 extern volatile unsigned char B4D7 @ 0xECD; #ifndef _LIB_BUILD asm("B4D7 equ 0ECDh"); #endif // bitfield definitions typedef union { struct { unsigned B4D7 :8; }; struct { unsigned B4D70 :1; unsigned B4D71 :1; unsigned B4D72 :1; unsigned B4D73 :1; unsigned B4D74 :1; unsigned B4D75 :1; unsigned B4D76 :1; unsigned B4D77 :1; }; } B4D7bits_t; extern volatile B4D7bits_t B4D7bits @ 0xECD; // bitfield macros #define _B4D7_B4D7_POSN 0x0 #define _B4D7_B4D7_POSITION 0x0 #define _B4D7_B4D7_SIZE 0x8 #define _B4D7_B4D7_LENGTH 0x8 #define _B4D7_B4D7_MASK 0xFF #define _B4D7_B4D70_POSN 0x0 #define _B4D7_B4D70_POSITION 0x0 #define _B4D7_B4D70_SIZE 0x1 #define _B4D7_B4D70_LENGTH 0x1 #define _B4D7_B4D70_MASK 0x1 #define _B4D7_B4D71_POSN 0x1 #define _B4D7_B4D71_POSITION 0x1 #define _B4D7_B4D71_SIZE 0x1 #define _B4D7_B4D71_LENGTH 0x1 #define _B4D7_B4D71_MASK 0x2 #define _B4D7_B4D72_POSN 0x2 #define _B4D7_B4D72_POSITION 0x2 #define _B4D7_B4D72_SIZE 0x1 #define _B4D7_B4D72_LENGTH 0x1 #define _B4D7_B4D72_MASK 0x4 #define _B4D7_B4D73_POSN 0x3 #define _B4D7_B4D73_POSITION 0x3 #define _B4D7_B4D73_SIZE 0x1 #define _B4D7_B4D73_LENGTH 0x1 #define _B4D7_B4D73_MASK 0x8 #define _B4D7_B4D74_POSN 0x4 #define _B4D7_B4D74_POSITION 0x4 #define _B4D7_B4D74_SIZE 0x1 #define _B4D7_B4D74_LENGTH 0x1 #define _B4D7_B4D74_MASK 0x10 #define _B4D7_B4D75_POSN 0x5 #define _B4D7_B4D75_POSITION 0x5 #define _B4D7_B4D75_SIZE 0x1 #define _B4D7_B4D75_LENGTH 0x1 #define _B4D7_B4D75_MASK 0x20 #define _B4D7_B4D76_POSN 0x6 #define _B4D7_B4D76_POSITION 0x6 #define _B4D7_B4D76_SIZE 0x1 #define _B4D7_B4D76_LENGTH 0x1 #define _B4D7_B4D76_MASK 0x40 #define _B4D7_B4D77_POSN 0x7 #define _B4D7_B4D77_POSITION 0x7 #define _B4D7_B4D77_SIZE 0x1 #define _B4D7_B4D77_LENGTH 0x1 #define _B4D7_B4D77_MASK 0x80 // Register: CANSTAT_RO5 #define CANSTAT_RO5 CANSTAT_RO5 extern volatile unsigned char CANSTAT_RO5 @ 0xECE; #ifndef _LIB_BUILD asm("CANSTAT_RO5 equ 0ECEh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO5bits_t; extern volatile CANSTAT_RO5bits_t CANSTAT_RO5bits @ 0xECE; // bitfield macros #define _CANSTAT_RO5_EICODE0_POSN 0x0 #define _CANSTAT_RO5_EICODE0_POSITION 0x0 #define _CANSTAT_RO5_EICODE0_SIZE 0x1 #define _CANSTAT_RO5_EICODE0_LENGTH 0x1 #define _CANSTAT_RO5_EICODE0_MASK 0x1 #define _CANSTAT_RO5_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO5_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO5_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO5_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO5_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO5_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO5_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO5_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO5_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO5_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO5_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO5_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO5_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO5_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO5_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO5_EICODE4_POSN 0x4 #define _CANSTAT_RO5_EICODE4_POSITION 0x4 #define _CANSTAT_RO5_EICODE4_SIZE 0x1 #define _CANSTAT_RO5_EICODE4_LENGTH 0x1 #define _CANSTAT_RO5_EICODE4_MASK 0x10 #define _CANSTAT_RO5_OPMODE_POSN 0x5 #define _CANSTAT_RO5_OPMODE_POSITION 0x5 #define _CANSTAT_RO5_OPMODE_SIZE 0x3 #define _CANSTAT_RO5_OPMODE_LENGTH 0x3 #define _CANSTAT_RO5_OPMODE_MASK 0xE0 #define _CANSTAT_RO5_EICODE1_POSN 0x1 #define _CANSTAT_RO5_EICODE1_POSITION 0x1 #define _CANSTAT_RO5_EICODE1_SIZE 0x1 #define _CANSTAT_RO5_EICODE1_LENGTH 0x1 #define _CANSTAT_RO5_EICODE1_MASK 0x2 #define _CANSTAT_RO5_EICODE2_POSN 0x2 #define _CANSTAT_RO5_EICODE2_POSITION 0x2 #define _CANSTAT_RO5_EICODE2_SIZE 0x1 #define _CANSTAT_RO5_EICODE2_LENGTH 0x1 #define _CANSTAT_RO5_EICODE2_MASK 0x4 #define _CANSTAT_RO5_EICODE3_POSN 0x3 #define _CANSTAT_RO5_EICODE3_POSITION 0x3 #define _CANSTAT_RO5_EICODE3_SIZE 0x1 #define _CANSTAT_RO5_EICODE3_LENGTH 0x1 #define _CANSTAT_RO5_EICODE3_MASK 0x8 #define _CANSTAT_RO5_OPMODE0_POSN 0x5 #define _CANSTAT_RO5_OPMODE0_POSITION 0x5 #define _CANSTAT_RO5_OPMODE0_SIZE 0x1 #define _CANSTAT_RO5_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO5_OPMODE0_MASK 0x20 #define _CANSTAT_RO5_OPMODE1_POSN 0x6 #define _CANSTAT_RO5_OPMODE1_POSITION 0x6 #define _CANSTAT_RO5_OPMODE1_SIZE 0x1 #define _CANSTAT_RO5_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO5_OPMODE1_MASK 0x40 #define _CANSTAT_RO5_OPMODE2_POSN 0x7 #define _CANSTAT_RO5_OPMODE2_POSITION 0x7 #define _CANSTAT_RO5_OPMODE2_SIZE 0x1 #define _CANSTAT_RO5_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO5_OPMODE2_MASK 0x80 #define _CANSTAT_RO5_ICODE0_POSN 0x1 #define _CANSTAT_RO5_ICODE0_POSITION 0x1 #define _CANSTAT_RO5_ICODE0_SIZE 0x1 #define _CANSTAT_RO5_ICODE0_LENGTH 0x1 #define _CANSTAT_RO5_ICODE0_MASK 0x2 #define _CANSTAT_RO5_ICODE1_POSN 0x2 #define _CANSTAT_RO5_ICODE1_POSITION 0x2 #define _CANSTAT_RO5_ICODE1_SIZE 0x1 #define _CANSTAT_RO5_ICODE1_LENGTH 0x1 #define _CANSTAT_RO5_ICODE1_MASK 0x4 #define _CANSTAT_RO5_ICODE2_POSN 0x3 #define _CANSTAT_RO5_ICODE2_POSITION 0x3 #define _CANSTAT_RO5_ICODE2_SIZE 0x1 #define _CANSTAT_RO5_ICODE2_LENGTH 0x1 #define _CANSTAT_RO5_ICODE2_MASK 0x8 // Register: CANCON_RO5 #define CANCON_RO5 CANCON_RO5 extern volatile unsigned char CANCON_RO5 @ 0xECF; #ifndef _LIB_BUILD asm("CANCON_RO5 equ 0ECFh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO5bits_t; extern volatile CANCON_RO5bits_t CANCON_RO5bits @ 0xECF; // bitfield macros #define _CANCON_RO5_FP0_POSN 0x0 #define _CANCON_RO5_FP0_POSITION 0x0 #define _CANCON_RO5_FP0_SIZE 0x1 #define _CANCON_RO5_FP0_LENGTH 0x1 #define _CANCON_RO5_FP0_MASK 0x1 #define _CANCON_RO5_WIN0_FP1_POSN 0x1 #define _CANCON_RO5_WIN0_FP1_POSITION 0x1 #define _CANCON_RO5_WIN0_FP1_SIZE 0x1 #define _CANCON_RO5_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO5_WIN0_FP1_MASK 0x2 #define _CANCON_RO5_WIN1_FP2_POSN 0x2 #define _CANCON_RO5_WIN1_FP2_POSITION 0x2 #define _CANCON_RO5_WIN1_FP2_SIZE 0x1 #define _CANCON_RO5_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO5_WIN1_FP2_MASK 0x4 #define _CANCON_RO5_WIN2_FP3_POSN 0x3 #define _CANCON_RO5_WIN2_FP3_POSITION 0x3 #define _CANCON_RO5_WIN2_FP3_SIZE 0x1 #define _CANCON_RO5_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO5_WIN2_FP3_MASK 0x8 #define _CANCON_RO5_ABAT_POSN 0x4 #define _CANCON_RO5_ABAT_POSITION 0x4 #define _CANCON_RO5_ABAT_SIZE 0x1 #define _CANCON_RO5_ABAT_LENGTH 0x1 #define _CANCON_RO5_ABAT_MASK 0x10 #define _CANCON_RO5_REQOP_POSN 0x5 #define _CANCON_RO5_REQOP_POSITION 0x5 #define _CANCON_RO5_REQOP_SIZE 0x3 #define _CANCON_RO5_REQOP_LENGTH 0x3 #define _CANCON_RO5_REQOP_MASK 0xE0 #define _CANCON_RO5_WIN0_POSN 0x1 #define _CANCON_RO5_WIN0_POSITION 0x1 #define _CANCON_RO5_WIN0_SIZE 0x1 #define _CANCON_RO5_WIN0_LENGTH 0x1 #define _CANCON_RO5_WIN0_MASK 0x2 #define _CANCON_RO5_WIN1_POSN 0x2 #define _CANCON_RO5_WIN1_POSITION 0x2 #define _CANCON_RO5_WIN1_SIZE 0x1 #define _CANCON_RO5_WIN1_LENGTH 0x1 #define _CANCON_RO5_WIN1_MASK 0x4 #define _CANCON_RO5_WIN2_POSN 0x3 #define _CANCON_RO5_WIN2_POSITION 0x3 #define _CANCON_RO5_WIN2_SIZE 0x1 #define _CANCON_RO5_WIN2_LENGTH 0x1 #define _CANCON_RO5_WIN2_MASK 0x8 #define _CANCON_RO5_FP1_POSN 0x1 #define _CANCON_RO5_FP1_POSITION 0x1 #define _CANCON_RO5_FP1_SIZE 0x1 #define _CANCON_RO5_FP1_LENGTH 0x1 #define _CANCON_RO5_FP1_MASK 0x2 #define _CANCON_RO5_FP2_POSN 0x2 #define _CANCON_RO5_FP2_POSITION 0x2 #define _CANCON_RO5_FP2_SIZE 0x1 #define _CANCON_RO5_FP2_LENGTH 0x1 #define _CANCON_RO5_FP2_MASK 0x4 #define _CANCON_RO5_FP3_POSN 0x3 #define _CANCON_RO5_FP3_POSITION 0x3 #define _CANCON_RO5_FP3_SIZE 0x1 #define _CANCON_RO5_FP3_LENGTH 0x1 #define _CANCON_RO5_FP3_MASK 0x8 // Register: B5CON #define B5CON B5CON extern volatile unsigned char B5CON @ 0xED0; #ifndef _LIB_BUILD asm("B5CON equ 0ED0h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0_TXPRI0 :1; unsigned FILHIT1_TXPRI1 :1; unsigned FILHIT2_RTREN :1; unsigned FILHIT3_TXREQ :1; unsigned FILHIT4_TXERR :1; unsigned RXRTRRO_TXLARB :1; unsigned RXM1_TXABT :1; unsigned RXFUL_TXBIF :1; }; struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXRTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; unsigned RTREN :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned B5FILHIT0 :1; unsigned B5FILHIT1 :1; unsigned B5FILHIT2 :1; unsigned B5FILHIT3 :1; unsigned B5FILHIT4 :1; unsigned B5RTRRO :1; unsigned B5RXM1 :1; unsigned B5RXFUL :1; }; struct { unsigned B5TXPRI0 :1; unsigned B5TXPRI1 :1; unsigned B5RTREN :1; unsigned B5TXREQ :1; unsigned B5TXERR :1; unsigned B5TXLARB :1; unsigned B5TXABT :1; unsigned B5TXBIF :1; }; } B5CONbits_t; extern volatile B5CONbits_t B5CONbits @ 0xED0; // bitfield macros #define _B5CON_FILHIT0_TXPRI0_POSN 0x0 #define _B5CON_FILHIT0_TXPRI0_POSITION 0x0 #define _B5CON_FILHIT0_TXPRI0_SIZE 0x1 #define _B5CON_FILHIT0_TXPRI0_LENGTH 0x1 #define _B5CON_FILHIT0_TXPRI0_MASK 0x1 #define _B5CON_FILHIT1_TXPRI1_POSN 0x1 #define _B5CON_FILHIT1_TXPRI1_POSITION 0x1 #define _B5CON_FILHIT1_TXPRI1_SIZE 0x1 #define _B5CON_FILHIT1_TXPRI1_LENGTH 0x1 #define _B5CON_FILHIT1_TXPRI1_MASK 0x2 #define _B5CON_FILHIT2_RTREN_POSN 0x2 #define _B5CON_FILHIT2_RTREN_POSITION 0x2 #define _B5CON_FILHIT2_RTREN_SIZE 0x1 #define _B5CON_FILHIT2_RTREN_LENGTH 0x1 #define _B5CON_FILHIT2_RTREN_MASK 0x4 #define _B5CON_FILHIT3_TXREQ_POSN 0x3 #define _B5CON_FILHIT3_TXREQ_POSITION 0x3 #define _B5CON_FILHIT3_TXREQ_SIZE 0x1 #define _B5CON_FILHIT3_TXREQ_LENGTH 0x1 #define _B5CON_FILHIT3_TXREQ_MASK 0x8 #define _B5CON_FILHIT4_TXERR_POSN 0x4 #define _B5CON_FILHIT4_TXERR_POSITION 0x4 #define _B5CON_FILHIT4_TXERR_SIZE 0x1 #define _B5CON_FILHIT4_TXERR_LENGTH 0x1 #define _B5CON_FILHIT4_TXERR_MASK 0x10 #define _B5CON_RXRTRRO_TXLARB_POSN 0x5 #define _B5CON_RXRTRRO_TXLARB_POSITION 0x5 #define _B5CON_RXRTRRO_TXLARB_SIZE 0x1 #define _B5CON_RXRTRRO_TXLARB_LENGTH 0x1 #define _B5CON_RXRTRRO_TXLARB_MASK 0x20 #define _B5CON_RXM1_TXABT_POSN 0x6 #define _B5CON_RXM1_TXABT_POSITION 0x6 #define _B5CON_RXM1_TXABT_SIZE 0x1 #define _B5CON_RXM1_TXABT_LENGTH 0x1 #define _B5CON_RXM1_TXABT_MASK 0x40 #define _B5CON_RXFUL_TXBIF_POSN 0x7 #define _B5CON_RXFUL_TXBIF_POSITION 0x7 #define _B5CON_RXFUL_TXBIF_SIZE 0x1 #define _B5CON_RXFUL_TXBIF_LENGTH 0x1 #define _B5CON_RXFUL_TXBIF_MASK 0x80 #define _B5CON_FILHIT0_POSN 0x0 #define _B5CON_FILHIT0_POSITION 0x0 #define _B5CON_FILHIT0_SIZE 0x1 #define _B5CON_FILHIT0_LENGTH 0x1 #define _B5CON_FILHIT0_MASK 0x1 #define _B5CON_FILHIT1_POSN 0x1 #define _B5CON_FILHIT1_POSITION 0x1 #define _B5CON_FILHIT1_SIZE 0x1 #define _B5CON_FILHIT1_LENGTH 0x1 #define _B5CON_FILHIT1_MASK 0x2 #define _B5CON_FILHIT2_POSN 0x2 #define _B5CON_FILHIT2_POSITION 0x2 #define _B5CON_FILHIT2_SIZE 0x1 #define _B5CON_FILHIT2_LENGTH 0x1 #define _B5CON_FILHIT2_MASK 0x4 #define _B5CON_FILHIT3_POSN 0x3 #define _B5CON_FILHIT3_POSITION 0x3 #define _B5CON_FILHIT3_SIZE 0x1 #define _B5CON_FILHIT3_LENGTH 0x1 #define _B5CON_FILHIT3_MASK 0x8 #define _B5CON_FILHIT4_POSN 0x4 #define _B5CON_FILHIT4_POSITION 0x4 #define _B5CON_FILHIT4_SIZE 0x1 #define _B5CON_FILHIT4_LENGTH 0x1 #define _B5CON_FILHIT4_MASK 0x10 #define _B5CON_RXRTRRO_POSN 0x5 #define _B5CON_RXRTRRO_POSITION 0x5 #define _B5CON_RXRTRRO_SIZE 0x1 #define _B5CON_RXRTRRO_LENGTH 0x1 #define _B5CON_RXRTRRO_MASK 0x20 #define _B5CON_RXM1_POSN 0x6 #define _B5CON_RXM1_POSITION 0x6 #define _B5CON_RXM1_SIZE 0x1 #define _B5CON_RXM1_LENGTH 0x1 #define _B5CON_RXM1_MASK 0x40 #define _B5CON_RXFUL_POSN 0x7 #define _B5CON_RXFUL_POSITION 0x7 #define _B5CON_RXFUL_SIZE 0x1 #define _B5CON_RXFUL_LENGTH 0x1 #define _B5CON_RXFUL_MASK 0x80 #define _B5CON_TXPRI0_POSN 0x0 #define _B5CON_TXPRI0_POSITION 0x0 #define _B5CON_TXPRI0_SIZE 0x1 #define _B5CON_TXPRI0_LENGTH 0x1 #define _B5CON_TXPRI0_MASK 0x1 #define _B5CON_TXPRI1_POSN 0x1 #define _B5CON_TXPRI1_POSITION 0x1 #define _B5CON_TXPRI1_SIZE 0x1 #define _B5CON_TXPRI1_LENGTH 0x1 #define _B5CON_TXPRI1_MASK 0x2 #define _B5CON_RTREN_POSN 0x2 #define _B5CON_RTREN_POSITION 0x2 #define _B5CON_RTREN_SIZE 0x1 #define _B5CON_RTREN_LENGTH 0x1 #define _B5CON_RTREN_MASK 0x4 #define _B5CON_TXREQ_POSN 0x3 #define _B5CON_TXREQ_POSITION 0x3 #define _B5CON_TXREQ_SIZE 0x1 #define _B5CON_TXREQ_LENGTH 0x1 #define _B5CON_TXREQ_MASK 0x8 #define _B5CON_TXERR_POSN 0x4 #define _B5CON_TXERR_POSITION 0x4 #define _B5CON_TXERR_SIZE 0x1 #define _B5CON_TXERR_LENGTH 0x1 #define _B5CON_TXERR_MASK 0x10 #define _B5CON_TXLARB_POSN 0x5 #define _B5CON_TXLARB_POSITION 0x5 #define _B5CON_TXLARB_SIZE 0x1 #define _B5CON_TXLARB_LENGTH 0x1 #define _B5CON_TXLARB_MASK 0x20 #define _B5CON_TXABT_POSN 0x6 #define _B5CON_TXABT_POSITION 0x6 #define _B5CON_TXABT_SIZE 0x1 #define _B5CON_TXABT_LENGTH 0x1 #define _B5CON_TXABT_MASK 0x40 #define _B5CON_TXBIF_POSN 0x7 #define _B5CON_TXBIF_POSITION 0x7 #define _B5CON_TXBIF_SIZE 0x1 #define _B5CON_TXBIF_LENGTH 0x1 #define _B5CON_TXBIF_MASK 0x80 #define _B5CON_B5FILHIT0_POSN 0x0 #define _B5CON_B5FILHIT0_POSITION 0x0 #define _B5CON_B5FILHIT0_SIZE 0x1 #define _B5CON_B5FILHIT0_LENGTH 0x1 #define _B5CON_B5FILHIT0_MASK 0x1 #define _B5CON_B5FILHIT1_POSN 0x1 #define _B5CON_B5FILHIT1_POSITION 0x1 #define _B5CON_B5FILHIT1_SIZE 0x1 #define _B5CON_B5FILHIT1_LENGTH 0x1 #define _B5CON_B5FILHIT1_MASK 0x2 #define _B5CON_B5FILHIT2_POSN 0x2 #define _B5CON_B5FILHIT2_POSITION 0x2 #define _B5CON_B5FILHIT2_SIZE 0x1 #define _B5CON_B5FILHIT2_LENGTH 0x1 #define _B5CON_B5FILHIT2_MASK 0x4 #define _B5CON_B5FILHIT3_POSN 0x3 #define _B5CON_B5FILHIT3_POSITION 0x3 #define _B5CON_B5FILHIT3_SIZE 0x1 #define _B5CON_B5FILHIT3_LENGTH 0x1 #define _B5CON_B5FILHIT3_MASK 0x8 #define _B5CON_B5FILHIT4_POSN 0x4 #define _B5CON_B5FILHIT4_POSITION 0x4 #define _B5CON_B5FILHIT4_SIZE 0x1 #define _B5CON_B5FILHIT4_LENGTH 0x1 #define _B5CON_B5FILHIT4_MASK 0x10 #define _B5CON_B5RTRRO_POSN 0x5 #define _B5CON_B5RTRRO_POSITION 0x5 #define _B5CON_B5RTRRO_SIZE 0x1 #define _B5CON_B5RTRRO_LENGTH 0x1 #define _B5CON_B5RTRRO_MASK 0x20 #define _B5CON_B5RXM1_POSN 0x6 #define _B5CON_B5RXM1_POSITION 0x6 #define _B5CON_B5RXM1_SIZE 0x1 #define _B5CON_B5RXM1_LENGTH 0x1 #define _B5CON_B5RXM1_MASK 0x40 #define _B5CON_B5RXFUL_POSN 0x7 #define _B5CON_B5RXFUL_POSITION 0x7 #define _B5CON_B5RXFUL_SIZE 0x1 #define _B5CON_B5RXFUL_LENGTH 0x1 #define _B5CON_B5RXFUL_MASK 0x80 #define _B5CON_B5TXPRI0_POSN 0x0 #define _B5CON_B5TXPRI0_POSITION 0x0 #define _B5CON_B5TXPRI0_SIZE 0x1 #define _B5CON_B5TXPRI0_LENGTH 0x1 #define _B5CON_B5TXPRI0_MASK 0x1 #define _B5CON_B5TXPRI1_POSN 0x1 #define _B5CON_B5TXPRI1_POSITION 0x1 #define _B5CON_B5TXPRI1_SIZE 0x1 #define _B5CON_B5TXPRI1_LENGTH 0x1 #define _B5CON_B5TXPRI1_MASK 0x2 #define _B5CON_B5RTREN_POSN 0x2 #define _B5CON_B5RTREN_POSITION 0x2 #define _B5CON_B5RTREN_SIZE 0x1 #define _B5CON_B5RTREN_LENGTH 0x1 #define _B5CON_B5RTREN_MASK 0x4 #define _B5CON_B5TXREQ_POSN 0x3 #define _B5CON_B5TXREQ_POSITION 0x3 #define _B5CON_B5TXREQ_SIZE 0x1 #define _B5CON_B5TXREQ_LENGTH 0x1 #define _B5CON_B5TXREQ_MASK 0x8 #define _B5CON_B5TXERR_POSN 0x4 #define _B5CON_B5TXERR_POSITION 0x4 #define _B5CON_B5TXERR_SIZE 0x1 #define _B5CON_B5TXERR_LENGTH 0x1 #define _B5CON_B5TXERR_MASK 0x10 #define _B5CON_B5TXLARB_POSN 0x5 #define _B5CON_B5TXLARB_POSITION 0x5 #define _B5CON_B5TXLARB_SIZE 0x1 #define _B5CON_B5TXLARB_LENGTH 0x1 #define _B5CON_B5TXLARB_MASK 0x20 #define _B5CON_B5TXABT_POSN 0x6 #define _B5CON_B5TXABT_POSITION 0x6 #define _B5CON_B5TXABT_SIZE 0x1 #define _B5CON_B5TXABT_LENGTH 0x1 #define _B5CON_B5TXABT_MASK 0x40 #define _B5CON_B5TXBIF_POSN 0x7 #define _B5CON_B5TXBIF_POSITION 0x7 #define _B5CON_B5TXBIF_SIZE 0x1 #define _B5CON_B5TXBIF_LENGTH 0x1 #define _B5CON_B5TXBIF_MASK 0x80 // Register: B5SIDH #define B5SIDH B5SIDH extern volatile unsigned char B5SIDH @ 0xED1; #ifndef _LIB_BUILD asm("B5SIDH equ 0ED1h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned B5SID3 :1; unsigned B5SID4 :1; unsigned B5SID5 :1; unsigned B5SID6 :1; unsigned B5SID7 :1; unsigned B5SID8 :1; unsigned B5SID9 :1; unsigned B5SID10 :1; }; } B5SIDHbits_t; extern volatile B5SIDHbits_t B5SIDHbits @ 0xED1; // bitfield macros #define _B5SIDH_SID_POSN 0x0 #define _B5SIDH_SID_POSITION 0x0 #define _B5SIDH_SID_SIZE 0x8 #define _B5SIDH_SID_LENGTH 0x8 #define _B5SIDH_SID_MASK 0xFF #define _B5SIDH_SID3_POSN 0x0 #define _B5SIDH_SID3_POSITION 0x0 #define _B5SIDH_SID3_SIZE 0x1 #define _B5SIDH_SID3_LENGTH 0x1 #define _B5SIDH_SID3_MASK 0x1 #define _B5SIDH_SID4_POSN 0x1 #define _B5SIDH_SID4_POSITION 0x1 #define _B5SIDH_SID4_SIZE 0x1 #define _B5SIDH_SID4_LENGTH 0x1 #define _B5SIDH_SID4_MASK 0x2 #define _B5SIDH_SID5_POSN 0x2 #define _B5SIDH_SID5_POSITION 0x2 #define _B5SIDH_SID5_SIZE 0x1 #define _B5SIDH_SID5_LENGTH 0x1 #define _B5SIDH_SID5_MASK 0x4 #define _B5SIDH_SID6_POSN 0x3 #define _B5SIDH_SID6_POSITION 0x3 #define _B5SIDH_SID6_SIZE 0x1 #define _B5SIDH_SID6_LENGTH 0x1 #define _B5SIDH_SID6_MASK 0x8 #define _B5SIDH_SID7_POSN 0x4 #define _B5SIDH_SID7_POSITION 0x4 #define _B5SIDH_SID7_SIZE 0x1 #define _B5SIDH_SID7_LENGTH 0x1 #define _B5SIDH_SID7_MASK 0x10 #define _B5SIDH_SID8_POSN 0x5 #define _B5SIDH_SID8_POSITION 0x5 #define _B5SIDH_SID8_SIZE 0x1 #define _B5SIDH_SID8_LENGTH 0x1 #define _B5SIDH_SID8_MASK 0x20 #define _B5SIDH_SID9_POSN 0x6 #define _B5SIDH_SID9_POSITION 0x6 #define _B5SIDH_SID9_SIZE 0x1 #define _B5SIDH_SID9_LENGTH 0x1 #define _B5SIDH_SID9_MASK 0x40 #define _B5SIDH_SID10_POSN 0x7 #define _B5SIDH_SID10_POSITION 0x7 #define _B5SIDH_SID10_SIZE 0x1 #define _B5SIDH_SID10_LENGTH 0x1 #define _B5SIDH_SID10_MASK 0x80 #define _B5SIDH_B5SID3_POSN 0x0 #define _B5SIDH_B5SID3_POSITION 0x0 #define _B5SIDH_B5SID3_SIZE 0x1 #define _B5SIDH_B5SID3_LENGTH 0x1 #define _B5SIDH_B5SID3_MASK 0x1 #define _B5SIDH_B5SID4_POSN 0x1 #define _B5SIDH_B5SID4_POSITION 0x1 #define _B5SIDH_B5SID4_SIZE 0x1 #define _B5SIDH_B5SID4_LENGTH 0x1 #define _B5SIDH_B5SID4_MASK 0x2 #define _B5SIDH_B5SID5_POSN 0x2 #define _B5SIDH_B5SID5_POSITION 0x2 #define _B5SIDH_B5SID5_SIZE 0x1 #define _B5SIDH_B5SID5_LENGTH 0x1 #define _B5SIDH_B5SID5_MASK 0x4 #define _B5SIDH_B5SID6_POSN 0x3 #define _B5SIDH_B5SID6_POSITION 0x3 #define _B5SIDH_B5SID6_SIZE 0x1 #define _B5SIDH_B5SID6_LENGTH 0x1 #define _B5SIDH_B5SID6_MASK 0x8 #define _B5SIDH_B5SID7_POSN 0x4 #define _B5SIDH_B5SID7_POSITION 0x4 #define _B5SIDH_B5SID7_SIZE 0x1 #define _B5SIDH_B5SID7_LENGTH 0x1 #define _B5SIDH_B5SID7_MASK 0x10 #define _B5SIDH_B5SID8_POSN 0x5 #define _B5SIDH_B5SID8_POSITION 0x5 #define _B5SIDH_B5SID8_SIZE 0x1 #define _B5SIDH_B5SID8_LENGTH 0x1 #define _B5SIDH_B5SID8_MASK 0x20 #define _B5SIDH_B5SID9_POSN 0x6 #define _B5SIDH_B5SID9_POSITION 0x6 #define _B5SIDH_B5SID9_SIZE 0x1 #define _B5SIDH_B5SID9_LENGTH 0x1 #define _B5SIDH_B5SID9_MASK 0x40 #define _B5SIDH_B5SID10_POSN 0x7 #define _B5SIDH_B5SID10_POSITION 0x7 #define _B5SIDH_B5SID10_SIZE 0x1 #define _B5SIDH_B5SID10_LENGTH 0x1 #define _B5SIDH_B5SID10_MASK 0x80 // Register: B5SIDL #define B5SIDL B5SIDL extern volatile unsigned char B5SIDL @ 0xED2; #ifndef _LIB_BUILD asm("B5SIDL equ 0ED2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned B5EID16 :1; unsigned B5EID17 :1; unsigned :1; unsigned B5EXID :1; unsigned B5SRR :1; unsigned B5SID0 :1; unsigned B5SID1 :1; unsigned B5SID2 :1; }; struct { unsigned :3; unsigned B5EXIDE :1; }; } B5SIDLbits_t; extern volatile B5SIDLbits_t B5SIDLbits @ 0xED2; // bitfield macros #define _B5SIDL_EID_POSN 0x0 #define _B5SIDL_EID_POSITION 0x0 #define _B5SIDL_EID_SIZE 0x2 #define _B5SIDL_EID_LENGTH 0x2 #define _B5SIDL_EID_MASK 0x3 #define _B5SIDL_EXIDE_POSN 0x3 #define _B5SIDL_EXIDE_POSITION 0x3 #define _B5SIDL_EXIDE_SIZE 0x1 #define _B5SIDL_EXIDE_LENGTH 0x1 #define _B5SIDL_EXIDE_MASK 0x8 #define _B5SIDL_SRR_POSN 0x4 #define _B5SIDL_SRR_POSITION 0x4 #define _B5SIDL_SRR_SIZE 0x1 #define _B5SIDL_SRR_LENGTH 0x1 #define _B5SIDL_SRR_MASK 0x10 #define _B5SIDL_SID_POSN 0x5 #define _B5SIDL_SID_POSITION 0x5 #define _B5SIDL_SID_SIZE 0x3 #define _B5SIDL_SID_LENGTH 0x3 #define _B5SIDL_SID_MASK 0xE0 #define _B5SIDL_EID16_POSN 0x0 #define _B5SIDL_EID16_POSITION 0x0 #define _B5SIDL_EID16_SIZE 0x1 #define _B5SIDL_EID16_LENGTH 0x1 #define _B5SIDL_EID16_MASK 0x1 #define _B5SIDL_EID17_POSN 0x1 #define _B5SIDL_EID17_POSITION 0x1 #define _B5SIDL_EID17_SIZE 0x1 #define _B5SIDL_EID17_LENGTH 0x1 #define _B5SIDL_EID17_MASK 0x2 #define _B5SIDL_SID0_POSN 0x5 #define _B5SIDL_SID0_POSITION 0x5 #define _B5SIDL_SID0_SIZE 0x1 #define _B5SIDL_SID0_LENGTH 0x1 #define _B5SIDL_SID0_MASK 0x20 #define _B5SIDL_SID1_POSN 0x6 #define _B5SIDL_SID1_POSITION 0x6 #define _B5SIDL_SID1_SIZE 0x1 #define _B5SIDL_SID1_LENGTH 0x1 #define _B5SIDL_SID1_MASK 0x40 #define _B5SIDL_SID2_POSN 0x7 #define _B5SIDL_SID2_POSITION 0x7 #define _B5SIDL_SID2_SIZE 0x1 #define _B5SIDL_SID2_LENGTH 0x1 #define _B5SIDL_SID2_MASK 0x80 #define _B5SIDL_B5EID16_POSN 0x0 #define _B5SIDL_B5EID16_POSITION 0x0 #define _B5SIDL_B5EID16_SIZE 0x1 #define _B5SIDL_B5EID16_LENGTH 0x1 #define _B5SIDL_B5EID16_MASK 0x1 #define _B5SIDL_B5EID17_POSN 0x1 #define _B5SIDL_B5EID17_POSITION 0x1 #define _B5SIDL_B5EID17_SIZE 0x1 #define _B5SIDL_B5EID17_LENGTH 0x1 #define _B5SIDL_B5EID17_MASK 0x2 #define _B5SIDL_B5EXID_POSN 0x3 #define _B5SIDL_B5EXID_POSITION 0x3 #define _B5SIDL_B5EXID_SIZE 0x1 #define _B5SIDL_B5EXID_LENGTH 0x1 #define _B5SIDL_B5EXID_MASK 0x8 #define _B5SIDL_B5SRR_POSN 0x4 #define _B5SIDL_B5SRR_POSITION 0x4 #define _B5SIDL_B5SRR_SIZE 0x1 #define _B5SIDL_B5SRR_LENGTH 0x1 #define _B5SIDL_B5SRR_MASK 0x10 #define _B5SIDL_B5SID0_POSN 0x5 #define _B5SIDL_B5SID0_POSITION 0x5 #define _B5SIDL_B5SID0_SIZE 0x1 #define _B5SIDL_B5SID0_LENGTH 0x1 #define _B5SIDL_B5SID0_MASK 0x20 #define _B5SIDL_B5SID1_POSN 0x6 #define _B5SIDL_B5SID1_POSITION 0x6 #define _B5SIDL_B5SID1_SIZE 0x1 #define _B5SIDL_B5SID1_LENGTH 0x1 #define _B5SIDL_B5SID1_MASK 0x40 #define _B5SIDL_B5SID2_POSN 0x7 #define _B5SIDL_B5SID2_POSITION 0x7 #define _B5SIDL_B5SID2_SIZE 0x1 #define _B5SIDL_B5SID2_LENGTH 0x1 #define _B5SIDL_B5SID2_MASK 0x80 #define _B5SIDL_B5EXIDE_POSN 0x3 #define _B5SIDL_B5EXIDE_POSITION 0x3 #define _B5SIDL_B5EXIDE_SIZE 0x1 #define _B5SIDL_B5EXIDE_LENGTH 0x1 #define _B5SIDL_B5EXIDE_MASK 0x8 // Register: B5EIDH #define B5EIDH B5EIDH extern volatile unsigned char B5EIDH @ 0xED3; #ifndef _LIB_BUILD asm("B5EIDH equ 0ED3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned B5EID8 :1; unsigned B5EID9 :1; unsigned B5EID10 :1; unsigned B5EID11 :1; unsigned B5EID12 :1; unsigned B5EID13 :1; unsigned B5EID14 :1; unsigned B5EID15 :1; }; } B5EIDHbits_t; extern volatile B5EIDHbits_t B5EIDHbits @ 0xED3; // bitfield macros #define _B5EIDH_EID_POSN 0x0 #define _B5EIDH_EID_POSITION 0x0 #define _B5EIDH_EID_SIZE 0x8 #define _B5EIDH_EID_LENGTH 0x8 #define _B5EIDH_EID_MASK 0xFF #define _B5EIDH_EID8_POSN 0x0 #define _B5EIDH_EID8_POSITION 0x0 #define _B5EIDH_EID8_SIZE 0x1 #define _B5EIDH_EID8_LENGTH 0x1 #define _B5EIDH_EID8_MASK 0x1 #define _B5EIDH_EID9_POSN 0x1 #define _B5EIDH_EID9_POSITION 0x1 #define _B5EIDH_EID9_SIZE 0x1 #define _B5EIDH_EID9_LENGTH 0x1 #define _B5EIDH_EID9_MASK 0x2 #define _B5EIDH_EID10_POSN 0x2 #define _B5EIDH_EID10_POSITION 0x2 #define _B5EIDH_EID10_SIZE 0x1 #define _B5EIDH_EID10_LENGTH 0x1 #define _B5EIDH_EID10_MASK 0x4 #define _B5EIDH_EID11_POSN 0x3 #define _B5EIDH_EID11_POSITION 0x3 #define _B5EIDH_EID11_SIZE 0x1 #define _B5EIDH_EID11_LENGTH 0x1 #define _B5EIDH_EID11_MASK 0x8 #define _B5EIDH_EID12_POSN 0x4 #define _B5EIDH_EID12_POSITION 0x4 #define _B5EIDH_EID12_SIZE 0x1 #define _B5EIDH_EID12_LENGTH 0x1 #define _B5EIDH_EID12_MASK 0x10 #define _B5EIDH_EID13_POSN 0x5 #define _B5EIDH_EID13_POSITION 0x5 #define _B5EIDH_EID13_SIZE 0x1 #define _B5EIDH_EID13_LENGTH 0x1 #define _B5EIDH_EID13_MASK 0x20 #define _B5EIDH_EID14_POSN 0x6 #define _B5EIDH_EID14_POSITION 0x6 #define _B5EIDH_EID14_SIZE 0x1 #define _B5EIDH_EID14_LENGTH 0x1 #define _B5EIDH_EID14_MASK 0x40 #define _B5EIDH_EID15_POSN 0x7 #define _B5EIDH_EID15_POSITION 0x7 #define _B5EIDH_EID15_SIZE 0x1 #define _B5EIDH_EID15_LENGTH 0x1 #define _B5EIDH_EID15_MASK 0x80 #define _B5EIDH_B5EID8_POSN 0x0 #define _B5EIDH_B5EID8_POSITION 0x0 #define _B5EIDH_B5EID8_SIZE 0x1 #define _B5EIDH_B5EID8_LENGTH 0x1 #define _B5EIDH_B5EID8_MASK 0x1 #define _B5EIDH_B5EID9_POSN 0x1 #define _B5EIDH_B5EID9_POSITION 0x1 #define _B5EIDH_B5EID9_SIZE 0x1 #define _B5EIDH_B5EID9_LENGTH 0x1 #define _B5EIDH_B5EID9_MASK 0x2 #define _B5EIDH_B5EID10_POSN 0x2 #define _B5EIDH_B5EID10_POSITION 0x2 #define _B5EIDH_B5EID10_SIZE 0x1 #define _B5EIDH_B5EID10_LENGTH 0x1 #define _B5EIDH_B5EID10_MASK 0x4 #define _B5EIDH_B5EID11_POSN 0x3 #define _B5EIDH_B5EID11_POSITION 0x3 #define _B5EIDH_B5EID11_SIZE 0x1 #define _B5EIDH_B5EID11_LENGTH 0x1 #define _B5EIDH_B5EID11_MASK 0x8 #define _B5EIDH_B5EID12_POSN 0x4 #define _B5EIDH_B5EID12_POSITION 0x4 #define _B5EIDH_B5EID12_SIZE 0x1 #define _B5EIDH_B5EID12_LENGTH 0x1 #define _B5EIDH_B5EID12_MASK 0x10 #define _B5EIDH_B5EID13_POSN 0x5 #define _B5EIDH_B5EID13_POSITION 0x5 #define _B5EIDH_B5EID13_SIZE 0x1 #define _B5EIDH_B5EID13_LENGTH 0x1 #define _B5EIDH_B5EID13_MASK 0x20 #define _B5EIDH_B5EID14_POSN 0x6 #define _B5EIDH_B5EID14_POSITION 0x6 #define _B5EIDH_B5EID14_SIZE 0x1 #define _B5EIDH_B5EID14_LENGTH 0x1 #define _B5EIDH_B5EID14_MASK 0x40 #define _B5EIDH_B5EID15_POSN 0x7 #define _B5EIDH_B5EID15_POSITION 0x7 #define _B5EIDH_B5EID15_SIZE 0x1 #define _B5EIDH_B5EID15_LENGTH 0x1 #define _B5EIDH_B5EID15_MASK 0x80 // Register: B5EIDL #define B5EIDL B5EIDL extern volatile unsigned char B5EIDL @ 0xED4; #ifndef _LIB_BUILD asm("B5EIDL equ 0ED4h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned B5EID0 :1; unsigned B5EID1 :1; unsigned B5EID2 :1; unsigned B5EID3 :1; unsigned B5EID4 :1; unsigned B5EID5 :1; unsigned B5EID6 :1; unsigned B5EID7 :1; }; } B5EIDLbits_t; extern volatile B5EIDLbits_t B5EIDLbits @ 0xED4; // bitfield macros #define _B5EIDL_EID_POSN 0x0 #define _B5EIDL_EID_POSITION 0x0 #define _B5EIDL_EID_SIZE 0x8 #define _B5EIDL_EID_LENGTH 0x8 #define _B5EIDL_EID_MASK 0xFF #define _B5EIDL_EID0_POSN 0x0 #define _B5EIDL_EID0_POSITION 0x0 #define _B5EIDL_EID0_SIZE 0x1 #define _B5EIDL_EID0_LENGTH 0x1 #define _B5EIDL_EID0_MASK 0x1 #define _B5EIDL_EID1_POSN 0x1 #define _B5EIDL_EID1_POSITION 0x1 #define _B5EIDL_EID1_SIZE 0x1 #define _B5EIDL_EID1_LENGTH 0x1 #define _B5EIDL_EID1_MASK 0x2 #define _B5EIDL_EID2_POSN 0x2 #define _B5EIDL_EID2_POSITION 0x2 #define _B5EIDL_EID2_SIZE 0x1 #define _B5EIDL_EID2_LENGTH 0x1 #define _B5EIDL_EID2_MASK 0x4 #define _B5EIDL_EID3_POSN 0x3 #define _B5EIDL_EID3_POSITION 0x3 #define _B5EIDL_EID3_SIZE 0x1 #define _B5EIDL_EID3_LENGTH 0x1 #define _B5EIDL_EID3_MASK 0x8 #define _B5EIDL_EID4_POSN 0x4 #define _B5EIDL_EID4_POSITION 0x4 #define _B5EIDL_EID4_SIZE 0x1 #define _B5EIDL_EID4_LENGTH 0x1 #define _B5EIDL_EID4_MASK 0x10 #define _B5EIDL_EID5_POSN 0x5 #define _B5EIDL_EID5_POSITION 0x5 #define _B5EIDL_EID5_SIZE 0x1 #define _B5EIDL_EID5_LENGTH 0x1 #define _B5EIDL_EID5_MASK 0x20 #define _B5EIDL_EID6_POSN 0x6 #define _B5EIDL_EID6_POSITION 0x6 #define _B5EIDL_EID6_SIZE 0x1 #define _B5EIDL_EID6_LENGTH 0x1 #define _B5EIDL_EID6_MASK 0x40 #define _B5EIDL_EID7_POSN 0x7 #define _B5EIDL_EID7_POSITION 0x7 #define _B5EIDL_EID7_SIZE 0x1 #define _B5EIDL_EID7_LENGTH 0x1 #define _B5EIDL_EID7_MASK 0x80 #define _B5EIDL_B5EID0_POSN 0x0 #define _B5EIDL_B5EID0_POSITION 0x0 #define _B5EIDL_B5EID0_SIZE 0x1 #define _B5EIDL_B5EID0_LENGTH 0x1 #define _B5EIDL_B5EID0_MASK 0x1 #define _B5EIDL_B5EID1_POSN 0x1 #define _B5EIDL_B5EID1_POSITION 0x1 #define _B5EIDL_B5EID1_SIZE 0x1 #define _B5EIDL_B5EID1_LENGTH 0x1 #define _B5EIDL_B5EID1_MASK 0x2 #define _B5EIDL_B5EID2_POSN 0x2 #define _B5EIDL_B5EID2_POSITION 0x2 #define _B5EIDL_B5EID2_SIZE 0x1 #define _B5EIDL_B5EID2_LENGTH 0x1 #define _B5EIDL_B5EID2_MASK 0x4 #define _B5EIDL_B5EID3_POSN 0x3 #define _B5EIDL_B5EID3_POSITION 0x3 #define _B5EIDL_B5EID3_SIZE 0x1 #define _B5EIDL_B5EID3_LENGTH 0x1 #define _B5EIDL_B5EID3_MASK 0x8 #define _B5EIDL_B5EID4_POSN 0x4 #define _B5EIDL_B5EID4_POSITION 0x4 #define _B5EIDL_B5EID4_SIZE 0x1 #define _B5EIDL_B5EID4_LENGTH 0x1 #define _B5EIDL_B5EID4_MASK 0x10 #define _B5EIDL_B5EID5_POSN 0x5 #define _B5EIDL_B5EID5_POSITION 0x5 #define _B5EIDL_B5EID5_SIZE 0x1 #define _B5EIDL_B5EID5_LENGTH 0x1 #define _B5EIDL_B5EID5_MASK 0x20 #define _B5EIDL_B5EID6_POSN 0x6 #define _B5EIDL_B5EID6_POSITION 0x6 #define _B5EIDL_B5EID6_SIZE 0x1 #define _B5EIDL_B5EID6_LENGTH 0x1 #define _B5EIDL_B5EID6_MASK 0x40 #define _B5EIDL_B5EID7_POSN 0x7 #define _B5EIDL_B5EID7_POSITION 0x7 #define _B5EIDL_B5EID7_SIZE 0x1 #define _B5EIDL_B5EID7_LENGTH 0x1 #define _B5EIDL_B5EID7_MASK 0x80 // Register: B5DLC #define B5DLC B5DLC extern volatile unsigned char B5DLC @ 0xED5; #ifndef _LIB_BUILD asm("B5DLC equ 0ED5h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR_TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; unsigned RXRTR :1; }; struct { unsigned :6; unsigned TXRTR :1; }; struct { unsigned B5DLC0 :1; unsigned B5DLC1 :1; unsigned B5DLC2 :1; unsigned B5DLC3 :1; unsigned B5RB0 :1; unsigned B5RB1 :1; unsigned B5RXRTR :1; }; } B5DLCbits_t; extern volatile B5DLCbits_t B5DLCbits @ 0xED5; // bitfield macros #define _B5DLC_DLC_POSN 0x0 #define _B5DLC_DLC_POSITION 0x0 #define _B5DLC_DLC_SIZE 0x4 #define _B5DLC_DLC_LENGTH 0x4 #define _B5DLC_DLC_MASK 0xF #define _B5DLC_RB_POSN 0x4 #define _B5DLC_RB_POSITION 0x4 #define _B5DLC_RB_SIZE 0x2 #define _B5DLC_RB_LENGTH 0x2 #define _B5DLC_RB_MASK 0x30 #define _B5DLC_RXRTR_TXRTR_POSN 0x6 #define _B5DLC_RXRTR_TXRTR_POSITION 0x6 #define _B5DLC_RXRTR_TXRTR_SIZE 0x1 #define _B5DLC_RXRTR_TXRTR_LENGTH 0x1 #define _B5DLC_RXRTR_TXRTR_MASK 0x40 #define _B5DLC_DLC0_POSN 0x0 #define _B5DLC_DLC0_POSITION 0x0 #define _B5DLC_DLC0_SIZE 0x1 #define _B5DLC_DLC0_LENGTH 0x1 #define _B5DLC_DLC0_MASK 0x1 #define _B5DLC_DLC1_POSN 0x1 #define _B5DLC_DLC1_POSITION 0x1 #define _B5DLC_DLC1_SIZE 0x1 #define _B5DLC_DLC1_LENGTH 0x1 #define _B5DLC_DLC1_MASK 0x2 #define _B5DLC_DLC2_POSN 0x2 #define _B5DLC_DLC2_POSITION 0x2 #define _B5DLC_DLC2_SIZE 0x1 #define _B5DLC_DLC2_LENGTH 0x1 #define _B5DLC_DLC2_MASK 0x4 #define _B5DLC_DLC3_POSN 0x3 #define _B5DLC_DLC3_POSITION 0x3 #define _B5DLC_DLC3_SIZE 0x1 #define _B5DLC_DLC3_LENGTH 0x1 #define _B5DLC_DLC3_MASK 0x8 #define _B5DLC_RB0_POSN 0x4 #define _B5DLC_RB0_POSITION 0x4 #define _B5DLC_RB0_SIZE 0x1 #define _B5DLC_RB0_LENGTH 0x1 #define _B5DLC_RB0_MASK 0x10 #define _B5DLC_RB1_POSN 0x5 #define _B5DLC_RB1_POSITION 0x5 #define _B5DLC_RB1_SIZE 0x1 #define _B5DLC_RB1_LENGTH 0x1 #define _B5DLC_RB1_MASK 0x20 #define _B5DLC_RXRTR_POSN 0x6 #define _B5DLC_RXRTR_POSITION 0x6 #define _B5DLC_RXRTR_SIZE 0x1 #define _B5DLC_RXRTR_LENGTH 0x1 #define _B5DLC_RXRTR_MASK 0x40 #define _B5DLC_TXRTR_POSN 0x6 #define _B5DLC_TXRTR_POSITION 0x6 #define _B5DLC_TXRTR_SIZE 0x1 #define _B5DLC_TXRTR_LENGTH 0x1 #define _B5DLC_TXRTR_MASK 0x40 #define _B5DLC_B5DLC0_POSN 0x0 #define _B5DLC_B5DLC0_POSITION 0x0 #define _B5DLC_B5DLC0_SIZE 0x1 #define _B5DLC_B5DLC0_LENGTH 0x1 #define _B5DLC_B5DLC0_MASK 0x1 #define _B5DLC_B5DLC1_POSN 0x1 #define _B5DLC_B5DLC1_POSITION 0x1 #define _B5DLC_B5DLC1_SIZE 0x1 #define _B5DLC_B5DLC1_LENGTH 0x1 #define _B5DLC_B5DLC1_MASK 0x2 #define _B5DLC_B5DLC2_POSN 0x2 #define _B5DLC_B5DLC2_POSITION 0x2 #define _B5DLC_B5DLC2_SIZE 0x1 #define _B5DLC_B5DLC2_LENGTH 0x1 #define _B5DLC_B5DLC2_MASK 0x4 #define _B5DLC_B5DLC3_POSN 0x3 #define _B5DLC_B5DLC3_POSITION 0x3 #define _B5DLC_B5DLC3_SIZE 0x1 #define _B5DLC_B5DLC3_LENGTH 0x1 #define _B5DLC_B5DLC3_MASK 0x8 #define _B5DLC_B5RB0_POSN 0x4 #define _B5DLC_B5RB0_POSITION 0x4 #define _B5DLC_B5RB0_SIZE 0x1 #define _B5DLC_B5RB0_LENGTH 0x1 #define _B5DLC_B5RB0_MASK 0x10 #define _B5DLC_B5RB1_POSN 0x5 #define _B5DLC_B5RB1_POSITION 0x5 #define _B5DLC_B5RB1_SIZE 0x1 #define _B5DLC_B5RB1_LENGTH 0x1 #define _B5DLC_B5RB1_MASK 0x20 #define _B5DLC_B5RXRTR_POSN 0x6 #define _B5DLC_B5RXRTR_POSITION 0x6 #define _B5DLC_B5RXRTR_SIZE 0x1 #define _B5DLC_B5RXRTR_LENGTH 0x1 #define _B5DLC_B5RXRTR_MASK 0x40 // Register: B5D0 #define B5D0 B5D0 extern volatile unsigned char B5D0 @ 0xED6; #ifndef _LIB_BUILD asm("B5D0 equ 0ED6h"); #endif // bitfield definitions typedef union { struct { unsigned B5D0 :8; }; struct { unsigned B5D00 :1; unsigned B5D01 :1; unsigned B5D02 :1; unsigned B5D03 :1; unsigned B5D04 :1; unsigned B5D05 :1; unsigned B5D06 :1; unsigned B5D07 :1; }; } B5D0bits_t; extern volatile B5D0bits_t B5D0bits @ 0xED6; // bitfield macros #define _B5D0_B5D0_POSN 0x0 #define _B5D0_B5D0_POSITION 0x0 #define _B5D0_B5D0_SIZE 0x8 #define _B5D0_B5D0_LENGTH 0x8 #define _B5D0_B5D0_MASK 0xFF #define _B5D0_B5D00_POSN 0x0 #define _B5D0_B5D00_POSITION 0x0 #define _B5D0_B5D00_SIZE 0x1 #define _B5D0_B5D00_LENGTH 0x1 #define _B5D0_B5D00_MASK 0x1 #define _B5D0_B5D01_POSN 0x1 #define _B5D0_B5D01_POSITION 0x1 #define _B5D0_B5D01_SIZE 0x1 #define _B5D0_B5D01_LENGTH 0x1 #define _B5D0_B5D01_MASK 0x2 #define _B5D0_B5D02_POSN 0x2 #define _B5D0_B5D02_POSITION 0x2 #define _B5D0_B5D02_SIZE 0x1 #define _B5D0_B5D02_LENGTH 0x1 #define _B5D0_B5D02_MASK 0x4 #define _B5D0_B5D03_POSN 0x3 #define _B5D0_B5D03_POSITION 0x3 #define _B5D0_B5D03_SIZE 0x1 #define _B5D0_B5D03_LENGTH 0x1 #define _B5D0_B5D03_MASK 0x8 #define _B5D0_B5D04_POSN 0x4 #define _B5D0_B5D04_POSITION 0x4 #define _B5D0_B5D04_SIZE 0x1 #define _B5D0_B5D04_LENGTH 0x1 #define _B5D0_B5D04_MASK 0x10 #define _B5D0_B5D05_POSN 0x5 #define _B5D0_B5D05_POSITION 0x5 #define _B5D0_B5D05_SIZE 0x1 #define _B5D0_B5D05_LENGTH 0x1 #define _B5D0_B5D05_MASK 0x20 #define _B5D0_B5D06_POSN 0x6 #define _B5D0_B5D06_POSITION 0x6 #define _B5D0_B5D06_SIZE 0x1 #define _B5D0_B5D06_LENGTH 0x1 #define _B5D0_B5D06_MASK 0x40 #define _B5D0_B5D07_POSN 0x7 #define _B5D0_B5D07_POSITION 0x7 #define _B5D0_B5D07_SIZE 0x1 #define _B5D0_B5D07_LENGTH 0x1 #define _B5D0_B5D07_MASK 0x80 // Register: B5D1 #define B5D1 B5D1 extern volatile unsigned char B5D1 @ 0xED7; #ifndef _LIB_BUILD asm("B5D1 equ 0ED7h"); #endif // bitfield definitions typedef union { struct { unsigned B5D1 :8; }; struct { unsigned B5D10 :1; unsigned B5D11 :1; unsigned B5D12 :1; unsigned B5D13 :1; unsigned B5D14 :1; unsigned B5D15 :1; unsigned B5D16 :1; unsigned B5D17 :1; }; } B5D1bits_t; extern volatile B5D1bits_t B5D1bits @ 0xED7; // bitfield macros #define _B5D1_B5D1_POSN 0x0 #define _B5D1_B5D1_POSITION 0x0 #define _B5D1_B5D1_SIZE 0x8 #define _B5D1_B5D1_LENGTH 0x8 #define _B5D1_B5D1_MASK 0xFF #define _B5D1_B5D10_POSN 0x0 #define _B5D1_B5D10_POSITION 0x0 #define _B5D1_B5D10_SIZE 0x1 #define _B5D1_B5D10_LENGTH 0x1 #define _B5D1_B5D10_MASK 0x1 #define _B5D1_B5D11_POSN 0x1 #define _B5D1_B5D11_POSITION 0x1 #define _B5D1_B5D11_SIZE 0x1 #define _B5D1_B5D11_LENGTH 0x1 #define _B5D1_B5D11_MASK 0x2 #define _B5D1_B5D12_POSN 0x2 #define _B5D1_B5D12_POSITION 0x2 #define _B5D1_B5D12_SIZE 0x1 #define _B5D1_B5D12_LENGTH 0x1 #define _B5D1_B5D12_MASK 0x4 #define _B5D1_B5D13_POSN 0x3 #define _B5D1_B5D13_POSITION 0x3 #define _B5D1_B5D13_SIZE 0x1 #define _B5D1_B5D13_LENGTH 0x1 #define _B5D1_B5D13_MASK 0x8 #define _B5D1_B5D14_POSN 0x4 #define _B5D1_B5D14_POSITION 0x4 #define _B5D1_B5D14_SIZE 0x1 #define _B5D1_B5D14_LENGTH 0x1 #define _B5D1_B5D14_MASK 0x10 #define _B5D1_B5D15_POSN 0x5 #define _B5D1_B5D15_POSITION 0x5 #define _B5D1_B5D15_SIZE 0x1 #define _B5D1_B5D15_LENGTH 0x1 #define _B5D1_B5D15_MASK 0x20 #define _B5D1_B5D16_POSN 0x6 #define _B5D1_B5D16_POSITION 0x6 #define _B5D1_B5D16_SIZE 0x1 #define _B5D1_B5D16_LENGTH 0x1 #define _B5D1_B5D16_MASK 0x40 #define _B5D1_B5D17_POSN 0x7 #define _B5D1_B5D17_POSITION 0x7 #define _B5D1_B5D17_SIZE 0x1 #define _B5D1_B5D17_LENGTH 0x1 #define _B5D1_B5D17_MASK 0x80 // Register: B5D2 #define B5D2 B5D2 extern volatile unsigned char B5D2 @ 0xED8; #ifndef _LIB_BUILD asm("B5D2 equ 0ED8h"); #endif // bitfield definitions typedef union { struct { unsigned B5D2 :8; }; struct { unsigned B5D20 :1; unsigned B5D21 :1; unsigned B5D22 :1; unsigned B5D23 :1; unsigned B5D24 :1; unsigned B5D25 :1; unsigned B5D26 :1; unsigned B5D27 :1; }; } B5D2bits_t; extern volatile B5D2bits_t B5D2bits @ 0xED8; // bitfield macros #define _B5D2_B5D2_POSN 0x0 #define _B5D2_B5D2_POSITION 0x0 #define _B5D2_B5D2_SIZE 0x8 #define _B5D2_B5D2_LENGTH 0x8 #define _B5D2_B5D2_MASK 0xFF #define _B5D2_B5D20_POSN 0x0 #define _B5D2_B5D20_POSITION 0x0 #define _B5D2_B5D20_SIZE 0x1 #define _B5D2_B5D20_LENGTH 0x1 #define _B5D2_B5D20_MASK 0x1 #define _B5D2_B5D21_POSN 0x1 #define _B5D2_B5D21_POSITION 0x1 #define _B5D2_B5D21_SIZE 0x1 #define _B5D2_B5D21_LENGTH 0x1 #define _B5D2_B5D21_MASK 0x2 #define _B5D2_B5D22_POSN 0x2 #define _B5D2_B5D22_POSITION 0x2 #define _B5D2_B5D22_SIZE 0x1 #define _B5D2_B5D22_LENGTH 0x1 #define _B5D2_B5D22_MASK 0x4 #define _B5D2_B5D23_POSN 0x3 #define _B5D2_B5D23_POSITION 0x3 #define _B5D2_B5D23_SIZE 0x1 #define _B5D2_B5D23_LENGTH 0x1 #define _B5D2_B5D23_MASK 0x8 #define _B5D2_B5D24_POSN 0x4 #define _B5D2_B5D24_POSITION 0x4 #define _B5D2_B5D24_SIZE 0x1 #define _B5D2_B5D24_LENGTH 0x1 #define _B5D2_B5D24_MASK 0x10 #define _B5D2_B5D25_POSN 0x5 #define _B5D2_B5D25_POSITION 0x5 #define _B5D2_B5D25_SIZE 0x1 #define _B5D2_B5D25_LENGTH 0x1 #define _B5D2_B5D25_MASK 0x20 #define _B5D2_B5D26_POSN 0x6 #define _B5D2_B5D26_POSITION 0x6 #define _B5D2_B5D26_SIZE 0x1 #define _B5D2_B5D26_LENGTH 0x1 #define _B5D2_B5D26_MASK 0x40 #define _B5D2_B5D27_POSN 0x7 #define _B5D2_B5D27_POSITION 0x7 #define _B5D2_B5D27_SIZE 0x1 #define _B5D2_B5D27_LENGTH 0x1 #define _B5D2_B5D27_MASK 0x80 // Register: B5D3 #define B5D3 B5D3 extern volatile unsigned char B5D3 @ 0xED9; #ifndef _LIB_BUILD asm("B5D3 equ 0ED9h"); #endif // bitfield definitions typedef union { struct { unsigned B5D3 :8; }; struct { unsigned B5D30 :1; unsigned B5D31 :1; unsigned B5D32 :1; unsigned B5D33 :1; unsigned B5D34 :1; unsigned B5D35 :1; unsigned B5D36 :1; unsigned B5D37 :1; }; } B5D3bits_t; extern volatile B5D3bits_t B5D3bits @ 0xED9; // bitfield macros #define _B5D3_B5D3_POSN 0x0 #define _B5D3_B5D3_POSITION 0x0 #define _B5D3_B5D3_SIZE 0x8 #define _B5D3_B5D3_LENGTH 0x8 #define _B5D3_B5D3_MASK 0xFF #define _B5D3_B5D30_POSN 0x0 #define _B5D3_B5D30_POSITION 0x0 #define _B5D3_B5D30_SIZE 0x1 #define _B5D3_B5D30_LENGTH 0x1 #define _B5D3_B5D30_MASK 0x1 #define _B5D3_B5D31_POSN 0x1 #define _B5D3_B5D31_POSITION 0x1 #define _B5D3_B5D31_SIZE 0x1 #define _B5D3_B5D31_LENGTH 0x1 #define _B5D3_B5D31_MASK 0x2 #define _B5D3_B5D32_POSN 0x2 #define _B5D3_B5D32_POSITION 0x2 #define _B5D3_B5D32_SIZE 0x1 #define _B5D3_B5D32_LENGTH 0x1 #define _B5D3_B5D32_MASK 0x4 #define _B5D3_B5D33_POSN 0x3 #define _B5D3_B5D33_POSITION 0x3 #define _B5D3_B5D33_SIZE 0x1 #define _B5D3_B5D33_LENGTH 0x1 #define _B5D3_B5D33_MASK 0x8 #define _B5D3_B5D34_POSN 0x4 #define _B5D3_B5D34_POSITION 0x4 #define _B5D3_B5D34_SIZE 0x1 #define _B5D3_B5D34_LENGTH 0x1 #define _B5D3_B5D34_MASK 0x10 #define _B5D3_B5D35_POSN 0x5 #define _B5D3_B5D35_POSITION 0x5 #define _B5D3_B5D35_SIZE 0x1 #define _B5D3_B5D35_LENGTH 0x1 #define _B5D3_B5D35_MASK 0x20 #define _B5D3_B5D36_POSN 0x6 #define _B5D3_B5D36_POSITION 0x6 #define _B5D3_B5D36_SIZE 0x1 #define _B5D3_B5D36_LENGTH 0x1 #define _B5D3_B5D36_MASK 0x40 #define _B5D3_B5D37_POSN 0x7 #define _B5D3_B5D37_POSITION 0x7 #define _B5D3_B5D37_SIZE 0x1 #define _B5D3_B5D37_LENGTH 0x1 #define _B5D3_B5D37_MASK 0x80 // Register: B5D4 #define B5D4 B5D4 extern volatile unsigned char B5D4 @ 0xEDA; #ifndef _LIB_BUILD asm("B5D4 equ 0EDAh"); #endif // bitfield definitions typedef union { struct { unsigned B5D4 :8; }; struct { unsigned B5D40 :1; unsigned B5D41 :1; unsigned B5D42 :1; unsigned B5D43 :1; unsigned B5D44 :1; unsigned B5D45 :1; unsigned B5D46 :1; unsigned B5D47 :1; }; } B5D4bits_t; extern volatile B5D4bits_t B5D4bits @ 0xEDA; // bitfield macros #define _B5D4_B5D4_POSN 0x0 #define _B5D4_B5D4_POSITION 0x0 #define _B5D4_B5D4_SIZE 0x8 #define _B5D4_B5D4_LENGTH 0x8 #define _B5D4_B5D4_MASK 0xFF #define _B5D4_B5D40_POSN 0x0 #define _B5D4_B5D40_POSITION 0x0 #define _B5D4_B5D40_SIZE 0x1 #define _B5D4_B5D40_LENGTH 0x1 #define _B5D4_B5D40_MASK 0x1 #define _B5D4_B5D41_POSN 0x1 #define _B5D4_B5D41_POSITION 0x1 #define _B5D4_B5D41_SIZE 0x1 #define _B5D4_B5D41_LENGTH 0x1 #define _B5D4_B5D41_MASK 0x2 #define _B5D4_B5D42_POSN 0x2 #define _B5D4_B5D42_POSITION 0x2 #define _B5D4_B5D42_SIZE 0x1 #define _B5D4_B5D42_LENGTH 0x1 #define _B5D4_B5D42_MASK 0x4 #define _B5D4_B5D43_POSN 0x3 #define _B5D4_B5D43_POSITION 0x3 #define _B5D4_B5D43_SIZE 0x1 #define _B5D4_B5D43_LENGTH 0x1 #define _B5D4_B5D43_MASK 0x8 #define _B5D4_B5D44_POSN 0x4 #define _B5D4_B5D44_POSITION 0x4 #define _B5D4_B5D44_SIZE 0x1 #define _B5D4_B5D44_LENGTH 0x1 #define _B5D4_B5D44_MASK 0x10 #define _B5D4_B5D45_POSN 0x5 #define _B5D4_B5D45_POSITION 0x5 #define _B5D4_B5D45_SIZE 0x1 #define _B5D4_B5D45_LENGTH 0x1 #define _B5D4_B5D45_MASK 0x20 #define _B5D4_B5D46_POSN 0x6 #define _B5D4_B5D46_POSITION 0x6 #define _B5D4_B5D46_SIZE 0x1 #define _B5D4_B5D46_LENGTH 0x1 #define _B5D4_B5D46_MASK 0x40 #define _B5D4_B5D47_POSN 0x7 #define _B5D4_B5D47_POSITION 0x7 #define _B5D4_B5D47_SIZE 0x1 #define _B5D4_B5D47_LENGTH 0x1 #define _B5D4_B5D47_MASK 0x80 // Register: B5D5 #define B5D5 B5D5 extern volatile unsigned char B5D5 @ 0xEDB; #ifndef _LIB_BUILD asm("B5D5 equ 0EDBh"); #endif // bitfield definitions typedef union { struct { unsigned B5D5 :8; }; struct { unsigned B5D50 :1; unsigned B5D51 :1; unsigned B5D52 :1; unsigned B5D53 :1; unsigned B5D54 :1; unsigned B5D55 :1; unsigned B5D56 :1; unsigned B5D57 :1; }; } B5D5bits_t; extern volatile B5D5bits_t B5D5bits @ 0xEDB; // bitfield macros #define _B5D5_B5D5_POSN 0x0 #define _B5D5_B5D5_POSITION 0x0 #define _B5D5_B5D5_SIZE 0x8 #define _B5D5_B5D5_LENGTH 0x8 #define _B5D5_B5D5_MASK 0xFF #define _B5D5_B5D50_POSN 0x0 #define _B5D5_B5D50_POSITION 0x0 #define _B5D5_B5D50_SIZE 0x1 #define _B5D5_B5D50_LENGTH 0x1 #define _B5D5_B5D50_MASK 0x1 #define _B5D5_B5D51_POSN 0x1 #define _B5D5_B5D51_POSITION 0x1 #define _B5D5_B5D51_SIZE 0x1 #define _B5D5_B5D51_LENGTH 0x1 #define _B5D5_B5D51_MASK 0x2 #define _B5D5_B5D52_POSN 0x2 #define _B5D5_B5D52_POSITION 0x2 #define _B5D5_B5D52_SIZE 0x1 #define _B5D5_B5D52_LENGTH 0x1 #define _B5D5_B5D52_MASK 0x4 #define _B5D5_B5D53_POSN 0x3 #define _B5D5_B5D53_POSITION 0x3 #define _B5D5_B5D53_SIZE 0x1 #define _B5D5_B5D53_LENGTH 0x1 #define _B5D5_B5D53_MASK 0x8 #define _B5D5_B5D54_POSN 0x4 #define _B5D5_B5D54_POSITION 0x4 #define _B5D5_B5D54_SIZE 0x1 #define _B5D5_B5D54_LENGTH 0x1 #define _B5D5_B5D54_MASK 0x10 #define _B5D5_B5D55_POSN 0x5 #define _B5D5_B5D55_POSITION 0x5 #define _B5D5_B5D55_SIZE 0x1 #define _B5D5_B5D55_LENGTH 0x1 #define _B5D5_B5D55_MASK 0x20 #define _B5D5_B5D56_POSN 0x6 #define _B5D5_B5D56_POSITION 0x6 #define _B5D5_B5D56_SIZE 0x1 #define _B5D5_B5D56_LENGTH 0x1 #define _B5D5_B5D56_MASK 0x40 #define _B5D5_B5D57_POSN 0x7 #define _B5D5_B5D57_POSITION 0x7 #define _B5D5_B5D57_SIZE 0x1 #define _B5D5_B5D57_LENGTH 0x1 #define _B5D5_B5D57_MASK 0x80 // Register: B5D6 #define B5D6 B5D6 extern volatile unsigned char B5D6 @ 0xEDC; #ifndef _LIB_BUILD asm("B5D6 equ 0EDCh"); #endif // bitfield definitions typedef union { struct { unsigned B5D6 :8; }; struct { unsigned B5D60 :1; unsigned B5D61 :1; unsigned B5D62 :1; unsigned B5D63 :1; unsigned B5D64 :1; unsigned B5D65 :1; unsigned B5D66 :1; unsigned B5D67 :1; }; } B5D6bits_t; extern volatile B5D6bits_t B5D6bits @ 0xEDC; // bitfield macros #define _B5D6_B5D6_POSN 0x0 #define _B5D6_B5D6_POSITION 0x0 #define _B5D6_B5D6_SIZE 0x8 #define _B5D6_B5D6_LENGTH 0x8 #define _B5D6_B5D6_MASK 0xFF #define _B5D6_B5D60_POSN 0x0 #define _B5D6_B5D60_POSITION 0x0 #define _B5D6_B5D60_SIZE 0x1 #define _B5D6_B5D60_LENGTH 0x1 #define _B5D6_B5D60_MASK 0x1 #define _B5D6_B5D61_POSN 0x1 #define _B5D6_B5D61_POSITION 0x1 #define _B5D6_B5D61_SIZE 0x1 #define _B5D6_B5D61_LENGTH 0x1 #define _B5D6_B5D61_MASK 0x2 #define _B5D6_B5D62_POSN 0x2 #define _B5D6_B5D62_POSITION 0x2 #define _B5D6_B5D62_SIZE 0x1 #define _B5D6_B5D62_LENGTH 0x1 #define _B5D6_B5D62_MASK 0x4 #define _B5D6_B5D63_POSN 0x3 #define _B5D6_B5D63_POSITION 0x3 #define _B5D6_B5D63_SIZE 0x1 #define _B5D6_B5D63_LENGTH 0x1 #define _B5D6_B5D63_MASK 0x8 #define _B5D6_B5D64_POSN 0x4 #define _B5D6_B5D64_POSITION 0x4 #define _B5D6_B5D64_SIZE 0x1 #define _B5D6_B5D64_LENGTH 0x1 #define _B5D6_B5D64_MASK 0x10 #define _B5D6_B5D65_POSN 0x5 #define _B5D6_B5D65_POSITION 0x5 #define _B5D6_B5D65_SIZE 0x1 #define _B5D6_B5D65_LENGTH 0x1 #define _B5D6_B5D65_MASK 0x20 #define _B5D6_B5D66_POSN 0x6 #define _B5D6_B5D66_POSITION 0x6 #define _B5D6_B5D66_SIZE 0x1 #define _B5D6_B5D66_LENGTH 0x1 #define _B5D6_B5D66_MASK 0x40 #define _B5D6_B5D67_POSN 0x7 #define _B5D6_B5D67_POSITION 0x7 #define _B5D6_B5D67_SIZE 0x1 #define _B5D6_B5D67_LENGTH 0x1 #define _B5D6_B5D67_MASK 0x80 // Register: B5D7 #define B5D7 B5D7 extern volatile unsigned char B5D7 @ 0xEDD; #ifndef _LIB_BUILD asm("B5D7 equ 0EDDh"); #endif // bitfield definitions typedef union { struct { unsigned B5D7 :8; }; struct { unsigned B5D70 :1; unsigned B5D71 :1; unsigned B5D72 :1; unsigned B5D73 :1; unsigned B5D74 :1; unsigned B5D75 :1; unsigned B5D76 :1; unsigned B5D77 :1; }; } B5D7bits_t; extern volatile B5D7bits_t B5D7bits @ 0xEDD; // bitfield macros #define _B5D7_B5D7_POSN 0x0 #define _B5D7_B5D7_POSITION 0x0 #define _B5D7_B5D7_SIZE 0x8 #define _B5D7_B5D7_LENGTH 0x8 #define _B5D7_B5D7_MASK 0xFF #define _B5D7_B5D70_POSN 0x0 #define _B5D7_B5D70_POSITION 0x0 #define _B5D7_B5D70_SIZE 0x1 #define _B5D7_B5D70_LENGTH 0x1 #define _B5D7_B5D70_MASK 0x1 #define _B5D7_B5D71_POSN 0x1 #define _B5D7_B5D71_POSITION 0x1 #define _B5D7_B5D71_SIZE 0x1 #define _B5D7_B5D71_LENGTH 0x1 #define _B5D7_B5D71_MASK 0x2 #define _B5D7_B5D72_POSN 0x2 #define _B5D7_B5D72_POSITION 0x2 #define _B5D7_B5D72_SIZE 0x1 #define _B5D7_B5D72_LENGTH 0x1 #define _B5D7_B5D72_MASK 0x4 #define _B5D7_B5D73_POSN 0x3 #define _B5D7_B5D73_POSITION 0x3 #define _B5D7_B5D73_SIZE 0x1 #define _B5D7_B5D73_LENGTH 0x1 #define _B5D7_B5D73_MASK 0x8 #define _B5D7_B5D74_POSN 0x4 #define _B5D7_B5D74_POSITION 0x4 #define _B5D7_B5D74_SIZE 0x1 #define _B5D7_B5D74_LENGTH 0x1 #define _B5D7_B5D74_MASK 0x10 #define _B5D7_B5D75_POSN 0x5 #define _B5D7_B5D75_POSITION 0x5 #define _B5D7_B5D75_SIZE 0x1 #define _B5D7_B5D75_LENGTH 0x1 #define _B5D7_B5D75_MASK 0x20 #define _B5D7_B5D76_POSN 0x6 #define _B5D7_B5D76_POSITION 0x6 #define _B5D7_B5D76_SIZE 0x1 #define _B5D7_B5D76_LENGTH 0x1 #define _B5D7_B5D76_MASK 0x40 #define _B5D7_B5D77_POSN 0x7 #define _B5D7_B5D77_POSITION 0x7 #define _B5D7_B5D77_SIZE 0x1 #define _B5D7_B5D77_LENGTH 0x1 #define _B5D7_B5D77_MASK 0x80 // Register: CANSTAT_RO4 #define CANSTAT_RO4 CANSTAT_RO4 extern volatile unsigned char CANSTAT_RO4 @ 0xEDE; #ifndef _LIB_BUILD asm("CANSTAT_RO4 equ 0EDEh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO4bits_t; extern volatile CANSTAT_RO4bits_t CANSTAT_RO4bits @ 0xEDE; // bitfield macros #define _CANSTAT_RO4_EICODE0_POSN 0x0 #define _CANSTAT_RO4_EICODE0_POSITION 0x0 #define _CANSTAT_RO4_EICODE0_SIZE 0x1 #define _CANSTAT_RO4_EICODE0_LENGTH 0x1 #define _CANSTAT_RO4_EICODE0_MASK 0x1 #define _CANSTAT_RO4_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO4_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO4_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO4_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO4_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO4_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO4_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO4_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO4_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO4_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO4_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO4_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO4_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO4_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO4_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO4_EICODE4_POSN 0x4 #define _CANSTAT_RO4_EICODE4_POSITION 0x4 #define _CANSTAT_RO4_EICODE4_SIZE 0x1 #define _CANSTAT_RO4_EICODE4_LENGTH 0x1 #define _CANSTAT_RO4_EICODE4_MASK 0x10 #define _CANSTAT_RO4_OPMODE_POSN 0x5 #define _CANSTAT_RO4_OPMODE_POSITION 0x5 #define _CANSTAT_RO4_OPMODE_SIZE 0x3 #define _CANSTAT_RO4_OPMODE_LENGTH 0x3 #define _CANSTAT_RO4_OPMODE_MASK 0xE0 #define _CANSTAT_RO4_EICODE1_POSN 0x1 #define _CANSTAT_RO4_EICODE1_POSITION 0x1 #define _CANSTAT_RO4_EICODE1_SIZE 0x1 #define _CANSTAT_RO4_EICODE1_LENGTH 0x1 #define _CANSTAT_RO4_EICODE1_MASK 0x2 #define _CANSTAT_RO4_EICODE2_POSN 0x2 #define _CANSTAT_RO4_EICODE2_POSITION 0x2 #define _CANSTAT_RO4_EICODE2_SIZE 0x1 #define _CANSTAT_RO4_EICODE2_LENGTH 0x1 #define _CANSTAT_RO4_EICODE2_MASK 0x4 #define _CANSTAT_RO4_EICODE3_POSN 0x3 #define _CANSTAT_RO4_EICODE3_POSITION 0x3 #define _CANSTAT_RO4_EICODE3_SIZE 0x1 #define _CANSTAT_RO4_EICODE3_LENGTH 0x1 #define _CANSTAT_RO4_EICODE3_MASK 0x8 #define _CANSTAT_RO4_OPMODE0_POSN 0x5 #define _CANSTAT_RO4_OPMODE0_POSITION 0x5 #define _CANSTAT_RO4_OPMODE0_SIZE 0x1 #define _CANSTAT_RO4_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO4_OPMODE0_MASK 0x20 #define _CANSTAT_RO4_OPMODE1_POSN 0x6 #define _CANSTAT_RO4_OPMODE1_POSITION 0x6 #define _CANSTAT_RO4_OPMODE1_SIZE 0x1 #define _CANSTAT_RO4_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO4_OPMODE1_MASK 0x40 #define _CANSTAT_RO4_OPMODE2_POSN 0x7 #define _CANSTAT_RO4_OPMODE2_POSITION 0x7 #define _CANSTAT_RO4_OPMODE2_SIZE 0x1 #define _CANSTAT_RO4_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO4_OPMODE2_MASK 0x80 #define _CANSTAT_RO4_ICODE0_POSN 0x1 #define _CANSTAT_RO4_ICODE0_POSITION 0x1 #define _CANSTAT_RO4_ICODE0_SIZE 0x1 #define _CANSTAT_RO4_ICODE0_LENGTH 0x1 #define _CANSTAT_RO4_ICODE0_MASK 0x2 #define _CANSTAT_RO4_ICODE1_POSN 0x2 #define _CANSTAT_RO4_ICODE1_POSITION 0x2 #define _CANSTAT_RO4_ICODE1_SIZE 0x1 #define _CANSTAT_RO4_ICODE1_LENGTH 0x1 #define _CANSTAT_RO4_ICODE1_MASK 0x4 #define _CANSTAT_RO4_ICODE2_POSN 0x3 #define _CANSTAT_RO4_ICODE2_POSITION 0x3 #define _CANSTAT_RO4_ICODE2_SIZE 0x1 #define _CANSTAT_RO4_ICODE2_LENGTH 0x1 #define _CANSTAT_RO4_ICODE2_MASK 0x8 // Register: CANCON_RO4 #define CANCON_RO4 CANCON_RO4 extern volatile unsigned char CANCON_RO4 @ 0xEDF; #ifndef _LIB_BUILD asm("CANCON_RO4 equ 0EDFh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO4bits_t; extern volatile CANCON_RO4bits_t CANCON_RO4bits @ 0xEDF; // bitfield macros #define _CANCON_RO4_FP0_POSN 0x0 #define _CANCON_RO4_FP0_POSITION 0x0 #define _CANCON_RO4_FP0_SIZE 0x1 #define _CANCON_RO4_FP0_LENGTH 0x1 #define _CANCON_RO4_FP0_MASK 0x1 #define _CANCON_RO4_WIN0_FP1_POSN 0x1 #define _CANCON_RO4_WIN0_FP1_POSITION 0x1 #define _CANCON_RO4_WIN0_FP1_SIZE 0x1 #define _CANCON_RO4_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO4_WIN0_FP1_MASK 0x2 #define _CANCON_RO4_WIN1_FP2_POSN 0x2 #define _CANCON_RO4_WIN1_FP2_POSITION 0x2 #define _CANCON_RO4_WIN1_FP2_SIZE 0x1 #define _CANCON_RO4_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO4_WIN1_FP2_MASK 0x4 #define _CANCON_RO4_WIN2_FP3_POSN 0x3 #define _CANCON_RO4_WIN2_FP3_POSITION 0x3 #define _CANCON_RO4_WIN2_FP3_SIZE 0x1 #define _CANCON_RO4_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO4_WIN2_FP3_MASK 0x8 #define _CANCON_RO4_ABAT_POSN 0x4 #define _CANCON_RO4_ABAT_POSITION 0x4 #define _CANCON_RO4_ABAT_SIZE 0x1 #define _CANCON_RO4_ABAT_LENGTH 0x1 #define _CANCON_RO4_ABAT_MASK 0x10 #define _CANCON_RO4_REQOP_POSN 0x5 #define _CANCON_RO4_REQOP_POSITION 0x5 #define _CANCON_RO4_REQOP_SIZE 0x3 #define _CANCON_RO4_REQOP_LENGTH 0x3 #define _CANCON_RO4_REQOP_MASK 0xE0 #define _CANCON_RO4_WIN0_POSN 0x1 #define _CANCON_RO4_WIN0_POSITION 0x1 #define _CANCON_RO4_WIN0_SIZE 0x1 #define _CANCON_RO4_WIN0_LENGTH 0x1 #define _CANCON_RO4_WIN0_MASK 0x2 #define _CANCON_RO4_WIN1_POSN 0x2 #define _CANCON_RO4_WIN1_POSITION 0x2 #define _CANCON_RO4_WIN1_SIZE 0x1 #define _CANCON_RO4_WIN1_LENGTH 0x1 #define _CANCON_RO4_WIN1_MASK 0x4 #define _CANCON_RO4_WIN2_POSN 0x3 #define _CANCON_RO4_WIN2_POSITION 0x3 #define _CANCON_RO4_WIN2_SIZE 0x1 #define _CANCON_RO4_WIN2_LENGTH 0x1 #define _CANCON_RO4_WIN2_MASK 0x8 #define _CANCON_RO4_FP1_POSN 0x1 #define _CANCON_RO4_FP1_POSITION 0x1 #define _CANCON_RO4_FP1_SIZE 0x1 #define _CANCON_RO4_FP1_LENGTH 0x1 #define _CANCON_RO4_FP1_MASK 0x2 #define _CANCON_RO4_FP2_POSN 0x2 #define _CANCON_RO4_FP2_POSITION 0x2 #define _CANCON_RO4_FP2_SIZE 0x1 #define _CANCON_RO4_FP2_LENGTH 0x1 #define _CANCON_RO4_FP2_MASK 0x4 #define _CANCON_RO4_FP3_POSN 0x3 #define _CANCON_RO4_FP3_POSITION 0x3 #define _CANCON_RO4_FP3_SIZE 0x1 #define _CANCON_RO4_FP3_LENGTH 0x1 #define _CANCON_RO4_FP3_MASK 0x8 // Register: RXF0SIDH #define RXF0SIDH RXF0SIDH extern volatile unsigned char RXF0SIDH @ 0xEE0; #ifndef _LIB_BUILD asm("RXF0SIDH equ 0EE0h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF0SID3 :1; unsigned RXF0SID4 :1; unsigned RXF0SID5 :1; unsigned RXF0SID6 :1; unsigned RXF0SID7 :1; unsigned RXF0SID8 :1; unsigned RXF0SID9 :1; unsigned RXF0SID10 :1; }; } RXF0SIDHbits_t; extern volatile RXF0SIDHbits_t RXF0SIDHbits @ 0xEE0; // bitfield macros #define _RXF0SIDH_SID_POSN 0x0 #define _RXF0SIDH_SID_POSITION 0x0 #define _RXF0SIDH_SID_SIZE 0x8 #define _RXF0SIDH_SID_LENGTH 0x8 #define _RXF0SIDH_SID_MASK 0xFF #define _RXF0SIDH_SID3_POSN 0x0 #define _RXF0SIDH_SID3_POSITION 0x0 #define _RXF0SIDH_SID3_SIZE 0x1 #define _RXF0SIDH_SID3_LENGTH 0x1 #define _RXF0SIDH_SID3_MASK 0x1 #define _RXF0SIDH_SID4_POSN 0x1 #define _RXF0SIDH_SID4_POSITION 0x1 #define _RXF0SIDH_SID4_SIZE 0x1 #define _RXF0SIDH_SID4_LENGTH 0x1 #define _RXF0SIDH_SID4_MASK 0x2 #define _RXF0SIDH_SID5_POSN 0x2 #define _RXF0SIDH_SID5_POSITION 0x2 #define _RXF0SIDH_SID5_SIZE 0x1 #define _RXF0SIDH_SID5_LENGTH 0x1 #define _RXF0SIDH_SID5_MASK 0x4 #define _RXF0SIDH_SID6_POSN 0x3 #define _RXF0SIDH_SID6_POSITION 0x3 #define _RXF0SIDH_SID6_SIZE 0x1 #define _RXF0SIDH_SID6_LENGTH 0x1 #define _RXF0SIDH_SID6_MASK 0x8 #define _RXF0SIDH_SID7_POSN 0x4 #define _RXF0SIDH_SID7_POSITION 0x4 #define _RXF0SIDH_SID7_SIZE 0x1 #define _RXF0SIDH_SID7_LENGTH 0x1 #define _RXF0SIDH_SID7_MASK 0x10 #define _RXF0SIDH_SID8_POSN 0x5 #define _RXF0SIDH_SID8_POSITION 0x5 #define _RXF0SIDH_SID8_SIZE 0x1 #define _RXF0SIDH_SID8_LENGTH 0x1 #define _RXF0SIDH_SID8_MASK 0x20 #define _RXF0SIDH_SID9_POSN 0x6 #define _RXF0SIDH_SID9_POSITION 0x6 #define _RXF0SIDH_SID9_SIZE 0x1 #define _RXF0SIDH_SID9_LENGTH 0x1 #define _RXF0SIDH_SID9_MASK 0x40 #define _RXF0SIDH_SID10_POSN 0x7 #define _RXF0SIDH_SID10_POSITION 0x7 #define _RXF0SIDH_SID10_SIZE 0x1 #define _RXF0SIDH_SID10_LENGTH 0x1 #define _RXF0SIDH_SID10_MASK 0x80 #define _RXF0SIDH_RXF0SID3_POSN 0x0 #define _RXF0SIDH_RXF0SID3_POSITION 0x0 #define _RXF0SIDH_RXF0SID3_SIZE 0x1 #define _RXF0SIDH_RXF0SID3_LENGTH 0x1 #define _RXF0SIDH_RXF0SID3_MASK 0x1 #define _RXF0SIDH_RXF0SID4_POSN 0x1 #define _RXF0SIDH_RXF0SID4_POSITION 0x1 #define _RXF0SIDH_RXF0SID4_SIZE 0x1 #define _RXF0SIDH_RXF0SID4_LENGTH 0x1 #define _RXF0SIDH_RXF0SID4_MASK 0x2 #define _RXF0SIDH_RXF0SID5_POSN 0x2 #define _RXF0SIDH_RXF0SID5_POSITION 0x2 #define _RXF0SIDH_RXF0SID5_SIZE 0x1 #define _RXF0SIDH_RXF0SID5_LENGTH 0x1 #define _RXF0SIDH_RXF0SID5_MASK 0x4 #define _RXF0SIDH_RXF0SID6_POSN 0x3 #define _RXF0SIDH_RXF0SID6_POSITION 0x3 #define _RXF0SIDH_RXF0SID6_SIZE 0x1 #define _RXF0SIDH_RXF0SID6_LENGTH 0x1 #define _RXF0SIDH_RXF0SID6_MASK 0x8 #define _RXF0SIDH_RXF0SID7_POSN 0x4 #define _RXF0SIDH_RXF0SID7_POSITION 0x4 #define _RXF0SIDH_RXF0SID7_SIZE 0x1 #define _RXF0SIDH_RXF0SID7_LENGTH 0x1 #define _RXF0SIDH_RXF0SID7_MASK 0x10 #define _RXF0SIDH_RXF0SID8_POSN 0x5 #define _RXF0SIDH_RXF0SID8_POSITION 0x5 #define _RXF0SIDH_RXF0SID8_SIZE 0x1 #define _RXF0SIDH_RXF0SID8_LENGTH 0x1 #define _RXF0SIDH_RXF0SID8_MASK 0x20 #define _RXF0SIDH_RXF0SID9_POSN 0x6 #define _RXF0SIDH_RXF0SID9_POSITION 0x6 #define _RXF0SIDH_RXF0SID9_SIZE 0x1 #define _RXF0SIDH_RXF0SID9_LENGTH 0x1 #define _RXF0SIDH_RXF0SID9_MASK 0x40 #define _RXF0SIDH_RXF0SID10_POSN 0x7 #define _RXF0SIDH_RXF0SID10_POSITION 0x7 #define _RXF0SIDH_RXF0SID10_SIZE 0x1 #define _RXF0SIDH_RXF0SID10_LENGTH 0x1 #define _RXF0SIDH_RXF0SID10_MASK 0x80 // Register: RXF0SIDL #define RXF0SIDL RXF0SIDL extern volatile unsigned char RXF0SIDL @ 0xEE1; #ifndef _LIB_BUILD asm("RXF0SIDL equ 0EE1h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF0EID16 :1; unsigned RXF0EID17 :1; unsigned :1; unsigned RXF0EXIDEN :1; unsigned :1; unsigned RXF0SID0 :1; unsigned RXF0SID1 :1; unsigned RXF0SID2 :1; }; } RXF0SIDLbits_t; extern volatile RXF0SIDLbits_t RXF0SIDLbits @ 0xEE1; // bitfield macros #define _RXF0SIDL_EID_POSN 0x0 #define _RXF0SIDL_EID_POSITION 0x0 #define _RXF0SIDL_EID_SIZE 0x2 #define _RXF0SIDL_EID_LENGTH 0x2 #define _RXF0SIDL_EID_MASK 0x3 #define _RXF0SIDL_EXIDEN_POSN 0x3 #define _RXF0SIDL_EXIDEN_POSITION 0x3 #define _RXF0SIDL_EXIDEN_SIZE 0x1 #define _RXF0SIDL_EXIDEN_LENGTH 0x1 #define _RXF0SIDL_EXIDEN_MASK 0x8 #define _RXF0SIDL_SID_POSN 0x5 #define _RXF0SIDL_SID_POSITION 0x5 #define _RXF0SIDL_SID_SIZE 0x3 #define _RXF0SIDL_SID_LENGTH 0x3 #define _RXF0SIDL_SID_MASK 0xE0 #define _RXF0SIDL_EID16_POSN 0x0 #define _RXF0SIDL_EID16_POSITION 0x0 #define _RXF0SIDL_EID16_SIZE 0x1 #define _RXF0SIDL_EID16_LENGTH 0x1 #define _RXF0SIDL_EID16_MASK 0x1 #define _RXF0SIDL_EID17_POSN 0x1 #define _RXF0SIDL_EID17_POSITION 0x1 #define _RXF0SIDL_EID17_SIZE 0x1 #define _RXF0SIDL_EID17_LENGTH 0x1 #define _RXF0SIDL_EID17_MASK 0x2 #define _RXF0SIDL_SID0_POSN 0x5 #define _RXF0SIDL_SID0_POSITION 0x5 #define _RXF0SIDL_SID0_SIZE 0x1 #define _RXF0SIDL_SID0_LENGTH 0x1 #define _RXF0SIDL_SID0_MASK 0x20 #define _RXF0SIDL_SID1_POSN 0x6 #define _RXF0SIDL_SID1_POSITION 0x6 #define _RXF0SIDL_SID1_SIZE 0x1 #define _RXF0SIDL_SID1_LENGTH 0x1 #define _RXF0SIDL_SID1_MASK 0x40 #define _RXF0SIDL_SID2_POSN 0x7 #define _RXF0SIDL_SID2_POSITION 0x7 #define _RXF0SIDL_SID2_SIZE 0x1 #define _RXF0SIDL_SID2_LENGTH 0x1 #define _RXF0SIDL_SID2_MASK 0x80 #define _RXF0SIDL_RXF0EID16_POSN 0x0 #define _RXF0SIDL_RXF0EID16_POSITION 0x0 #define _RXF0SIDL_RXF0EID16_SIZE 0x1 #define _RXF0SIDL_RXF0EID16_LENGTH 0x1 #define _RXF0SIDL_RXF0EID16_MASK 0x1 #define _RXF0SIDL_RXF0EID17_POSN 0x1 #define _RXF0SIDL_RXF0EID17_POSITION 0x1 #define _RXF0SIDL_RXF0EID17_SIZE 0x1 #define _RXF0SIDL_RXF0EID17_LENGTH 0x1 #define _RXF0SIDL_RXF0EID17_MASK 0x2 #define _RXF0SIDL_RXF0EXIDEN_POSN 0x3 #define _RXF0SIDL_RXF0EXIDEN_POSITION 0x3 #define _RXF0SIDL_RXF0EXIDEN_SIZE 0x1 #define _RXF0SIDL_RXF0EXIDEN_LENGTH 0x1 #define _RXF0SIDL_RXF0EXIDEN_MASK 0x8 #define _RXF0SIDL_RXF0SID0_POSN 0x5 #define _RXF0SIDL_RXF0SID0_POSITION 0x5 #define _RXF0SIDL_RXF0SID0_SIZE 0x1 #define _RXF0SIDL_RXF0SID0_LENGTH 0x1 #define _RXF0SIDL_RXF0SID0_MASK 0x20 #define _RXF0SIDL_RXF0SID1_POSN 0x6 #define _RXF0SIDL_RXF0SID1_POSITION 0x6 #define _RXF0SIDL_RXF0SID1_SIZE 0x1 #define _RXF0SIDL_RXF0SID1_LENGTH 0x1 #define _RXF0SIDL_RXF0SID1_MASK 0x40 #define _RXF0SIDL_RXF0SID2_POSN 0x7 #define _RXF0SIDL_RXF0SID2_POSITION 0x7 #define _RXF0SIDL_RXF0SID2_SIZE 0x1 #define _RXF0SIDL_RXF0SID2_LENGTH 0x1 #define _RXF0SIDL_RXF0SID2_MASK 0x80 // Register: RXF0EIDH #define RXF0EIDH RXF0EIDH extern volatile unsigned char RXF0EIDH @ 0xEE2; #ifndef _LIB_BUILD asm("RXF0EIDH equ 0EE2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF0EID8 :1; unsigned RXF0EID9 :1; unsigned RXF0EID10 :1; unsigned RXF0EID11 :1; unsigned RXF0EID12 :1; unsigned RXF0EID13 :1; unsigned RXF0EID14 :1; unsigned RXF0EID15 :1; }; } RXF0EIDHbits_t; extern volatile RXF0EIDHbits_t RXF0EIDHbits @ 0xEE2; // bitfield macros #define _RXF0EIDH_EID_POSN 0x0 #define _RXF0EIDH_EID_POSITION 0x0 #define _RXF0EIDH_EID_SIZE 0x8 #define _RXF0EIDH_EID_LENGTH 0x8 #define _RXF0EIDH_EID_MASK 0xFF #define _RXF0EIDH_EID8_POSN 0x0 #define _RXF0EIDH_EID8_POSITION 0x0 #define _RXF0EIDH_EID8_SIZE 0x1 #define _RXF0EIDH_EID8_LENGTH 0x1 #define _RXF0EIDH_EID8_MASK 0x1 #define _RXF0EIDH_EID9_POSN 0x1 #define _RXF0EIDH_EID9_POSITION 0x1 #define _RXF0EIDH_EID9_SIZE 0x1 #define _RXF0EIDH_EID9_LENGTH 0x1 #define _RXF0EIDH_EID9_MASK 0x2 #define _RXF0EIDH_EID10_POSN 0x2 #define _RXF0EIDH_EID10_POSITION 0x2 #define _RXF0EIDH_EID10_SIZE 0x1 #define _RXF0EIDH_EID10_LENGTH 0x1 #define _RXF0EIDH_EID10_MASK 0x4 #define _RXF0EIDH_EID11_POSN 0x3 #define _RXF0EIDH_EID11_POSITION 0x3 #define _RXF0EIDH_EID11_SIZE 0x1 #define _RXF0EIDH_EID11_LENGTH 0x1 #define _RXF0EIDH_EID11_MASK 0x8 #define _RXF0EIDH_EID12_POSN 0x4 #define _RXF0EIDH_EID12_POSITION 0x4 #define _RXF0EIDH_EID12_SIZE 0x1 #define _RXF0EIDH_EID12_LENGTH 0x1 #define _RXF0EIDH_EID12_MASK 0x10 #define _RXF0EIDH_EID13_POSN 0x5 #define _RXF0EIDH_EID13_POSITION 0x5 #define _RXF0EIDH_EID13_SIZE 0x1 #define _RXF0EIDH_EID13_LENGTH 0x1 #define _RXF0EIDH_EID13_MASK 0x20 #define _RXF0EIDH_EID14_POSN 0x6 #define _RXF0EIDH_EID14_POSITION 0x6 #define _RXF0EIDH_EID14_SIZE 0x1 #define _RXF0EIDH_EID14_LENGTH 0x1 #define _RXF0EIDH_EID14_MASK 0x40 #define _RXF0EIDH_EID15_POSN 0x7 #define _RXF0EIDH_EID15_POSITION 0x7 #define _RXF0EIDH_EID15_SIZE 0x1 #define _RXF0EIDH_EID15_LENGTH 0x1 #define _RXF0EIDH_EID15_MASK 0x80 #define _RXF0EIDH_RXF0EID8_POSN 0x0 #define _RXF0EIDH_RXF0EID8_POSITION 0x0 #define _RXF0EIDH_RXF0EID8_SIZE 0x1 #define _RXF0EIDH_RXF0EID8_LENGTH 0x1 #define _RXF0EIDH_RXF0EID8_MASK 0x1 #define _RXF0EIDH_RXF0EID9_POSN 0x1 #define _RXF0EIDH_RXF0EID9_POSITION 0x1 #define _RXF0EIDH_RXF0EID9_SIZE 0x1 #define _RXF0EIDH_RXF0EID9_LENGTH 0x1 #define _RXF0EIDH_RXF0EID9_MASK 0x2 #define _RXF0EIDH_RXF0EID10_POSN 0x2 #define _RXF0EIDH_RXF0EID10_POSITION 0x2 #define _RXF0EIDH_RXF0EID10_SIZE 0x1 #define _RXF0EIDH_RXF0EID10_LENGTH 0x1 #define _RXF0EIDH_RXF0EID10_MASK 0x4 #define _RXF0EIDH_RXF0EID11_POSN 0x3 #define _RXF0EIDH_RXF0EID11_POSITION 0x3 #define _RXF0EIDH_RXF0EID11_SIZE 0x1 #define _RXF0EIDH_RXF0EID11_LENGTH 0x1 #define _RXF0EIDH_RXF0EID11_MASK 0x8 #define _RXF0EIDH_RXF0EID12_POSN 0x4 #define _RXF0EIDH_RXF0EID12_POSITION 0x4 #define _RXF0EIDH_RXF0EID12_SIZE 0x1 #define _RXF0EIDH_RXF0EID12_LENGTH 0x1 #define _RXF0EIDH_RXF0EID12_MASK 0x10 #define _RXF0EIDH_RXF0EID13_POSN 0x5 #define _RXF0EIDH_RXF0EID13_POSITION 0x5 #define _RXF0EIDH_RXF0EID13_SIZE 0x1 #define _RXF0EIDH_RXF0EID13_LENGTH 0x1 #define _RXF0EIDH_RXF0EID13_MASK 0x20 #define _RXF0EIDH_RXF0EID14_POSN 0x6 #define _RXF0EIDH_RXF0EID14_POSITION 0x6 #define _RXF0EIDH_RXF0EID14_SIZE 0x1 #define _RXF0EIDH_RXF0EID14_LENGTH 0x1 #define _RXF0EIDH_RXF0EID14_MASK 0x40 #define _RXF0EIDH_RXF0EID15_POSN 0x7 #define _RXF0EIDH_RXF0EID15_POSITION 0x7 #define _RXF0EIDH_RXF0EID15_SIZE 0x1 #define _RXF0EIDH_RXF0EID15_LENGTH 0x1 #define _RXF0EIDH_RXF0EID15_MASK 0x80 // Register: RXF0EIDL #define RXF0EIDL RXF0EIDL extern volatile unsigned char RXF0EIDL @ 0xEE3; #ifndef _LIB_BUILD asm("RXF0EIDL equ 0EE3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF0EID0 :1; unsigned RXF0EID1 :1; unsigned RXF0EID2 :1; unsigned RXF0EID3 :1; unsigned RXF0EID4 :1; unsigned RXF0EID5 :1; unsigned RXF0EID6 :1; unsigned RXF0EID7 :1; }; } RXF0EIDLbits_t; extern volatile RXF0EIDLbits_t RXF0EIDLbits @ 0xEE3; // bitfield macros #define _RXF0EIDL_EID_POSN 0x0 #define _RXF0EIDL_EID_POSITION 0x0 #define _RXF0EIDL_EID_SIZE 0x8 #define _RXF0EIDL_EID_LENGTH 0x8 #define _RXF0EIDL_EID_MASK 0xFF #define _RXF0EIDL_EID0_POSN 0x0 #define _RXF0EIDL_EID0_POSITION 0x0 #define _RXF0EIDL_EID0_SIZE 0x1 #define _RXF0EIDL_EID0_LENGTH 0x1 #define _RXF0EIDL_EID0_MASK 0x1 #define _RXF0EIDL_EID1_POSN 0x1 #define _RXF0EIDL_EID1_POSITION 0x1 #define _RXF0EIDL_EID1_SIZE 0x1 #define _RXF0EIDL_EID1_LENGTH 0x1 #define _RXF0EIDL_EID1_MASK 0x2 #define _RXF0EIDL_EID2_POSN 0x2 #define _RXF0EIDL_EID2_POSITION 0x2 #define _RXF0EIDL_EID2_SIZE 0x1 #define _RXF0EIDL_EID2_LENGTH 0x1 #define _RXF0EIDL_EID2_MASK 0x4 #define _RXF0EIDL_EID3_POSN 0x3 #define _RXF0EIDL_EID3_POSITION 0x3 #define _RXF0EIDL_EID3_SIZE 0x1 #define _RXF0EIDL_EID3_LENGTH 0x1 #define _RXF0EIDL_EID3_MASK 0x8 #define _RXF0EIDL_EID4_POSN 0x4 #define _RXF0EIDL_EID4_POSITION 0x4 #define _RXF0EIDL_EID4_SIZE 0x1 #define _RXF0EIDL_EID4_LENGTH 0x1 #define _RXF0EIDL_EID4_MASK 0x10 #define _RXF0EIDL_EID5_POSN 0x5 #define _RXF0EIDL_EID5_POSITION 0x5 #define _RXF0EIDL_EID5_SIZE 0x1 #define _RXF0EIDL_EID5_LENGTH 0x1 #define _RXF0EIDL_EID5_MASK 0x20 #define _RXF0EIDL_EID6_POSN 0x6 #define _RXF0EIDL_EID6_POSITION 0x6 #define _RXF0EIDL_EID6_SIZE 0x1 #define _RXF0EIDL_EID6_LENGTH 0x1 #define _RXF0EIDL_EID6_MASK 0x40 #define _RXF0EIDL_EID7_POSN 0x7 #define _RXF0EIDL_EID7_POSITION 0x7 #define _RXF0EIDL_EID7_SIZE 0x1 #define _RXF0EIDL_EID7_LENGTH 0x1 #define _RXF0EIDL_EID7_MASK 0x80 #define _RXF0EIDL_RXF0EID0_POSN 0x0 #define _RXF0EIDL_RXF0EID0_POSITION 0x0 #define _RXF0EIDL_RXF0EID0_SIZE 0x1 #define _RXF0EIDL_RXF0EID0_LENGTH 0x1 #define _RXF0EIDL_RXF0EID0_MASK 0x1 #define _RXF0EIDL_RXF0EID1_POSN 0x1 #define _RXF0EIDL_RXF0EID1_POSITION 0x1 #define _RXF0EIDL_RXF0EID1_SIZE 0x1 #define _RXF0EIDL_RXF0EID1_LENGTH 0x1 #define _RXF0EIDL_RXF0EID1_MASK 0x2 #define _RXF0EIDL_RXF0EID2_POSN 0x2 #define _RXF0EIDL_RXF0EID2_POSITION 0x2 #define _RXF0EIDL_RXF0EID2_SIZE 0x1 #define _RXF0EIDL_RXF0EID2_LENGTH 0x1 #define _RXF0EIDL_RXF0EID2_MASK 0x4 #define _RXF0EIDL_RXF0EID3_POSN 0x3 #define _RXF0EIDL_RXF0EID3_POSITION 0x3 #define _RXF0EIDL_RXF0EID3_SIZE 0x1 #define _RXF0EIDL_RXF0EID3_LENGTH 0x1 #define _RXF0EIDL_RXF0EID3_MASK 0x8 #define _RXF0EIDL_RXF0EID4_POSN 0x4 #define _RXF0EIDL_RXF0EID4_POSITION 0x4 #define _RXF0EIDL_RXF0EID4_SIZE 0x1 #define _RXF0EIDL_RXF0EID4_LENGTH 0x1 #define _RXF0EIDL_RXF0EID4_MASK 0x10 #define _RXF0EIDL_RXF0EID5_POSN 0x5 #define _RXF0EIDL_RXF0EID5_POSITION 0x5 #define _RXF0EIDL_RXF0EID5_SIZE 0x1 #define _RXF0EIDL_RXF0EID5_LENGTH 0x1 #define _RXF0EIDL_RXF0EID5_MASK 0x20 #define _RXF0EIDL_RXF0EID6_POSN 0x6 #define _RXF0EIDL_RXF0EID6_POSITION 0x6 #define _RXF0EIDL_RXF0EID6_SIZE 0x1 #define _RXF0EIDL_RXF0EID6_LENGTH 0x1 #define _RXF0EIDL_RXF0EID6_MASK 0x40 #define _RXF0EIDL_RXF0EID7_POSN 0x7 #define _RXF0EIDL_RXF0EID7_POSITION 0x7 #define _RXF0EIDL_RXF0EID7_SIZE 0x1 #define _RXF0EIDL_RXF0EID7_LENGTH 0x1 #define _RXF0EIDL_RXF0EID7_MASK 0x80 // Register: RXF1SIDH #define RXF1SIDH RXF1SIDH extern volatile unsigned char RXF1SIDH @ 0xEE4; #ifndef _LIB_BUILD asm("RXF1SIDH equ 0EE4h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF1SID3 :1; unsigned RXF1SID4 :1; unsigned RXF1SID5 :1; unsigned RXF1SID6 :1; unsigned RXF1SID7 :1; unsigned RXF1SID8 :1; unsigned RXF1SID9 :1; unsigned RXF1SID10 :1; }; } RXF1SIDHbits_t; extern volatile RXF1SIDHbits_t RXF1SIDHbits @ 0xEE4; // bitfield macros #define _RXF1SIDH_SID_POSN 0x0 #define _RXF1SIDH_SID_POSITION 0x0 #define _RXF1SIDH_SID_SIZE 0x8 #define _RXF1SIDH_SID_LENGTH 0x8 #define _RXF1SIDH_SID_MASK 0xFF #define _RXF1SIDH_SID3_POSN 0x0 #define _RXF1SIDH_SID3_POSITION 0x0 #define _RXF1SIDH_SID3_SIZE 0x1 #define _RXF1SIDH_SID3_LENGTH 0x1 #define _RXF1SIDH_SID3_MASK 0x1 #define _RXF1SIDH_SID4_POSN 0x1 #define _RXF1SIDH_SID4_POSITION 0x1 #define _RXF1SIDH_SID4_SIZE 0x1 #define _RXF1SIDH_SID4_LENGTH 0x1 #define _RXF1SIDH_SID4_MASK 0x2 #define _RXF1SIDH_SID5_POSN 0x2 #define _RXF1SIDH_SID5_POSITION 0x2 #define _RXF1SIDH_SID5_SIZE 0x1 #define _RXF1SIDH_SID5_LENGTH 0x1 #define _RXF1SIDH_SID5_MASK 0x4 #define _RXF1SIDH_SID6_POSN 0x3 #define _RXF1SIDH_SID6_POSITION 0x3 #define _RXF1SIDH_SID6_SIZE 0x1 #define _RXF1SIDH_SID6_LENGTH 0x1 #define _RXF1SIDH_SID6_MASK 0x8 #define _RXF1SIDH_SID7_POSN 0x4 #define _RXF1SIDH_SID7_POSITION 0x4 #define _RXF1SIDH_SID7_SIZE 0x1 #define _RXF1SIDH_SID7_LENGTH 0x1 #define _RXF1SIDH_SID7_MASK 0x10 #define _RXF1SIDH_SID8_POSN 0x5 #define _RXF1SIDH_SID8_POSITION 0x5 #define _RXF1SIDH_SID8_SIZE 0x1 #define _RXF1SIDH_SID8_LENGTH 0x1 #define _RXF1SIDH_SID8_MASK 0x20 #define _RXF1SIDH_SID9_POSN 0x6 #define _RXF1SIDH_SID9_POSITION 0x6 #define _RXF1SIDH_SID9_SIZE 0x1 #define _RXF1SIDH_SID9_LENGTH 0x1 #define _RXF1SIDH_SID9_MASK 0x40 #define _RXF1SIDH_SID10_POSN 0x7 #define _RXF1SIDH_SID10_POSITION 0x7 #define _RXF1SIDH_SID10_SIZE 0x1 #define _RXF1SIDH_SID10_LENGTH 0x1 #define _RXF1SIDH_SID10_MASK 0x80 #define _RXF1SIDH_RXF1SID3_POSN 0x0 #define _RXF1SIDH_RXF1SID3_POSITION 0x0 #define _RXF1SIDH_RXF1SID3_SIZE 0x1 #define _RXF1SIDH_RXF1SID3_LENGTH 0x1 #define _RXF1SIDH_RXF1SID3_MASK 0x1 #define _RXF1SIDH_RXF1SID4_POSN 0x1 #define _RXF1SIDH_RXF1SID4_POSITION 0x1 #define _RXF1SIDH_RXF1SID4_SIZE 0x1 #define _RXF1SIDH_RXF1SID4_LENGTH 0x1 #define _RXF1SIDH_RXF1SID4_MASK 0x2 #define _RXF1SIDH_RXF1SID5_POSN 0x2 #define _RXF1SIDH_RXF1SID5_POSITION 0x2 #define _RXF1SIDH_RXF1SID5_SIZE 0x1 #define _RXF1SIDH_RXF1SID5_LENGTH 0x1 #define _RXF1SIDH_RXF1SID5_MASK 0x4 #define _RXF1SIDH_RXF1SID6_POSN 0x3 #define _RXF1SIDH_RXF1SID6_POSITION 0x3 #define _RXF1SIDH_RXF1SID6_SIZE 0x1 #define _RXF1SIDH_RXF1SID6_LENGTH 0x1 #define _RXF1SIDH_RXF1SID6_MASK 0x8 #define _RXF1SIDH_RXF1SID7_POSN 0x4 #define _RXF1SIDH_RXF1SID7_POSITION 0x4 #define _RXF1SIDH_RXF1SID7_SIZE 0x1 #define _RXF1SIDH_RXF1SID7_LENGTH 0x1 #define _RXF1SIDH_RXF1SID7_MASK 0x10 #define _RXF1SIDH_RXF1SID8_POSN 0x5 #define _RXF1SIDH_RXF1SID8_POSITION 0x5 #define _RXF1SIDH_RXF1SID8_SIZE 0x1 #define _RXF1SIDH_RXF1SID8_LENGTH 0x1 #define _RXF1SIDH_RXF1SID8_MASK 0x20 #define _RXF1SIDH_RXF1SID9_POSN 0x6 #define _RXF1SIDH_RXF1SID9_POSITION 0x6 #define _RXF1SIDH_RXF1SID9_SIZE 0x1 #define _RXF1SIDH_RXF1SID9_LENGTH 0x1 #define _RXF1SIDH_RXF1SID9_MASK 0x40 #define _RXF1SIDH_RXF1SID10_POSN 0x7 #define _RXF1SIDH_RXF1SID10_POSITION 0x7 #define _RXF1SIDH_RXF1SID10_SIZE 0x1 #define _RXF1SIDH_RXF1SID10_LENGTH 0x1 #define _RXF1SIDH_RXF1SID10_MASK 0x80 // Register: RXF1SIDL #define RXF1SIDL RXF1SIDL extern volatile unsigned char RXF1SIDL @ 0xEE5; #ifndef _LIB_BUILD asm("RXF1SIDL equ 0EE5h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF1EID16 :1; unsigned RXF1EID17 :1; unsigned :1; unsigned RXF1EXIDEN :1; unsigned :1; unsigned RXF1SID0 :1; unsigned RXF1SID1 :1; unsigned RXF1SID2 :1; }; } RXF1SIDLbits_t; extern volatile RXF1SIDLbits_t RXF1SIDLbits @ 0xEE5; // bitfield macros #define _RXF1SIDL_EID_POSN 0x0 #define _RXF1SIDL_EID_POSITION 0x0 #define _RXF1SIDL_EID_SIZE 0x2 #define _RXF1SIDL_EID_LENGTH 0x2 #define _RXF1SIDL_EID_MASK 0x3 #define _RXF1SIDL_EXIDEN_POSN 0x3 #define _RXF1SIDL_EXIDEN_POSITION 0x3 #define _RXF1SIDL_EXIDEN_SIZE 0x1 #define _RXF1SIDL_EXIDEN_LENGTH 0x1 #define _RXF1SIDL_EXIDEN_MASK 0x8 #define _RXF1SIDL_SID_POSN 0x5 #define _RXF1SIDL_SID_POSITION 0x5 #define _RXF1SIDL_SID_SIZE 0x3 #define _RXF1SIDL_SID_LENGTH 0x3 #define _RXF1SIDL_SID_MASK 0xE0 #define _RXF1SIDL_EID16_POSN 0x0 #define _RXF1SIDL_EID16_POSITION 0x0 #define _RXF1SIDL_EID16_SIZE 0x1 #define _RXF1SIDL_EID16_LENGTH 0x1 #define _RXF1SIDL_EID16_MASK 0x1 #define _RXF1SIDL_EID17_POSN 0x1 #define _RXF1SIDL_EID17_POSITION 0x1 #define _RXF1SIDL_EID17_SIZE 0x1 #define _RXF1SIDL_EID17_LENGTH 0x1 #define _RXF1SIDL_EID17_MASK 0x2 #define _RXF1SIDL_SID0_POSN 0x5 #define _RXF1SIDL_SID0_POSITION 0x5 #define _RXF1SIDL_SID0_SIZE 0x1 #define _RXF1SIDL_SID0_LENGTH 0x1 #define _RXF1SIDL_SID0_MASK 0x20 #define _RXF1SIDL_SID1_POSN 0x6 #define _RXF1SIDL_SID1_POSITION 0x6 #define _RXF1SIDL_SID1_SIZE 0x1 #define _RXF1SIDL_SID1_LENGTH 0x1 #define _RXF1SIDL_SID1_MASK 0x40 #define _RXF1SIDL_SID2_POSN 0x7 #define _RXF1SIDL_SID2_POSITION 0x7 #define _RXF1SIDL_SID2_SIZE 0x1 #define _RXF1SIDL_SID2_LENGTH 0x1 #define _RXF1SIDL_SID2_MASK 0x80 #define _RXF1SIDL_RXF1EID16_POSN 0x0 #define _RXF1SIDL_RXF1EID16_POSITION 0x0 #define _RXF1SIDL_RXF1EID16_SIZE 0x1 #define _RXF1SIDL_RXF1EID16_LENGTH 0x1 #define _RXF1SIDL_RXF1EID16_MASK 0x1 #define _RXF1SIDL_RXF1EID17_POSN 0x1 #define _RXF1SIDL_RXF1EID17_POSITION 0x1 #define _RXF1SIDL_RXF1EID17_SIZE 0x1 #define _RXF1SIDL_RXF1EID17_LENGTH 0x1 #define _RXF1SIDL_RXF1EID17_MASK 0x2 #define _RXF1SIDL_RXF1EXIDEN_POSN 0x3 #define _RXF1SIDL_RXF1EXIDEN_POSITION 0x3 #define _RXF1SIDL_RXF1EXIDEN_SIZE 0x1 #define _RXF1SIDL_RXF1EXIDEN_LENGTH 0x1 #define _RXF1SIDL_RXF1EXIDEN_MASK 0x8 #define _RXF1SIDL_RXF1SID0_POSN 0x5 #define _RXF1SIDL_RXF1SID0_POSITION 0x5 #define _RXF1SIDL_RXF1SID0_SIZE 0x1 #define _RXF1SIDL_RXF1SID0_LENGTH 0x1 #define _RXF1SIDL_RXF1SID0_MASK 0x20 #define _RXF1SIDL_RXF1SID1_POSN 0x6 #define _RXF1SIDL_RXF1SID1_POSITION 0x6 #define _RXF1SIDL_RXF1SID1_SIZE 0x1 #define _RXF1SIDL_RXF1SID1_LENGTH 0x1 #define _RXF1SIDL_RXF1SID1_MASK 0x40 #define _RXF1SIDL_RXF1SID2_POSN 0x7 #define _RXF1SIDL_RXF1SID2_POSITION 0x7 #define _RXF1SIDL_RXF1SID2_SIZE 0x1 #define _RXF1SIDL_RXF1SID2_LENGTH 0x1 #define _RXF1SIDL_RXF1SID2_MASK 0x80 // Register: RXF1EIDH #define RXF1EIDH RXF1EIDH extern volatile unsigned char RXF1EIDH @ 0xEE6; #ifndef _LIB_BUILD asm("RXF1EIDH equ 0EE6h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF1EID8 :1; unsigned RXF1EID9 :1; unsigned RXF1EID10 :1; unsigned RXF1EID11 :1; unsigned RXF1EID12 :1; unsigned RXF1EID13 :1; unsigned RXF1EID14 :1; unsigned RXF1EID15 :1; }; } RXF1EIDHbits_t; extern volatile RXF1EIDHbits_t RXF1EIDHbits @ 0xEE6; // bitfield macros #define _RXF1EIDH_EID_POSN 0x0 #define _RXF1EIDH_EID_POSITION 0x0 #define _RXF1EIDH_EID_SIZE 0x8 #define _RXF1EIDH_EID_LENGTH 0x8 #define _RXF1EIDH_EID_MASK 0xFF #define _RXF1EIDH_EID8_POSN 0x0 #define _RXF1EIDH_EID8_POSITION 0x0 #define _RXF1EIDH_EID8_SIZE 0x1 #define _RXF1EIDH_EID8_LENGTH 0x1 #define _RXF1EIDH_EID8_MASK 0x1 #define _RXF1EIDH_EID9_POSN 0x1 #define _RXF1EIDH_EID9_POSITION 0x1 #define _RXF1EIDH_EID9_SIZE 0x1 #define _RXF1EIDH_EID9_LENGTH 0x1 #define _RXF1EIDH_EID9_MASK 0x2 #define _RXF1EIDH_EID10_POSN 0x2 #define _RXF1EIDH_EID10_POSITION 0x2 #define _RXF1EIDH_EID10_SIZE 0x1 #define _RXF1EIDH_EID10_LENGTH 0x1 #define _RXF1EIDH_EID10_MASK 0x4 #define _RXF1EIDH_EID11_POSN 0x3 #define _RXF1EIDH_EID11_POSITION 0x3 #define _RXF1EIDH_EID11_SIZE 0x1 #define _RXF1EIDH_EID11_LENGTH 0x1 #define _RXF1EIDH_EID11_MASK 0x8 #define _RXF1EIDH_EID12_POSN 0x4 #define _RXF1EIDH_EID12_POSITION 0x4 #define _RXF1EIDH_EID12_SIZE 0x1 #define _RXF1EIDH_EID12_LENGTH 0x1 #define _RXF1EIDH_EID12_MASK 0x10 #define _RXF1EIDH_EID13_POSN 0x5 #define _RXF1EIDH_EID13_POSITION 0x5 #define _RXF1EIDH_EID13_SIZE 0x1 #define _RXF1EIDH_EID13_LENGTH 0x1 #define _RXF1EIDH_EID13_MASK 0x20 #define _RXF1EIDH_EID14_POSN 0x6 #define _RXF1EIDH_EID14_POSITION 0x6 #define _RXF1EIDH_EID14_SIZE 0x1 #define _RXF1EIDH_EID14_LENGTH 0x1 #define _RXF1EIDH_EID14_MASK 0x40 #define _RXF1EIDH_EID15_POSN 0x7 #define _RXF1EIDH_EID15_POSITION 0x7 #define _RXF1EIDH_EID15_SIZE 0x1 #define _RXF1EIDH_EID15_LENGTH 0x1 #define _RXF1EIDH_EID15_MASK 0x80 #define _RXF1EIDH_RXF1EID8_POSN 0x0 #define _RXF1EIDH_RXF1EID8_POSITION 0x0 #define _RXF1EIDH_RXF1EID8_SIZE 0x1 #define _RXF1EIDH_RXF1EID8_LENGTH 0x1 #define _RXF1EIDH_RXF1EID8_MASK 0x1 #define _RXF1EIDH_RXF1EID9_POSN 0x1 #define _RXF1EIDH_RXF1EID9_POSITION 0x1 #define _RXF1EIDH_RXF1EID9_SIZE 0x1 #define _RXF1EIDH_RXF1EID9_LENGTH 0x1 #define _RXF1EIDH_RXF1EID9_MASK 0x2 #define _RXF1EIDH_RXF1EID10_POSN 0x2 #define _RXF1EIDH_RXF1EID10_POSITION 0x2 #define _RXF1EIDH_RXF1EID10_SIZE 0x1 #define _RXF1EIDH_RXF1EID10_LENGTH 0x1 #define _RXF1EIDH_RXF1EID10_MASK 0x4 #define _RXF1EIDH_RXF1EID11_POSN 0x3 #define _RXF1EIDH_RXF1EID11_POSITION 0x3 #define _RXF1EIDH_RXF1EID11_SIZE 0x1 #define _RXF1EIDH_RXF1EID11_LENGTH 0x1 #define _RXF1EIDH_RXF1EID11_MASK 0x8 #define _RXF1EIDH_RXF1EID12_POSN 0x4 #define _RXF1EIDH_RXF1EID12_POSITION 0x4 #define _RXF1EIDH_RXF1EID12_SIZE 0x1 #define _RXF1EIDH_RXF1EID12_LENGTH 0x1 #define _RXF1EIDH_RXF1EID12_MASK 0x10 #define _RXF1EIDH_RXF1EID13_POSN 0x5 #define _RXF1EIDH_RXF1EID13_POSITION 0x5 #define _RXF1EIDH_RXF1EID13_SIZE 0x1 #define _RXF1EIDH_RXF1EID13_LENGTH 0x1 #define _RXF1EIDH_RXF1EID13_MASK 0x20 #define _RXF1EIDH_RXF1EID14_POSN 0x6 #define _RXF1EIDH_RXF1EID14_POSITION 0x6 #define _RXF1EIDH_RXF1EID14_SIZE 0x1 #define _RXF1EIDH_RXF1EID14_LENGTH 0x1 #define _RXF1EIDH_RXF1EID14_MASK 0x40 #define _RXF1EIDH_RXF1EID15_POSN 0x7 #define _RXF1EIDH_RXF1EID15_POSITION 0x7 #define _RXF1EIDH_RXF1EID15_SIZE 0x1 #define _RXF1EIDH_RXF1EID15_LENGTH 0x1 #define _RXF1EIDH_RXF1EID15_MASK 0x80 // Register: RXF1EIDL #define RXF1EIDL RXF1EIDL extern volatile unsigned char RXF1EIDL @ 0xEE7; #ifndef _LIB_BUILD asm("RXF1EIDL equ 0EE7h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF1EID0 :1; unsigned RXF1EID1 :1; unsigned RXF1EID2 :1; unsigned RXF1EID3 :1; unsigned RXF1EID4 :1; unsigned RXF1EID5 :1; unsigned RXF1EID6 :1; unsigned RXF1EID7 :1; }; } RXF1EIDLbits_t; extern volatile RXF1EIDLbits_t RXF1EIDLbits @ 0xEE7; // bitfield macros #define _RXF1EIDL_EID_POSN 0x0 #define _RXF1EIDL_EID_POSITION 0x0 #define _RXF1EIDL_EID_SIZE 0x8 #define _RXF1EIDL_EID_LENGTH 0x8 #define _RXF1EIDL_EID_MASK 0xFF #define _RXF1EIDL_EID0_POSN 0x0 #define _RXF1EIDL_EID0_POSITION 0x0 #define _RXF1EIDL_EID0_SIZE 0x1 #define _RXF1EIDL_EID0_LENGTH 0x1 #define _RXF1EIDL_EID0_MASK 0x1 #define _RXF1EIDL_EID1_POSN 0x1 #define _RXF1EIDL_EID1_POSITION 0x1 #define _RXF1EIDL_EID1_SIZE 0x1 #define _RXF1EIDL_EID1_LENGTH 0x1 #define _RXF1EIDL_EID1_MASK 0x2 #define _RXF1EIDL_EID2_POSN 0x2 #define _RXF1EIDL_EID2_POSITION 0x2 #define _RXF1EIDL_EID2_SIZE 0x1 #define _RXF1EIDL_EID2_LENGTH 0x1 #define _RXF1EIDL_EID2_MASK 0x4 #define _RXF1EIDL_EID3_POSN 0x3 #define _RXF1EIDL_EID3_POSITION 0x3 #define _RXF1EIDL_EID3_SIZE 0x1 #define _RXF1EIDL_EID3_LENGTH 0x1 #define _RXF1EIDL_EID3_MASK 0x8 #define _RXF1EIDL_EID4_POSN 0x4 #define _RXF1EIDL_EID4_POSITION 0x4 #define _RXF1EIDL_EID4_SIZE 0x1 #define _RXF1EIDL_EID4_LENGTH 0x1 #define _RXF1EIDL_EID4_MASK 0x10 #define _RXF1EIDL_EID5_POSN 0x5 #define _RXF1EIDL_EID5_POSITION 0x5 #define _RXF1EIDL_EID5_SIZE 0x1 #define _RXF1EIDL_EID5_LENGTH 0x1 #define _RXF1EIDL_EID5_MASK 0x20 #define _RXF1EIDL_EID6_POSN 0x6 #define _RXF1EIDL_EID6_POSITION 0x6 #define _RXF1EIDL_EID6_SIZE 0x1 #define _RXF1EIDL_EID6_LENGTH 0x1 #define _RXF1EIDL_EID6_MASK 0x40 #define _RXF1EIDL_EID7_POSN 0x7 #define _RXF1EIDL_EID7_POSITION 0x7 #define _RXF1EIDL_EID7_SIZE 0x1 #define _RXF1EIDL_EID7_LENGTH 0x1 #define _RXF1EIDL_EID7_MASK 0x80 #define _RXF1EIDL_RXF1EID0_POSN 0x0 #define _RXF1EIDL_RXF1EID0_POSITION 0x0 #define _RXF1EIDL_RXF1EID0_SIZE 0x1 #define _RXF1EIDL_RXF1EID0_LENGTH 0x1 #define _RXF1EIDL_RXF1EID0_MASK 0x1 #define _RXF1EIDL_RXF1EID1_POSN 0x1 #define _RXF1EIDL_RXF1EID1_POSITION 0x1 #define _RXF1EIDL_RXF1EID1_SIZE 0x1 #define _RXF1EIDL_RXF1EID1_LENGTH 0x1 #define _RXF1EIDL_RXF1EID1_MASK 0x2 #define _RXF1EIDL_RXF1EID2_POSN 0x2 #define _RXF1EIDL_RXF1EID2_POSITION 0x2 #define _RXF1EIDL_RXF1EID2_SIZE 0x1 #define _RXF1EIDL_RXF1EID2_LENGTH 0x1 #define _RXF1EIDL_RXF1EID2_MASK 0x4 #define _RXF1EIDL_RXF1EID3_POSN 0x3 #define _RXF1EIDL_RXF1EID3_POSITION 0x3 #define _RXF1EIDL_RXF1EID3_SIZE 0x1 #define _RXF1EIDL_RXF1EID3_LENGTH 0x1 #define _RXF1EIDL_RXF1EID3_MASK 0x8 #define _RXF1EIDL_RXF1EID4_POSN 0x4 #define _RXF1EIDL_RXF1EID4_POSITION 0x4 #define _RXF1EIDL_RXF1EID4_SIZE 0x1 #define _RXF1EIDL_RXF1EID4_LENGTH 0x1 #define _RXF1EIDL_RXF1EID4_MASK 0x10 #define _RXF1EIDL_RXF1EID5_POSN 0x5 #define _RXF1EIDL_RXF1EID5_POSITION 0x5 #define _RXF1EIDL_RXF1EID5_SIZE 0x1 #define _RXF1EIDL_RXF1EID5_LENGTH 0x1 #define _RXF1EIDL_RXF1EID5_MASK 0x20 #define _RXF1EIDL_RXF1EID6_POSN 0x6 #define _RXF1EIDL_RXF1EID6_POSITION 0x6 #define _RXF1EIDL_RXF1EID6_SIZE 0x1 #define _RXF1EIDL_RXF1EID6_LENGTH 0x1 #define _RXF1EIDL_RXF1EID6_MASK 0x40 #define _RXF1EIDL_RXF1EID7_POSN 0x7 #define _RXF1EIDL_RXF1EID7_POSITION 0x7 #define _RXF1EIDL_RXF1EID7_SIZE 0x1 #define _RXF1EIDL_RXF1EID7_LENGTH 0x1 #define _RXF1EIDL_RXF1EID7_MASK 0x80 // Register: RXF2SIDH #define RXF2SIDH RXF2SIDH extern volatile unsigned char RXF2SIDH @ 0xEE8; #ifndef _LIB_BUILD asm("RXF2SIDH equ 0EE8h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF2SID3 :1; unsigned RXF2SID4 :1; unsigned RXF2SID5 :1; unsigned RXF2SID6 :1; unsigned RXF2SID7 :1; unsigned RXF2SID8 :1; unsigned RXF2SID9 :1; unsigned RXF2SID10 :1; }; } RXF2SIDHbits_t; extern volatile RXF2SIDHbits_t RXF2SIDHbits @ 0xEE8; // bitfield macros #define _RXF2SIDH_SID_POSN 0x0 #define _RXF2SIDH_SID_POSITION 0x0 #define _RXF2SIDH_SID_SIZE 0x8 #define _RXF2SIDH_SID_LENGTH 0x8 #define _RXF2SIDH_SID_MASK 0xFF #define _RXF2SIDH_SID3_POSN 0x0 #define _RXF2SIDH_SID3_POSITION 0x0 #define _RXF2SIDH_SID3_SIZE 0x1 #define _RXF2SIDH_SID3_LENGTH 0x1 #define _RXF2SIDH_SID3_MASK 0x1 #define _RXF2SIDH_SID4_POSN 0x1 #define _RXF2SIDH_SID4_POSITION 0x1 #define _RXF2SIDH_SID4_SIZE 0x1 #define _RXF2SIDH_SID4_LENGTH 0x1 #define _RXF2SIDH_SID4_MASK 0x2 #define _RXF2SIDH_SID5_POSN 0x2 #define _RXF2SIDH_SID5_POSITION 0x2 #define _RXF2SIDH_SID5_SIZE 0x1 #define _RXF2SIDH_SID5_LENGTH 0x1 #define _RXF2SIDH_SID5_MASK 0x4 #define _RXF2SIDH_SID6_POSN 0x3 #define _RXF2SIDH_SID6_POSITION 0x3 #define _RXF2SIDH_SID6_SIZE 0x1 #define _RXF2SIDH_SID6_LENGTH 0x1 #define _RXF2SIDH_SID6_MASK 0x8 #define _RXF2SIDH_SID7_POSN 0x4 #define _RXF2SIDH_SID7_POSITION 0x4 #define _RXF2SIDH_SID7_SIZE 0x1 #define _RXF2SIDH_SID7_LENGTH 0x1 #define _RXF2SIDH_SID7_MASK 0x10 #define _RXF2SIDH_SID8_POSN 0x5 #define _RXF2SIDH_SID8_POSITION 0x5 #define _RXF2SIDH_SID8_SIZE 0x1 #define _RXF2SIDH_SID8_LENGTH 0x1 #define _RXF2SIDH_SID8_MASK 0x20 #define _RXF2SIDH_SID9_POSN 0x6 #define _RXF2SIDH_SID9_POSITION 0x6 #define _RXF2SIDH_SID9_SIZE 0x1 #define _RXF2SIDH_SID9_LENGTH 0x1 #define _RXF2SIDH_SID9_MASK 0x40 #define _RXF2SIDH_SID10_POSN 0x7 #define _RXF2SIDH_SID10_POSITION 0x7 #define _RXF2SIDH_SID10_SIZE 0x1 #define _RXF2SIDH_SID10_LENGTH 0x1 #define _RXF2SIDH_SID10_MASK 0x80 #define _RXF2SIDH_RXF2SID3_POSN 0x0 #define _RXF2SIDH_RXF2SID3_POSITION 0x0 #define _RXF2SIDH_RXF2SID3_SIZE 0x1 #define _RXF2SIDH_RXF2SID3_LENGTH 0x1 #define _RXF2SIDH_RXF2SID3_MASK 0x1 #define _RXF2SIDH_RXF2SID4_POSN 0x1 #define _RXF2SIDH_RXF2SID4_POSITION 0x1 #define _RXF2SIDH_RXF2SID4_SIZE 0x1 #define _RXF2SIDH_RXF2SID4_LENGTH 0x1 #define _RXF2SIDH_RXF2SID4_MASK 0x2 #define _RXF2SIDH_RXF2SID5_POSN 0x2 #define _RXF2SIDH_RXF2SID5_POSITION 0x2 #define _RXF2SIDH_RXF2SID5_SIZE 0x1 #define _RXF2SIDH_RXF2SID5_LENGTH 0x1 #define _RXF2SIDH_RXF2SID5_MASK 0x4 #define _RXF2SIDH_RXF2SID6_POSN 0x3 #define _RXF2SIDH_RXF2SID6_POSITION 0x3 #define _RXF2SIDH_RXF2SID6_SIZE 0x1 #define _RXF2SIDH_RXF2SID6_LENGTH 0x1 #define _RXF2SIDH_RXF2SID6_MASK 0x8 #define _RXF2SIDH_RXF2SID7_POSN 0x4 #define _RXF2SIDH_RXF2SID7_POSITION 0x4 #define _RXF2SIDH_RXF2SID7_SIZE 0x1 #define _RXF2SIDH_RXF2SID7_LENGTH 0x1 #define _RXF2SIDH_RXF2SID7_MASK 0x10 #define _RXF2SIDH_RXF2SID8_POSN 0x5 #define _RXF2SIDH_RXF2SID8_POSITION 0x5 #define _RXF2SIDH_RXF2SID8_SIZE 0x1 #define _RXF2SIDH_RXF2SID8_LENGTH 0x1 #define _RXF2SIDH_RXF2SID8_MASK 0x20 #define _RXF2SIDH_RXF2SID9_POSN 0x6 #define _RXF2SIDH_RXF2SID9_POSITION 0x6 #define _RXF2SIDH_RXF2SID9_SIZE 0x1 #define _RXF2SIDH_RXF2SID9_LENGTH 0x1 #define _RXF2SIDH_RXF2SID9_MASK 0x40 #define _RXF2SIDH_RXF2SID10_POSN 0x7 #define _RXF2SIDH_RXF2SID10_POSITION 0x7 #define _RXF2SIDH_RXF2SID10_SIZE 0x1 #define _RXF2SIDH_RXF2SID10_LENGTH 0x1 #define _RXF2SIDH_RXF2SID10_MASK 0x80 // Register: RXF2SIDL #define RXF2SIDL RXF2SIDL extern volatile unsigned char RXF2SIDL @ 0xEE9; #ifndef _LIB_BUILD asm("RXF2SIDL equ 0EE9h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF2EID16 :1; unsigned RXF2EID17 :1; unsigned :1; unsigned RXF2EXIDEN :1; unsigned :1; unsigned RXF2SID0 :1; unsigned RXF2SID1 :1; unsigned RXF2SID2 :1; }; } RXF2SIDLbits_t; extern volatile RXF2SIDLbits_t RXF2SIDLbits @ 0xEE9; // bitfield macros #define _RXF2SIDL_EID_POSN 0x0 #define _RXF2SIDL_EID_POSITION 0x0 #define _RXF2SIDL_EID_SIZE 0x2 #define _RXF2SIDL_EID_LENGTH 0x2 #define _RXF2SIDL_EID_MASK 0x3 #define _RXF2SIDL_EXIDEN_POSN 0x3 #define _RXF2SIDL_EXIDEN_POSITION 0x3 #define _RXF2SIDL_EXIDEN_SIZE 0x1 #define _RXF2SIDL_EXIDEN_LENGTH 0x1 #define _RXF2SIDL_EXIDEN_MASK 0x8 #define _RXF2SIDL_SID_POSN 0x5 #define _RXF2SIDL_SID_POSITION 0x5 #define _RXF2SIDL_SID_SIZE 0x3 #define _RXF2SIDL_SID_LENGTH 0x3 #define _RXF2SIDL_SID_MASK 0xE0 #define _RXF2SIDL_EID16_POSN 0x0 #define _RXF2SIDL_EID16_POSITION 0x0 #define _RXF2SIDL_EID16_SIZE 0x1 #define _RXF2SIDL_EID16_LENGTH 0x1 #define _RXF2SIDL_EID16_MASK 0x1 #define _RXF2SIDL_EID17_POSN 0x1 #define _RXF2SIDL_EID17_POSITION 0x1 #define _RXF2SIDL_EID17_SIZE 0x1 #define _RXF2SIDL_EID17_LENGTH 0x1 #define _RXF2SIDL_EID17_MASK 0x2 #define _RXF2SIDL_SID0_POSN 0x5 #define _RXF2SIDL_SID0_POSITION 0x5 #define _RXF2SIDL_SID0_SIZE 0x1 #define _RXF2SIDL_SID0_LENGTH 0x1 #define _RXF2SIDL_SID0_MASK 0x20 #define _RXF2SIDL_SID1_POSN 0x6 #define _RXF2SIDL_SID1_POSITION 0x6 #define _RXF2SIDL_SID1_SIZE 0x1 #define _RXF2SIDL_SID1_LENGTH 0x1 #define _RXF2SIDL_SID1_MASK 0x40 #define _RXF2SIDL_SID2_POSN 0x7 #define _RXF2SIDL_SID2_POSITION 0x7 #define _RXF2SIDL_SID2_SIZE 0x1 #define _RXF2SIDL_SID2_LENGTH 0x1 #define _RXF2SIDL_SID2_MASK 0x80 #define _RXF2SIDL_RXF2EID16_POSN 0x0 #define _RXF2SIDL_RXF2EID16_POSITION 0x0 #define _RXF2SIDL_RXF2EID16_SIZE 0x1 #define _RXF2SIDL_RXF2EID16_LENGTH 0x1 #define _RXF2SIDL_RXF2EID16_MASK 0x1 #define _RXF2SIDL_RXF2EID17_POSN 0x1 #define _RXF2SIDL_RXF2EID17_POSITION 0x1 #define _RXF2SIDL_RXF2EID17_SIZE 0x1 #define _RXF2SIDL_RXF2EID17_LENGTH 0x1 #define _RXF2SIDL_RXF2EID17_MASK 0x2 #define _RXF2SIDL_RXF2EXIDEN_POSN 0x3 #define _RXF2SIDL_RXF2EXIDEN_POSITION 0x3 #define _RXF2SIDL_RXF2EXIDEN_SIZE 0x1 #define _RXF2SIDL_RXF2EXIDEN_LENGTH 0x1 #define _RXF2SIDL_RXF2EXIDEN_MASK 0x8 #define _RXF2SIDL_RXF2SID0_POSN 0x5 #define _RXF2SIDL_RXF2SID0_POSITION 0x5 #define _RXF2SIDL_RXF2SID0_SIZE 0x1 #define _RXF2SIDL_RXF2SID0_LENGTH 0x1 #define _RXF2SIDL_RXF2SID0_MASK 0x20 #define _RXF2SIDL_RXF2SID1_POSN 0x6 #define _RXF2SIDL_RXF2SID1_POSITION 0x6 #define _RXF2SIDL_RXF2SID1_SIZE 0x1 #define _RXF2SIDL_RXF2SID1_LENGTH 0x1 #define _RXF2SIDL_RXF2SID1_MASK 0x40 #define _RXF2SIDL_RXF2SID2_POSN 0x7 #define _RXF2SIDL_RXF2SID2_POSITION 0x7 #define _RXF2SIDL_RXF2SID2_SIZE 0x1 #define _RXF2SIDL_RXF2SID2_LENGTH 0x1 #define _RXF2SIDL_RXF2SID2_MASK 0x80 // Register: RXF2EIDH #define RXF2EIDH RXF2EIDH extern volatile unsigned char RXF2EIDH @ 0xEEA; #ifndef _LIB_BUILD asm("RXF2EIDH equ 0EEAh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF2EID8 :1; unsigned RXF2EID9 :1; unsigned RXF2EID10 :1; unsigned RXF2EID11 :1; unsigned RXF2EID12 :1; unsigned RXF2EID13 :1; unsigned RXF2EID14 :1; unsigned RXF2EID15 :1; }; } RXF2EIDHbits_t; extern volatile RXF2EIDHbits_t RXF2EIDHbits @ 0xEEA; // bitfield macros #define _RXF2EIDH_EID_POSN 0x0 #define _RXF2EIDH_EID_POSITION 0x0 #define _RXF2EIDH_EID_SIZE 0x8 #define _RXF2EIDH_EID_LENGTH 0x8 #define _RXF2EIDH_EID_MASK 0xFF #define _RXF2EIDH_EID8_POSN 0x0 #define _RXF2EIDH_EID8_POSITION 0x0 #define _RXF2EIDH_EID8_SIZE 0x1 #define _RXF2EIDH_EID8_LENGTH 0x1 #define _RXF2EIDH_EID8_MASK 0x1 #define _RXF2EIDH_EID9_POSN 0x1 #define _RXF2EIDH_EID9_POSITION 0x1 #define _RXF2EIDH_EID9_SIZE 0x1 #define _RXF2EIDH_EID9_LENGTH 0x1 #define _RXF2EIDH_EID9_MASK 0x2 #define _RXF2EIDH_EID10_POSN 0x2 #define _RXF2EIDH_EID10_POSITION 0x2 #define _RXF2EIDH_EID10_SIZE 0x1 #define _RXF2EIDH_EID10_LENGTH 0x1 #define _RXF2EIDH_EID10_MASK 0x4 #define _RXF2EIDH_EID11_POSN 0x3 #define _RXF2EIDH_EID11_POSITION 0x3 #define _RXF2EIDH_EID11_SIZE 0x1 #define _RXF2EIDH_EID11_LENGTH 0x1 #define _RXF2EIDH_EID11_MASK 0x8 #define _RXF2EIDH_EID12_POSN 0x4 #define _RXF2EIDH_EID12_POSITION 0x4 #define _RXF2EIDH_EID12_SIZE 0x1 #define _RXF2EIDH_EID12_LENGTH 0x1 #define _RXF2EIDH_EID12_MASK 0x10 #define _RXF2EIDH_EID13_POSN 0x5 #define _RXF2EIDH_EID13_POSITION 0x5 #define _RXF2EIDH_EID13_SIZE 0x1 #define _RXF2EIDH_EID13_LENGTH 0x1 #define _RXF2EIDH_EID13_MASK 0x20 #define _RXF2EIDH_EID14_POSN 0x6 #define _RXF2EIDH_EID14_POSITION 0x6 #define _RXF2EIDH_EID14_SIZE 0x1 #define _RXF2EIDH_EID14_LENGTH 0x1 #define _RXF2EIDH_EID14_MASK 0x40 #define _RXF2EIDH_EID15_POSN 0x7 #define _RXF2EIDH_EID15_POSITION 0x7 #define _RXF2EIDH_EID15_SIZE 0x1 #define _RXF2EIDH_EID15_LENGTH 0x1 #define _RXF2EIDH_EID15_MASK 0x80 #define _RXF2EIDH_RXF2EID8_POSN 0x0 #define _RXF2EIDH_RXF2EID8_POSITION 0x0 #define _RXF2EIDH_RXF2EID8_SIZE 0x1 #define _RXF2EIDH_RXF2EID8_LENGTH 0x1 #define _RXF2EIDH_RXF2EID8_MASK 0x1 #define _RXF2EIDH_RXF2EID9_POSN 0x1 #define _RXF2EIDH_RXF2EID9_POSITION 0x1 #define _RXF2EIDH_RXF2EID9_SIZE 0x1 #define _RXF2EIDH_RXF2EID9_LENGTH 0x1 #define _RXF2EIDH_RXF2EID9_MASK 0x2 #define _RXF2EIDH_RXF2EID10_POSN 0x2 #define _RXF2EIDH_RXF2EID10_POSITION 0x2 #define _RXF2EIDH_RXF2EID10_SIZE 0x1 #define _RXF2EIDH_RXF2EID10_LENGTH 0x1 #define _RXF2EIDH_RXF2EID10_MASK 0x4 #define _RXF2EIDH_RXF2EID11_POSN 0x3 #define _RXF2EIDH_RXF2EID11_POSITION 0x3 #define _RXF2EIDH_RXF2EID11_SIZE 0x1 #define _RXF2EIDH_RXF2EID11_LENGTH 0x1 #define _RXF2EIDH_RXF2EID11_MASK 0x8 #define _RXF2EIDH_RXF2EID12_POSN 0x4 #define _RXF2EIDH_RXF2EID12_POSITION 0x4 #define _RXF2EIDH_RXF2EID12_SIZE 0x1 #define _RXF2EIDH_RXF2EID12_LENGTH 0x1 #define _RXF2EIDH_RXF2EID12_MASK 0x10 #define _RXF2EIDH_RXF2EID13_POSN 0x5 #define _RXF2EIDH_RXF2EID13_POSITION 0x5 #define _RXF2EIDH_RXF2EID13_SIZE 0x1 #define _RXF2EIDH_RXF2EID13_LENGTH 0x1 #define _RXF2EIDH_RXF2EID13_MASK 0x20 #define _RXF2EIDH_RXF2EID14_POSN 0x6 #define _RXF2EIDH_RXF2EID14_POSITION 0x6 #define _RXF2EIDH_RXF2EID14_SIZE 0x1 #define _RXF2EIDH_RXF2EID14_LENGTH 0x1 #define _RXF2EIDH_RXF2EID14_MASK 0x40 #define _RXF2EIDH_RXF2EID15_POSN 0x7 #define _RXF2EIDH_RXF2EID15_POSITION 0x7 #define _RXF2EIDH_RXF2EID15_SIZE 0x1 #define _RXF2EIDH_RXF2EID15_LENGTH 0x1 #define _RXF2EIDH_RXF2EID15_MASK 0x80 // Register: RXF2EIDL #define RXF2EIDL RXF2EIDL extern volatile unsigned char RXF2EIDL @ 0xEEB; #ifndef _LIB_BUILD asm("RXF2EIDL equ 0EEBh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF2EID0 :1; unsigned RXF2EID1 :1; unsigned RXF2EID2 :1; unsigned RXF2EID3 :1; unsigned RXF2EID4 :1; unsigned RXF2EID5 :1; unsigned RXF2EID6 :1; unsigned RXF2EID7 :1; }; } RXF2EIDLbits_t; extern volatile RXF2EIDLbits_t RXF2EIDLbits @ 0xEEB; // bitfield macros #define _RXF2EIDL_EID_POSN 0x0 #define _RXF2EIDL_EID_POSITION 0x0 #define _RXF2EIDL_EID_SIZE 0x8 #define _RXF2EIDL_EID_LENGTH 0x8 #define _RXF2EIDL_EID_MASK 0xFF #define _RXF2EIDL_EID0_POSN 0x0 #define _RXF2EIDL_EID0_POSITION 0x0 #define _RXF2EIDL_EID0_SIZE 0x1 #define _RXF2EIDL_EID0_LENGTH 0x1 #define _RXF2EIDL_EID0_MASK 0x1 #define _RXF2EIDL_EID1_POSN 0x1 #define _RXF2EIDL_EID1_POSITION 0x1 #define _RXF2EIDL_EID1_SIZE 0x1 #define _RXF2EIDL_EID1_LENGTH 0x1 #define _RXF2EIDL_EID1_MASK 0x2 #define _RXF2EIDL_EID2_POSN 0x2 #define _RXF2EIDL_EID2_POSITION 0x2 #define _RXF2EIDL_EID2_SIZE 0x1 #define _RXF2EIDL_EID2_LENGTH 0x1 #define _RXF2EIDL_EID2_MASK 0x4 #define _RXF2EIDL_EID3_POSN 0x3 #define _RXF2EIDL_EID3_POSITION 0x3 #define _RXF2EIDL_EID3_SIZE 0x1 #define _RXF2EIDL_EID3_LENGTH 0x1 #define _RXF2EIDL_EID3_MASK 0x8 #define _RXF2EIDL_EID4_POSN 0x4 #define _RXF2EIDL_EID4_POSITION 0x4 #define _RXF2EIDL_EID4_SIZE 0x1 #define _RXF2EIDL_EID4_LENGTH 0x1 #define _RXF2EIDL_EID4_MASK 0x10 #define _RXF2EIDL_EID5_POSN 0x5 #define _RXF2EIDL_EID5_POSITION 0x5 #define _RXF2EIDL_EID5_SIZE 0x1 #define _RXF2EIDL_EID5_LENGTH 0x1 #define _RXF2EIDL_EID5_MASK 0x20 #define _RXF2EIDL_EID6_POSN 0x6 #define _RXF2EIDL_EID6_POSITION 0x6 #define _RXF2EIDL_EID6_SIZE 0x1 #define _RXF2EIDL_EID6_LENGTH 0x1 #define _RXF2EIDL_EID6_MASK 0x40 #define _RXF2EIDL_EID7_POSN 0x7 #define _RXF2EIDL_EID7_POSITION 0x7 #define _RXF2EIDL_EID7_SIZE 0x1 #define _RXF2EIDL_EID7_LENGTH 0x1 #define _RXF2EIDL_EID7_MASK 0x80 #define _RXF2EIDL_RXF2EID0_POSN 0x0 #define _RXF2EIDL_RXF2EID0_POSITION 0x0 #define _RXF2EIDL_RXF2EID0_SIZE 0x1 #define _RXF2EIDL_RXF2EID0_LENGTH 0x1 #define _RXF2EIDL_RXF2EID0_MASK 0x1 #define _RXF2EIDL_RXF2EID1_POSN 0x1 #define _RXF2EIDL_RXF2EID1_POSITION 0x1 #define _RXF2EIDL_RXF2EID1_SIZE 0x1 #define _RXF2EIDL_RXF2EID1_LENGTH 0x1 #define _RXF2EIDL_RXF2EID1_MASK 0x2 #define _RXF2EIDL_RXF2EID2_POSN 0x2 #define _RXF2EIDL_RXF2EID2_POSITION 0x2 #define _RXF2EIDL_RXF2EID2_SIZE 0x1 #define _RXF2EIDL_RXF2EID2_LENGTH 0x1 #define _RXF2EIDL_RXF2EID2_MASK 0x4 #define _RXF2EIDL_RXF2EID3_POSN 0x3 #define _RXF2EIDL_RXF2EID3_POSITION 0x3 #define _RXF2EIDL_RXF2EID3_SIZE 0x1 #define _RXF2EIDL_RXF2EID3_LENGTH 0x1 #define _RXF2EIDL_RXF2EID3_MASK 0x8 #define _RXF2EIDL_RXF2EID4_POSN 0x4 #define _RXF2EIDL_RXF2EID4_POSITION 0x4 #define _RXF2EIDL_RXF2EID4_SIZE 0x1 #define _RXF2EIDL_RXF2EID4_LENGTH 0x1 #define _RXF2EIDL_RXF2EID4_MASK 0x10 #define _RXF2EIDL_RXF2EID5_POSN 0x5 #define _RXF2EIDL_RXF2EID5_POSITION 0x5 #define _RXF2EIDL_RXF2EID5_SIZE 0x1 #define _RXF2EIDL_RXF2EID5_LENGTH 0x1 #define _RXF2EIDL_RXF2EID5_MASK 0x20 #define _RXF2EIDL_RXF2EID6_POSN 0x6 #define _RXF2EIDL_RXF2EID6_POSITION 0x6 #define _RXF2EIDL_RXF2EID6_SIZE 0x1 #define _RXF2EIDL_RXF2EID6_LENGTH 0x1 #define _RXF2EIDL_RXF2EID6_MASK 0x40 #define _RXF2EIDL_RXF2EID7_POSN 0x7 #define _RXF2EIDL_RXF2EID7_POSITION 0x7 #define _RXF2EIDL_RXF2EID7_SIZE 0x1 #define _RXF2EIDL_RXF2EID7_LENGTH 0x1 #define _RXF2EIDL_RXF2EID7_MASK 0x80 // Register: RXF3SIDH #define RXF3SIDH RXF3SIDH extern volatile unsigned char RXF3SIDH @ 0xEEC; #ifndef _LIB_BUILD asm("RXF3SIDH equ 0EECh"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF3SID3 :1; unsigned RXF3SID4 :1; unsigned RXF3SID5 :1; unsigned RXF3SID6 :1; unsigned RXF3SID7 :1; unsigned RXF3SID8 :1; unsigned RXF3SID9 :1; unsigned RXF3SID10 :1; }; } RXF3SIDHbits_t; extern volatile RXF3SIDHbits_t RXF3SIDHbits @ 0xEEC; // bitfield macros #define _RXF3SIDH_SID_POSN 0x0 #define _RXF3SIDH_SID_POSITION 0x0 #define _RXF3SIDH_SID_SIZE 0x8 #define _RXF3SIDH_SID_LENGTH 0x8 #define _RXF3SIDH_SID_MASK 0xFF #define _RXF3SIDH_SID3_POSN 0x0 #define _RXF3SIDH_SID3_POSITION 0x0 #define _RXF3SIDH_SID3_SIZE 0x1 #define _RXF3SIDH_SID3_LENGTH 0x1 #define _RXF3SIDH_SID3_MASK 0x1 #define _RXF3SIDH_SID4_POSN 0x1 #define _RXF3SIDH_SID4_POSITION 0x1 #define _RXF3SIDH_SID4_SIZE 0x1 #define _RXF3SIDH_SID4_LENGTH 0x1 #define _RXF3SIDH_SID4_MASK 0x2 #define _RXF3SIDH_SID5_POSN 0x2 #define _RXF3SIDH_SID5_POSITION 0x2 #define _RXF3SIDH_SID5_SIZE 0x1 #define _RXF3SIDH_SID5_LENGTH 0x1 #define _RXF3SIDH_SID5_MASK 0x4 #define _RXF3SIDH_SID6_POSN 0x3 #define _RXF3SIDH_SID6_POSITION 0x3 #define _RXF3SIDH_SID6_SIZE 0x1 #define _RXF3SIDH_SID6_LENGTH 0x1 #define _RXF3SIDH_SID6_MASK 0x8 #define _RXF3SIDH_SID7_POSN 0x4 #define _RXF3SIDH_SID7_POSITION 0x4 #define _RXF3SIDH_SID7_SIZE 0x1 #define _RXF3SIDH_SID7_LENGTH 0x1 #define _RXF3SIDH_SID7_MASK 0x10 #define _RXF3SIDH_SID8_POSN 0x5 #define _RXF3SIDH_SID8_POSITION 0x5 #define _RXF3SIDH_SID8_SIZE 0x1 #define _RXF3SIDH_SID8_LENGTH 0x1 #define _RXF3SIDH_SID8_MASK 0x20 #define _RXF3SIDH_SID9_POSN 0x6 #define _RXF3SIDH_SID9_POSITION 0x6 #define _RXF3SIDH_SID9_SIZE 0x1 #define _RXF3SIDH_SID9_LENGTH 0x1 #define _RXF3SIDH_SID9_MASK 0x40 #define _RXF3SIDH_SID10_POSN 0x7 #define _RXF3SIDH_SID10_POSITION 0x7 #define _RXF3SIDH_SID10_SIZE 0x1 #define _RXF3SIDH_SID10_LENGTH 0x1 #define _RXF3SIDH_SID10_MASK 0x80 #define _RXF3SIDH_RXF3SID3_POSN 0x0 #define _RXF3SIDH_RXF3SID3_POSITION 0x0 #define _RXF3SIDH_RXF3SID3_SIZE 0x1 #define _RXF3SIDH_RXF3SID3_LENGTH 0x1 #define _RXF3SIDH_RXF3SID3_MASK 0x1 #define _RXF3SIDH_RXF3SID4_POSN 0x1 #define _RXF3SIDH_RXF3SID4_POSITION 0x1 #define _RXF3SIDH_RXF3SID4_SIZE 0x1 #define _RXF3SIDH_RXF3SID4_LENGTH 0x1 #define _RXF3SIDH_RXF3SID4_MASK 0x2 #define _RXF3SIDH_RXF3SID5_POSN 0x2 #define _RXF3SIDH_RXF3SID5_POSITION 0x2 #define _RXF3SIDH_RXF3SID5_SIZE 0x1 #define _RXF3SIDH_RXF3SID5_LENGTH 0x1 #define _RXF3SIDH_RXF3SID5_MASK 0x4 #define _RXF3SIDH_RXF3SID6_POSN 0x3 #define _RXF3SIDH_RXF3SID6_POSITION 0x3 #define _RXF3SIDH_RXF3SID6_SIZE 0x1 #define _RXF3SIDH_RXF3SID6_LENGTH 0x1 #define _RXF3SIDH_RXF3SID6_MASK 0x8 #define _RXF3SIDH_RXF3SID7_POSN 0x4 #define _RXF3SIDH_RXF3SID7_POSITION 0x4 #define _RXF3SIDH_RXF3SID7_SIZE 0x1 #define _RXF3SIDH_RXF3SID7_LENGTH 0x1 #define _RXF3SIDH_RXF3SID7_MASK 0x10 #define _RXF3SIDH_RXF3SID8_POSN 0x5 #define _RXF3SIDH_RXF3SID8_POSITION 0x5 #define _RXF3SIDH_RXF3SID8_SIZE 0x1 #define _RXF3SIDH_RXF3SID8_LENGTH 0x1 #define _RXF3SIDH_RXF3SID8_MASK 0x20 #define _RXF3SIDH_RXF3SID9_POSN 0x6 #define _RXF3SIDH_RXF3SID9_POSITION 0x6 #define _RXF3SIDH_RXF3SID9_SIZE 0x1 #define _RXF3SIDH_RXF3SID9_LENGTH 0x1 #define _RXF3SIDH_RXF3SID9_MASK 0x40 #define _RXF3SIDH_RXF3SID10_POSN 0x7 #define _RXF3SIDH_RXF3SID10_POSITION 0x7 #define _RXF3SIDH_RXF3SID10_SIZE 0x1 #define _RXF3SIDH_RXF3SID10_LENGTH 0x1 #define _RXF3SIDH_RXF3SID10_MASK 0x80 // Register: RXF3SIDL #define RXF3SIDL RXF3SIDL extern volatile unsigned char RXF3SIDL @ 0xEED; #ifndef _LIB_BUILD asm("RXF3SIDL equ 0EEDh"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF3EID16 :1; unsigned RXF3EID17 :1; unsigned :1; unsigned RXF3EXIDEN :1; unsigned :1; unsigned RXF3SID0 :1; unsigned RXF3SID1 :1; unsigned RXF3SID2 :1; }; } RXF3SIDLbits_t; extern volatile RXF3SIDLbits_t RXF3SIDLbits @ 0xEED; // bitfield macros #define _RXF3SIDL_EID_POSN 0x0 #define _RXF3SIDL_EID_POSITION 0x0 #define _RXF3SIDL_EID_SIZE 0x2 #define _RXF3SIDL_EID_LENGTH 0x2 #define _RXF3SIDL_EID_MASK 0x3 #define _RXF3SIDL_EXIDEN_POSN 0x3 #define _RXF3SIDL_EXIDEN_POSITION 0x3 #define _RXF3SIDL_EXIDEN_SIZE 0x1 #define _RXF3SIDL_EXIDEN_LENGTH 0x1 #define _RXF3SIDL_EXIDEN_MASK 0x8 #define _RXF3SIDL_SID_POSN 0x5 #define _RXF3SIDL_SID_POSITION 0x5 #define _RXF3SIDL_SID_SIZE 0x3 #define _RXF3SIDL_SID_LENGTH 0x3 #define _RXF3SIDL_SID_MASK 0xE0 #define _RXF3SIDL_EID16_POSN 0x0 #define _RXF3SIDL_EID16_POSITION 0x0 #define _RXF3SIDL_EID16_SIZE 0x1 #define _RXF3SIDL_EID16_LENGTH 0x1 #define _RXF3SIDL_EID16_MASK 0x1 #define _RXF3SIDL_EID17_POSN 0x1 #define _RXF3SIDL_EID17_POSITION 0x1 #define _RXF3SIDL_EID17_SIZE 0x1 #define _RXF3SIDL_EID17_LENGTH 0x1 #define _RXF3SIDL_EID17_MASK 0x2 #define _RXF3SIDL_SID0_POSN 0x5 #define _RXF3SIDL_SID0_POSITION 0x5 #define _RXF3SIDL_SID0_SIZE 0x1 #define _RXF3SIDL_SID0_LENGTH 0x1 #define _RXF3SIDL_SID0_MASK 0x20 #define _RXF3SIDL_SID1_POSN 0x6 #define _RXF3SIDL_SID1_POSITION 0x6 #define _RXF3SIDL_SID1_SIZE 0x1 #define _RXF3SIDL_SID1_LENGTH 0x1 #define _RXF3SIDL_SID1_MASK 0x40 #define _RXF3SIDL_SID2_POSN 0x7 #define _RXF3SIDL_SID2_POSITION 0x7 #define _RXF3SIDL_SID2_SIZE 0x1 #define _RXF3SIDL_SID2_LENGTH 0x1 #define _RXF3SIDL_SID2_MASK 0x80 #define _RXF3SIDL_RXF3EID16_POSN 0x0 #define _RXF3SIDL_RXF3EID16_POSITION 0x0 #define _RXF3SIDL_RXF3EID16_SIZE 0x1 #define _RXF3SIDL_RXF3EID16_LENGTH 0x1 #define _RXF3SIDL_RXF3EID16_MASK 0x1 #define _RXF3SIDL_RXF3EID17_POSN 0x1 #define _RXF3SIDL_RXF3EID17_POSITION 0x1 #define _RXF3SIDL_RXF3EID17_SIZE 0x1 #define _RXF3SIDL_RXF3EID17_LENGTH 0x1 #define _RXF3SIDL_RXF3EID17_MASK 0x2 #define _RXF3SIDL_RXF3EXIDEN_POSN 0x3 #define _RXF3SIDL_RXF3EXIDEN_POSITION 0x3 #define _RXF3SIDL_RXF3EXIDEN_SIZE 0x1 #define _RXF3SIDL_RXF3EXIDEN_LENGTH 0x1 #define _RXF3SIDL_RXF3EXIDEN_MASK 0x8 #define _RXF3SIDL_RXF3SID0_POSN 0x5 #define _RXF3SIDL_RXF3SID0_POSITION 0x5 #define _RXF3SIDL_RXF3SID0_SIZE 0x1 #define _RXF3SIDL_RXF3SID0_LENGTH 0x1 #define _RXF3SIDL_RXF3SID0_MASK 0x20 #define _RXF3SIDL_RXF3SID1_POSN 0x6 #define _RXF3SIDL_RXF3SID1_POSITION 0x6 #define _RXF3SIDL_RXF3SID1_SIZE 0x1 #define _RXF3SIDL_RXF3SID1_LENGTH 0x1 #define _RXF3SIDL_RXF3SID1_MASK 0x40 #define _RXF3SIDL_RXF3SID2_POSN 0x7 #define _RXF3SIDL_RXF3SID2_POSITION 0x7 #define _RXF3SIDL_RXF3SID2_SIZE 0x1 #define _RXF3SIDL_RXF3SID2_LENGTH 0x1 #define _RXF3SIDL_RXF3SID2_MASK 0x80 // Register: RXF3EIDH #define RXF3EIDH RXF3EIDH extern volatile unsigned char RXF3EIDH @ 0xEEE; #ifndef _LIB_BUILD asm("RXF3EIDH equ 0EEEh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF3EID8 :1; unsigned RXF3EID9 :1; unsigned RXF3EID10 :1; unsigned RXF3EID11 :1; unsigned RXF3EID12 :1; unsigned RXF3EID13 :1; unsigned RXF3EID14 :1; unsigned RXF3EID15 :1; }; } RXF3EIDHbits_t; extern volatile RXF3EIDHbits_t RXF3EIDHbits @ 0xEEE; // bitfield macros #define _RXF3EIDH_EID_POSN 0x0 #define _RXF3EIDH_EID_POSITION 0x0 #define _RXF3EIDH_EID_SIZE 0x8 #define _RXF3EIDH_EID_LENGTH 0x8 #define _RXF3EIDH_EID_MASK 0xFF #define _RXF3EIDH_EID8_POSN 0x0 #define _RXF3EIDH_EID8_POSITION 0x0 #define _RXF3EIDH_EID8_SIZE 0x1 #define _RXF3EIDH_EID8_LENGTH 0x1 #define _RXF3EIDH_EID8_MASK 0x1 #define _RXF3EIDH_EID9_POSN 0x1 #define _RXF3EIDH_EID9_POSITION 0x1 #define _RXF3EIDH_EID9_SIZE 0x1 #define _RXF3EIDH_EID9_LENGTH 0x1 #define _RXF3EIDH_EID9_MASK 0x2 #define _RXF3EIDH_EID10_POSN 0x2 #define _RXF3EIDH_EID10_POSITION 0x2 #define _RXF3EIDH_EID10_SIZE 0x1 #define _RXF3EIDH_EID10_LENGTH 0x1 #define _RXF3EIDH_EID10_MASK 0x4 #define _RXF3EIDH_EID11_POSN 0x3 #define _RXF3EIDH_EID11_POSITION 0x3 #define _RXF3EIDH_EID11_SIZE 0x1 #define _RXF3EIDH_EID11_LENGTH 0x1 #define _RXF3EIDH_EID11_MASK 0x8 #define _RXF3EIDH_EID12_POSN 0x4 #define _RXF3EIDH_EID12_POSITION 0x4 #define _RXF3EIDH_EID12_SIZE 0x1 #define _RXF3EIDH_EID12_LENGTH 0x1 #define _RXF3EIDH_EID12_MASK 0x10 #define _RXF3EIDH_EID13_POSN 0x5 #define _RXF3EIDH_EID13_POSITION 0x5 #define _RXF3EIDH_EID13_SIZE 0x1 #define _RXF3EIDH_EID13_LENGTH 0x1 #define _RXF3EIDH_EID13_MASK 0x20 #define _RXF3EIDH_EID14_POSN 0x6 #define _RXF3EIDH_EID14_POSITION 0x6 #define _RXF3EIDH_EID14_SIZE 0x1 #define _RXF3EIDH_EID14_LENGTH 0x1 #define _RXF3EIDH_EID14_MASK 0x40 #define _RXF3EIDH_EID15_POSN 0x7 #define _RXF3EIDH_EID15_POSITION 0x7 #define _RXF3EIDH_EID15_SIZE 0x1 #define _RXF3EIDH_EID15_LENGTH 0x1 #define _RXF3EIDH_EID15_MASK 0x80 #define _RXF3EIDH_RXF3EID8_POSN 0x0 #define _RXF3EIDH_RXF3EID8_POSITION 0x0 #define _RXF3EIDH_RXF3EID8_SIZE 0x1 #define _RXF3EIDH_RXF3EID8_LENGTH 0x1 #define _RXF3EIDH_RXF3EID8_MASK 0x1 #define _RXF3EIDH_RXF3EID9_POSN 0x1 #define _RXF3EIDH_RXF3EID9_POSITION 0x1 #define _RXF3EIDH_RXF3EID9_SIZE 0x1 #define _RXF3EIDH_RXF3EID9_LENGTH 0x1 #define _RXF3EIDH_RXF3EID9_MASK 0x2 #define _RXF3EIDH_RXF3EID10_POSN 0x2 #define _RXF3EIDH_RXF3EID10_POSITION 0x2 #define _RXF3EIDH_RXF3EID10_SIZE 0x1 #define _RXF3EIDH_RXF3EID10_LENGTH 0x1 #define _RXF3EIDH_RXF3EID10_MASK 0x4 #define _RXF3EIDH_RXF3EID11_POSN 0x3 #define _RXF3EIDH_RXF3EID11_POSITION 0x3 #define _RXF3EIDH_RXF3EID11_SIZE 0x1 #define _RXF3EIDH_RXF3EID11_LENGTH 0x1 #define _RXF3EIDH_RXF3EID11_MASK 0x8 #define _RXF3EIDH_RXF3EID12_POSN 0x4 #define _RXF3EIDH_RXF3EID12_POSITION 0x4 #define _RXF3EIDH_RXF3EID12_SIZE 0x1 #define _RXF3EIDH_RXF3EID12_LENGTH 0x1 #define _RXF3EIDH_RXF3EID12_MASK 0x10 #define _RXF3EIDH_RXF3EID13_POSN 0x5 #define _RXF3EIDH_RXF3EID13_POSITION 0x5 #define _RXF3EIDH_RXF3EID13_SIZE 0x1 #define _RXF3EIDH_RXF3EID13_LENGTH 0x1 #define _RXF3EIDH_RXF3EID13_MASK 0x20 #define _RXF3EIDH_RXF3EID14_POSN 0x6 #define _RXF3EIDH_RXF3EID14_POSITION 0x6 #define _RXF3EIDH_RXF3EID14_SIZE 0x1 #define _RXF3EIDH_RXF3EID14_LENGTH 0x1 #define _RXF3EIDH_RXF3EID14_MASK 0x40 #define _RXF3EIDH_RXF3EID15_POSN 0x7 #define _RXF3EIDH_RXF3EID15_POSITION 0x7 #define _RXF3EIDH_RXF3EID15_SIZE 0x1 #define _RXF3EIDH_RXF3EID15_LENGTH 0x1 #define _RXF3EIDH_RXF3EID15_MASK 0x80 // Register: RXF3EIDL #define RXF3EIDL RXF3EIDL extern volatile unsigned char RXF3EIDL @ 0xEEF; #ifndef _LIB_BUILD asm("RXF3EIDL equ 0EEFh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF3EID0 :1; unsigned RXF3EID1 :1; unsigned RXF3EID2 :1; unsigned RXF3EID3 :1; unsigned RXF3EID4 :1; unsigned RXF3EID5 :1; unsigned RXF3EID6 :1; unsigned RXF3EID7 :1; }; } RXF3EIDLbits_t; extern volatile RXF3EIDLbits_t RXF3EIDLbits @ 0xEEF; // bitfield macros #define _RXF3EIDL_EID_POSN 0x0 #define _RXF3EIDL_EID_POSITION 0x0 #define _RXF3EIDL_EID_SIZE 0x8 #define _RXF3EIDL_EID_LENGTH 0x8 #define _RXF3EIDL_EID_MASK 0xFF #define _RXF3EIDL_EID0_POSN 0x0 #define _RXF3EIDL_EID0_POSITION 0x0 #define _RXF3EIDL_EID0_SIZE 0x1 #define _RXF3EIDL_EID0_LENGTH 0x1 #define _RXF3EIDL_EID0_MASK 0x1 #define _RXF3EIDL_EID1_POSN 0x1 #define _RXF3EIDL_EID1_POSITION 0x1 #define _RXF3EIDL_EID1_SIZE 0x1 #define _RXF3EIDL_EID1_LENGTH 0x1 #define _RXF3EIDL_EID1_MASK 0x2 #define _RXF3EIDL_EID2_POSN 0x2 #define _RXF3EIDL_EID2_POSITION 0x2 #define _RXF3EIDL_EID2_SIZE 0x1 #define _RXF3EIDL_EID2_LENGTH 0x1 #define _RXF3EIDL_EID2_MASK 0x4 #define _RXF3EIDL_EID3_POSN 0x3 #define _RXF3EIDL_EID3_POSITION 0x3 #define _RXF3EIDL_EID3_SIZE 0x1 #define _RXF3EIDL_EID3_LENGTH 0x1 #define _RXF3EIDL_EID3_MASK 0x8 #define _RXF3EIDL_EID4_POSN 0x4 #define _RXF3EIDL_EID4_POSITION 0x4 #define _RXF3EIDL_EID4_SIZE 0x1 #define _RXF3EIDL_EID4_LENGTH 0x1 #define _RXF3EIDL_EID4_MASK 0x10 #define _RXF3EIDL_EID5_POSN 0x5 #define _RXF3EIDL_EID5_POSITION 0x5 #define _RXF3EIDL_EID5_SIZE 0x1 #define _RXF3EIDL_EID5_LENGTH 0x1 #define _RXF3EIDL_EID5_MASK 0x20 #define _RXF3EIDL_EID6_POSN 0x6 #define _RXF3EIDL_EID6_POSITION 0x6 #define _RXF3EIDL_EID6_SIZE 0x1 #define _RXF3EIDL_EID6_LENGTH 0x1 #define _RXF3EIDL_EID6_MASK 0x40 #define _RXF3EIDL_EID7_POSN 0x7 #define _RXF3EIDL_EID7_POSITION 0x7 #define _RXF3EIDL_EID7_SIZE 0x1 #define _RXF3EIDL_EID7_LENGTH 0x1 #define _RXF3EIDL_EID7_MASK 0x80 #define _RXF3EIDL_RXF3EID0_POSN 0x0 #define _RXF3EIDL_RXF3EID0_POSITION 0x0 #define _RXF3EIDL_RXF3EID0_SIZE 0x1 #define _RXF3EIDL_RXF3EID0_LENGTH 0x1 #define _RXF3EIDL_RXF3EID0_MASK 0x1 #define _RXF3EIDL_RXF3EID1_POSN 0x1 #define _RXF3EIDL_RXF3EID1_POSITION 0x1 #define _RXF3EIDL_RXF3EID1_SIZE 0x1 #define _RXF3EIDL_RXF3EID1_LENGTH 0x1 #define _RXF3EIDL_RXF3EID1_MASK 0x2 #define _RXF3EIDL_RXF3EID2_POSN 0x2 #define _RXF3EIDL_RXF3EID2_POSITION 0x2 #define _RXF3EIDL_RXF3EID2_SIZE 0x1 #define _RXF3EIDL_RXF3EID2_LENGTH 0x1 #define _RXF3EIDL_RXF3EID2_MASK 0x4 #define _RXF3EIDL_RXF3EID3_POSN 0x3 #define _RXF3EIDL_RXF3EID3_POSITION 0x3 #define _RXF3EIDL_RXF3EID3_SIZE 0x1 #define _RXF3EIDL_RXF3EID3_LENGTH 0x1 #define _RXF3EIDL_RXF3EID3_MASK 0x8 #define _RXF3EIDL_RXF3EID4_POSN 0x4 #define _RXF3EIDL_RXF3EID4_POSITION 0x4 #define _RXF3EIDL_RXF3EID4_SIZE 0x1 #define _RXF3EIDL_RXF3EID4_LENGTH 0x1 #define _RXF3EIDL_RXF3EID4_MASK 0x10 #define _RXF3EIDL_RXF3EID5_POSN 0x5 #define _RXF3EIDL_RXF3EID5_POSITION 0x5 #define _RXF3EIDL_RXF3EID5_SIZE 0x1 #define _RXF3EIDL_RXF3EID5_LENGTH 0x1 #define _RXF3EIDL_RXF3EID5_MASK 0x20 #define _RXF3EIDL_RXF3EID6_POSN 0x6 #define _RXF3EIDL_RXF3EID6_POSITION 0x6 #define _RXF3EIDL_RXF3EID6_SIZE 0x1 #define _RXF3EIDL_RXF3EID6_LENGTH 0x1 #define _RXF3EIDL_RXF3EID6_MASK 0x40 #define _RXF3EIDL_RXF3EID7_POSN 0x7 #define _RXF3EIDL_RXF3EID7_POSITION 0x7 #define _RXF3EIDL_RXF3EID7_SIZE 0x1 #define _RXF3EIDL_RXF3EID7_LENGTH 0x1 #define _RXF3EIDL_RXF3EID7_MASK 0x80 // Register: RXF4SIDH #define RXF4SIDH RXF4SIDH extern volatile unsigned char RXF4SIDH @ 0xEF0; #ifndef _LIB_BUILD asm("RXF4SIDH equ 0EF0h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF4SID3 :1; unsigned RXF4SID4 :1; unsigned RXF4SID5 :1; unsigned RXF4SID6 :1; unsigned RXF4SID7 :1; unsigned RXF4SID8 :1; unsigned RXF4SID9 :1; unsigned RXF4SID10 :1; }; } RXF4SIDHbits_t; extern volatile RXF4SIDHbits_t RXF4SIDHbits @ 0xEF0; // bitfield macros #define _RXF4SIDH_SID_POSN 0x0 #define _RXF4SIDH_SID_POSITION 0x0 #define _RXF4SIDH_SID_SIZE 0x8 #define _RXF4SIDH_SID_LENGTH 0x8 #define _RXF4SIDH_SID_MASK 0xFF #define _RXF4SIDH_SID3_POSN 0x0 #define _RXF4SIDH_SID3_POSITION 0x0 #define _RXF4SIDH_SID3_SIZE 0x1 #define _RXF4SIDH_SID3_LENGTH 0x1 #define _RXF4SIDH_SID3_MASK 0x1 #define _RXF4SIDH_SID4_POSN 0x1 #define _RXF4SIDH_SID4_POSITION 0x1 #define _RXF4SIDH_SID4_SIZE 0x1 #define _RXF4SIDH_SID4_LENGTH 0x1 #define _RXF4SIDH_SID4_MASK 0x2 #define _RXF4SIDH_SID5_POSN 0x2 #define _RXF4SIDH_SID5_POSITION 0x2 #define _RXF4SIDH_SID5_SIZE 0x1 #define _RXF4SIDH_SID5_LENGTH 0x1 #define _RXF4SIDH_SID5_MASK 0x4 #define _RXF4SIDH_SID6_POSN 0x3 #define _RXF4SIDH_SID6_POSITION 0x3 #define _RXF4SIDH_SID6_SIZE 0x1 #define _RXF4SIDH_SID6_LENGTH 0x1 #define _RXF4SIDH_SID6_MASK 0x8 #define _RXF4SIDH_SID7_POSN 0x4 #define _RXF4SIDH_SID7_POSITION 0x4 #define _RXF4SIDH_SID7_SIZE 0x1 #define _RXF4SIDH_SID7_LENGTH 0x1 #define _RXF4SIDH_SID7_MASK 0x10 #define _RXF4SIDH_SID8_POSN 0x5 #define _RXF4SIDH_SID8_POSITION 0x5 #define _RXF4SIDH_SID8_SIZE 0x1 #define _RXF4SIDH_SID8_LENGTH 0x1 #define _RXF4SIDH_SID8_MASK 0x20 #define _RXF4SIDH_SID9_POSN 0x6 #define _RXF4SIDH_SID9_POSITION 0x6 #define _RXF4SIDH_SID9_SIZE 0x1 #define _RXF4SIDH_SID9_LENGTH 0x1 #define _RXF4SIDH_SID9_MASK 0x40 #define _RXF4SIDH_SID10_POSN 0x7 #define _RXF4SIDH_SID10_POSITION 0x7 #define _RXF4SIDH_SID10_SIZE 0x1 #define _RXF4SIDH_SID10_LENGTH 0x1 #define _RXF4SIDH_SID10_MASK 0x80 #define _RXF4SIDH_RXF4SID3_POSN 0x0 #define _RXF4SIDH_RXF4SID3_POSITION 0x0 #define _RXF4SIDH_RXF4SID3_SIZE 0x1 #define _RXF4SIDH_RXF4SID3_LENGTH 0x1 #define _RXF4SIDH_RXF4SID3_MASK 0x1 #define _RXF4SIDH_RXF4SID4_POSN 0x1 #define _RXF4SIDH_RXF4SID4_POSITION 0x1 #define _RXF4SIDH_RXF4SID4_SIZE 0x1 #define _RXF4SIDH_RXF4SID4_LENGTH 0x1 #define _RXF4SIDH_RXF4SID4_MASK 0x2 #define _RXF4SIDH_RXF4SID5_POSN 0x2 #define _RXF4SIDH_RXF4SID5_POSITION 0x2 #define _RXF4SIDH_RXF4SID5_SIZE 0x1 #define _RXF4SIDH_RXF4SID5_LENGTH 0x1 #define _RXF4SIDH_RXF4SID5_MASK 0x4 #define _RXF4SIDH_RXF4SID6_POSN 0x3 #define _RXF4SIDH_RXF4SID6_POSITION 0x3 #define _RXF4SIDH_RXF4SID6_SIZE 0x1 #define _RXF4SIDH_RXF4SID6_LENGTH 0x1 #define _RXF4SIDH_RXF4SID6_MASK 0x8 #define _RXF4SIDH_RXF4SID7_POSN 0x4 #define _RXF4SIDH_RXF4SID7_POSITION 0x4 #define _RXF4SIDH_RXF4SID7_SIZE 0x1 #define _RXF4SIDH_RXF4SID7_LENGTH 0x1 #define _RXF4SIDH_RXF4SID7_MASK 0x10 #define _RXF4SIDH_RXF4SID8_POSN 0x5 #define _RXF4SIDH_RXF4SID8_POSITION 0x5 #define _RXF4SIDH_RXF4SID8_SIZE 0x1 #define _RXF4SIDH_RXF4SID8_LENGTH 0x1 #define _RXF4SIDH_RXF4SID8_MASK 0x20 #define _RXF4SIDH_RXF4SID9_POSN 0x6 #define _RXF4SIDH_RXF4SID9_POSITION 0x6 #define _RXF4SIDH_RXF4SID9_SIZE 0x1 #define _RXF4SIDH_RXF4SID9_LENGTH 0x1 #define _RXF4SIDH_RXF4SID9_MASK 0x40 #define _RXF4SIDH_RXF4SID10_POSN 0x7 #define _RXF4SIDH_RXF4SID10_POSITION 0x7 #define _RXF4SIDH_RXF4SID10_SIZE 0x1 #define _RXF4SIDH_RXF4SID10_LENGTH 0x1 #define _RXF4SIDH_RXF4SID10_MASK 0x80 // Register: RXF4SIDL #define RXF4SIDL RXF4SIDL extern volatile unsigned char RXF4SIDL @ 0xEF1; #ifndef _LIB_BUILD asm("RXF4SIDL equ 0EF1h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF4EID16 :1; unsigned RXF4EID17 :1; unsigned :1; unsigned RXF4EXIDEN :1; unsigned :1; unsigned RXF4SID0 :1; unsigned RXF4SID1 :1; unsigned RXF4SID2 :1; }; } RXF4SIDLbits_t; extern volatile RXF4SIDLbits_t RXF4SIDLbits @ 0xEF1; // bitfield macros #define _RXF4SIDL_EID_POSN 0x0 #define _RXF4SIDL_EID_POSITION 0x0 #define _RXF4SIDL_EID_SIZE 0x2 #define _RXF4SIDL_EID_LENGTH 0x2 #define _RXF4SIDL_EID_MASK 0x3 #define _RXF4SIDL_EXIDEN_POSN 0x3 #define _RXF4SIDL_EXIDEN_POSITION 0x3 #define _RXF4SIDL_EXIDEN_SIZE 0x1 #define _RXF4SIDL_EXIDEN_LENGTH 0x1 #define _RXF4SIDL_EXIDEN_MASK 0x8 #define _RXF4SIDL_SID_POSN 0x5 #define _RXF4SIDL_SID_POSITION 0x5 #define _RXF4SIDL_SID_SIZE 0x3 #define _RXF4SIDL_SID_LENGTH 0x3 #define _RXF4SIDL_SID_MASK 0xE0 #define _RXF4SIDL_EID16_POSN 0x0 #define _RXF4SIDL_EID16_POSITION 0x0 #define _RXF4SIDL_EID16_SIZE 0x1 #define _RXF4SIDL_EID16_LENGTH 0x1 #define _RXF4SIDL_EID16_MASK 0x1 #define _RXF4SIDL_EID17_POSN 0x1 #define _RXF4SIDL_EID17_POSITION 0x1 #define _RXF4SIDL_EID17_SIZE 0x1 #define _RXF4SIDL_EID17_LENGTH 0x1 #define _RXF4SIDL_EID17_MASK 0x2 #define _RXF4SIDL_SID0_POSN 0x5 #define _RXF4SIDL_SID0_POSITION 0x5 #define _RXF4SIDL_SID0_SIZE 0x1 #define _RXF4SIDL_SID0_LENGTH 0x1 #define _RXF4SIDL_SID0_MASK 0x20 #define _RXF4SIDL_SID1_POSN 0x6 #define _RXF4SIDL_SID1_POSITION 0x6 #define _RXF4SIDL_SID1_SIZE 0x1 #define _RXF4SIDL_SID1_LENGTH 0x1 #define _RXF4SIDL_SID1_MASK 0x40 #define _RXF4SIDL_SID2_POSN 0x7 #define _RXF4SIDL_SID2_POSITION 0x7 #define _RXF4SIDL_SID2_SIZE 0x1 #define _RXF4SIDL_SID2_LENGTH 0x1 #define _RXF4SIDL_SID2_MASK 0x80 #define _RXF4SIDL_RXF4EID16_POSN 0x0 #define _RXF4SIDL_RXF4EID16_POSITION 0x0 #define _RXF4SIDL_RXF4EID16_SIZE 0x1 #define _RXF4SIDL_RXF4EID16_LENGTH 0x1 #define _RXF4SIDL_RXF4EID16_MASK 0x1 #define _RXF4SIDL_RXF4EID17_POSN 0x1 #define _RXF4SIDL_RXF4EID17_POSITION 0x1 #define _RXF4SIDL_RXF4EID17_SIZE 0x1 #define _RXF4SIDL_RXF4EID17_LENGTH 0x1 #define _RXF4SIDL_RXF4EID17_MASK 0x2 #define _RXF4SIDL_RXF4EXIDEN_POSN 0x3 #define _RXF4SIDL_RXF4EXIDEN_POSITION 0x3 #define _RXF4SIDL_RXF4EXIDEN_SIZE 0x1 #define _RXF4SIDL_RXF4EXIDEN_LENGTH 0x1 #define _RXF4SIDL_RXF4EXIDEN_MASK 0x8 #define _RXF4SIDL_RXF4SID0_POSN 0x5 #define _RXF4SIDL_RXF4SID0_POSITION 0x5 #define _RXF4SIDL_RXF4SID0_SIZE 0x1 #define _RXF4SIDL_RXF4SID0_LENGTH 0x1 #define _RXF4SIDL_RXF4SID0_MASK 0x20 #define _RXF4SIDL_RXF4SID1_POSN 0x6 #define _RXF4SIDL_RXF4SID1_POSITION 0x6 #define _RXF4SIDL_RXF4SID1_SIZE 0x1 #define _RXF4SIDL_RXF4SID1_LENGTH 0x1 #define _RXF4SIDL_RXF4SID1_MASK 0x40 #define _RXF4SIDL_RXF4SID2_POSN 0x7 #define _RXF4SIDL_RXF4SID2_POSITION 0x7 #define _RXF4SIDL_RXF4SID2_SIZE 0x1 #define _RXF4SIDL_RXF4SID2_LENGTH 0x1 #define _RXF4SIDL_RXF4SID2_MASK 0x80 // Register: RXF4EIDH #define RXF4EIDH RXF4EIDH extern volatile unsigned char RXF4EIDH @ 0xEF2; #ifndef _LIB_BUILD asm("RXF4EIDH equ 0EF2h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF4EID8 :1; unsigned RXF4EID9 :1; unsigned RXF4EID10 :1; unsigned RXF4EID11 :1; unsigned RXF4EID12 :1; unsigned RXF4EID13 :1; unsigned RXF4EID14 :1; unsigned RXF4EID15 :1; }; } RXF4EIDHbits_t; extern volatile RXF4EIDHbits_t RXF4EIDHbits @ 0xEF2; // bitfield macros #define _RXF4EIDH_EID_POSN 0x0 #define _RXF4EIDH_EID_POSITION 0x0 #define _RXF4EIDH_EID_SIZE 0x8 #define _RXF4EIDH_EID_LENGTH 0x8 #define _RXF4EIDH_EID_MASK 0xFF #define _RXF4EIDH_EID8_POSN 0x0 #define _RXF4EIDH_EID8_POSITION 0x0 #define _RXF4EIDH_EID8_SIZE 0x1 #define _RXF4EIDH_EID8_LENGTH 0x1 #define _RXF4EIDH_EID8_MASK 0x1 #define _RXF4EIDH_EID9_POSN 0x1 #define _RXF4EIDH_EID9_POSITION 0x1 #define _RXF4EIDH_EID9_SIZE 0x1 #define _RXF4EIDH_EID9_LENGTH 0x1 #define _RXF4EIDH_EID9_MASK 0x2 #define _RXF4EIDH_EID10_POSN 0x2 #define _RXF4EIDH_EID10_POSITION 0x2 #define _RXF4EIDH_EID10_SIZE 0x1 #define _RXF4EIDH_EID10_LENGTH 0x1 #define _RXF4EIDH_EID10_MASK 0x4 #define _RXF4EIDH_EID11_POSN 0x3 #define _RXF4EIDH_EID11_POSITION 0x3 #define _RXF4EIDH_EID11_SIZE 0x1 #define _RXF4EIDH_EID11_LENGTH 0x1 #define _RXF4EIDH_EID11_MASK 0x8 #define _RXF4EIDH_EID12_POSN 0x4 #define _RXF4EIDH_EID12_POSITION 0x4 #define _RXF4EIDH_EID12_SIZE 0x1 #define _RXF4EIDH_EID12_LENGTH 0x1 #define _RXF4EIDH_EID12_MASK 0x10 #define _RXF4EIDH_EID13_POSN 0x5 #define _RXF4EIDH_EID13_POSITION 0x5 #define _RXF4EIDH_EID13_SIZE 0x1 #define _RXF4EIDH_EID13_LENGTH 0x1 #define _RXF4EIDH_EID13_MASK 0x20 #define _RXF4EIDH_EID14_POSN 0x6 #define _RXF4EIDH_EID14_POSITION 0x6 #define _RXF4EIDH_EID14_SIZE 0x1 #define _RXF4EIDH_EID14_LENGTH 0x1 #define _RXF4EIDH_EID14_MASK 0x40 #define _RXF4EIDH_EID15_POSN 0x7 #define _RXF4EIDH_EID15_POSITION 0x7 #define _RXF4EIDH_EID15_SIZE 0x1 #define _RXF4EIDH_EID15_LENGTH 0x1 #define _RXF4EIDH_EID15_MASK 0x80 #define _RXF4EIDH_RXF4EID8_POSN 0x0 #define _RXF4EIDH_RXF4EID8_POSITION 0x0 #define _RXF4EIDH_RXF4EID8_SIZE 0x1 #define _RXF4EIDH_RXF4EID8_LENGTH 0x1 #define _RXF4EIDH_RXF4EID8_MASK 0x1 #define _RXF4EIDH_RXF4EID9_POSN 0x1 #define _RXF4EIDH_RXF4EID9_POSITION 0x1 #define _RXF4EIDH_RXF4EID9_SIZE 0x1 #define _RXF4EIDH_RXF4EID9_LENGTH 0x1 #define _RXF4EIDH_RXF4EID9_MASK 0x2 #define _RXF4EIDH_RXF4EID10_POSN 0x2 #define _RXF4EIDH_RXF4EID10_POSITION 0x2 #define _RXF4EIDH_RXF4EID10_SIZE 0x1 #define _RXF4EIDH_RXF4EID10_LENGTH 0x1 #define _RXF4EIDH_RXF4EID10_MASK 0x4 #define _RXF4EIDH_RXF4EID11_POSN 0x3 #define _RXF4EIDH_RXF4EID11_POSITION 0x3 #define _RXF4EIDH_RXF4EID11_SIZE 0x1 #define _RXF4EIDH_RXF4EID11_LENGTH 0x1 #define _RXF4EIDH_RXF4EID11_MASK 0x8 #define _RXF4EIDH_RXF4EID12_POSN 0x4 #define _RXF4EIDH_RXF4EID12_POSITION 0x4 #define _RXF4EIDH_RXF4EID12_SIZE 0x1 #define _RXF4EIDH_RXF4EID12_LENGTH 0x1 #define _RXF4EIDH_RXF4EID12_MASK 0x10 #define _RXF4EIDH_RXF4EID13_POSN 0x5 #define _RXF4EIDH_RXF4EID13_POSITION 0x5 #define _RXF4EIDH_RXF4EID13_SIZE 0x1 #define _RXF4EIDH_RXF4EID13_LENGTH 0x1 #define _RXF4EIDH_RXF4EID13_MASK 0x20 #define _RXF4EIDH_RXF4EID14_POSN 0x6 #define _RXF4EIDH_RXF4EID14_POSITION 0x6 #define _RXF4EIDH_RXF4EID14_SIZE 0x1 #define _RXF4EIDH_RXF4EID14_LENGTH 0x1 #define _RXF4EIDH_RXF4EID14_MASK 0x40 #define _RXF4EIDH_RXF4EID15_POSN 0x7 #define _RXF4EIDH_RXF4EID15_POSITION 0x7 #define _RXF4EIDH_RXF4EID15_SIZE 0x1 #define _RXF4EIDH_RXF4EID15_LENGTH 0x1 #define _RXF4EIDH_RXF4EID15_MASK 0x80 // Register: RXF4EIDL #define RXF4EIDL RXF4EIDL extern volatile unsigned char RXF4EIDL @ 0xEF3; #ifndef _LIB_BUILD asm("RXF4EIDL equ 0EF3h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF4EID0 :1; unsigned RXF4EID1 :1; unsigned RXF4EID2 :1; unsigned RXF4EID3 :1; unsigned RXF4EID4 :1; unsigned RXF4EID5 :1; unsigned RXF4EID6 :1; unsigned RXF4EID7 :1; }; } RXF4EIDLbits_t; extern volatile RXF4EIDLbits_t RXF4EIDLbits @ 0xEF3; // bitfield macros #define _RXF4EIDL_EID_POSN 0x0 #define _RXF4EIDL_EID_POSITION 0x0 #define _RXF4EIDL_EID_SIZE 0x8 #define _RXF4EIDL_EID_LENGTH 0x8 #define _RXF4EIDL_EID_MASK 0xFF #define _RXF4EIDL_EID0_POSN 0x0 #define _RXF4EIDL_EID0_POSITION 0x0 #define _RXF4EIDL_EID0_SIZE 0x1 #define _RXF4EIDL_EID0_LENGTH 0x1 #define _RXF4EIDL_EID0_MASK 0x1 #define _RXF4EIDL_EID1_POSN 0x1 #define _RXF4EIDL_EID1_POSITION 0x1 #define _RXF4EIDL_EID1_SIZE 0x1 #define _RXF4EIDL_EID1_LENGTH 0x1 #define _RXF4EIDL_EID1_MASK 0x2 #define _RXF4EIDL_EID2_POSN 0x2 #define _RXF4EIDL_EID2_POSITION 0x2 #define _RXF4EIDL_EID2_SIZE 0x1 #define _RXF4EIDL_EID2_LENGTH 0x1 #define _RXF4EIDL_EID2_MASK 0x4 #define _RXF4EIDL_EID3_POSN 0x3 #define _RXF4EIDL_EID3_POSITION 0x3 #define _RXF4EIDL_EID3_SIZE 0x1 #define _RXF4EIDL_EID3_LENGTH 0x1 #define _RXF4EIDL_EID3_MASK 0x8 #define _RXF4EIDL_EID4_POSN 0x4 #define _RXF4EIDL_EID4_POSITION 0x4 #define _RXF4EIDL_EID4_SIZE 0x1 #define _RXF4EIDL_EID4_LENGTH 0x1 #define _RXF4EIDL_EID4_MASK 0x10 #define _RXF4EIDL_EID5_POSN 0x5 #define _RXF4EIDL_EID5_POSITION 0x5 #define _RXF4EIDL_EID5_SIZE 0x1 #define _RXF4EIDL_EID5_LENGTH 0x1 #define _RXF4EIDL_EID5_MASK 0x20 #define _RXF4EIDL_EID6_POSN 0x6 #define _RXF4EIDL_EID6_POSITION 0x6 #define _RXF4EIDL_EID6_SIZE 0x1 #define _RXF4EIDL_EID6_LENGTH 0x1 #define _RXF4EIDL_EID6_MASK 0x40 #define _RXF4EIDL_EID7_POSN 0x7 #define _RXF4EIDL_EID7_POSITION 0x7 #define _RXF4EIDL_EID7_SIZE 0x1 #define _RXF4EIDL_EID7_LENGTH 0x1 #define _RXF4EIDL_EID7_MASK 0x80 #define _RXF4EIDL_RXF4EID0_POSN 0x0 #define _RXF4EIDL_RXF4EID0_POSITION 0x0 #define _RXF4EIDL_RXF4EID0_SIZE 0x1 #define _RXF4EIDL_RXF4EID0_LENGTH 0x1 #define _RXF4EIDL_RXF4EID0_MASK 0x1 #define _RXF4EIDL_RXF4EID1_POSN 0x1 #define _RXF4EIDL_RXF4EID1_POSITION 0x1 #define _RXF4EIDL_RXF4EID1_SIZE 0x1 #define _RXF4EIDL_RXF4EID1_LENGTH 0x1 #define _RXF4EIDL_RXF4EID1_MASK 0x2 #define _RXF4EIDL_RXF4EID2_POSN 0x2 #define _RXF4EIDL_RXF4EID2_POSITION 0x2 #define _RXF4EIDL_RXF4EID2_SIZE 0x1 #define _RXF4EIDL_RXF4EID2_LENGTH 0x1 #define _RXF4EIDL_RXF4EID2_MASK 0x4 #define _RXF4EIDL_RXF4EID3_POSN 0x3 #define _RXF4EIDL_RXF4EID3_POSITION 0x3 #define _RXF4EIDL_RXF4EID3_SIZE 0x1 #define _RXF4EIDL_RXF4EID3_LENGTH 0x1 #define _RXF4EIDL_RXF4EID3_MASK 0x8 #define _RXF4EIDL_RXF4EID4_POSN 0x4 #define _RXF4EIDL_RXF4EID4_POSITION 0x4 #define _RXF4EIDL_RXF4EID4_SIZE 0x1 #define _RXF4EIDL_RXF4EID4_LENGTH 0x1 #define _RXF4EIDL_RXF4EID4_MASK 0x10 #define _RXF4EIDL_RXF4EID5_POSN 0x5 #define _RXF4EIDL_RXF4EID5_POSITION 0x5 #define _RXF4EIDL_RXF4EID5_SIZE 0x1 #define _RXF4EIDL_RXF4EID5_LENGTH 0x1 #define _RXF4EIDL_RXF4EID5_MASK 0x20 #define _RXF4EIDL_RXF4EID6_POSN 0x6 #define _RXF4EIDL_RXF4EID6_POSITION 0x6 #define _RXF4EIDL_RXF4EID6_SIZE 0x1 #define _RXF4EIDL_RXF4EID6_LENGTH 0x1 #define _RXF4EIDL_RXF4EID6_MASK 0x40 #define _RXF4EIDL_RXF4EID7_POSN 0x7 #define _RXF4EIDL_RXF4EID7_POSITION 0x7 #define _RXF4EIDL_RXF4EID7_SIZE 0x1 #define _RXF4EIDL_RXF4EID7_LENGTH 0x1 #define _RXF4EIDL_RXF4EID7_MASK 0x80 // Register: RXF5SIDH #define RXF5SIDH RXF5SIDH extern volatile unsigned char RXF5SIDH @ 0xEF4; #ifndef _LIB_BUILD asm("RXF5SIDH equ 0EF4h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXF5SID3 :1; unsigned RXF5SID4 :1; unsigned RXF5SID5 :1; unsigned RXF5SID6 :1; unsigned RXF5SID7 :1; unsigned RXF5SID8 :1; unsigned RXF5SID9 :1; unsigned RXF5SID10 :1; }; } RXF5SIDHbits_t; extern volatile RXF5SIDHbits_t RXF5SIDHbits @ 0xEF4; // bitfield macros #define _RXF5SIDH_SID_POSN 0x0 #define _RXF5SIDH_SID_POSITION 0x0 #define _RXF5SIDH_SID_SIZE 0x8 #define _RXF5SIDH_SID_LENGTH 0x8 #define _RXF5SIDH_SID_MASK 0xFF #define _RXF5SIDH_SID3_POSN 0x0 #define _RXF5SIDH_SID3_POSITION 0x0 #define _RXF5SIDH_SID3_SIZE 0x1 #define _RXF5SIDH_SID3_LENGTH 0x1 #define _RXF5SIDH_SID3_MASK 0x1 #define _RXF5SIDH_SID4_POSN 0x1 #define _RXF5SIDH_SID4_POSITION 0x1 #define _RXF5SIDH_SID4_SIZE 0x1 #define _RXF5SIDH_SID4_LENGTH 0x1 #define _RXF5SIDH_SID4_MASK 0x2 #define _RXF5SIDH_SID5_POSN 0x2 #define _RXF5SIDH_SID5_POSITION 0x2 #define _RXF5SIDH_SID5_SIZE 0x1 #define _RXF5SIDH_SID5_LENGTH 0x1 #define _RXF5SIDH_SID5_MASK 0x4 #define _RXF5SIDH_SID6_POSN 0x3 #define _RXF5SIDH_SID6_POSITION 0x3 #define _RXF5SIDH_SID6_SIZE 0x1 #define _RXF5SIDH_SID6_LENGTH 0x1 #define _RXF5SIDH_SID6_MASK 0x8 #define _RXF5SIDH_SID7_POSN 0x4 #define _RXF5SIDH_SID7_POSITION 0x4 #define _RXF5SIDH_SID7_SIZE 0x1 #define _RXF5SIDH_SID7_LENGTH 0x1 #define _RXF5SIDH_SID7_MASK 0x10 #define _RXF5SIDH_SID8_POSN 0x5 #define _RXF5SIDH_SID8_POSITION 0x5 #define _RXF5SIDH_SID8_SIZE 0x1 #define _RXF5SIDH_SID8_LENGTH 0x1 #define _RXF5SIDH_SID8_MASK 0x20 #define _RXF5SIDH_SID9_POSN 0x6 #define _RXF5SIDH_SID9_POSITION 0x6 #define _RXF5SIDH_SID9_SIZE 0x1 #define _RXF5SIDH_SID9_LENGTH 0x1 #define _RXF5SIDH_SID9_MASK 0x40 #define _RXF5SIDH_SID10_POSN 0x7 #define _RXF5SIDH_SID10_POSITION 0x7 #define _RXF5SIDH_SID10_SIZE 0x1 #define _RXF5SIDH_SID10_LENGTH 0x1 #define _RXF5SIDH_SID10_MASK 0x80 #define _RXF5SIDH_RXF5SID3_POSN 0x0 #define _RXF5SIDH_RXF5SID3_POSITION 0x0 #define _RXF5SIDH_RXF5SID3_SIZE 0x1 #define _RXF5SIDH_RXF5SID3_LENGTH 0x1 #define _RXF5SIDH_RXF5SID3_MASK 0x1 #define _RXF5SIDH_RXF5SID4_POSN 0x1 #define _RXF5SIDH_RXF5SID4_POSITION 0x1 #define _RXF5SIDH_RXF5SID4_SIZE 0x1 #define _RXF5SIDH_RXF5SID4_LENGTH 0x1 #define _RXF5SIDH_RXF5SID4_MASK 0x2 #define _RXF5SIDH_RXF5SID5_POSN 0x2 #define _RXF5SIDH_RXF5SID5_POSITION 0x2 #define _RXF5SIDH_RXF5SID5_SIZE 0x1 #define _RXF5SIDH_RXF5SID5_LENGTH 0x1 #define _RXF5SIDH_RXF5SID5_MASK 0x4 #define _RXF5SIDH_RXF5SID6_POSN 0x3 #define _RXF5SIDH_RXF5SID6_POSITION 0x3 #define _RXF5SIDH_RXF5SID6_SIZE 0x1 #define _RXF5SIDH_RXF5SID6_LENGTH 0x1 #define _RXF5SIDH_RXF5SID6_MASK 0x8 #define _RXF5SIDH_RXF5SID7_POSN 0x4 #define _RXF5SIDH_RXF5SID7_POSITION 0x4 #define _RXF5SIDH_RXF5SID7_SIZE 0x1 #define _RXF5SIDH_RXF5SID7_LENGTH 0x1 #define _RXF5SIDH_RXF5SID7_MASK 0x10 #define _RXF5SIDH_RXF5SID8_POSN 0x5 #define _RXF5SIDH_RXF5SID8_POSITION 0x5 #define _RXF5SIDH_RXF5SID8_SIZE 0x1 #define _RXF5SIDH_RXF5SID8_LENGTH 0x1 #define _RXF5SIDH_RXF5SID8_MASK 0x20 #define _RXF5SIDH_RXF5SID9_POSN 0x6 #define _RXF5SIDH_RXF5SID9_POSITION 0x6 #define _RXF5SIDH_RXF5SID9_SIZE 0x1 #define _RXF5SIDH_RXF5SID9_LENGTH 0x1 #define _RXF5SIDH_RXF5SID9_MASK 0x40 #define _RXF5SIDH_RXF5SID10_POSN 0x7 #define _RXF5SIDH_RXF5SID10_POSITION 0x7 #define _RXF5SIDH_RXF5SID10_SIZE 0x1 #define _RXF5SIDH_RXF5SID10_LENGTH 0x1 #define _RXF5SIDH_RXF5SID10_MASK 0x80 // Register: RXF5SIDL #define RXF5SIDL RXF5SIDL extern volatile unsigned char RXF5SIDL @ 0xEF5; #ifndef _LIB_BUILD asm("RXF5SIDL equ 0EF5h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXF5EID16 :1; unsigned RXF5EID17 :1; unsigned :1; unsigned RXF5EXIDEN :1; unsigned :1; unsigned RXF5SID0 :1; unsigned RXF5SID1 :1; unsigned RXF5SID2 :1; }; } RXF5SIDLbits_t; extern volatile RXF5SIDLbits_t RXF5SIDLbits @ 0xEF5; // bitfield macros #define _RXF5SIDL_EID_POSN 0x0 #define _RXF5SIDL_EID_POSITION 0x0 #define _RXF5SIDL_EID_SIZE 0x2 #define _RXF5SIDL_EID_LENGTH 0x2 #define _RXF5SIDL_EID_MASK 0x3 #define _RXF5SIDL_EXIDEN_POSN 0x3 #define _RXF5SIDL_EXIDEN_POSITION 0x3 #define _RXF5SIDL_EXIDEN_SIZE 0x1 #define _RXF5SIDL_EXIDEN_LENGTH 0x1 #define _RXF5SIDL_EXIDEN_MASK 0x8 #define _RXF5SIDL_SID_POSN 0x5 #define _RXF5SIDL_SID_POSITION 0x5 #define _RXF5SIDL_SID_SIZE 0x3 #define _RXF5SIDL_SID_LENGTH 0x3 #define _RXF5SIDL_SID_MASK 0xE0 #define _RXF5SIDL_EID16_POSN 0x0 #define _RXF5SIDL_EID16_POSITION 0x0 #define _RXF5SIDL_EID16_SIZE 0x1 #define _RXF5SIDL_EID16_LENGTH 0x1 #define _RXF5SIDL_EID16_MASK 0x1 #define _RXF5SIDL_EID17_POSN 0x1 #define _RXF5SIDL_EID17_POSITION 0x1 #define _RXF5SIDL_EID17_SIZE 0x1 #define _RXF5SIDL_EID17_LENGTH 0x1 #define _RXF5SIDL_EID17_MASK 0x2 #define _RXF5SIDL_SID0_POSN 0x5 #define _RXF5SIDL_SID0_POSITION 0x5 #define _RXF5SIDL_SID0_SIZE 0x1 #define _RXF5SIDL_SID0_LENGTH 0x1 #define _RXF5SIDL_SID0_MASK 0x20 #define _RXF5SIDL_SID1_POSN 0x6 #define _RXF5SIDL_SID1_POSITION 0x6 #define _RXF5SIDL_SID1_SIZE 0x1 #define _RXF5SIDL_SID1_LENGTH 0x1 #define _RXF5SIDL_SID1_MASK 0x40 #define _RXF5SIDL_SID2_POSN 0x7 #define _RXF5SIDL_SID2_POSITION 0x7 #define _RXF5SIDL_SID2_SIZE 0x1 #define _RXF5SIDL_SID2_LENGTH 0x1 #define _RXF5SIDL_SID2_MASK 0x80 #define _RXF5SIDL_RXF5EID16_POSN 0x0 #define _RXF5SIDL_RXF5EID16_POSITION 0x0 #define _RXF5SIDL_RXF5EID16_SIZE 0x1 #define _RXF5SIDL_RXF5EID16_LENGTH 0x1 #define _RXF5SIDL_RXF5EID16_MASK 0x1 #define _RXF5SIDL_RXF5EID17_POSN 0x1 #define _RXF5SIDL_RXF5EID17_POSITION 0x1 #define _RXF5SIDL_RXF5EID17_SIZE 0x1 #define _RXF5SIDL_RXF5EID17_LENGTH 0x1 #define _RXF5SIDL_RXF5EID17_MASK 0x2 #define _RXF5SIDL_RXF5EXIDEN_POSN 0x3 #define _RXF5SIDL_RXF5EXIDEN_POSITION 0x3 #define _RXF5SIDL_RXF5EXIDEN_SIZE 0x1 #define _RXF5SIDL_RXF5EXIDEN_LENGTH 0x1 #define _RXF5SIDL_RXF5EXIDEN_MASK 0x8 #define _RXF5SIDL_RXF5SID0_POSN 0x5 #define _RXF5SIDL_RXF5SID0_POSITION 0x5 #define _RXF5SIDL_RXF5SID0_SIZE 0x1 #define _RXF5SIDL_RXF5SID0_LENGTH 0x1 #define _RXF5SIDL_RXF5SID0_MASK 0x20 #define _RXF5SIDL_RXF5SID1_POSN 0x6 #define _RXF5SIDL_RXF5SID1_POSITION 0x6 #define _RXF5SIDL_RXF5SID1_SIZE 0x1 #define _RXF5SIDL_RXF5SID1_LENGTH 0x1 #define _RXF5SIDL_RXF5SID1_MASK 0x40 #define _RXF5SIDL_RXF5SID2_POSN 0x7 #define _RXF5SIDL_RXF5SID2_POSITION 0x7 #define _RXF5SIDL_RXF5SID2_SIZE 0x1 #define _RXF5SIDL_RXF5SID2_LENGTH 0x1 #define _RXF5SIDL_RXF5SID2_MASK 0x80 // Register: RXF5EIDH #define RXF5EIDH RXF5EIDH extern volatile unsigned char RXF5EIDH @ 0xEF6; #ifndef _LIB_BUILD asm("RXF5EIDH equ 0EF6h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXF5EID8 :1; unsigned RXF5EID9 :1; unsigned RXF5EID10 :1; unsigned RXF5EID11 :1; unsigned RXF5EID12 :1; unsigned RXF5EID13 :1; unsigned RXF5EID14 :1; unsigned RXF5EID15 :1; }; } RXF5EIDHbits_t; extern volatile RXF5EIDHbits_t RXF5EIDHbits @ 0xEF6; // bitfield macros #define _RXF5EIDH_EID_POSN 0x0 #define _RXF5EIDH_EID_POSITION 0x0 #define _RXF5EIDH_EID_SIZE 0x8 #define _RXF5EIDH_EID_LENGTH 0x8 #define _RXF5EIDH_EID_MASK 0xFF #define _RXF5EIDH_EID8_POSN 0x0 #define _RXF5EIDH_EID8_POSITION 0x0 #define _RXF5EIDH_EID8_SIZE 0x1 #define _RXF5EIDH_EID8_LENGTH 0x1 #define _RXF5EIDH_EID8_MASK 0x1 #define _RXF5EIDH_EID9_POSN 0x1 #define _RXF5EIDH_EID9_POSITION 0x1 #define _RXF5EIDH_EID9_SIZE 0x1 #define _RXF5EIDH_EID9_LENGTH 0x1 #define _RXF5EIDH_EID9_MASK 0x2 #define _RXF5EIDH_EID10_POSN 0x2 #define _RXF5EIDH_EID10_POSITION 0x2 #define _RXF5EIDH_EID10_SIZE 0x1 #define _RXF5EIDH_EID10_LENGTH 0x1 #define _RXF5EIDH_EID10_MASK 0x4 #define _RXF5EIDH_EID11_POSN 0x3 #define _RXF5EIDH_EID11_POSITION 0x3 #define _RXF5EIDH_EID11_SIZE 0x1 #define _RXF5EIDH_EID11_LENGTH 0x1 #define _RXF5EIDH_EID11_MASK 0x8 #define _RXF5EIDH_EID12_POSN 0x4 #define _RXF5EIDH_EID12_POSITION 0x4 #define _RXF5EIDH_EID12_SIZE 0x1 #define _RXF5EIDH_EID12_LENGTH 0x1 #define _RXF5EIDH_EID12_MASK 0x10 #define _RXF5EIDH_EID13_POSN 0x5 #define _RXF5EIDH_EID13_POSITION 0x5 #define _RXF5EIDH_EID13_SIZE 0x1 #define _RXF5EIDH_EID13_LENGTH 0x1 #define _RXF5EIDH_EID13_MASK 0x20 #define _RXF5EIDH_EID14_POSN 0x6 #define _RXF5EIDH_EID14_POSITION 0x6 #define _RXF5EIDH_EID14_SIZE 0x1 #define _RXF5EIDH_EID14_LENGTH 0x1 #define _RXF5EIDH_EID14_MASK 0x40 #define _RXF5EIDH_EID15_POSN 0x7 #define _RXF5EIDH_EID15_POSITION 0x7 #define _RXF5EIDH_EID15_SIZE 0x1 #define _RXF5EIDH_EID15_LENGTH 0x1 #define _RXF5EIDH_EID15_MASK 0x80 #define _RXF5EIDH_RXF5EID8_POSN 0x0 #define _RXF5EIDH_RXF5EID8_POSITION 0x0 #define _RXF5EIDH_RXF5EID8_SIZE 0x1 #define _RXF5EIDH_RXF5EID8_LENGTH 0x1 #define _RXF5EIDH_RXF5EID8_MASK 0x1 #define _RXF5EIDH_RXF5EID9_POSN 0x1 #define _RXF5EIDH_RXF5EID9_POSITION 0x1 #define _RXF5EIDH_RXF5EID9_SIZE 0x1 #define _RXF5EIDH_RXF5EID9_LENGTH 0x1 #define _RXF5EIDH_RXF5EID9_MASK 0x2 #define _RXF5EIDH_RXF5EID10_POSN 0x2 #define _RXF5EIDH_RXF5EID10_POSITION 0x2 #define _RXF5EIDH_RXF5EID10_SIZE 0x1 #define _RXF5EIDH_RXF5EID10_LENGTH 0x1 #define _RXF5EIDH_RXF5EID10_MASK 0x4 #define _RXF5EIDH_RXF5EID11_POSN 0x3 #define _RXF5EIDH_RXF5EID11_POSITION 0x3 #define _RXF5EIDH_RXF5EID11_SIZE 0x1 #define _RXF5EIDH_RXF5EID11_LENGTH 0x1 #define _RXF5EIDH_RXF5EID11_MASK 0x8 #define _RXF5EIDH_RXF5EID12_POSN 0x4 #define _RXF5EIDH_RXF5EID12_POSITION 0x4 #define _RXF5EIDH_RXF5EID12_SIZE 0x1 #define _RXF5EIDH_RXF5EID12_LENGTH 0x1 #define _RXF5EIDH_RXF5EID12_MASK 0x10 #define _RXF5EIDH_RXF5EID13_POSN 0x5 #define _RXF5EIDH_RXF5EID13_POSITION 0x5 #define _RXF5EIDH_RXF5EID13_SIZE 0x1 #define _RXF5EIDH_RXF5EID13_LENGTH 0x1 #define _RXF5EIDH_RXF5EID13_MASK 0x20 #define _RXF5EIDH_RXF5EID14_POSN 0x6 #define _RXF5EIDH_RXF5EID14_POSITION 0x6 #define _RXF5EIDH_RXF5EID14_SIZE 0x1 #define _RXF5EIDH_RXF5EID14_LENGTH 0x1 #define _RXF5EIDH_RXF5EID14_MASK 0x40 #define _RXF5EIDH_RXF5EID15_POSN 0x7 #define _RXF5EIDH_RXF5EID15_POSITION 0x7 #define _RXF5EIDH_RXF5EID15_SIZE 0x1 #define _RXF5EIDH_RXF5EID15_LENGTH 0x1 #define _RXF5EIDH_RXF5EID15_MASK 0x80 // Register: RXF5EIDL #define RXF5EIDL RXF5EIDL extern volatile unsigned char RXF5EIDL @ 0xEF7; #ifndef _LIB_BUILD asm("RXF5EIDL equ 0EF7h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXF5EID0 :1; unsigned RXF5EID1 :1; unsigned RXF5EID2 :1; unsigned RXF5EID3 :1; unsigned RXF5EID4 :1; unsigned RXF5EID5 :1; unsigned RXF5EID6 :1; unsigned RXF5EID7 :1; }; } RXF5EIDLbits_t; extern volatile RXF5EIDLbits_t RXF5EIDLbits @ 0xEF7; // bitfield macros #define _RXF5EIDL_EID_POSN 0x0 #define _RXF5EIDL_EID_POSITION 0x0 #define _RXF5EIDL_EID_SIZE 0x8 #define _RXF5EIDL_EID_LENGTH 0x8 #define _RXF5EIDL_EID_MASK 0xFF #define _RXF5EIDL_EID0_POSN 0x0 #define _RXF5EIDL_EID0_POSITION 0x0 #define _RXF5EIDL_EID0_SIZE 0x1 #define _RXF5EIDL_EID0_LENGTH 0x1 #define _RXF5EIDL_EID0_MASK 0x1 #define _RXF5EIDL_EID1_POSN 0x1 #define _RXF5EIDL_EID1_POSITION 0x1 #define _RXF5EIDL_EID1_SIZE 0x1 #define _RXF5EIDL_EID1_LENGTH 0x1 #define _RXF5EIDL_EID1_MASK 0x2 #define _RXF5EIDL_EID2_POSN 0x2 #define _RXF5EIDL_EID2_POSITION 0x2 #define _RXF5EIDL_EID2_SIZE 0x1 #define _RXF5EIDL_EID2_LENGTH 0x1 #define _RXF5EIDL_EID2_MASK 0x4 #define _RXF5EIDL_EID3_POSN 0x3 #define _RXF5EIDL_EID3_POSITION 0x3 #define _RXF5EIDL_EID3_SIZE 0x1 #define _RXF5EIDL_EID3_LENGTH 0x1 #define _RXF5EIDL_EID3_MASK 0x8 #define _RXF5EIDL_EID4_POSN 0x4 #define _RXF5EIDL_EID4_POSITION 0x4 #define _RXF5EIDL_EID4_SIZE 0x1 #define _RXF5EIDL_EID4_LENGTH 0x1 #define _RXF5EIDL_EID4_MASK 0x10 #define _RXF5EIDL_EID5_POSN 0x5 #define _RXF5EIDL_EID5_POSITION 0x5 #define _RXF5EIDL_EID5_SIZE 0x1 #define _RXF5EIDL_EID5_LENGTH 0x1 #define _RXF5EIDL_EID5_MASK 0x20 #define _RXF5EIDL_EID6_POSN 0x6 #define _RXF5EIDL_EID6_POSITION 0x6 #define _RXF5EIDL_EID6_SIZE 0x1 #define _RXF5EIDL_EID6_LENGTH 0x1 #define _RXF5EIDL_EID6_MASK 0x40 #define _RXF5EIDL_EID7_POSN 0x7 #define _RXF5EIDL_EID7_POSITION 0x7 #define _RXF5EIDL_EID7_SIZE 0x1 #define _RXF5EIDL_EID7_LENGTH 0x1 #define _RXF5EIDL_EID7_MASK 0x80 #define _RXF5EIDL_RXF5EID0_POSN 0x0 #define _RXF5EIDL_RXF5EID0_POSITION 0x0 #define _RXF5EIDL_RXF5EID0_SIZE 0x1 #define _RXF5EIDL_RXF5EID0_LENGTH 0x1 #define _RXF5EIDL_RXF5EID0_MASK 0x1 #define _RXF5EIDL_RXF5EID1_POSN 0x1 #define _RXF5EIDL_RXF5EID1_POSITION 0x1 #define _RXF5EIDL_RXF5EID1_SIZE 0x1 #define _RXF5EIDL_RXF5EID1_LENGTH 0x1 #define _RXF5EIDL_RXF5EID1_MASK 0x2 #define _RXF5EIDL_RXF5EID2_POSN 0x2 #define _RXF5EIDL_RXF5EID2_POSITION 0x2 #define _RXF5EIDL_RXF5EID2_SIZE 0x1 #define _RXF5EIDL_RXF5EID2_LENGTH 0x1 #define _RXF5EIDL_RXF5EID2_MASK 0x4 #define _RXF5EIDL_RXF5EID3_POSN 0x3 #define _RXF5EIDL_RXF5EID3_POSITION 0x3 #define _RXF5EIDL_RXF5EID3_SIZE 0x1 #define _RXF5EIDL_RXF5EID3_LENGTH 0x1 #define _RXF5EIDL_RXF5EID3_MASK 0x8 #define _RXF5EIDL_RXF5EID4_POSN 0x4 #define _RXF5EIDL_RXF5EID4_POSITION 0x4 #define _RXF5EIDL_RXF5EID4_SIZE 0x1 #define _RXF5EIDL_RXF5EID4_LENGTH 0x1 #define _RXF5EIDL_RXF5EID4_MASK 0x10 #define _RXF5EIDL_RXF5EID5_POSN 0x5 #define _RXF5EIDL_RXF5EID5_POSITION 0x5 #define _RXF5EIDL_RXF5EID5_SIZE 0x1 #define _RXF5EIDL_RXF5EID5_LENGTH 0x1 #define _RXF5EIDL_RXF5EID5_MASK 0x20 #define _RXF5EIDL_RXF5EID6_POSN 0x6 #define _RXF5EIDL_RXF5EID6_POSITION 0x6 #define _RXF5EIDL_RXF5EID6_SIZE 0x1 #define _RXF5EIDL_RXF5EID6_LENGTH 0x1 #define _RXF5EIDL_RXF5EID6_MASK 0x40 #define _RXF5EIDL_RXF5EID7_POSN 0x7 #define _RXF5EIDL_RXF5EID7_POSITION 0x7 #define _RXF5EIDL_RXF5EID7_SIZE 0x1 #define _RXF5EIDL_RXF5EID7_LENGTH 0x1 #define _RXF5EIDL_RXF5EID7_MASK 0x80 // Register: RXM0SIDH #define RXM0SIDH RXM0SIDH extern volatile unsigned char RXM0SIDH @ 0xEF8; #ifndef _LIB_BUILD asm("RXM0SIDH equ 0EF8h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXM0SID3 :1; unsigned RXM0SID4 :1; unsigned RXM0SID5 :1; unsigned RXM0SID6 :1; unsigned RXM0SID7 :1; unsigned RXM0SID8 :1; unsigned RXM0SID9 :1; unsigned RXM0SID10 :1; }; } RXM0SIDHbits_t; extern volatile RXM0SIDHbits_t RXM0SIDHbits @ 0xEF8; // bitfield macros #define _RXM0SIDH_SID_POSN 0x0 #define _RXM0SIDH_SID_POSITION 0x0 #define _RXM0SIDH_SID_SIZE 0x8 #define _RXM0SIDH_SID_LENGTH 0x8 #define _RXM0SIDH_SID_MASK 0xFF #define _RXM0SIDH_SID3_POSN 0x0 #define _RXM0SIDH_SID3_POSITION 0x0 #define _RXM0SIDH_SID3_SIZE 0x1 #define _RXM0SIDH_SID3_LENGTH 0x1 #define _RXM0SIDH_SID3_MASK 0x1 #define _RXM0SIDH_SID4_POSN 0x1 #define _RXM0SIDH_SID4_POSITION 0x1 #define _RXM0SIDH_SID4_SIZE 0x1 #define _RXM0SIDH_SID4_LENGTH 0x1 #define _RXM0SIDH_SID4_MASK 0x2 #define _RXM0SIDH_SID5_POSN 0x2 #define _RXM0SIDH_SID5_POSITION 0x2 #define _RXM0SIDH_SID5_SIZE 0x1 #define _RXM0SIDH_SID5_LENGTH 0x1 #define _RXM0SIDH_SID5_MASK 0x4 #define _RXM0SIDH_SID6_POSN 0x3 #define _RXM0SIDH_SID6_POSITION 0x3 #define _RXM0SIDH_SID6_SIZE 0x1 #define _RXM0SIDH_SID6_LENGTH 0x1 #define _RXM0SIDH_SID6_MASK 0x8 #define _RXM0SIDH_SID7_POSN 0x4 #define _RXM0SIDH_SID7_POSITION 0x4 #define _RXM0SIDH_SID7_SIZE 0x1 #define _RXM0SIDH_SID7_LENGTH 0x1 #define _RXM0SIDH_SID7_MASK 0x10 #define _RXM0SIDH_SID8_POSN 0x5 #define _RXM0SIDH_SID8_POSITION 0x5 #define _RXM0SIDH_SID8_SIZE 0x1 #define _RXM0SIDH_SID8_LENGTH 0x1 #define _RXM0SIDH_SID8_MASK 0x20 #define _RXM0SIDH_SID9_POSN 0x6 #define _RXM0SIDH_SID9_POSITION 0x6 #define _RXM0SIDH_SID9_SIZE 0x1 #define _RXM0SIDH_SID9_LENGTH 0x1 #define _RXM0SIDH_SID9_MASK 0x40 #define _RXM0SIDH_SID10_POSN 0x7 #define _RXM0SIDH_SID10_POSITION 0x7 #define _RXM0SIDH_SID10_SIZE 0x1 #define _RXM0SIDH_SID10_LENGTH 0x1 #define _RXM0SIDH_SID10_MASK 0x80 #define _RXM0SIDH_RXM0SID3_POSN 0x0 #define _RXM0SIDH_RXM0SID3_POSITION 0x0 #define _RXM0SIDH_RXM0SID3_SIZE 0x1 #define _RXM0SIDH_RXM0SID3_LENGTH 0x1 #define _RXM0SIDH_RXM0SID3_MASK 0x1 #define _RXM0SIDH_RXM0SID4_POSN 0x1 #define _RXM0SIDH_RXM0SID4_POSITION 0x1 #define _RXM0SIDH_RXM0SID4_SIZE 0x1 #define _RXM0SIDH_RXM0SID4_LENGTH 0x1 #define _RXM0SIDH_RXM0SID4_MASK 0x2 #define _RXM0SIDH_RXM0SID5_POSN 0x2 #define _RXM0SIDH_RXM0SID5_POSITION 0x2 #define _RXM0SIDH_RXM0SID5_SIZE 0x1 #define _RXM0SIDH_RXM0SID5_LENGTH 0x1 #define _RXM0SIDH_RXM0SID5_MASK 0x4 #define _RXM0SIDH_RXM0SID6_POSN 0x3 #define _RXM0SIDH_RXM0SID6_POSITION 0x3 #define _RXM0SIDH_RXM0SID6_SIZE 0x1 #define _RXM0SIDH_RXM0SID6_LENGTH 0x1 #define _RXM0SIDH_RXM0SID6_MASK 0x8 #define _RXM0SIDH_RXM0SID7_POSN 0x4 #define _RXM0SIDH_RXM0SID7_POSITION 0x4 #define _RXM0SIDH_RXM0SID7_SIZE 0x1 #define _RXM0SIDH_RXM0SID7_LENGTH 0x1 #define _RXM0SIDH_RXM0SID7_MASK 0x10 #define _RXM0SIDH_RXM0SID8_POSN 0x5 #define _RXM0SIDH_RXM0SID8_POSITION 0x5 #define _RXM0SIDH_RXM0SID8_SIZE 0x1 #define _RXM0SIDH_RXM0SID8_LENGTH 0x1 #define _RXM0SIDH_RXM0SID8_MASK 0x20 #define _RXM0SIDH_RXM0SID9_POSN 0x6 #define _RXM0SIDH_RXM0SID9_POSITION 0x6 #define _RXM0SIDH_RXM0SID9_SIZE 0x1 #define _RXM0SIDH_RXM0SID9_LENGTH 0x1 #define _RXM0SIDH_RXM0SID9_MASK 0x40 #define _RXM0SIDH_RXM0SID10_POSN 0x7 #define _RXM0SIDH_RXM0SID10_POSITION 0x7 #define _RXM0SIDH_RXM0SID10_SIZE 0x1 #define _RXM0SIDH_RXM0SID10_LENGTH 0x1 #define _RXM0SIDH_RXM0SID10_MASK 0x80 // Register: RXM0SIDL #define RXM0SIDL RXM0SIDL extern volatile unsigned char RXM0SIDL @ 0xEF9; #ifndef _LIB_BUILD asm("RXM0SIDL equ 0EF9h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXM0EID16 :1; unsigned RXM0EID17 :1; unsigned :1; unsigned RXM0EXIDM :1; unsigned :1; unsigned RXM0SID0 :1; unsigned RXM0SID1 :1; unsigned RXM0SID2 :1; }; } RXM0SIDLbits_t; extern volatile RXM0SIDLbits_t RXM0SIDLbits @ 0xEF9; // bitfield macros #define _RXM0SIDL_EID_POSN 0x0 #define _RXM0SIDL_EID_POSITION 0x0 #define _RXM0SIDL_EID_SIZE 0x2 #define _RXM0SIDL_EID_LENGTH 0x2 #define _RXM0SIDL_EID_MASK 0x3 #define _RXM0SIDL_EXIDEN_POSN 0x3 #define _RXM0SIDL_EXIDEN_POSITION 0x3 #define _RXM0SIDL_EXIDEN_SIZE 0x1 #define _RXM0SIDL_EXIDEN_LENGTH 0x1 #define _RXM0SIDL_EXIDEN_MASK 0x8 #define _RXM0SIDL_SID_POSN 0x5 #define _RXM0SIDL_SID_POSITION 0x5 #define _RXM0SIDL_SID_SIZE 0x3 #define _RXM0SIDL_SID_LENGTH 0x3 #define _RXM0SIDL_SID_MASK 0xE0 #define _RXM0SIDL_EID16_POSN 0x0 #define _RXM0SIDL_EID16_POSITION 0x0 #define _RXM0SIDL_EID16_SIZE 0x1 #define _RXM0SIDL_EID16_LENGTH 0x1 #define _RXM0SIDL_EID16_MASK 0x1 #define _RXM0SIDL_EID17_POSN 0x1 #define _RXM0SIDL_EID17_POSITION 0x1 #define _RXM0SIDL_EID17_SIZE 0x1 #define _RXM0SIDL_EID17_LENGTH 0x1 #define _RXM0SIDL_EID17_MASK 0x2 #define _RXM0SIDL_SID0_POSN 0x5 #define _RXM0SIDL_SID0_POSITION 0x5 #define _RXM0SIDL_SID0_SIZE 0x1 #define _RXM0SIDL_SID0_LENGTH 0x1 #define _RXM0SIDL_SID0_MASK 0x20 #define _RXM0SIDL_SID1_POSN 0x6 #define _RXM0SIDL_SID1_POSITION 0x6 #define _RXM0SIDL_SID1_SIZE 0x1 #define _RXM0SIDL_SID1_LENGTH 0x1 #define _RXM0SIDL_SID1_MASK 0x40 #define _RXM0SIDL_SID2_POSN 0x7 #define _RXM0SIDL_SID2_POSITION 0x7 #define _RXM0SIDL_SID2_SIZE 0x1 #define _RXM0SIDL_SID2_LENGTH 0x1 #define _RXM0SIDL_SID2_MASK 0x80 #define _RXM0SIDL_RXM0EID16_POSN 0x0 #define _RXM0SIDL_RXM0EID16_POSITION 0x0 #define _RXM0SIDL_RXM0EID16_SIZE 0x1 #define _RXM0SIDL_RXM0EID16_LENGTH 0x1 #define _RXM0SIDL_RXM0EID16_MASK 0x1 #define _RXM0SIDL_RXM0EID17_POSN 0x1 #define _RXM0SIDL_RXM0EID17_POSITION 0x1 #define _RXM0SIDL_RXM0EID17_SIZE 0x1 #define _RXM0SIDL_RXM0EID17_LENGTH 0x1 #define _RXM0SIDL_RXM0EID17_MASK 0x2 #define _RXM0SIDL_RXM0EXIDM_POSN 0x3 #define _RXM0SIDL_RXM0EXIDM_POSITION 0x3 #define _RXM0SIDL_RXM0EXIDM_SIZE 0x1 #define _RXM0SIDL_RXM0EXIDM_LENGTH 0x1 #define _RXM0SIDL_RXM0EXIDM_MASK 0x8 #define _RXM0SIDL_RXM0SID0_POSN 0x5 #define _RXM0SIDL_RXM0SID0_POSITION 0x5 #define _RXM0SIDL_RXM0SID0_SIZE 0x1 #define _RXM0SIDL_RXM0SID0_LENGTH 0x1 #define _RXM0SIDL_RXM0SID0_MASK 0x20 #define _RXM0SIDL_RXM0SID1_POSN 0x6 #define _RXM0SIDL_RXM0SID1_POSITION 0x6 #define _RXM0SIDL_RXM0SID1_SIZE 0x1 #define _RXM0SIDL_RXM0SID1_LENGTH 0x1 #define _RXM0SIDL_RXM0SID1_MASK 0x40 #define _RXM0SIDL_RXM0SID2_POSN 0x7 #define _RXM0SIDL_RXM0SID2_POSITION 0x7 #define _RXM0SIDL_RXM0SID2_SIZE 0x1 #define _RXM0SIDL_RXM0SID2_LENGTH 0x1 #define _RXM0SIDL_RXM0SID2_MASK 0x80 // Register: RXM0EIDH #define RXM0EIDH RXM0EIDH extern volatile unsigned char RXM0EIDH @ 0xEFA; #ifndef _LIB_BUILD asm("RXM0EIDH equ 0EFAh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXM0EID8 :1; unsigned RXM0EID9 :1; unsigned RXM0EID10 :1; unsigned RXM0EID11 :1; unsigned RXM0EID12 :1; unsigned RXM0EID13 :1; unsigned RXM0EID14 :1; unsigned RXM0EID15 :1; }; } RXM0EIDHbits_t; extern volatile RXM0EIDHbits_t RXM0EIDHbits @ 0xEFA; // bitfield macros #define _RXM0EIDH_EID_POSN 0x0 #define _RXM0EIDH_EID_POSITION 0x0 #define _RXM0EIDH_EID_SIZE 0x8 #define _RXM0EIDH_EID_LENGTH 0x8 #define _RXM0EIDH_EID_MASK 0xFF #define _RXM0EIDH_EID8_POSN 0x0 #define _RXM0EIDH_EID8_POSITION 0x0 #define _RXM0EIDH_EID8_SIZE 0x1 #define _RXM0EIDH_EID8_LENGTH 0x1 #define _RXM0EIDH_EID8_MASK 0x1 #define _RXM0EIDH_EID9_POSN 0x1 #define _RXM0EIDH_EID9_POSITION 0x1 #define _RXM0EIDH_EID9_SIZE 0x1 #define _RXM0EIDH_EID9_LENGTH 0x1 #define _RXM0EIDH_EID9_MASK 0x2 #define _RXM0EIDH_EID10_POSN 0x2 #define _RXM0EIDH_EID10_POSITION 0x2 #define _RXM0EIDH_EID10_SIZE 0x1 #define _RXM0EIDH_EID10_LENGTH 0x1 #define _RXM0EIDH_EID10_MASK 0x4 #define _RXM0EIDH_EID11_POSN 0x3 #define _RXM0EIDH_EID11_POSITION 0x3 #define _RXM0EIDH_EID11_SIZE 0x1 #define _RXM0EIDH_EID11_LENGTH 0x1 #define _RXM0EIDH_EID11_MASK 0x8 #define _RXM0EIDH_EID12_POSN 0x4 #define _RXM0EIDH_EID12_POSITION 0x4 #define _RXM0EIDH_EID12_SIZE 0x1 #define _RXM0EIDH_EID12_LENGTH 0x1 #define _RXM0EIDH_EID12_MASK 0x10 #define _RXM0EIDH_EID13_POSN 0x5 #define _RXM0EIDH_EID13_POSITION 0x5 #define _RXM0EIDH_EID13_SIZE 0x1 #define _RXM0EIDH_EID13_LENGTH 0x1 #define _RXM0EIDH_EID13_MASK 0x20 #define _RXM0EIDH_EID14_POSN 0x6 #define _RXM0EIDH_EID14_POSITION 0x6 #define _RXM0EIDH_EID14_SIZE 0x1 #define _RXM0EIDH_EID14_LENGTH 0x1 #define _RXM0EIDH_EID14_MASK 0x40 #define _RXM0EIDH_EID15_POSN 0x7 #define _RXM0EIDH_EID15_POSITION 0x7 #define _RXM0EIDH_EID15_SIZE 0x1 #define _RXM0EIDH_EID15_LENGTH 0x1 #define _RXM0EIDH_EID15_MASK 0x80 #define _RXM0EIDH_RXM0EID8_POSN 0x0 #define _RXM0EIDH_RXM0EID8_POSITION 0x0 #define _RXM0EIDH_RXM0EID8_SIZE 0x1 #define _RXM0EIDH_RXM0EID8_LENGTH 0x1 #define _RXM0EIDH_RXM0EID8_MASK 0x1 #define _RXM0EIDH_RXM0EID9_POSN 0x1 #define _RXM0EIDH_RXM0EID9_POSITION 0x1 #define _RXM0EIDH_RXM0EID9_SIZE 0x1 #define _RXM0EIDH_RXM0EID9_LENGTH 0x1 #define _RXM0EIDH_RXM0EID9_MASK 0x2 #define _RXM0EIDH_RXM0EID10_POSN 0x2 #define _RXM0EIDH_RXM0EID10_POSITION 0x2 #define _RXM0EIDH_RXM0EID10_SIZE 0x1 #define _RXM0EIDH_RXM0EID10_LENGTH 0x1 #define _RXM0EIDH_RXM0EID10_MASK 0x4 #define _RXM0EIDH_RXM0EID11_POSN 0x3 #define _RXM0EIDH_RXM0EID11_POSITION 0x3 #define _RXM0EIDH_RXM0EID11_SIZE 0x1 #define _RXM0EIDH_RXM0EID11_LENGTH 0x1 #define _RXM0EIDH_RXM0EID11_MASK 0x8 #define _RXM0EIDH_RXM0EID12_POSN 0x4 #define _RXM0EIDH_RXM0EID12_POSITION 0x4 #define _RXM0EIDH_RXM0EID12_SIZE 0x1 #define _RXM0EIDH_RXM0EID12_LENGTH 0x1 #define _RXM0EIDH_RXM0EID12_MASK 0x10 #define _RXM0EIDH_RXM0EID13_POSN 0x5 #define _RXM0EIDH_RXM0EID13_POSITION 0x5 #define _RXM0EIDH_RXM0EID13_SIZE 0x1 #define _RXM0EIDH_RXM0EID13_LENGTH 0x1 #define _RXM0EIDH_RXM0EID13_MASK 0x20 #define _RXM0EIDH_RXM0EID14_POSN 0x6 #define _RXM0EIDH_RXM0EID14_POSITION 0x6 #define _RXM0EIDH_RXM0EID14_SIZE 0x1 #define _RXM0EIDH_RXM0EID14_LENGTH 0x1 #define _RXM0EIDH_RXM0EID14_MASK 0x40 #define _RXM0EIDH_RXM0EID15_POSN 0x7 #define _RXM0EIDH_RXM0EID15_POSITION 0x7 #define _RXM0EIDH_RXM0EID15_SIZE 0x1 #define _RXM0EIDH_RXM0EID15_LENGTH 0x1 #define _RXM0EIDH_RXM0EID15_MASK 0x80 // Register: RXM0EIDL #define RXM0EIDL RXM0EIDL extern volatile unsigned char RXM0EIDL @ 0xEFB; #ifndef _LIB_BUILD asm("RXM0EIDL equ 0EFBh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXM0EID0 :1; unsigned RXM0EID1 :1; unsigned RXM0EID2 :1; unsigned RXM0EID3 :1; unsigned RXM0EID4 :1; unsigned RXM0EID5 :1; unsigned RXM0EID6 :1; unsigned RXM0EID7 :1; }; } RXM0EIDLbits_t; extern volatile RXM0EIDLbits_t RXM0EIDLbits @ 0xEFB; // bitfield macros #define _RXM0EIDL_EID_POSN 0x0 #define _RXM0EIDL_EID_POSITION 0x0 #define _RXM0EIDL_EID_SIZE 0x8 #define _RXM0EIDL_EID_LENGTH 0x8 #define _RXM0EIDL_EID_MASK 0xFF #define _RXM0EIDL_EID0_POSN 0x0 #define _RXM0EIDL_EID0_POSITION 0x0 #define _RXM0EIDL_EID0_SIZE 0x1 #define _RXM0EIDL_EID0_LENGTH 0x1 #define _RXM0EIDL_EID0_MASK 0x1 #define _RXM0EIDL_EID1_POSN 0x1 #define _RXM0EIDL_EID1_POSITION 0x1 #define _RXM0EIDL_EID1_SIZE 0x1 #define _RXM0EIDL_EID1_LENGTH 0x1 #define _RXM0EIDL_EID1_MASK 0x2 #define _RXM0EIDL_EID2_POSN 0x2 #define _RXM0EIDL_EID2_POSITION 0x2 #define _RXM0EIDL_EID2_SIZE 0x1 #define _RXM0EIDL_EID2_LENGTH 0x1 #define _RXM0EIDL_EID2_MASK 0x4 #define _RXM0EIDL_EID3_POSN 0x3 #define _RXM0EIDL_EID3_POSITION 0x3 #define _RXM0EIDL_EID3_SIZE 0x1 #define _RXM0EIDL_EID3_LENGTH 0x1 #define _RXM0EIDL_EID3_MASK 0x8 #define _RXM0EIDL_EID4_POSN 0x4 #define _RXM0EIDL_EID4_POSITION 0x4 #define _RXM0EIDL_EID4_SIZE 0x1 #define _RXM0EIDL_EID4_LENGTH 0x1 #define _RXM0EIDL_EID4_MASK 0x10 #define _RXM0EIDL_EID5_POSN 0x5 #define _RXM0EIDL_EID5_POSITION 0x5 #define _RXM0EIDL_EID5_SIZE 0x1 #define _RXM0EIDL_EID5_LENGTH 0x1 #define _RXM0EIDL_EID5_MASK 0x20 #define _RXM0EIDL_EID6_POSN 0x6 #define _RXM0EIDL_EID6_POSITION 0x6 #define _RXM0EIDL_EID6_SIZE 0x1 #define _RXM0EIDL_EID6_LENGTH 0x1 #define _RXM0EIDL_EID6_MASK 0x40 #define _RXM0EIDL_EID7_POSN 0x7 #define _RXM0EIDL_EID7_POSITION 0x7 #define _RXM0EIDL_EID7_SIZE 0x1 #define _RXM0EIDL_EID7_LENGTH 0x1 #define _RXM0EIDL_EID7_MASK 0x80 #define _RXM0EIDL_RXM0EID0_POSN 0x0 #define _RXM0EIDL_RXM0EID0_POSITION 0x0 #define _RXM0EIDL_RXM0EID0_SIZE 0x1 #define _RXM0EIDL_RXM0EID0_LENGTH 0x1 #define _RXM0EIDL_RXM0EID0_MASK 0x1 #define _RXM0EIDL_RXM0EID1_POSN 0x1 #define _RXM0EIDL_RXM0EID1_POSITION 0x1 #define _RXM0EIDL_RXM0EID1_SIZE 0x1 #define _RXM0EIDL_RXM0EID1_LENGTH 0x1 #define _RXM0EIDL_RXM0EID1_MASK 0x2 #define _RXM0EIDL_RXM0EID2_POSN 0x2 #define _RXM0EIDL_RXM0EID2_POSITION 0x2 #define _RXM0EIDL_RXM0EID2_SIZE 0x1 #define _RXM0EIDL_RXM0EID2_LENGTH 0x1 #define _RXM0EIDL_RXM0EID2_MASK 0x4 #define _RXM0EIDL_RXM0EID3_POSN 0x3 #define _RXM0EIDL_RXM0EID3_POSITION 0x3 #define _RXM0EIDL_RXM0EID3_SIZE 0x1 #define _RXM0EIDL_RXM0EID3_LENGTH 0x1 #define _RXM0EIDL_RXM0EID3_MASK 0x8 #define _RXM0EIDL_RXM0EID4_POSN 0x4 #define _RXM0EIDL_RXM0EID4_POSITION 0x4 #define _RXM0EIDL_RXM0EID4_SIZE 0x1 #define _RXM0EIDL_RXM0EID4_LENGTH 0x1 #define _RXM0EIDL_RXM0EID4_MASK 0x10 #define _RXM0EIDL_RXM0EID5_POSN 0x5 #define _RXM0EIDL_RXM0EID5_POSITION 0x5 #define _RXM0EIDL_RXM0EID5_SIZE 0x1 #define _RXM0EIDL_RXM0EID5_LENGTH 0x1 #define _RXM0EIDL_RXM0EID5_MASK 0x20 #define _RXM0EIDL_RXM0EID6_POSN 0x6 #define _RXM0EIDL_RXM0EID6_POSITION 0x6 #define _RXM0EIDL_RXM0EID6_SIZE 0x1 #define _RXM0EIDL_RXM0EID6_LENGTH 0x1 #define _RXM0EIDL_RXM0EID6_MASK 0x40 #define _RXM0EIDL_RXM0EID7_POSN 0x7 #define _RXM0EIDL_RXM0EID7_POSITION 0x7 #define _RXM0EIDL_RXM0EID7_SIZE 0x1 #define _RXM0EIDL_RXM0EID7_LENGTH 0x1 #define _RXM0EIDL_RXM0EID7_MASK 0x80 // Register: RXM1SIDH #define RXM1SIDH RXM1SIDH extern volatile unsigned char RXM1SIDH @ 0xEFC; #ifndef _LIB_BUILD asm("RXM1SIDH equ 0EFCh"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXM1SID3 :1; unsigned RXM1SID4 :1; unsigned RXM1SID5 :1; unsigned RXM1SID6 :1; unsigned RXM1SID7 :1; unsigned RXM1SID8 :1; unsigned RXM1SID9 :1; unsigned RXM1SID10 :1; }; } RXM1SIDHbits_t; extern volatile RXM1SIDHbits_t RXM1SIDHbits @ 0xEFC; // bitfield macros #define _RXM1SIDH_SID_POSN 0x0 #define _RXM1SIDH_SID_POSITION 0x0 #define _RXM1SIDH_SID_SIZE 0x8 #define _RXM1SIDH_SID_LENGTH 0x8 #define _RXM1SIDH_SID_MASK 0xFF #define _RXM1SIDH_SID3_POSN 0x0 #define _RXM1SIDH_SID3_POSITION 0x0 #define _RXM1SIDH_SID3_SIZE 0x1 #define _RXM1SIDH_SID3_LENGTH 0x1 #define _RXM1SIDH_SID3_MASK 0x1 #define _RXM1SIDH_SID4_POSN 0x1 #define _RXM1SIDH_SID4_POSITION 0x1 #define _RXM1SIDH_SID4_SIZE 0x1 #define _RXM1SIDH_SID4_LENGTH 0x1 #define _RXM1SIDH_SID4_MASK 0x2 #define _RXM1SIDH_SID5_POSN 0x2 #define _RXM1SIDH_SID5_POSITION 0x2 #define _RXM1SIDH_SID5_SIZE 0x1 #define _RXM1SIDH_SID5_LENGTH 0x1 #define _RXM1SIDH_SID5_MASK 0x4 #define _RXM1SIDH_SID6_POSN 0x3 #define _RXM1SIDH_SID6_POSITION 0x3 #define _RXM1SIDH_SID6_SIZE 0x1 #define _RXM1SIDH_SID6_LENGTH 0x1 #define _RXM1SIDH_SID6_MASK 0x8 #define _RXM1SIDH_SID7_POSN 0x4 #define _RXM1SIDH_SID7_POSITION 0x4 #define _RXM1SIDH_SID7_SIZE 0x1 #define _RXM1SIDH_SID7_LENGTH 0x1 #define _RXM1SIDH_SID7_MASK 0x10 #define _RXM1SIDH_SID8_POSN 0x5 #define _RXM1SIDH_SID8_POSITION 0x5 #define _RXM1SIDH_SID8_SIZE 0x1 #define _RXM1SIDH_SID8_LENGTH 0x1 #define _RXM1SIDH_SID8_MASK 0x20 #define _RXM1SIDH_SID9_POSN 0x6 #define _RXM1SIDH_SID9_POSITION 0x6 #define _RXM1SIDH_SID9_SIZE 0x1 #define _RXM1SIDH_SID9_LENGTH 0x1 #define _RXM1SIDH_SID9_MASK 0x40 #define _RXM1SIDH_SID10_POSN 0x7 #define _RXM1SIDH_SID10_POSITION 0x7 #define _RXM1SIDH_SID10_SIZE 0x1 #define _RXM1SIDH_SID10_LENGTH 0x1 #define _RXM1SIDH_SID10_MASK 0x80 #define _RXM1SIDH_RXM1SID3_POSN 0x0 #define _RXM1SIDH_RXM1SID3_POSITION 0x0 #define _RXM1SIDH_RXM1SID3_SIZE 0x1 #define _RXM1SIDH_RXM1SID3_LENGTH 0x1 #define _RXM1SIDH_RXM1SID3_MASK 0x1 #define _RXM1SIDH_RXM1SID4_POSN 0x1 #define _RXM1SIDH_RXM1SID4_POSITION 0x1 #define _RXM1SIDH_RXM1SID4_SIZE 0x1 #define _RXM1SIDH_RXM1SID4_LENGTH 0x1 #define _RXM1SIDH_RXM1SID4_MASK 0x2 #define _RXM1SIDH_RXM1SID5_POSN 0x2 #define _RXM1SIDH_RXM1SID5_POSITION 0x2 #define _RXM1SIDH_RXM1SID5_SIZE 0x1 #define _RXM1SIDH_RXM1SID5_LENGTH 0x1 #define _RXM1SIDH_RXM1SID5_MASK 0x4 #define _RXM1SIDH_RXM1SID6_POSN 0x3 #define _RXM1SIDH_RXM1SID6_POSITION 0x3 #define _RXM1SIDH_RXM1SID6_SIZE 0x1 #define _RXM1SIDH_RXM1SID6_LENGTH 0x1 #define _RXM1SIDH_RXM1SID6_MASK 0x8 #define _RXM1SIDH_RXM1SID7_POSN 0x4 #define _RXM1SIDH_RXM1SID7_POSITION 0x4 #define _RXM1SIDH_RXM1SID7_SIZE 0x1 #define _RXM1SIDH_RXM1SID7_LENGTH 0x1 #define _RXM1SIDH_RXM1SID7_MASK 0x10 #define _RXM1SIDH_RXM1SID8_POSN 0x5 #define _RXM1SIDH_RXM1SID8_POSITION 0x5 #define _RXM1SIDH_RXM1SID8_SIZE 0x1 #define _RXM1SIDH_RXM1SID8_LENGTH 0x1 #define _RXM1SIDH_RXM1SID8_MASK 0x20 #define _RXM1SIDH_RXM1SID9_POSN 0x6 #define _RXM1SIDH_RXM1SID9_POSITION 0x6 #define _RXM1SIDH_RXM1SID9_SIZE 0x1 #define _RXM1SIDH_RXM1SID9_LENGTH 0x1 #define _RXM1SIDH_RXM1SID9_MASK 0x40 #define _RXM1SIDH_RXM1SID10_POSN 0x7 #define _RXM1SIDH_RXM1SID10_POSITION 0x7 #define _RXM1SIDH_RXM1SID10_SIZE 0x1 #define _RXM1SIDH_RXM1SID10_LENGTH 0x1 #define _RXM1SIDH_RXM1SID10_MASK 0x80 // Register: RXM1SIDL #define RXM1SIDL RXM1SIDL extern volatile unsigned char RXM1SIDL @ 0xEFD; #ifndef _LIB_BUILD asm("RXM1SIDL equ 0EFDh"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDEN :1; unsigned :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXM1EID16 :1; unsigned RXM1EID17 :1; unsigned :1; unsigned RXM1EXIDEN :1; unsigned :1; unsigned RXM1SID0 :1; unsigned RXM1SID1 :1; unsigned RXM1SID2 :1; }; } RXM1SIDLbits_t; extern volatile RXM1SIDLbits_t RXM1SIDLbits @ 0xEFD; // bitfield macros #define _RXM1SIDL_EID_POSN 0x0 #define _RXM1SIDL_EID_POSITION 0x0 #define _RXM1SIDL_EID_SIZE 0x2 #define _RXM1SIDL_EID_LENGTH 0x2 #define _RXM1SIDL_EID_MASK 0x3 #define _RXM1SIDL_EXIDEN_POSN 0x3 #define _RXM1SIDL_EXIDEN_POSITION 0x3 #define _RXM1SIDL_EXIDEN_SIZE 0x1 #define _RXM1SIDL_EXIDEN_LENGTH 0x1 #define _RXM1SIDL_EXIDEN_MASK 0x8 #define _RXM1SIDL_SID_POSN 0x5 #define _RXM1SIDL_SID_POSITION 0x5 #define _RXM1SIDL_SID_SIZE 0x3 #define _RXM1SIDL_SID_LENGTH 0x3 #define _RXM1SIDL_SID_MASK 0xE0 #define _RXM1SIDL_EID16_POSN 0x0 #define _RXM1SIDL_EID16_POSITION 0x0 #define _RXM1SIDL_EID16_SIZE 0x1 #define _RXM1SIDL_EID16_LENGTH 0x1 #define _RXM1SIDL_EID16_MASK 0x1 #define _RXM1SIDL_EID17_POSN 0x1 #define _RXM1SIDL_EID17_POSITION 0x1 #define _RXM1SIDL_EID17_SIZE 0x1 #define _RXM1SIDL_EID17_LENGTH 0x1 #define _RXM1SIDL_EID17_MASK 0x2 #define _RXM1SIDL_SID0_POSN 0x5 #define _RXM1SIDL_SID0_POSITION 0x5 #define _RXM1SIDL_SID0_SIZE 0x1 #define _RXM1SIDL_SID0_LENGTH 0x1 #define _RXM1SIDL_SID0_MASK 0x20 #define _RXM1SIDL_SID1_POSN 0x6 #define _RXM1SIDL_SID1_POSITION 0x6 #define _RXM1SIDL_SID1_SIZE 0x1 #define _RXM1SIDL_SID1_LENGTH 0x1 #define _RXM1SIDL_SID1_MASK 0x40 #define _RXM1SIDL_SID2_POSN 0x7 #define _RXM1SIDL_SID2_POSITION 0x7 #define _RXM1SIDL_SID2_SIZE 0x1 #define _RXM1SIDL_SID2_LENGTH 0x1 #define _RXM1SIDL_SID2_MASK 0x80 #define _RXM1SIDL_RXM1EID16_POSN 0x0 #define _RXM1SIDL_RXM1EID16_POSITION 0x0 #define _RXM1SIDL_RXM1EID16_SIZE 0x1 #define _RXM1SIDL_RXM1EID16_LENGTH 0x1 #define _RXM1SIDL_RXM1EID16_MASK 0x1 #define _RXM1SIDL_RXM1EID17_POSN 0x1 #define _RXM1SIDL_RXM1EID17_POSITION 0x1 #define _RXM1SIDL_RXM1EID17_SIZE 0x1 #define _RXM1SIDL_RXM1EID17_LENGTH 0x1 #define _RXM1SIDL_RXM1EID17_MASK 0x2 #define _RXM1SIDL_RXM1EXIDEN_POSN 0x3 #define _RXM1SIDL_RXM1EXIDEN_POSITION 0x3 #define _RXM1SIDL_RXM1EXIDEN_SIZE 0x1 #define _RXM1SIDL_RXM1EXIDEN_LENGTH 0x1 #define _RXM1SIDL_RXM1EXIDEN_MASK 0x8 #define _RXM1SIDL_RXM1SID0_POSN 0x5 #define _RXM1SIDL_RXM1SID0_POSITION 0x5 #define _RXM1SIDL_RXM1SID0_SIZE 0x1 #define _RXM1SIDL_RXM1SID0_LENGTH 0x1 #define _RXM1SIDL_RXM1SID0_MASK 0x20 #define _RXM1SIDL_RXM1SID1_POSN 0x6 #define _RXM1SIDL_RXM1SID1_POSITION 0x6 #define _RXM1SIDL_RXM1SID1_SIZE 0x1 #define _RXM1SIDL_RXM1SID1_LENGTH 0x1 #define _RXM1SIDL_RXM1SID1_MASK 0x40 #define _RXM1SIDL_RXM1SID2_POSN 0x7 #define _RXM1SIDL_RXM1SID2_POSITION 0x7 #define _RXM1SIDL_RXM1SID2_SIZE 0x1 #define _RXM1SIDL_RXM1SID2_LENGTH 0x1 #define _RXM1SIDL_RXM1SID2_MASK 0x80 // Register: RXM1EIDH #define RXM1EIDH RXM1EIDH extern volatile unsigned char RXM1EIDH @ 0xEFE; #ifndef _LIB_BUILD asm("RXM1EIDH equ 0EFEh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXM1EID8 :1; unsigned RXM1EID9 :1; unsigned RXM1EID10 :1; unsigned RXM1EID11 :1; unsigned RXM1EID12 :1; unsigned RXM1EID13 :1; unsigned RXM1EID14 :1; unsigned RXM1EID15 :1; }; } RXM1EIDHbits_t; extern volatile RXM1EIDHbits_t RXM1EIDHbits @ 0xEFE; // bitfield macros #define _RXM1EIDH_EID_POSN 0x0 #define _RXM1EIDH_EID_POSITION 0x0 #define _RXM1EIDH_EID_SIZE 0x8 #define _RXM1EIDH_EID_LENGTH 0x8 #define _RXM1EIDH_EID_MASK 0xFF #define _RXM1EIDH_EID8_POSN 0x0 #define _RXM1EIDH_EID8_POSITION 0x0 #define _RXM1EIDH_EID8_SIZE 0x1 #define _RXM1EIDH_EID8_LENGTH 0x1 #define _RXM1EIDH_EID8_MASK 0x1 #define _RXM1EIDH_EID9_POSN 0x1 #define _RXM1EIDH_EID9_POSITION 0x1 #define _RXM1EIDH_EID9_SIZE 0x1 #define _RXM1EIDH_EID9_LENGTH 0x1 #define _RXM1EIDH_EID9_MASK 0x2 #define _RXM1EIDH_EID10_POSN 0x2 #define _RXM1EIDH_EID10_POSITION 0x2 #define _RXM1EIDH_EID10_SIZE 0x1 #define _RXM1EIDH_EID10_LENGTH 0x1 #define _RXM1EIDH_EID10_MASK 0x4 #define _RXM1EIDH_EID11_POSN 0x3 #define _RXM1EIDH_EID11_POSITION 0x3 #define _RXM1EIDH_EID11_SIZE 0x1 #define _RXM1EIDH_EID11_LENGTH 0x1 #define _RXM1EIDH_EID11_MASK 0x8 #define _RXM1EIDH_EID12_POSN 0x4 #define _RXM1EIDH_EID12_POSITION 0x4 #define _RXM1EIDH_EID12_SIZE 0x1 #define _RXM1EIDH_EID12_LENGTH 0x1 #define _RXM1EIDH_EID12_MASK 0x10 #define _RXM1EIDH_EID13_POSN 0x5 #define _RXM1EIDH_EID13_POSITION 0x5 #define _RXM1EIDH_EID13_SIZE 0x1 #define _RXM1EIDH_EID13_LENGTH 0x1 #define _RXM1EIDH_EID13_MASK 0x20 #define _RXM1EIDH_EID14_POSN 0x6 #define _RXM1EIDH_EID14_POSITION 0x6 #define _RXM1EIDH_EID14_SIZE 0x1 #define _RXM1EIDH_EID14_LENGTH 0x1 #define _RXM1EIDH_EID14_MASK 0x40 #define _RXM1EIDH_EID15_POSN 0x7 #define _RXM1EIDH_EID15_POSITION 0x7 #define _RXM1EIDH_EID15_SIZE 0x1 #define _RXM1EIDH_EID15_LENGTH 0x1 #define _RXM1EIDH_EID15_MASK 0x80 #define _RXM1EIDH_RXM1EID8_POSN 0x0 #define _RXM1EIDH_RXM1EID8_POSITION 0x0 #define _RXM1EIDH_RXM1EID8_SIZE 0x1 #define _RXM1EIDH_RXM1EID8_LENGTH 0x1 #define _RXM1EIDH_RXM1EID8_MASK 0x1 #define _RXM1EIDH_RXM1EID9_POSN 0x1 #define _RXM1EIDH_RXM1EID9_POSITION 0x1 #define _RXM1EIDH_RXM1EID9_SIZE 0x1 #define _RXM1EIDH_RXM1EID9_LENGTH 0x1 #define _RXM1EIDH_RXM1EID9_MASK 0x2 #define _RXM1EIDH_RXM1EID10_POSN 0x2 #define _RXM1EIDH_RXM1EID10_POSITION 0x2 #define _RXM1EIDH_RXM1EID10_SIZE 0x1 #define _RXM1EIDH_RXM1EID10_LENGTH 0x1 #define _RXM1EIDH_RXM1EID10_MASK 0x4 #define _RXM1EIDH_RXM1EID11_POSN 0x3 #define _RXM1EIDH_RXM1EID11_POSITION 0x3 #define _RXM1EIDH_RXM1EID11_SIZE 0x1 #define _RXM1EIDH_RXM1EID11_LENGTH 0x1 #define _RXM1EIDH_RXM1EID11_MASK 0x8 #define _RXM1EIDH_RXM1EID12_POSN 0x4 #define _RXM1EIDH_RXM1EID12_POSITION 0x4 #define _RXM1EIDH_RXM1EID12_SIZE 0x1 #define _RXM1EIDH_RXM1EID12_LENGTH 0x1 #define _RXM1EIDH_RXM1EID12_MASK 0x10 #define _RXM1EIDH_RXM1EID13_POSN 0x5 #define _RXM1EIDH_RXM1EID13_POSITION 0x5 #define _RXM1EIDH_RXM1EID13_SIZE 0x1 #define _RXM1EIDH_RXM1EID13_LENGTH 0x1 #define _RXM1EIDH_RXM1EID13_MASK 0x20 #define _RXM1EIDH_RXM1EID14_POSN 0x6 #define _RXM1EIDH_RXM1EID14_POSITION 0x6 #define _RXM1EIDH_RXM1EID14_SIZE 0x1 #define _RXM1EIDH_RXM1EID14_LENGTH 0x1 #define _RXM1EIDH_RXM1EID14_MASK 0x40 #define _RXM1EIDH_RXM1EID15_POSN 0x7 #define _RXM1EIDH_RXM1EID15_POSITION 0x7 #define _RXM1EIDH_RXM1EID15_SIZE 0x1 #define _RXM1EIDH_RXM1EID15_LENGTH 0x1 #define _RXM1EIDH_RXM1EID15_MASK 0x80 // Register: RXM1EIDL #define RXM1EIDL RXM1EIDL extern volatile unsigned char RXM1EIDL @ 0xEFF; #ifndef _LIB_BUILD asm("RXM1EIDL equ 0EFFh"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXM1EID0 :1; unsigned RXM1EID1 :1; unsigned RXM1EID2 :1; unsigned RXM1EID3 :1; unsigned RXM1EID4 :1; unsigned RXM1EID5 :1; unsigned RXM1EID6 :1; unsigned RXM1EID7 :1; }; } RXM1EIDLbits_t; extern volatile RXM1EIDLbits_t RXM1EIDLbits @ 0xEFF; // bitfield macros #define _RXM1EIDL_EID_POSN 0x0 #define _RXM1EIDL_EID_POSITION 0x0 #define _RXM1EIDL_EID_SIZE 0x8 #define _RXM1EIDL_EID_LENGTH 0x8 #define _RXM1EIDL_EID_MASK 0xFF #define _RXM1EIDL_EID0_POSN 0x0 #define _RXM1EIDL_EID0_POSITION 0x0 #define _RXM1EIDL_EID0_SIZE 0x1 #define _RXM1EIDL_EID0_LENGTH 0x1 #define _RXM1EIDL_EID0_MASK 0x1 #define _RXM1EIDL_EID1_POSN 0x1 #define _RXM1EIDL_EID1_POSITION 0x1 #define _RXM1EIDL_EID1_SIZE 0x1 #define _RXM1EIDL_EID1_LENGTH 0x1 #define _RXM1EIDL_EID1_MASK 0x2 #define _RXM1EIDL_EID2_POSN 0x2 #define _RXM1EIDL_EID2_POSITION 0x2 #define _RXM1EIDL_EID2_SIZE 0x1 #define _RXM1EIDL_EID2_LENGTH 0x1 #define _RXM1EIDL_EID2_MASK 0x4 #define _RXM1EIDL_EID3_POSN 0x3 #define _RXM1EIDL_EID3_POSITION 0x3 #define _RXM1EIDL_EID3_SIZE 0x1 #define _RXM1EIDL_EID3_LENGTH 0x1 #define _RXM1EIDL_EID3_MASK 0x8 #define _RXM1EIDL_EID4_POSN 0x4 #define _RXM1EIDL_EID4_POSITION 0x4 #define _RXM1EIDL_EID4_SIZE 0x1 #define _RXM1EIDL_EID4_LENGTH 0x1 #define _RXM1EIDL_EID4_MASK 0x10 #define _RXM1EIDL_EID5_POSN 0x5 #define _RXM1EIDL_EID5_POSITION 0x5 #define _RXM1EIDL_EID5_SIZE 0x1 #define _RXM1EIDL_EID5_LENGTH 0x1 #define _RXM1EIDL_EID5_MASK 0x20 #define _RXM1EIDL_EID6_POSN 0x6 #define _RXM1EIDL_EID6_POSITION 0x6 #define _RXM1EIDL_EID6_SIZE 0x1 #define _RXM1EIDL_EID6_LENGTH 0x1 #define _RXM1EIDL_EID6_MASK 0x40 #define _RXM1EIDL_EID7_POSN 0x7 #define _RXM1EIDL_EID7_POSITION 0x7 #define _RXM1EIDL_EID7_SIZE 0x1 #define _RXM1EIDL_EID7_LENGTH 0x1 #define _RXM1EIDL_EID7_MASK 0x80 #define _RXM1EIDL_RXM1EID0_POSN 0x0 #define _RXM1EIDL_RXM1EID0_POSITION 0x0 #define _RXM1EIDL_RXM1EID0_SIZE 0x1 #define _RXM1EIDL_RXM1EID0_LENGTH 0x1 #define _RXM1EIDL_RXM1EID0_MASK 0x1 #define _RXM1EIDL_RXM1EID1_POSN 0x1 #define _RXM1EIDL_RXM1EID1_POSITION 0x1 #define _RXM1EIDL_RXM1EID1_SIZE 0x1 #define _RXM1EIDL_RXM1EID1_LENGTH 0x1 #define _RXM1EIDL_RXM1EID1_MASK 0x2 #define _RXM1EIDL_RXM1EID2_POSN 0x2 #define _RXM1EIDL_RXM1EID2_POSITION 0x2 #define _RXM1EIDL_RXM1EID2_SIZE 0x1 #define _RXM1EIDL_RXM1EID2_LENGTH 0x1 #define _RXM1EIDL_RXM1EID2_MASK 0x4 #define _RXM1EIDL_RXM1EID3_POSN 0x3 #define _RXM1EIDL_RXM1EID3_POSITION 0x3 #define _RXM1EIDL_RXM1EID3_SIZE 0x1 #define _RXM1EIDL_RXM1EID3_LENGTH 0x1 #define _RXM1EIDL_RXM1EID3_MASK 0x8 #define _RXM1EIDL_RXM1EID4_POSN 0x4 #define _RXM1EIDL_RXM1EID4_POSITION 0x4 #define _RXM1EIDL_RXM1EID4_SIZE 0x1 #define _RXM1EIDL_RXM1EID4_LENGTH 0x1 #define _RXM1EIDL_RXM1EID4_MASK 0x10 #define _RXM1EIDL_RXM1EID5_POSN 0x5 #define _RXM1EIDL_RXM1EID5_POSITION 0x5 #define _RXM1EIDL_RXM1EID5_SIZE 0x1 #define _RXM1EIDL_RXM1EID5_LENGTH 0x1 #define _RXM1EIDL_RXM1EID5_MASK 0x20 #define _RXM1EIDL_RXM1EID6_POSN 0x6 #define _RXM1EIDL_RXM1EID6_POSITION 0x6 #define _RXM1EIDL_RXM1EID6_SIZE 0x1 #define _RXM1EIDL_RXM1EID6_LENGTH 0x1 #define _RXM1EIDL_RXM1EID6_MASK 0x40 #define _RXM1EIDL_RXM1EID7_POSN 0x7 #define _RXM1EIDL_RXM1EID7_POSITION 0x7 #define _RXM1EIDL_RXM1EID7_SIZE 0x1 #define _RXM1EIDL_RXM1EID7_LENGTH 0x1 #define _RXM1EIDL_RXM1EID7_MASK 0x80 // Register: TXB2CON #define TXB2CON TXB2CON extern volatile unsigned char TXB2CON @ 0xF00; #ifndef _LIB_BUILD asm("TXB2CON equ 0F00h"); #endif // bitfield definitions typedef union { struct { unsigned TXPRI :2; unsigned :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; }; struct { unsigned TXB2PRI0 :1; unsigned TXB2PRI1 :1; unsigned :1; unsigned TXB2REQ :1; unsigned TXB2ERR :1; unsigned TXB2LARB :1; unsigned TXB2ABT :1; unsigned TX2IF :1; }; } TXB2CONbits_t; extern volatile TXB2CONbits_t TXB2CONbits @ 0xF00; // bitfield macros #define _TXB2CON_TXPRI_POSN 0x0 #define _TXB2CON_TXPRI_POSITION 0x0 #define _TXB2CON_TXPRI_SIZE 0x2 #define _TXB2CON_TXPRI_LENGTH 0x2 #define _TXB2CON_TXPRI_MASK 0x3 #define _TXB2CON_TXREQ_POSN 0x3 #define _TXB2CON_TXREQ_POSITION 0x3 #define _TXB2CON_TXREQ_SIZE 0x1 #define _TXB2CON_TXREQ_LENGTH 0x1 #define _TXB2CON_TXREQ_MASK 0x8 #define _TXB2CON_TXERR_POSN 0x4 #define _TXB2CON_TXERR_POSITION 0x4 #define _TXB2CON_TXERR_SIZE 0x1 #define _TXB2CON_TXERR_LENGTH 0x1 #define _TXB2CON_TXERR_MASK 0x10 #define _TXB2CON_TXLARB_POSN 0x5 #define _TXB2CON_TXLARB_POSITION 0x5 #define _TXB2CON_TXLARB_SIZE 0x1 #define _TXB2CON_TXLARB_LENGTH 0x1 #define _TXB2CON_TXLARB_MASK 0x20 #define _TXB2CON_TXABT_POSN 0x6 #define _TXB2CON_TXABT_POSITION 0x6 #define _TXB2CON_TXABT_SIZE 0x1 #define _TXB2CON_TXABT_LENGTH 0x1 #define _TXB2CON_TXABT_MASK 0x40 #define _TXB2CON_TXBIF_POSN 0x7 #define _TXB2CON_TXBIF_POSITION 0x7 #define _TXB2CON_TXBIF_SIZE 0x1 #define _TXB2CON_TXBIF_LENGTH 0x1 #define _TXB2CON_TXBIF_MASK 0x80 #define _TXB2CON_TXPRI0_POSN 0x0 #define _TXB2CON_TXPRI0_POSITION 0x0 #define _TXB2CON_TXPRI0_SIZE 0x1 #define _TXB2CON_TXPRI0_LENGTH 0x1 #define _TXB2CON_TXPRI0_MASK 0x1 #define _TXB2CON_TXPRI1_POSN 0x1 #define _TXB2CON_TXPRI1_POSITION 0x1 #define _TXB2CON_TXPRI1_SIZE 0x1 #define _TXB2CON_TXPRI1_LENGTH 0x1 #define _TXB2CON_TXPRI1_MASK 0x2 #define _TXB2CON_TXB2PRI0_POSN 0x0 #define _TXB2CON_TXB2PRI0_POSITION 0x0 #define _TXB2CON_TXB2PRI0_SIZE 0x1 #define _TXB2CON_TXB2PRI0_LENGTH 0x1 #define _TXB2CON_TXB2PRI0_MASK 0x1 #define _TXB2CON_TXB2PRI1_POSN 0x1 #define _TXB2CON_TXB2PRI1_POSITION 0x1 #define _TXB2CON_TXB2PRI1_SIZE 0x1 #define _TXB2CON_TXB2PRI1_LENGTH 0x1 #define _TXB2CON_TXB2PRI1_MASK 0x2 #define _TXB2CON_TXB2REQ_POSN 0x3 #define _TXB2CON_TXB2REQ_POSITION 0x3 #define _TXB2CON_TXB2REQ_SIZE 0x1 #define _TXB2CON_TXB2REQ_LENGTH 0x1 #define _TXB2CON_TXB2REQ_MASK 0x8 #define _TXB2CON_TXB2ERR_POSN 0x4 #define _TXB2CON_TXB2ERR_POSITION 0x4 #define _TXB2CON_TXB2ERR_SIZE 0x1 #define _TXB2CON_TXB2ERR_LENGTH 0x1 #define _TXB2CON_TXB2ERR_MASK 0x10 #define _TXB2CON_TXB2LARB_POSN 0x5 #define _TXB2CON_TXB2LARB_POSITION 0x5 #define _TXB2CON_TXB2LARB_SIZE 0x1 #define _TXB2CON_TXB2LARB_LENGTH 0x1 #define _TXB2CON_TXB2LARB_MASK 0x20 #define _TXB2CON_TXB2ABT_POSN 0x6 #define _TXB2CON_TXB2ABT_POSITION 0x6 #define _TXB2CON_TXB2ABT_SIZE 0x1 #define _TXB2CON_TXB2ABT_LENGTH 0x1 #define _TXB2CON_TXB2ABT_MASK 0x40 #define _TXB2CON_TX2IF_POSN 0x7 #define _TXB2CON_TX2IF_POSITION 0x7 #define _TXB2CON_TX2IF_SIZE 0x1 #define _TXB2CON_TX2IF_LENGTH 0x1 #define _TXB2CON_TX2IF_MASK 0x80 // Register: TXB2SIDH #define TXB2SIDH TXB2SIDH extern volatile unsigned char TXB2SIDH @ 0xF01; #ifndef _LIB_BUILD asm("TXB2SIDH equ 0F01h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned TXB2SID3 :1; unsigned TXB2SID4 :1; unsigned TXB2SID5 :1; unsigned TXB2SID6 :1; unsigned TXB2SID7 :1; unsigned TXB2SID8 :1; unsigned TXB2SID9 :1; unsigned TXB2SID10 :1; }; } TXB2SIDHbits_t; extern volatile TXB2SIDHbits_t TXB2SIDHbits @ 0xF01; // bitfield macros #define _TXB2SIDH_SID_POSN 0x0 #define _TXB2SIDH_SID_POSITION 0x0 #define _TXB2SIDH_SID_SIZE 0x8 #define _TXB2SIDH_SID_LENGTH 0x8 #define _TXB2SIDH_SID_MASK 0xFF #define _TXB2SIDH_SID3_POSN 0x0 #define _TXB2SIDH_SID3_POSITION 0x0 #define _TXB2SIDH_SID3_SIZE 0x1 #define _TXB2SIDH_SID3_LENGTH 0x1 #define _TXB2SIDH_SID3_MASK 0x1 #define _TXB2SIDH_SID4_POSN 0x1 #define _TXB2SIDH_SID4_POSITION 0x1 #define _TXB2SIDH_SID4_SIZE 0x1 #define _TXB2SIDH_SID4_LENGTH 0x1 #define _TXB2SIDH_SID4_MASK 0x2 #define _TXB2SIDH_SID5_POSN 0x2 #define _TXB2SIDH_SID5_POSITION 0x2 #define _TXB2SIDH_SID5_SIZE 0x1 #define _TXB2SIDH_SID5_LENGTH 0x1 #define _TXB2SIDH_SID5_MASK 0x4 #define _TXB2SIDH_SID6_POSN 0x3 #define _TXB2SIDH_SID6_POSITION 0x3 #define _TXB2SIDH_SID6_SIZE 0x1 #define _TXB2SIDH_SID6_LENGTH 0x1 #define _TXB2SIDH_SID6_MASK 0x8 #define _TXB2SIDH_SID7_POSN 0x4 #define _TXB2SIDH_SID7_POSITION 0x4 #define _TXB2SIDH_SID7_SIZE 0x1 #define _TXB2SIDH_SID7_LENGTH 0x1 #define _TXB2SIDH_SID7_MASK 0x10 #define _TXB2SIDH_SID8_POSN 0x5 #define _TXB2SIDH_SID8_POSITION 0x5 #define _TXB2SIDH_SID8_SIZE 0x1 #define _TXB2SIDH_SID8_LENGTH 0x1 #define _TXB2SIDH_SID8_MASK 0x20 #define _TXB2SIDH_SID9_POSN 0x6 #define _TXB2SIDH_SID9_POSITION 0x6 #define _TXB2SIDH_SID9_SIZE 0x1 #define _TXB2SIDH_SID9_LENGTH 0x1 #define _TXB2SIDH_SID9_MASK 0x40 #define _TXB2SIDH_SID10_POSN 0x7 #define _TXB2SIDH_SID10_POSITION 0x7 #define _TXB2SIDH_SID10_SIZE 0x1 #define _TXB2SIDH_SID10_LENGTH 0x1 #define _TXB2SIDH_SID10_MASK 0x80 #define _TXB2SIDH_TXB2SID3_POSN 0x0 #define _TXB2SIDH_TXB2SID3_POSITION 0x0 #define _TXB2SIDH_TXB2SID3_SIZE 0x1 #define _TXB2SIDH_TXB2SID3_LENGTH 0x1 #define _TXB2SIDH_TXB2SID3_MASK 0x1 #define _TXB2SIDH_TXB2SID4_POSN 0x1 #define _TXB2SIDH_TXB2SID4_POSITION 0x1 #define _TXB2SIDH_TXB2SID4_SIZE 0x1 #define _TXB2SIDH_TXB2SID4_LENGTH 0x1 #define _TXB2SIDH_TXB2SID4_MASK 0x2 #define _TXB2SIDH_TXB2SID5_POSN 0x2 #define _TXB2SIDH_TXB2SID5_POSITION 0x2 #define _TXB2SIDH_TXB2SID5_SIZE 0x1 #define _TXB2SIDH_TXB2SID5_LENGTH 0x1 #define _TXB2SIDH_TXB2SID5_MASK 0x4 #define _TXB2SIDH_TXB2SID6_POSN 0x3 #define _TXB2SIDH_TXB2SID6_POSITION 0x3 #define _TXB2SIDH_TXB2SID6_SIZE 0x1 #define _TXB2SIDH_TXB2SID6_LENGTH 0x1 #define _TXB2SIDH_TXB2SID6_MASK 0x8 #define _TXB2SIDH_TXB2SID7_POSN 0x4 #define _TXB2SIDH_TXB2SID7_POSITION 0x4 #define _TXB2SIDH_TXB2SID7_SIZE 0x1 #define _TXB2SIDH_TXB2SID7_LENGTH 0x1 #define _TXB2SIDH_TXB2SID7_MASK 0x10 #define _TXB2SIDH_TXB2SID8_POSN 0x5 #define _TXB2SIDH_TXB2SID8_POSITION 0x5 #define _TXB2SIDH_TXB2SID8_SIZE 0x1 #define _TXB2SIDH_TXB2SID8_LENGTH 0x1 #define _TXB2SIDH_TXB2SID8_MASK 0x20 #define _TXB2SIDH_TXB2SID9_POSN 0x6 #define _TXB2SIDH_TXB2SID9_POSITION 0x6 #define _TXB2SIDH_TXB2SID9_SIZE 0x1 #define _TXB2SIDH_TXB2SID9_LENGTH 0x1 #define _TXB2SIDH_TXB2SID9_MASK 0x40 #define _TXB2SIDH_TXB2SID10_POSN 0x7 #define _TXB2SIDH_TXB2SID10_POSITION 0x7 #define _TXB2SIDH_TXB2SID10_SIZE 0x1 #define _TXB2SIDH_TXB2SID10_LENGTH 0x1 #define _TXB2SIDH_TXB2SID10_MASK 0x80 // Register: TXB2SIDL #define TXB2SIDL TXB2SIDL extern volatile unsigned char TXB2SIDL @ 0xF02; #ifndef _LIB_BUILD asm("TXB2SIDL equ 0F02h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned TXB2EID16 :1; unsigned TXB2EID17 :1; unsigned :1; unsigned TXB2EXIDE :1; unsigned :1; unsigned TXB2SID0 :1; unsigned TXB2SID1 :1; unsigned TXB2SID2 :1; }; } TXB2SIDLbits_t; extern volatile TXB2SIDLbits_t TXB2SIDLbits @ 0xF02; // bitfield macros #define _TXB2SIDL_EID_POSN 0x0 #define _TXB2SIDL_EID_POSITION 0x0 #define _TXB2SIDL_EID_SIZE 0x2 #define _TXB2SIDL_EID_LENGTH 0x2 #define _TXB2SIDL_EID_MASK 0x3 #define _TXB2SIDL_EXIDE_POSN 0x3 #define _TXB2SIDL_EXIDE_POSITION 0x3 #define _TXB2SIDL_EXIDE_SIZE 0x1 #define _TXB2SIDL_EXIDE_LENGTH 0x1 #define _TXB2SIDL_EXIDE_MASK 0x8 #define _TXB2SIDL_SRR_POSN 0x4 #define _TXB2SIDL_SRR_POSITION 0x4 #define _TXB2SIDL_SRR_SIZE 0x1 #define _TXB2SIDL_SRR_LENGTH 0x1 #define _TXB2SIDL_SRR_MASK 0x10 #define _TXB2SIDL_SID_POSN 0x5 #define _TXB2SIDL_SID_POSITION 0x5 #define _TXB2SIDL_SID_SIZE 0x3 #define _TXB2SIDL_SID_LENGTH 0x3 #define _TXB2SIDL_SID_MASK 0xE0 #define _TXB2SIDL_EID16_POSN 0x0 #define _TXB2SIDL_EID16_POSITION 0x0 #define _TXB2SIDL_EID16_SIZE 0x1 #define _TXB2SIDL_EID16_LENGTH 0x1 #define _TXB2SIDL_EID16_MASK 0x1 #define _TXB2SIDL_EID17_POSN 0x1 #define _TXB2SIDL_EID17_POSITION 0x1 #define _TXB2SIDL_EID17_SIZE 0x1 #define _TXB2SIDL_EID17_LENGTH 0x1 #define _TXB2SIDL_EID17_MASK 0x2 #define _TXB2SIDL_SID0_POSN 0x5 #define _TXB2SIDL_SID0_POSITION 0x5 #define _TXB2SIDL_SID0_SIZE 0x1 #define _TXB2SIDL_SID0_LENGTH 0x1 #define _TXB2SIDL_SID0_MASK 0x20 #define _TXB2SIDL_SID1_POSN 0x6 #define _TXB2SIDL_SID1_POSITION 0x6 #define _TXB2SIDL_SID1_SIZE 0x1 #define _TXB2SIDL_SID1_LENGTH 0x1 #define _TXB2SIDL_SID1_MASK 0x40 #define _TXB2SIDL_SID2_POSN 0x7 #define _TXB2SIDL_SID2_POSITION 0x7 #define _TXB2SIDL_SID2_SIZE 0x1 #define _TXB2SIDL_SID2_LENGTH 0x1 #define _TXB2SIDL_SID2_MASK 0x80 #define _TXB2SIDL_TXB2EID16_POSN 0x0 #define _TXB2SIDL_TXB2EID16_POSITION 0x0 #define _TXB2SIDL_TXB2EID16_SIZE 0x1 #define _TXB2SIDL_TXB2EID16_LENGTH 0x1 #define _TXB2SIDL_TXB2EID16_MASK 0x1 #define _TXB2SIDL_TXB2EID17_POSN 0x1 #define _TXB2SIDL_TXB2EID17_POSITION 0x1 #define _TXB2SIDL_TXB2EID17_SIZE 0x1 #define _TXB2SIDL_TXB2EID17_LENGTH 0x1 #define _TXB2SIDL_TXB2EID17_MASK 0x2 #define _TXB2SIDL_TXB2EXIDE_POSN 0x3 #define _TXB2SIDL_TXB2EXIDE_POSITION 0x3 #define _TXB2SIDL_TXB2EXIDE_SIZE 0x1 #define _TXB2SIDL_TXB2EXIDE_LENGTH 0x1 #define _TXB2SIDL_TXB2EXIDE_MASK 0x8 #define _TXB2SIDL_TXB2SID0_POSN 0x5 #define _TXB2SIDL_TXB2SID0_POSITION 0x5 #define _TXB2SIDL_TXB2SID0_SIZE 0x1 #define _TXB2SIDL_TXB2SID0_LENGTH 0x1 #define _TXB2SIDL_TXB2SID0_MASK 0x20 #define _TXB2SIDL_TXB2SID1_POSN 0x6 #define _TXB2SIDL_TXB2SID1_POSITION 0x6 #define _TXB2SIDL_TXB2SID1_SIZE 0x1 #define _TXB2SIDL_TXB2SID1_LENGTH 0x1 #define _TXB2SIDL_TXB2SID1_MASK 0x40 #define _TXB2SIDL_TXB2SID2_POSN 0x7 #define _TXB2SIDL_TXB2SID2_POSITION 0x7 #define _TXB2SIDL_TXB2SID2_SIZE 0x1 #define _TXB2SIDL_TXB2SID2_LENGTH 0x1 #define _TXB2SIDL_TXB2SID2_MASK 0x80 // Register: TXB2EIDH #define TXB2EIDH TXB2EIDH extern volatile unsigned char TXB2EIDH @ 0xF03; #ifndef _LIB_BUILD asm("TXB2EIDH equ 0F03h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned TXB2EID8 :1; unsigned TXB2EID9 :1; unsigned TXB2EID10 :1; unsigned TXB2EID11 :1; unsigned TXB2EID12 :1; unsigned TXB2EID13 :1; unsigned TXB2EID14 :1; unsigned TXB2EID15 :1; }; } TXB2EIDHbits_t; extern volatile TXB2EIDHbits_t TXB2EIDHbits @ 0xF03; // bitfield macros #define _TXB2EIDH_EID_POSN 0x0 #define _TXB2EIDH_EID_POSITION 0x0 #define _TXB2EIDH_EID_SIZE 0x8 #define _TXB2EIDH_EID_LENGTH 0x8 #define _TXB2EIDH_EID_MASK 0xFF #define _TXB2EIDH_EID8_POSN 0x0 #define _TXB2EIDH_EID8_POSITION 0x0 #define _TXB2EIDH_EID8_SIZE 0x1 #define _TXB2EIDH_EID8_LENGTH 0x1 #define _TXB2EIDH_EID8_MASK 0x1 #define _TXB2EIDH_EID9_POSN 0x1 #define _TXB2EIDH_EID9_POSITION 0x1 #define _TXB2EIDH_EID9_SIZE 0x1 #define _TXB2EIDH_EID9_LENGTH 0x1 #define _TXB2EIDH_EID9_MASK 0x2 #define _TXB2EIDH_EID10_POSN 0x2 #define _TXB2EIDH_EID10_POSITION 0x2 #define _TXB2EIDH_EID10_SIZE 0x1 #define _TXB2EIDH_EID10_LENGTH 0x1 #define _TXB2EIDH_EID10_MASK 0x4 #define _TXB2EIDH_EID11_POSN 0x3 #define _TXB2EIDH_EID11_POSITION 0x3 #define _TXB2EIDH_EID11_SIZE 0x1 #define _TXB2EIDH_EID11_LENGTH 0x1 #define _TXB2EIDH_EID11_MASK 0x8 #define _TXB2EIDH_EID12_POSN 0x4 #define _TXB2EIDH_EID12_POSITION 0x4 #define _TXB2EIDH_EID12_SIZE 0x1 #define _TXB2EIDH_EID12_LENGTH 0x1 #define _TXB2EIDH_EID12_MASK 0x10 #define _TXB2EIDH_EID13_POSN 0x5 #define _TXB2EIDH_EID13_POSITION 0x5 #define _TXB2EIDH_EID13_SIZE 0x1 #define _TXB2EIDH_EID13_LENGTH 0x1 #define _TXB2EIDH_EID13_MASK 0x20 #define _TXB2EIDH_EID14_POSN 0x6 #define _TXB2EIDH_EID14_POSITION 0x6 #define _TXB2EIDH_EID14_SIZE 0x1 #define _TXB2EIDH_EID14_LENGTH 0x1 #define _TXB2EIDH_EID14_MASK 0x40 #define _TXB2EIDH_EID15_POSN 0x7 #define _TXB2EIDH_EID15_POSITION 0x7 #define _TXB2EIDH_EID15_SIZE 0x1 #define _TXB2EIDH_EID15_LENGTH 0x1 #define _TXB2EIDH_EID15_MASK 0x80 #define _TXB2EIDH_TXB2EID8_POSN 0x0 #define _TXB2EIDH_TXB2EID8_POSITION 0x0 #define _TXB2EIDH_TXB2EID8_SIZE 0x1 #define _TXB2EIDH_TXB2EID8_LENGTH 0x1 #define _TXB2EIDH_TXB2EID8_MASK 0x1 #define _TXB2EIDH_TXB2EID9_POSN 0x1 #define _TXB2EIDH_TXB2EID9_POSITION 0x1 #define _TXB2EIDH_TXB2EID9_SIZE 0x1 #define _TXB2EIDH_TXB2EID9_LENGTH 0x1 #define _TXB2EIDH_TXB2EID9_MASK 0x2 #define _TXB2EIDH_TXB2EID10_POSN 0x2 #define _TXB2EIDH_TXB2EID10_POSITION 0x2 #define _TXB2EIDH_TXB2EID10_SIZE 0x1 #define _TXB2EIDH_TXB2EID10_LENGTH 0x1 #define _TXB2EIDH_TXB2EID10_MASK 0x4 #define _TXB2EIDH_TXB2EID11_POSN 0x3 #define _TXB2EIDH_TXB2EID11_POSITION 0x3 #define _TXB2EIDH_TXB2EID11_SIZE 0x1 #define _TXB2EIDH_TXB2EID11_LENGTH 0x1 #define _TXB2EIDH_TXB2EID11_MASK 0x8 #define _TXB2EIDH_TXB2EID12_POSN 0x4 #define _TXB2EIDH_TXB2EID12_POSITION 0x4 #define _TXB2EIDH_TXB2EID12_SIZE 0x1 #define _TXB2EIDH_TXB2EID12_LENGTH 0x1 #define _TXB2EIDH_TXB2EID12_MASK 0x10 #define _TXB2EIDH_TXB2EID13_POSN 0x5 #define _TXB2EIDH_TXB2EID13_POSITION 0x5 #define _TXB2EIDH_TXB2EID13_SIZE 0x1 #define _TXB2EIDH_TXB2EID13_LENGTH 0x1 #define _TXB2EIDH_TXB2EID13_MASK 0x20 #define _TXB2EIDH_TXB2EID14_POSN 0x6 #define _TXB2EIDH_TXB2EID14_POSITION 0x6 #define _TXB2EIDH_TXB2EID14_SIZE 0x1 #define _TXB2EIDH_TXB2EID14_LENGTH 0x1 #define _TXB2EIDH_TXB2EID14_MASK 0x40 #define _TXB2EIDH_TXB2EID15_POSN 0x7 #define _TXB2EIDH_TXB2EID15_POSITION 0x7 #define _TXB2EIDH_TXB2EID15_SIZE 0x1 #define _TXB2EIDH_TXB2EID15_LENGTH 0x1 #define _TXB2EIDH_TXB2EID15_MASK 0x80 // Register: TXB2EIDL #define TXB2EIDL TXB2EIDL extern volatile unsigned char TXB2EIDL @ 0xF04; #ifndef _LIB_BUILD asm("TXB2EIDL equ 0F04h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned TXB2EID0 :1; unsigned TXB2EID1 :1; unsigned TXB2EID2 :1; unsigned TXB2EID3 :1; unsigned TXB2EID4 :1; unsigned TXB2EID5 :1; unsigned TXB2EID6 :1; unsigned TXB2EID7 :1; }; } TXB2EIDLbits_t; extern volatile TXB2EIDLbits_t TXB2EIDLbits @ 0xF04; // bitfield macros #define _TXB2EIDL_EID_POSN 0x0 #define _TXB2EIDL_EID_POSITION 0x0 #define _TXB2EIDL_EID_SIZE 0x8 #define _TXB2EIDL_EID_LENGTH 0x8 #define _TXB2EIDL_EID_MASK 0xFF #define _TXB2EIDL_EID0_POSN 0x0 #define _TXB2EIDL_EID0_POSITION 0x0 #define _TXB2EIDL_EID0_SIZE 0x1 #define _TXB2EIDL_EID0_LENGTH 0x1 #define _TXB2EIDL_EID0_MASK 0x1 #define _TXB2EIDL_EID1_POSN 0x1 #define _TXB2EIDL_EID1_POSITION 0x1 #define _TXB2EIDL_EID1_SIZE 0x1 #define _TXB2EIDL_EID1_LENGTH 0x1 #define _TXB2EIDL_EID1_MASK 0x2 #define _TXB2EIDL_EID2_POSN 0x2 #define _TXB2EIDL_EID2_POSITION 0x2 #define _TXB2EIDL_EID2_SIZE 0x1 #define _TXB2EIDL_EID2_LENGTH 0x1 #define _TXB2EIDL_EID2_MASK 0x4 #define _TXB2EIDL_EID3_POSN 0x3 #define _TXB2EIDL_EID3_POSITION 0x3 #define _TXB2EIDL_EID3_SIZE 0x1 #define _TXB2EIDL_EID3_LENGTH 0x1 #define _TXB2EIDL_EID3_MASK 0x8 #define _TXB2EIDL_EID4_POSN 0x4 #define _TXB2EIDL_EID4_POSITION 0x4 #define _TXB2EIDL_EID4_SIZE 0x1 #define _TXB2EIDL_EID4_LENGTH 0x1 #define _TXB2EIDL_EID4_MASK 0x10 #define _TXB2EIDL_EID5_POSN 0x5 #define _TXB2EIDL_EID5_POSITION 0x5 #define _TXB2EIDL_EID5_SIZE 0x1 #define _TXB2EIDL_EID5_LENGTH 0x1 #define _TXB2EIDL_EID5_MASK 0x20 #define _TXB2EIDL_EID6_POSN 0x6 #define _TXB2EIDL_EID6_POSITION 0x6 #define _TXB2EIDL_EID6_SIZE 0x1 #define _TXB2EIDL_EID6_LENGTH 0x1 #define _TXB2EIDL_EID6_MASK 0x40 #define _TXB2EIDL_EID7_POSN 0x7 #define _TXB2EIDL_EID7_POSITION 0x7 #define _TXB2EIDL_EID7_SIZE 0x1 #define _TXB2EIDL_EID7_LENGTH 0x1 #define _TXB2EIDL_EID7_MASK 0x80 #define _TXB2EIDL_TXB2EID0_POSN 0x0 #define _TXB2EIDL_TXB2EID0_POSITION 0x0 #define _TXB2EIDL_TXB2EID0_SIZE 0x1 #define _TXB2EIDL_TXB2EID0_LENGTH 0x1 #define _TXB2EIDL_TXB2EID0_MASK 0x1 #define _TXB2EIDL_TXB2EID1_POSN 0x1 #define _TXB2EIDL_TXB2EID1_POSITION 0x1 #define _TXB2EIDL_TXB2EID1_SIZE 0x1 #define _TXB2EIDL_TXB2EID1_LENGTH 0x1 #define _TXB2EIDL_TXB2EID1_MASK 0x2 #define _TXB2EIDL_TXB2EID2_POSN 0x2 #define _TXB2EIDL_TXB2EID2_POSITION 0x2 #define _TXB2EIDL_TXB2EID2_SIZE 0x1 #define _TXB2EIDL_TXB2EID2_LENGTH 0x1 #define _TXB2EIDL_TXB2EID2_MASK 0x4 #define _TXB2EIDL_TXB2EID3_POSN 0x3 #define _TXB2EIDL_TXB2EID3_POSITION 0x3 #define _TXB2EIDL_TXB2EID3_SIZE 0x1 #define _TXB2EIDL_TXB2EID3_LENGTH 0x1 #define _TXB2EIDL_TXB2EID3_MASK 0x8 #define _TXB2EIDL_TXB2EID4_POSN 0x4 #define _TXB2EIDL_TXB2EID4_POSITION 0x4 #define _TXB2EIDL_TXB2EID4_SIZE 0x1 #define _TXB2EIDL_TXB2EID4_LENGTH 0x1 #define _TXB2EIDL_TXB2EID4_MASK 0x10 #define _TXB2EIDL_TXB2EID5_POSN 0x5 #define _TXB2EIDL_TXB2EID5_POSITION 0x5 #define _TXB2EIDL_TXB2EID5_SIZE 0x1 #define _TXB2EIDL_TXB2EID5_LENGTH 0x1 #define _TXB2EIDL_TXB2EID5_MASK 0x20 #define _TXB2EIDL_TXB2EID6_POSN 0x6 #define _TXB2EIDL_TXB2EID6_POSITION 0x6 #define _TXB2EIDL_TXB2EID6_SIZE 0x1 #define _TXB2EIDL_TXB2EID6_LENGTH 0x1 #define _TXB2EIDL_TXB2EID6_MASK 0x40 #define _TXB2EIDL_TXB2EID7_POSN 0x7 #define _TXB2EIDL_TXB2EID7_POSITION 0x7 #define _TXB2EIDL_TXB2EID7_SIZE 0x1 #define _TXB2EIDL_TXB2EID7_LENGTH 0x1 #define _TXB2EIDL_TXB2EID7_MASK 0x80 // Register: TXB2DLC #define TXB2DLC TXB2DLC extern volatile unsigned char TXB2DLC @ 0xF05; #ifndef _LIB_BUILD asm("TXB2DLC equ 0F05h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned :2; unsigned TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; }; struct { unsigned TXB2DLC0 :1; unsigned TXB2DLC1 :1; unsigned TXB2DLC2 :1; unsigned TXB2DLC3 :1; unsigned :2; unsigned TXB2RTR :1; }; } TXB2DLCbits_t; extern volatile TXB2DLCbits_t TXB2DLCbits @ 0xF05; // bitfield macros #define _TXB2DLC_DLC_POSN 0x0 #define _TXB2DLC_DLC_POSITION 0x0 #define _TXB2DLC_DLC_SIZE 0x4 #define _TXB2DLC_DLC_LENGTH 0x4 #define _TXB2DLC_DLC_MASK 0xF #define _TXB2DLC_TXRTR_POSN 0x6 #define _TXB2DLC_TXRTR_POSITION 0x6 #define _TXB2DLC_TXRTR_SIZE 0x1 #define _TXB2DLC_TXRTR_LENGTH 0x1 #define _TXB2DLC_TXRTR_MASK 0x40 #define _TXB2DLC_DLC0_POSN 0x0 #define _TXB2DLC_DLC0_POSITION 0x0 #define _TXB2DLC_DLC0_SIZE 0x1 #define _TXB2DLC_DLC0_LENGTH 0x1 #define _TXB2DLC_DLC0_MASK 0x1 #define _TXB2DLC_DLC1_POSN 0x1 #define _TXB2DLC_DLC1_POSITION 0x1 #define _TXB2DLC_DLC1_SIZE 0x1 #define _TXB2DLC_DLC1_LENGTH 0x1 #define _TXB2DLC_DLC1_MASK 0x2 #define _TXB2DLC_DLC2_POSN 0x2 #define _TXB2DLC_DLC2_POSITION 0x2 #define _TXB2DLC_DLC2_SIZE 0x1 #define _TXB2DLC_DLC2_LENGTH 0x1 #define _TXB2DLC_DLC2_MASK 0x4 #define _TXB2DLC_DLC3_POSN 0x3 #define _TXB2DLC_DLC3_POSITION 0x3 #define _TXB2DLC_DLC3_SIZE 0x1 #define _TXB2DLC_DLC3_LENGTH 0x1 #define _TXB2DLC_DLC3_MASK 0x8 #define _TXB2DLC_TXB2DLC0_POSN 0x0 #define _TXB2DLC_TXB2DLC0_POSITION 0x0 #define _TXB2DLC_TXB2DLC0_SIZE 0x1 #define _TXB2DLC_TXB2DLC0_LENGTH 0x1 #define _TXB2DLC_TXB2DLC0_MASK 0x1 #define _TXB2DLC_TXB2DLC1_POSN 0x1 #define _TXB2DLC_TXB2DLC1_POSITION 0x1 #define _TXB2DLC_TXB2DLC1_SIZE 0x1 #define _TXB2DLC_TXB2DLC1_LENGTH 0x1 #define _TXB2DLC_TXB2DLC1_MASK 0x2 #define _TXB2DLC_TXB2DLC2_POSN 0x2 #define _TXB2DLC_TXB2DLC2_POSITION 0x2 #define _TXB2DLC_TXB2DLC2_SIZE 0x1 #define _TXB2DLC_TXB2DLC2_LENGTH 0x1 #define _TXB2DLC_TXB2DLC2_MASK 0x4 #define _TXB2DLC_TXB2DLC3_POSN 0x3 #define _TXB2DLC_TXB2DLC3_POSITION 0x3 #define _TXB2DLC_TXB2DLC3_SIZE 0x1 #define _TXB2DLC_TXB2DLC3_LENGTH 0x1 #define _TXB2DLC_TXB2DLC3_MASK 0x8 #define _TXB2DLC_TXB2RTR_POSN 0x6 #define _TXB2DLC_TXB2RTR_POSITION 0x6 #define _TXB2DLC_TXB2RTR_SIZE 0x1 #define _TXB2DLC_TXB2RTR_LENGTH 0x1 #define _TXB2DLC_TXB2RTR_MASK 0x40 // Register: TXB2D0 #define TXB2D0 TXB2D0 extern volatile unsigned char TXB2D0 @ 0xF06; #ifndef _LIB_BUILD asm("TXB2D0 equ 0F06h"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D0 :8; }; struct { unsigned TXB2D00 :1; unsigned TXB2D01 :1; unsigned TXB2D02 :1; unsigned TXB2D03 :1; unsigned TXB2D04 :1; unsigned TXB2D05 :1; unsigned TXB2D06 :1; unsigned TXB2D07 :1; }; } TXB2D0bits_t; extern volatile TXB2D0bits_t TXB2D0bits @ 0xF06; // bitfield macros #define _TXB2D0_TXB2D0_POSN 0x0 #define _TXB2D0_TXB2D0_POSITION 0x0 #define _TXB2D0_TXB2D0_SIZE 0x8 #define _TXB2D0_TXB2D0_LENGTH 0x8 #define _TXB2D0_TXB2D0_MASK 0xFF #define _TXB2D0_TXB2D00_POSN 0x0 #define _TXB2D0_TXB2D00_POSITION 0x0 #define _TXB2D0_TXB2D00_SIZE 0x1 #define _TXB2D0_TXB2D00_LENGTH 0x1 #define _TXB2D0_TXB2D00_MASK 0x1 #define _TXB2D0_TXB2D01_POSN 0x1 #define _TXB2D0_TXB2D01_POSITION 0x1 #define _TXB2D0_TXB2D01_SIZE 0x1 #define _TXB2D0_TXB2D01_LENGTH 0x1 #define _TXB2D0_TXB2D01_MASK 0x2 #define _TXB2D0_TXB2D02_POSN 0x2 #define _TXB2D0_TXB2D02_POSITION 0x2 #define _TXB2D0_TXB2D02_SIZE 0x1 #define _TXB2D0_TXB2D02_LENGTH 0x1 #define _TXB2D0_TXB2D02_MASK 0x4 #define _TXB2D0_TXB2D03_POSN 0x3 #define _TXB2D0_TXB2D03_POSITION 0x3 #define _TXB2D0_TXB2D03_SIZE 0x1 #define _TXB2D0_TXB2D03_LENGTH 0x1 #define _TXB2D0_TXB2D03_MASK 0x8 #define _TXB2D0_TXB2D04_POSN 0x4 #define _TXB2D0_TXB2D04_POSITION 0x4 #define _TXB2D0_TXB2D04_SIZE 0x1 #define _TXB2D0_TXB2D04_LENGTH 0x1 #define _TXB2D0_TXB2D04_MASK 0x10 #define _TXB2D0_TXB2D05_POSN 0x5 #define _TXB2D0_TXB2D05_POSITION 0x5 #define _TXB2D0_TXB2D05_SIZE 0x1 #define _TXB2D0_TXB2D05_LENGTH 0x1 #define _TXB2D0_TXB2D05_MASK 0x20 #define _TXB2D0_TXB2D06_POSN 0x6 #define _TXB2D0_TXB2D06_POSITION 0x6 #define _TXB2D0_TXB2D06_SIZE 0x1 #define _TXB2D0_TXB2D06_LENGTH 0x1 #define _TXB2D0_TXB2D06_MASK 0x40 #define _TXB2D0_TXB2D07_POSN 0x7 #define _TXB2D0_TXB2D07_POSITION 0x7 #define _TXB2D0_TXB2D07_SIZE 0x1 #define _TXB2D0_TXB2D07_LENGTH 0x1 #define _TXB2D0_TXB2D07_MASK 0x80 // Register: TXB2D1 #define TXB2D1 TXB2D1 extern volatile unsigned char TXB2D1 @ 0xF07; #ifndef _LIB_BUILD asm("TXB2D1 equ 0F07h"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D1 :8; }; struct { unsigned TXB2D10 :1; unsigned TXB2D11 :1; unsigned TXB2D12 :1; unsigned TXB2D13 :1; unsigned TXB2D14 :1; unsigned TXB2D15 :1; unsigned TXB2D16 :1; unsigned TXB2D17 :1; }; } TXB2D1bits_t; extern volatile TXB2D1bits_t TXB2D1bits @ 0xF07; // bitfield macros #define _TXB2D1_TXB2D1_POSN 0x0 #define _TXB2D1_TXB2D1_POSITION 0x0 #define _TXB2D1_TXB2D1_SIZE 0x8 #define _TXB2D1_TXB2D1_LENGTH 0x8 #define _TXB2D1_TXB2D1_MASK 0xFF #define _TXB2D1_TXB2D10_POSN 0x0 #define _TXB2D1_TXB2D10_POSITION 0x0 #define _TXB2D1_TXB2D10_SIZE 0x1 #define _TXB2D1_TXB2D10_LENGTH 0x1 #define _TXB2D1_TXB2D10_MASK 0x1 #define _TXB2D1_TXB2D11_POSN 0x1 #define _TXB2D1_TXB2D11_POSITION 0x1 #define _TXB2D1_TXB2D11_SIZE 0x1 #define _TXB2D1_TXB2D11_LENGTH 0x1 #define _TXB2D1_TXB2D11_MASK 0x2 #define _TXB2D1_TXB2D12_POSN 0x2 #define _TXB2D1_TXB2D12_POSITION 0x2 #define _TXB2D1_TXB2D12_SIZE 0x1 #define _TXB2D1_TXB2D12_LENGTH 0x1 #define _TXB2D1_TXB2D12_MASK 0x4 #define _TXB2D1_TXB2D13_POSN 0x3 #define _TXB2D1_TXB2D13_POSITION 0x3 #define _TXB2D1_TXB2D13_SIZE 0x1 #define _TXB2D1_TXB2D13_LENGTH 0x1 #define _TXB2D1_TXB2D13_MASK 0x8 #define _TXB2D1_TXB2D14_POSN 0x4 #define _TXB2D1_TXB2D14_POSITION 0x4 #define _TXB2D1_TXB2D14_SIZE 0x1 #define _TXB2D1_TXB2D14_LENGTH 0x1 #define _TXB2D1_TXB2D14_MASK 0x10 #define _TXB2D1_TXB2D15_POSN 0x5 #define _TXB2D1_TXB2D15_POSITION 0x5 #define _TXB2D1_TXB2D15_SIZE 0x1 #define _TXB2D1_TXB2D15_LENGTH 0x1 #define _TXB2D1_TXB2D15_MASK 0x20 #define _TXB2D1_TXB2D16_POSN 0x6 #define _TXB2D1_TXB2D16_POSITION 0x6 #define _TXB2D1_TXB2D16_SIZE 0x1 #define _TXB2D1_TXB2D16_LENGTH 0x1 #define _TXB2D1_TXB2D16_MASK 0x40 #define _TXB2D1_TXB2D17_POSN 0x7 #define _TXB2D1_TXB2D17_POSITION 0x7 #define _TXB2D1_TXB2D17_SIZE 0x1 #define _TXB2D1_TXB2D17_LENGTH 0x1 #define _TXB2D1_TXB2D17_MASK 0x80 // Register: TXB2D2 #define TXB2D2 TXB2D2 extern volatile unsigned char TXB2D2 @ 0xF08; #ifndef _LIB_BUILD asm("TXB2D2 equ 0F08h"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D2 :8; }; struct { unsigned TXB2D20 :1; unsigned TXB2D21 :1; unsigned TXB2D22 :1; unsigned TXB2D23 :1; unsigned TXB2D24 :1; unsigned TXB2D25 :1; unsigned TXB2D26 :1; unsigned TXB2D27 :1; }; } TXB2D2bits_t; extern volatile TXB2D2bits_t TXB2D2bits @ 0xF08; // bitfield macros #define _TXB2D2_TXB2D2_POSN 0x0 #define _TXB2D2_TXB2D2_POSITION 0x0 #define _TXB2D2_TXB2D2_SIZE 0x8 #define _TXB2D2_TXB2D2_LENGTH 0x8 #define _TXB2D2_TXB2D2_MASK 0xFF #define _TXB2D2_TXB2D20_POSN 0x0 #define _TXB2D2_TXB2D20_POSITION 0x0 #define _TXB2D2_TXB2D20_SIZE 0x1 #define _TXB2D2_TXB2D20_LENGTH 0x1 #define _TXB2D2_TXB2D20_MASK 0x1 #define _TXB2D2_TXB2D21_POSN 0x1 #define _TXB2D2_TXB2D21_POSITION 0x1 #define _TXB2D2_TXB2D21_SIZE 0x1 #define _TXB2D2_TXB2D21_LENGTH 0x1 #define _TXB2D2_TXB2D21_MASK 0x2 #define _TXB2D2_TXB2D22_POSN 0x2 #define _TXB2D2_TXB2D22_POSITION 0x2 #define _TXB2D2_TXB2D22_SIZE 0x1 #define _TXB2D2_TXB2D22_LENGTH 0x1 #define _TXB2D2_TXB2D22_MASK 0x4 #define _TXB2D2_TXB2D23_POSN 0x3 #define _TXB2D2_TXB2D23_POSITION 0x3 #define _TXB2D2_TXB2D23_SIZE 0x1 #define _TXB2D2_TXB2D23_LENGTH 0x1 #define _TXB2D2_TXB2D23_MASK 0x8 #define _TXB2D2_TXB2D24_POSN 0x4 #define _TXB2D2_TXB2D24_POSITION 0x4 #define _TXB2D2_TXB2D24_SIZE 0x1 #define _TXB2D2_TXB2D24_LENGTH 0x1 #define _TXB2D2_TXB2D24_MASK 0x10 #define _TXB2D2_TXB2D25_POSN 0x5 #define _TXB2D2_TXB2D25_POSITION 0x5 #define _TXB2D2_TXB2D25_SIZE 0x1 #define _TXB2D2_TXB2D25_LENGTH 0x1 #define _TXB2D2_TXB2D25_MASK 0x20 #define _TXB2D2_TXB2D26_POSN 0x6 #define _TXB2D2_TXB2D26_POSITION 0x6 #define _TXB2D2_TXB2D26_SIZE 0x1 #define _TXB2D2_TXB2D26_LENGTH 0x1 #define _TXB2D2_TXB2D26_MASK 0x40 #define _TXB2D2_TXB2D27_POSN 0x7 #define _TXB2D2_TXB2D27_POSITION 0x7 #define _TXB2D2_TXB2D27_SIZE 0x1 #define _TXB2D2_TXB2D27_LENGTH 0x1 #define _TXB2D2_TXB2D27_MASK 0x80 // Register: TXB2D3 #define TXB2D3 TXB2D3 extern volatile unsigned char TXB2D3 @ 0xF09; #ifndef _LIB_BUILD asm("TXB2D3 equ 0F09h"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D3 :8; }; struct { unsigned TXB2D30 :1; unsigned TXB2D31 :1; unsigned TXB2D32 :1; unsigned TXB2D33 :1; unsigned TXB2D34 :1; unsigned TXB2D35 :1; unsigned TXB2D36 :1; unsigned TXB2D37 :1; }; } TXB2D3bits_t; extern volatile TXB2D3bits_t TXB2D3bits @ 0xF09; // bitfield macros #define _TXB2D3_TXB2D3_POSN 0x0 #define _TXB2D3_TXB2D3_POSITION 0x0 #define _TXB2D3_TXB2D3_SIZE 0x8 #define _TXB2D3_TXB2D3_LENGTH 0x8 #define _TXB2D3_TXB2D3_MASK 0xFF #define _TXB2D3_TXB2D30_POSN 0x0 #define _TXB2D3_TXB2D30_POSITION 0x0 #define _TXB2D3_TXB2D30_SIZE 0x1 #define _TXB2D3_TXB2D30_LENGTH 0x1 #define _TXB2D3_TXB2D30_MASK 0x1 #define _TXB2D3_TXB2D31_POSN 0x1 #define _TXB2D3_TXB2D31_POSITION 0x1 #define _TXB2D3_TXB2D31_SIZE 0x1 #define _TXB2D3_TXB2D31_LENGTH 0x1 #define _TXB2D3_TXB2D31_MASK 0x2 #define _TXB2D3_TXB2D32_POSN 0x2 #define _TXB2D3_TXB2D32_POSITION 0x2 #define _TXB2D3_TXB2D32_SIZE 0x1 #define _TXB2D3_TXB2D32_LENGTH 0x1 #define _TXB2D3_TXB2D32_MASK 0x4 #define _TXB2D3_TXB2D33_POSN 0x3 #define _TXB2D3_TXB2D33_POSITION 0x3 #define _TXB2D3_TXB2D33_SIZE 0x1 #define _TXB2D3_TXB2D33_LENGTH 0x1 #define _TXB2D3_TXB2D33_MASK 0x8 #define _TXB2D3_TXB2D34_POSN 0x4 #define _TXB2D3_TXB2D34_POSITION 0x4 #define _TXB2D3_TXB2D34_SIZE 0x1 #define _TXB2D3_TXB2D34_LENGTH 0x1 #define _TXB2D3_TXB2D34_MASK 0x10 #define _TXB2D3_TXB2D35_POSN 0x5 #define _TXB2D3_TXB2D35_POSITION 0x5 #define _TXB2D3_TXB2D35_SIZE 0x1 #define _TXB2D3_TXB2D35_LENGTH 0x1 #define _TXB2D3_TXB2D35_MASK 0x20 #define _TXB2D3_TXB2D36_POSN 0x6 #define _TXB2D3_TXB2D36_POSITION 0x6 #define _TXB2D3_TXB2D36_SIZE 0x1 #define _TXB2D3_TXB2D36_LENGTH 0x1 #define _TXB2D3_TXB2D36_MASK 0x40 #define _TXB2D3_TXB2D37_POSN 0x7 #define _TXB2D3_TXB2D37_POSITION 0x7 #define _TXB2D3_TXB2D37_SIZE 0x1 #define _TXB2D3_TXB2D37_LENGTH 0x1 #define _TXB2D3_TXB2D37_MASK 0x80 // Register: TXB2D4 #define TXB2D4 TXB2D4 extern volatile unsigned char TXB2D4 @ 0xF0A; #ifndef _LIB_BUILD asm("TXB2D4 equ 0F0Ah"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D4 :8; }; struct { unsigned TXB2D40 :1; unsigned TXB2D41 :1; unsigned TXB2D42 :1; unsigned TXB2D43 :1; unsigned TXB2D44 :1; unsigned TXB2D45 :1; unsigned TXB2D46 :1; unsigned TXB2D47 :1; }; } TXB2D4bits_t; extern volatile TXB2D4bits_t TXB2D4bits @ 0xF0A; // bitfield macros #define _TXB2D4_TXB2D4_POSN 0x0 #define _TXB2D4_TXB2D4_POSITION 0x0 #define _TXB2D4_TXB2D4_SIZE 0x8 #define _TXB2D4_TXB2D4_LENGTH 0x8 #define _TXB2D4_TXB2D4_MASK 0xFF #define _TXB2D4_TXB2D40_POSN 0x0 #define _TXB2D4_TXB2D40_POSITION 0x0 #define _TXB2D4_TXB2D40_SIZE 0x1 #define _TXB2D4_TXB2D40_LENGTH 0x1 #define _TXB2D4_TXB2D40_MASK 0x1 #define _TXB2D4_TXB2D41_POSN 0x1 #define _TXB2D4_TXB2D41_POSITION 0x1 #define _TXB2D4_TXB2D41_SIZE 0x1 #define _TXB2D4_TXB2D41_LENGTH 0x1 #define _TXB2D4_TXB2D41_MASK 0x2 #define _TXB2D4_TXB2D42_POSN 0x2 #define _TXB2D4_TXB2D42_POSITION 0x2 #define _TXB2D4_TXB2D42_SIZE 0x1 #define _TXB2D4_TXB2D42_LENGTH 0x1 #define _TXB2D4_TXB2D42_MASK 0x4 #define _TXB2D4_TXB2D43_POSN 0x3 #define _TXB2D4_TXB2D43_POSITION 0x3 #define _TXB2D4_TXB2D43_SIZE 0x1 #define _TXB2D4_TXB2D43_LENGTH 0x1 #define _TXB2D4_TXB2D43_MASK 0x8 #define _TXB2D4_TXB2D44_POSN 0x4 #define _TXB2D4_TXB2D44_POSITION 0x4 #define _TXB2D4_TXB2D44_SIZE 0x1 #define _TXB2D4_TXB2D44_LENGTH 0x1 #define _TXB2D4_TXB2D44_MASK 0x10 #define _TXB2D4_TXB2D45_POSN 0x5 #define _TXB2D4_TXB2D45_POSITION 0x5 #define _TXB2D4_TXB2D45_SIZE 0x1 #define _TXB2D4_TXB2D45_LENGTH 0x1 #define _TXB2D4_TXB2D45_MASK 0x20 #define _TXB2D4_TXB2D46_POSN 0x6 #define _TXB2D4_TXB2D46_POSITION 0x6 #define _TXB2D4_TXB2D46_SIZE 0x1 #define _TXB2D4_TXB2D46_LENGTH 0x1 #define _TXB2D4_TXB2D46_MASK 0x40 #define _TXB2D4_TXB2D47_POSN 0x7 #define _TXB2D4_TXB2D47_POSITION 0x7 #define _TXB2D4_TXB2D47_SIZE 0x1 #define _TXB2D4_TXB2D47_LENGTH 0x1 #define _TXB2D4_TXB2D47_MASK 0x80 // Register: TXB2D5 #define TXB2D5 TXB2D5 extern volatile unsigned char TXB2D5 @ 0xF0B; #ifndef _LIB_BUILD asm("TXB2D5 equ 0F0Bh"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D5 :8; }; struct { unsigned TXB2D50 :1; unsigned TXB2D51 :1; unsigned TXB2D52 :1; unsigned TXB2D53 :1; unsigned TXB2D54 :1; unsigned TXB2D55 :1; unsigned TXB2D56 :1; unsigned TXB2D57 :1; }; } TXB2D5bits_t; extern volatile TXB2D5bits_t TXB2D5bits @ 0xF0B; // bitfield macros #define _TXB2D5_TXB2D5_POSN 0x0 #define _TXB2D5_TXB2D5_POSITION 0x0 #define _TXB2D5_TXB2D5_SIZE 0x8 #define _TXB2D5_TXB2D5_LENGTH 0x8 #define _TXB2D5_TXB2D5_MASK 0xFF #define _TXB2D5_TXB2D50_POSN 0x0 #define _TXB2D5_TXB2D50_POSITION 0x0 #define _TXB2D5_TXB2D50_SIZE 0x1 #define _TXB2D5_TXB2D50_LENGTH 0x1 #define _TXB2D5_TXB2D50_MASK 0x1 #define _TXB2D5_TXB2D51_POSN 0x1 #define _TXB2D5_TXB2D51_POSITION 0x1 #define _TXB2D5_TXB2D51_SIZE 0x1 #define _TXB2D5_TXB2D51_LENGTH 0x1 #define _TXB2D5_TXB2D51_MASK 0x2 #define _TXB2D5_TXB2D52_POSN 0x2 #define _TXB2D5_TXB2D52_POSITION 0x2 #define _TXB2D5_TXB2D52_SIZE 0x1 #define _TXB2D5_TXB2D52_LENGTH 0x1 #define _TXB2D5_TXB2D52_MASK 0x4 #define _TXB2D5_TXB2D53_POSN 0x3 #define _TXB2D5_TXB2D53_POSITION 0x3 #define _TXB2D5_TXB2D53_SIZE 0x1 #define _TXB2D5_TXB2D53_LENGTH 0x1 #define _TXB2D5_TXB2D53_MASK 0x8 #define _TXB2D5_TXB2D54_POSN 0x4 #define _TXB2D5_TXB2D54_POSITION 0x4 #define _TXB2D5_TXB2D54_SIZE 0x1 #define _TXB2D5_TXB2D54_LENGTH 0x1 #define _TXB2D5_TXB2D54_MASK 0x10 #define _TXB2D5_TXB2D55_POSN 0x5 #define _TXB2D5_TXB2D55_POSITION 0x5 #define _TXB2D5_TXB2D55_SIZE 0x1 #define _TXB2D5_TXB2D55_LENGTH 0x1 #define _TXB2D5_TXB2D55_MASK 0x20 #define _TXB2D5_TXB2D56_POSN 0x6 #define _TXB2D5_TXB2D56_POSITION 0x6 #define _TXB2D5_TXB2D56_SIZE 0x1 #define _TXB2D5_TXB2D56_LENGTH 0x1 #define _TXB2D5_TXB2D56_MASK 0x40 #define _TXB2D5_TXB2D57_POSN 0x7 #define _TXB2D5_TXB2D57_POSITION 0x7 #define _TXB2D5_TXB2D57_SIZE 0x1 #define _TXB2D5_TXB2D57_LENGTH 0x1 #define _TXB2D5_TXB2D57_MASK 0x80 // Register: TXB2D6 #define TXB2D6 TXB2D6 extern volatile unsigned char TXB2D6 @ 0xF0C; #ifndef _LIB_BUILD asm("TXB2D6 equ 0F0Ch"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D6 :8; }; struct { unsigned TXB2D60 :1; unsigned TXB2D61 :1; unsigned TXB2D62 :1; unsigned TXB2D63 :1; unsigned TXB2D64 :1; unsigned TXB2D65 :1; unsigned TXB2D66 :1; unsigned TXB2D67 :1; }; } TXB2D6bits_t; extern volatile TXB2D6bits_t TXB2D6bits @ 0xF0C; // bitfield macros #define _TXB2D6_TXB2D6_POSN 0x0 #define _TXB2D6_TXB2D6_POSITION 0x0 #define _TXB2D6_TXB2D6_SIZE 0x8 #define _TXB2D6_TXB2D6_LENGTH 0x8 #define _TXB2D6_TXB2D6_MASK 0xFF #define _TXB2D6_TXB2D60_POSN 0x0 #define _TXB2D6_TXB2D60_POSITION 0x0 #define _TXB2D6_TXB2D60_SIZE 0x1 #define _TXB2D6_TXB2D60_LENGTH 0x1 #define _TXB2D6_TXB2D60_MASK 0x1 #define _TXB2D6_TXB2D61_POSN 0x1 #define _TXB2D6_TXB2D61_POSITION 0x1 #define _TXB2D6_TXB2D61_SIZE 0x1 #define _TXB2D6_TXB2D61_LENGTH 0x1 #define _TXB2D6_TXB2D61_MASK 0x2 #define _TXB2D6_TXB2D62_POSN 0x2 #define _TXB2D6_TXB2D62_POSITION 0x2 #define _TXB2D6_TXB2D62_SIZE 0x1 #define _TXB2D6_TXB2D62_LENGTH 0x1 #define _TXB2D6_TXB2D62_MASK 0x4 #define _TXB2D6_TXB2D63_POSN 0x3 #define _TXB2D6_TXB2D63_POSITION 0x3 #define _TXB2D6_TXB2D63_SIZE 0x1 #define _TXB2D6_TXB2D63_LENGTH 0x1 #define _TXB2D6_TXB2D63_MASK 0x8 #define _TXB2D6_TXB2D64_POSN 0x4 #define _TXB2D6_TXB2D64_POSITION 0x4 #define _TXB2D6_TXB2D64_SIZE 0x1 #define _TXB2D6_TXB2D64_LENGTH 0x1 #define _TXB2D6_TXB2D64_MASK 0x10 #define _TXB2D6_TXB2D65_POSN 0x5 #define _TXB2D6_TXB2D65_POSITION 0x5 #define _TXB2D6_TXB2D65_SIZE 0x1 #define _TXB2D6_TXB2D65_LENGTH 0x1 #define _TXB2D6_TXB2D65_MASK 0x20 #define _TXB2D6_TXB2D66_POSN 0x6 #define _TXB2D6_TXB2D66_POSITION 0x6 #define _TXB2D6_TXB2D66_SIZE 0x1 #define _TXB2D6_TXB2D66_LENGTH 0x1 #define _TXB2D6_TXB2D66_MASK 0x40 #define _TXB2D6_TXB2D67_POSN 0x7 #define _TXB2D6_TXB2D67_POSITION 0x7 #define _TXB2D6_TXB2D67_SIZE 0x1 #define _TXB2D6_TXB2D67_LENGTH 0x1 #define _TXB2D6_TXB2D67_MASK 0x80 // Register: TXB2D7 #define TXB2D7 TXB2D7 extern volatile unsigned char TXB2D7 @ 0xF0D; #ifndef _LIB_BUILD asm("TXB2D7 equ 0F0Dh"); #endif // bitfield definitions typedef union { struct { unsigned TXB2D7 :8; }; struct { unsigned TXB2D70 :1; unsigned TXB2D71 :1; unsigned TXB2D72 :1; unsigned TXB2D73 :1; unsigned TXB2D74 :1; unsigned TXB2D75 :1; unsigned TXB2D76 :1; unsigned TXB2D77 :1; }; } TXB2D7bits_t; extern volatile TXB2D7bits_t TXB2D7bits @ 0xF0D; // bitfield macros #define _TXB2D7_TXB2D7_POSN 0x0 #define _TXB2D7_TXB2D7_POSITION 0x0 #define _TXB2D7_TXB2D7_SIZE 0x8 #define _TXB2D7_TXB2D7_LENGTH 0x8 #define _TXB2D7_TXB2D7_MASK 0xFF #define _TXB2D7_TXB2D70_POSN 0x0 #define _TXB2D7_TXB2D70_POSITION 0x0 #define _TXB2D7_TXB2D70_SIZE 0x1 #define _TXB2D7_TXB2D70_LENGTH 0x1 #define _TXB2D7_TXB2D70_MASK 0x1 #define _TXB2D7_TXB2D71_POSN 0x1 #define _TXB2D7_TXB2D71_POSITION 0x1 #define _TXB2D7_TXB2D71_SIZE 0x1 #define _TXB2D7_TXB2D71_LENGTH 0x1 #define _TXB2D7_TXB2D71_MASK 0x2 #define _TXB2D7_TXB2D72_POSN 0x2 #define _TXB2D7_TXB2D72_POSITION 0x2 #define _TXB2D7_TXB2D72_SIZE 0x1 #define _TXB2D7_TXB2D72_LENGTH 0x1 #define _TXB2D7_TXB2D72_MASK 0x4 #define _TXB2D7_TXB2D73_POSN 0x3 #define _TXB2D7_TXB2D73_POSITION 0x3 #define _TXB2D7_TXB2D73_SIZE 0x1 #define _TXB2D7_TXB2D73_LENGTH 0x1 #define _TXB2D7_TXB2D73_MASK 0x8 #define _TXB2D7_TXB2D74_POSN 0x4 #define _TXB2D7_TXB2D74_POSITION 0x4 #define _TXB2D7_TXB2D74_SIZE 0x1 #define _TXB2D7_TXB2D74_LENGTH 0x1 #define _TXB2D7_TXB2D74_MASK 0x10 #define _TXB2D7_TXB2D75_POSN 0x5 #define _TXB2D7_TXB2D75_POSITION 0x5 #define _TXB2D7_TXB2D75_SIZE 0x1 #define _TXB2D7_TXB2D75_LENGTH 0x1 #define _TXB2D7_TXB2D75_MASK 0x20 #define _TXB2D7_TXB2D76_POSN 0x6 #define _TXB2D7_TXB2D76_POSITION 0x6 #define _TXB2D7_TXB2D76_SIZE 0x1 #define _TXB2D7_TXB2D76_LENGTH 0x1 #define _TXB2D7_TXB2D76_MASK 0x40 #define _TXB2D7_TXB2D77_POSN 0x7 #define _TXB2D7_TXB2D77_POSITION 0x7 #define _TXB2D7_TXB2D77_SIZE 0x1 #define _TXB2D7_TXB2D77_LENGTH 0x1 #define _TXB2D7_TXB2D77_MASK 0x80 // Register: CANSTAT_RO3 #define CANSTAT_RO3 CANSTAT_RO3 extern volatile unsigned char CANSTAT_RO3 @ 0xF0E; #ifndef _LIB_BUILD asm("CANSTAT_RO3 equ 0F0Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO3bits_t; extern volatile CANSTAT_RO3bits_t CANSTAT_RO3bits @ 0xF0E; // bitfield macros #define _CANSTAT_RO3_EICODE0_POSN 0x0 #define _CANSTAT_RO3_EICODE0_POSITION 0x0 #define _CANSTAT_RO3_EICODE0_SIZE 0x1 #define _CANSTAT_RO3_EICODE0_LENGTH 0x1 #define _CANSTAT_RO3_EICODE0_MASK 0x1 #define _CANSTAT_RO3_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO3_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO3_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO3_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO3_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO3_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO3_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO3_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO3_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO3_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO3_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO3_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO3_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO3_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO3_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO3_EICODE4_POSN 0x4 #define _CANSTAT_RO3_EICODE4_POSITION 0x4 #define _CANSTAT_RO3_EICODE4_SIZE 0x1 #define _CANSTAT_RO3_EICODE4_LENGTH 0x1 #define _CANSTAT_RO3_EICODE4_MASK 0x10 #define _CANSTAT_RO3_OPMODE_POSN 0x5 #define _CANSTAT_RO3_OPMODE_POSITION 0x5 #define _CANSTAT_RO3_OPMODE_SIZE 0x3 #define _CANSTAT_RO3_OPMODE_LENGTH 0x3 #define _CANSTAT_RO3_OPMODE_MASK 0xE0 #define _CANSTAT_RO3_EICODE1_POSN 0x1 #define _CANSTAT_RO3_EICODE1_POSITION 0x1 #define _CANSTAT_RO3_EICODE1_SIZE 0x1 #define _CANSTAT_RO3_EICODE1_LENGTH 0x1 #define _CANSTAT_RO3_EICODE1_MASK 0x2 #define _CANSTAT_RO3_EICODE2_POSN 0x2 #define _CANSTAT_RO3_EICODE2_POSITION 0x2 #define _CANSTAT_RO3_EICODE2_SIZE 0x1 #define _CANSTAT_RO3_EICODE2_LENGTH 0x1 #define _CANSTAT_RO3_EICODE2_MASK 0x4 #define _CANSTAT_RO3_EICODE3_POSN 0x3 #define _CANSTAT_RO3_EICODE3_POSITION 0x3 #define _CANSTAT_RO3_EICODE3_SIZE 0x1 #define _CANSTAT_RO3_EICODE3_LENGTH 0x1 #define _CANSTAT_RO3_EICODE3_MASK 0x8 #define _CANSTAT_RO3_OPMODE0_POSN 0x5 #define _CANSTAT_RO3_OPMODE0_POSITION 0x5 #define _CANSTAT_RO3_OPMODE0_SIZE 0x1 #define _CANSTAT_RO3_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO3_OPMODE0_MASK 0x20 #define _CANSTAT_RO3_OPMODE1_POSN 0x6 #define _CANSTAT_RO3_OPMODE1_POSITION 0x6 #define _CANSTAT_RO3_OPMODE1_SIZE 0x1 #define _CANSTAT_RO3_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO3_OPMODE1_MASK 0x40 #define _CANSTAT_RO3_OPMODE2_POSN 0x7 #define _CANSTAT_RO3_OPMODE2_POSITION 0x7 #define _CANSTAT_RO3_OPMODE2_SIZE 0x1 #define _CANSTAT_RO3_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO3_OPMODE2_MASK 0x80 #define _CANSTAT_RO3_ICODE0_POSN 0x1 #define _CANSTAT_RO3_ICODE0_POSITION 0x1 #define _CANSTAT_RO3_ICODE0_SIZE 0x1 #define _CANSTAT_RO3_ICODE0_LENGTH 0x1 #define _CANSTAT_RO3_ICODE0_MASK 0x2 #define _CANSTAT_RO3_ICODE1_POSN 0x2 #define _CANSTAT_RO3_ICODE1_POSITION 0x2 #define _CANSTAT_RO3_ICODE1_SIZE 0x1 #define _CANSTAT_RO3_ICODE1_LENGTH 0x1 #define _CANSTAT_RO3_ICODE1_MASK 0x4 #define _CANSTAT_RO3_ICODE2_POSN 0x3 #define _CANSTAT_RO3_ICODE2_POSITION 0x3 #define _CANSTAT_RO3_ICODE2_SIZE 0x1 #define _CANSTAT_RO3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO3_ICODE2_MASK 0x8 // Register: CANCON_RO3 #define CANCON_RO3 CANCON_RO3 extern volatile unsigned char CANCON_RO3 @ 0xF0F; #ifndef _LIB_BUILD asm("CANCON_RO3 equ 0F0Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO3bits_t; extern volatile CANCON_RO3bits_t CANCON_RO3bits @ 0xF0F; // bitfield macros #define _CANCON_RO3_FP0_POSN 0x0 #define _CANCON_RO3_FP0_POSITION 0x0 #define _CANCON_RO3_FP0_SIZE 0x1 #define _CANCON_RO3_FP0_LENGTH 0x1 #define _CANCON_RO3_FP0_MASK 0x1 #define _CANCON_RO3_WIN0_FP1_POSN 0x1 #define _CANCON_RO3_WIN0_FP1_POSITION 0x1 #define _CANCON_RO3_WIN0_FP1_SIZE 0x1 #define _CANCON_RO3_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO3_WIN0_FP1_MASK 0x2 #define _CANCON_RO3_WIN1_FP2_POSN 0x2 #define _CANCON_RO3_WIN1_FP2_POSITION 0x2 #define _CANCON_RO3_WIN1_FP2_SIZE 0x1 #define _CANCON_RO3_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO3_WIN1_FP2_MASK 0x4 #define _CANCON_RO3_WIN2_FP3_POSN 0x3 #define _CANCON_RO3_WIN2_FP3_POSITION 0x3 #define _CANCON_RO3_WIN2_FP3_SIZE 0x1 #define _CANCON_RO3_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO3_WIN2_FP3_MASK 0x8 #define _CANCON_RO3_ABAT_POSN 0x4 #define _CANCON_RO3_ABAT_POSITION 0x4 #define _CANCON_RO3_ABAT_SIZE 0x1 #define _CANCON_RO3_ABAT_LENGTH 0x1 #define _CANCON_RO3_ABAT_MASK 0x10 #define _CANCON_RO3_REQOP_POSN 0x5 #define _CANCON_RO3_REQOP_POSITION 0x5 #define _CANCON_RO3_REQOP_SIZE 0x3 #define _CANCON_RO3_REQOP_LENGTH 0x3 #define _CANCON_RO3_REQOP_MASK 0xE0 #define _CANCON_RO3_WIN0_POSN 0x1 #define _CANCON_RO3_WIN0_POSITION 0x1 #define _CANCON_RO3_WIN0_SIZE 0x1 #define _CANCON_RO3_WIN0_LENGTH 0x1 #define _CANCON_RO3_WIN0_MASK 0x2 #define _CANCON_RO3_WIN1_POSN 0x2 #define _CANCON_RO3_WIN1_POSITION 0x2 #define _CANCON_RO3_WIN1_SIZE 0x1 #define _CANCON_RO3_WIN1_LENGTH 0x1 #define _CANCON_RO3_WIN1_MASK 0x4 #define _CANCON_RO3_WIN2_POSN 0x3 #define _CANCON_RO3_WIN2_POSITION 0x3 #define _CANCON_RO3_WIN2_SIZE 0x1 #define _CANCON_RO3_WIN2_LENGTH 0x1 #define _CANCON_RO3_WIN2_MASK 0x8 #define _CANCON_RO3_FP1_POSN 0x1 #define _CANCON_RO3_FP1_POSITION 0x1 #define _CANCON_RO3_FP1_SIZE 0x1 #define _CANCON_RO3_FP1_LENGTH 0x1 #define _CANCON_RO3_FP1_MASK 0x2 #define _CANCON_RO3_FP2_POSN 0x2 #define _CANCON_RO3_FP2_POSITION 0x2 #define _CANCON_RO3_FP2_SIZE 0x1 #define _CANCON_RO3_FP2_LENGTH 0x1 #define _CANCON_RO3_FP2_MASK 0x4 #define _CANCON_RO3_FP3_POSN 0x3 #define _CANCON_RO3_FP3_POSITION 0x3 #define _CANCON_RO3_FP3_SIZE 0x1 #define _CANCON_RO3_FP3_LENGTH 0x1 #define _CANCON_RO3_FP3_MASK 0x8 // Register: TXB1CON #define TXB1CON TXB1CON extern volatile unsigned char TXB1CON @ 0xF10; #ifndef _LIB_BUILD asm("TXB1CON equ 0F10h"); #endif // bitfield definitions typedef union { struct { unsigned TXPRI :2; unsigned :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; }; struct { unsigned TXB1PRI0 :1; unsigned TXB1PRI1 :1; unsigned :1; unsigned TXB1REQ :1; unsigned TXB1ERR :1; unsigned TXB1LARB :1; unsigned TXB1ABT :1; unsigned TX1IF :1; }; } TXB1CONbits_t; extern volatile TXB1CONbits_t TXB1CONbits @ 0xF10; // bitfield macros #define _TXB1CON_TXPRI_POSN 0x0 #define _TXB1CON_TXPRI_POSITION 0x0 #define _TXB1CON_TXPRI_SIZE 0x2 #define _TXB1CON_TXPRI_LENGTH 0x2 #define _TXB1CON_TXPRI_MASK 0x3 #define _TXB1CON_TXREQ_POSN 0x3 #define _TXB1CON_TXREQ_POSITION 0x3 #define _TXB1CON_TXREQ_SIZE 0x1 #define _TXB1CON_TXREQ_LENGTH 0x1 #define _TXB1CON_TXREQ_MASK 0x8 #define _TXB1CON_TXERR_POSN 0x4 #define _TXB1CON_TXERR_POSITION 0x4 #define _TXB1CON_TXERR_SIZE 0x1 #define _TXB1CON_TXERR_LENGTH 0x1 #define _TXB1CON_TXERR_MASK 0x10 #define _TXB1CON_TXLARB_POSN 0x5 #define _TXB1CON_TXLARB_POSITION 0x5 #define _TXB1CON_TXLARB_SIZE 0x1 #define _TXB1CON_TXLARB_LENGTH 0x1 #define _TXB1CON_TXLARB_MASK 0x20 #define _TXB1CON_TXABT_POSN 0x6 #define _TXB1CON_TXABT_POSITION 0x6 #define _TXB1CON_TXABT_SIZE 0x1 #define _TXB1CON_TXABT_LENGTH 0x1 #define _TXB1CON_TXABT_MASK 0x40 #define _TXB1CON_TXBIF_POSN 0x7 #define _TXB1CON_TXBIF_POSITION 0x7 #define _TXB1CON_TXBIF_SIZE 0x1 #define _TXB1CON_TXBIF_LENGTH 0x1 #define _TXB1CON_TXBIF_MASK 0x80 #define _TXB1CON_TXPRI0_POSN 0x0 #define _TXB1CON_TXPRI0_POSITION 0x0 #define _TXB1CON_TXPRI0_SIZE 0x1 #define _TXB1CON_TXPRI0_LENGTH 0x1 #define _TXB1CON_TXPRI0_MASK 0x1 #define _TXB1CON_TXPRI1_POSN 0x1 #define _TXB1CON_TXPRI1_POSITION 0x1 #define _TXB1CON_TXPRI1_SIZE 0x1 #define _TXB1CON_TXPRI1_LENGTH 0x1 #define _TXB1CON_TXPRI1_MASK 0x2 #define _TXB1CON_TXB1PRI0_POSN 0x0 #define _TXB1CON_TXB1PRI0_POSITION 0x0 #define _TXB1CON_TXB1PRI0_SIZE 0x1 #define _TXB1CON_TXB1PRI0_LENGTH 0x1 #define _TXB1CON_TXB1PRI0_MASK 0x1 #define _TXB1CON_TXB1PRI1_POSN 0x1 #define _TXB1CON_TXB1PRI1_POSITION 0x1 #define _TXB1CON_TXB1PRI1_SIZE 0x1 #define _TXB1CON_TXB1PRI1_LENGTH 0x1 #define _TXB1CON_TXB1PRI1_MASK 0x2 #define _TXB1CON_TXB1REQ_POSN 0x3 #define _TXB1CON_TXB1REQ_POSITION 0x3 #define _TXB1CON_TXB1REQ_SIZE 0x1 #define _TXB1CON_TXB1REQ_LENGTH 0x1 #define _TXB1CON_TXB1REQ_MASK 0x8 #define _TXB1CON_TXB1ERR_POSN 0x4 #define _TXB1CON_TXB1ERR_POSITION 0x4 #define _TXB1CON_TXB1ERR_SIZE 0x1 #define _TXB1CON_TXB1ERR_LENGTH 0x1 #define _TXB1CON_TXB1ERR_MASK 0x10 #define _TXB1CON_TXB1LARB_POSN 0x5 #define _TXB1CON_TXB1LARB_POSITION 0x5 #define _TXB1CON_TXB1LARB_SIZE 0x1 #define _TXB1CON_TXB1LARB_LENGTH 0x1 #define _TXB1CON_TXB1LARB_MASK 0x20 #define _TXB1CON_TXB1ABT_POSN 0x6 #define _TXB1CON_TXB1ABT_POSITION 0x6 #define _TXB1CON_TXB1ABT_SIZE 0x1 #define _TXB1CON_TXB1ABT_LENGTH 0x1 #define _TXB1CON_TXB1ABT_MASK 0x40 #define _TXB1CON_TX1IF_POSN 0x7 #define _TXB1CON_TX1IF_POSITION 0x7 #define _TXB1CON_TX1IF_SIZE 0x1 #define _TXB1CON_TX1IF_LENGTH 0x1 #define _TXB1CON_TX1IF_MASK 0x80 // Register: TXB1SIDH #define TXB1SIDH TXB1SIDH extern volatile unsigned char TXB1SIDH @ 0xF11; #ifndef _LIB_BUILD asm("TXB1SIDH equ 0F11h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned TXB1SID3 :1; unsigned TXB1SID4 :1; unsigned TXB1SID5 :1; unsigned TXB1SID6 :1; unsigned TXB1SID7 :1; unsigned TXB1SID8 :1; unsigned TXB1SID9 :1; unsigned TXB1SID10 :1; }; } TXB1SIDHbits_t; extern volatile TXB1SIDHbits_t TXB1SIDHbits @ 0xF11; // bitfield macros #define _TXB1SIDH_SID_POSN 0x0 #define _TXB1SIDH_SID_POSITION 0x0 #define _TXB1SIDH_SID_SIZE 0x8 #define _TXB1SIDH_SID_LENGTH 0x8 #define _TXB1SIDH_SID_MASK 0xFF #define _TXB1SIDH_SID3_POSN 0x0 #define _TXB1SIDH_SID3_POSITION 0x0 #define _TXB1SIDH_SID3_SIZE 0x1 #define _TXB1SIDH_SID3_LENGTH 0x1 #define _TXB1SIDH_SID3_MASK 0x1 #define _TXB1SIDH_SID4_POSN 0x1 #define _TXB1SIDH_SID4_POSITION 0x1 #define _TXB1SIDH_SID4_SIZE 0x1 #define _TXB1SIDH_SID4_LENGTH 0x1 #define _TXB1SIDH_SID4_MASK 0x2 #define _TXB1SIDH_SID5_POSN 0x2 #define _TXB1SIDH_SID5_POSITION 0x2 #define _TXB1SIDH_SID5_SIZE 0x1 #define _TXB1SIDH_SID5_LENGTH 0x1 #define _TXB1SIDH_SID5_MASK 0x4 #define _TXB1SIDH_SID6_POSN 0x3 #define _TXB1SIDH_SID6_POSITION 0x3 #define _TXB1SIDH_SID6_SIZE 0x1 #define _TXB1SIDH_SID6_LENGTH 0x1 #define _TXB1SIDH_SID6_MASK 0x8 #define _TXB1SIDH_SID7_POSN 0x4 #define _TXB1SIDH_SID7_POSITION 0x4 #define _TXB1SIDH_SID7_SIZE 0x1 #define _TXB1SIDH_SID7_LENGTH 0x1 #define _TXB1SIDH_SID7_MASK 0x10 #define _TXB1SIDH_SID8_POSN 0x5 #define _TXB1SIDH_SID8_POSITION 0x5 #define _TXB1SIDH_SID8_SIZE 0x1 #define _TXB1SIDH_SID8_LENGTH 0x1 #define _TXB1SIDH_SID8_MASK 0x20 #define _TXB1SIDH_SID9_POSN 0x6 #define _TXB1SIDH_SID9_POSITION 0x6 #define _TXB1SIDH_SID9_SIZE 0x1 #define _TXB1SIDH_SID9_LENGTH 0x1 #define _TXB1SIDH_SID9_MASK 0x40 #define _TXB1SIDH_SID10_POSN 0x7 #define _TXB1SIDH_SID10_POSITION 0x7 #define _TXB1SIDH_SID10_SIZE 0x1 #define _TXB1SIDH_SID10_LENGTH 0x1 #define _TXB1SIDH_SID10_MASK 0x80 #define _TXB1SIDH_TXB1SID3_POSN 0x0 #define _TXB1SIDH_TXB1SID3_POSITION 0x0 #define _TXB1SIDH_TXB1SID3_SIZE 0x1 #define _TXB1SIDH_TXB1SID3_LENGTH 0x1 #define _TXB1SIDH_TXB1SID3_MASK 0x1 #define _TXB1SIDH_TXB1SID4_POSN 0x1 #define _TXB1SIDH_TXB1SID4_POSITION 0x1 #define _TXB1SIDH_TXB1SID4_SIZE 0x1 #define _TXB1SIDH_TXB1SID4_LENGTH 0x1 #define _TXB1SIDH_TXB1SID4_MASK 0x2 #define _TXB1SIDH_TXB1SID5_POSN 0x2 #define _TXB1SIDH_TXB1SID5_POSITION 0x2 #define _TXB1SIDH_TXB1SID5_SIZE 0x1 #define _TXB1SIDH_TXB1SID5_LENGTH 0x1 #define _TXB1SIDH_TXB1SID5_MASK 0x4 #define _TXB1SIDH_TXB1SID6_POSN 0x3 #define _TXB1SIDH_TXB1SID6_POSITION 0x3 #define _TXB1SIDH_TXB1SID6_SIZE 0x1 #define _TXB1SIDH_TXB1SID6_LENGTH 0x1 #define _TXB1SIDH_TXB1SID6_MASK 0x8 #define _TXB1SIDH_TXB1SID7_POSN 0x4 #define _TXB1SIDH_TXB1SID7_POSITION 0x4 #define _TXB1SIDH_TXB1SID7_SIZE 0x1 #define _TXB1SIDH_TXB1SID7_LENGTH 0x1 #define _TXB1SIDH_TXB1SID7_MASK 0x10 #define _TXB1SIDH_TXB1SID8_POSN 0x5 #define _TXB1SIDH_TXB1SID8_POSITION 0x5 #define _TXB1SIDH_TXB1SID8_SIZE 0x1 #define _TXB1SIDH_TXB1SID8_LENGTH 0x1 #define _TXB1SIDH_TXB1SID8_MASK 0x20 #define _TXB1SIDH_TXB1SID9_POSN 0x6 #define _TXB1SIDH_TXB1SID9_POSITION 0x6 #define _TXB1SIDH_TXB1SID9_SIZE 0x1 #define _TXB1SIDH_TXB1SID9_LENGTH 0x1 #define _TXB1SIDH_TXB1SID9_MASK 0x40 #define _TXB1SIDH_TXB1SID10_POSN 0x7 #define _TXB1SIDH_TXB1SID10_POSITION 0x7 #define _TXB1SIDH_TXB1SID10_SIZE 0x1 #define _TXB1SIDH_TXB1SID10_LENGTH 0x1 #define _TXB1SIDH_TXB1SID10_MASK 0x80 // Register: TXB1SIDL #define TXB1SIDL TXB1SIDL extern volatile unsigned char TXB1SIDL @ 0xF12; #ifndef _LIB_BUILD asm("TXB1SIDL equ 0F12h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned TXB1EID16 :1; unsigned TXB1EID17 :1; unsigned :1; unsigned TXB1EXIDE :1; unsigned :1; unsigned TXB1SID0 :1; unsigned TXB1SID1 :1; unsigned TXB1SID2 :1; }; } TXB1SIDLbits_t; extern volatile TXB1SIDLbits_t TXB1SIDLbits @ 0xF12; // bitfield macros #define _TXB1SIDL_EID_POSN 0x0 #define _TXB1SIDL_EID_POSITION 0x0 #define _TXB1SIDL_EID_SIZE 0x2 #define _TXB1SIDL_EID_LENGTH 0x2 #define _TXB1SIDL_EID_MASK 0x3 #define _TXB1SIDL_EXIDE_POSN 0x3 #define _TXB1SIDL_EXIDE_POSITION 0x3 #define _TXB1SIDL_EXIDE_SIZE 0x1 #define _TXB1SIDL_EXIDE_LENGTH 0x1 #define _TXB1SIDL_EXIDE_MASK 0x8 #define _TXB1SIDL_SRR_POSN 0x4 #define _TXB1SIDL_SRR_POSITION 0x4 #define _TXB1SIDL_SRR_SIZE 0x1 #define _TXB1SIDL_SRR_LENGTH 0x1 #define _TXB1SIDL_SRR_MASK 0x10 #define _TXB1SIDL_SID_POSN 0x5 #define _TXB1SIDL_SID_POSITION 0x5 #define _TXB1SIDL_SID_SIZE 0x3 #define _TXB1SIDL_SID_LENGTH 0x3 #define _TXB1SIDL_SID_MASK 0xE0 #define _TXB1SIDL_EID16_POSN 0x0 #define _TXB1SIDL_EID16_POSITION 0x0 #define _TXB1SIDL_EID16_SIZE 0x1 #define _TXB1SIDL_EID16_LENGTH 0x1 #define _TXB1SIDL_EID16_MASK 0x1 #define _TXB1SIDL_EID17_POSN 0x1 #define _TXB1SIDL_EID17_POSITION 0x1 #define _TXB1SIDL_EID17_SIZE 0x1 #define _TXB1SIDL_EID17_LENGTH 0x1 #define _TXB1SIDL_EID17_MASK 0x2 #define _TXB1SIDL_SID0_POSN 0x5 #define _TXB1SIDL_SID0_POSITION 0x5 #define _TXB1SIDL_SID0_SIZE 0x1 #define _TXB1SIDL_SID0_LENGTH 0x1 #define _TXB1SIDL_SID0_MASK 0x20 #define _TXB1SIDL_SID1_POSN 0x6 #define _TXB1SIDL_SID1_POSITION 0x6 #define _TXB1SIDL_SID1_SIZE 0x1 #define _TXB1SIDL_SID1_LENGTH 0x1 #define _TXB1SIDL_SID1_MASK 0x40 #define _TXB1SIDL_SID2_POSN 0x7 #define _TXB1SIDL_SID2_POSITION 0x7 #define _TXB1SIDL_SID2_SIZE 0x1 #define _TXB1SIDL_SID2_LENGTH 0x1 #define _TXB1SIDL_SID2_MASK 0x80 #define _TXB1SIDL_TXB1EID16_POSN 0x0 #define _TXB1SIDL_TXB1EID16_POSITION 0x0 #define _TXB1SIDL_TXB1EID16_SIZE 0x1 #define _TXB1SIDL_TXB1EID16_LENGTH 0x1 #define _TXB1SIDL_TXB1EID16_MASK 0x1 #define _TXB1SIDL_TXB1EID17_POSN 0x1 #define _TXB1SIDL_TXB1EID17_POSITION 0x1 #define _TXB1SIDL_TXB1EID17_SIZE 0x1 #define _TXB1SIDL_TXB1EID17_LENGTH 0x1 #define _TXB1SIDL_TXB1EID17_MASK 0x2 #define _TXB1SIDL_TXB1EXIDE_POSN 0x3 #define _TXB1SIDL_TXB1EXIDE_POSITION 0x3 #define _TXB1SIDL_TXB1EXIDE_SIZE 0x1 #define _TXB1SIDL_TXB1EXIDE_LENGTH 0x1 #define _TXB1SIDL_TXB1EXIDE_MASK 0x8 #define _TXB1SIDL_TXB1SID0_POSN 0x5 #define _TXB1SIDL_TXB1SID0_POSITION 0x5 #define _TXB1SIDL_TXB1SID0_SIZE 0x1 #define _TXB1SIDL_TXB1SID0_LENGTH 0x1 #define _TXB1SIDL_TXB1SID0_MASK 0x20 #define _TXB1SIDL_TXB1SID1_POSN 0x6 #define _TXB1SIDL_TXB1SID1_POSITION 0x6 #define _TXB1SIDL_TXB1SID1_SIZE 0x1 #define _TXB1SIDL_TXB1SID1_LENGTH 0x1 #define _TXB1SIDL_TXB1SID1_MASK 0x40 #define _TXB1SIDL_TXB1SID2_POSN 0x7 #define _TXB1SIDL_TXB1SID2_POSITION 0x7 #define _TXB1SIDL_TXB1SID2_SIZE 0x1 #define _TXB1SIDL_TXB1SID2_LENGTH 0x1 #define _TXB1SIDL_TXB1SID2_MASK 0x80 // Register: TXB1EIDH #define TXB1EIDH TXB1EIDH extern volatile unsigned char TXB1EIDH @ 0xF13; #ifndef _LIB_BUILD asm("TXB1EIDH equ 0F13h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned TXB1EID8 :1; unsigned TXB1EID9 :1; unsigned TXB1EID10 :1; unsigned TXB1EID11 :1; unsigned TXB1EID12 :1; unsigned TXB1EID13 :1; unsigned TXB1EID14 :1; unsigned TXB1EID15 :1; }; } TXB1EIDHbits_t; extern volatile TXB1EIDHbits_t TXB1EIDHbits @ 0xF13; // bitfield macros #define _TXB1EIDH_EID_POSN 0x0 #define _TXB1EIDH_EID_POSITION 0x0 #define _TXB1EIDH_EID_SIZE 0x8 #define _TXB1EIDH_EID_LENGTH 0x8 #define _TXB1EIDH_EID_MASK 0xFF #define _TXB1EIDH_EID8_POSN 0x0 #define _TXB1EIDH_EID8_POSITION 0x0 #define _TXB1EIDH_EID8_SIZE 0x1 #define _TXB1EIDH_EID8_LENGTH 0x1 #define _TXB1EIDH_EID8_MASK 0x1 #define _TXB1EIDH_EID9_POSN 0x1 #define _TXB1EIDH_EID9_POSITION 0x1 #define _TXB1EIDH_EID9_SIZE 0x1 #define _TXB1EIDH_EID9_LENGTH 0x1 #define _TXB1EIDH_EID9_MASK 0x2 #define _TXB1EIDH_EID10_POSN 0x2 #define _TXB1EIDH_EID10_POSITION 0x2 #define _TXB1EIDH_EID10_SIZE 0x1 #define _TXB1EIDH_EID10_LENGTH 0x1 #define _TXB1EIDH_EID10_MASK 0x4 #define _TXB1EIDH_EID11_POSN 0x3 #define _TXB1EIDH_EID11_POSITION 0x3 #define _TXB1EIDH_EID11_SIZE 0x1 #define _TXB1EIDH_EID11_LENGTH 0x1 #define _TXB1EIDH_EID11_MASK 0x8 #define _TXB1EIDH_EID12_POSN 0x4 #define _TXB1EIDH_EID12_POSITION 0x4 #define _TXB1EIDH_EID12_SIZE 0x1 #define _TXB1EIDH_EID12_LENGTH 0x1 #define _TXB1EIDH_EID12_MASK 0x10 #define _TXB1EIDH_EID13_POSN 0x5 #define _TXB1EIDH_EID13_POSITION 0x5 #define _TXB1EIDH_EID13_SIZE 0x1 #define _TXB1EIDH_EID13_LENGTH 0x1 #define _TXB1EIDH_EID13_MASK 0x20 #define _TXB1EIDH_EID14_POSN 0x6 #define _TXB1EIDH_EID14_POSITION 0x6 #define _TXB1EIDH_EID14_SIZE 0x1 #define _TXB1EIDH_EID14_LENGTH 0x1 #define _TXB1EIDH_EID14_MASK 0x40 #define _TXB1EIDH_EID15_POSN 0x7 #define _TXB1EIDH_EID15_POSITION 0x7 #define _TXB1EIDH_EID15_SIZE 0x1 #define _TXB1EIDH_EID15_LENGTH 0x1 #define _TXB1EIDH_EID15_MASK 0x80 #define _TXB1EIDH_TXB1EID8_POSN 0x0 #define _TXB1EIDH_TXB1EID8_POSITION 0x0 #define _TXB1EIDH_TXB1EID8_SIZE 0x1 #define _TXB1EIDH_TXB1EID8_LENGTH 0x1 #define _TXB1EIDH_TXB1EID8_MASK 0x1 #define _TXB1EIDH_TXB1EID9_POSN 0x1 #define _TXB1EIDH_TXB1EID9_POSITION 0x1 #define _TXB1EIDH_TXB1EID9_SIZE 0x1 #define _TXB1EIDH_TXB1EID9_LENGTH 0x1 #define _TXB1EIDH_TXB1EID9_MASK 0x2 #define _TXB1EIDH_TXB1EID10_POSN 0x2 #define _TXB1EIDH_TXB1EID10_POSITION 0x2 #define _TXB1EIDH_TXB1EID10_SIZE 0x1 #define _TXB1EIDH_TXB1EID10_LENGTH 0x1 #define _TXB1EIDH_TXB1EID10_MASK 0x4 #define _TXB1EIDH_TXB1EID11_POSN 0x3 #define _TXB1EIDH_TXB1EID11_POSITION 0x3 #define _TXB1EIDH_TXB1EID11_SIZE 0x1 #define _TXB1EIDH_TXB1EID11_LENGTH 0x1 #define _TXB1EIDH_TXB1EID11_MASK 0x8 #define _TXB1EIDH_TXB1EID12_POSN 0x4 #define _TXB1EIDH_TXB1EID12_POSITION 0x4 #define _TXB1EIDH_TXB1EID12_SIZE 0x1 #define _TXB1EIDH_TXB1EID12_LENGTH 0x1 #define _TXB1EIDH_TXB1EID12_MASK 0x10 #define _TXB1EIDH_TXB1EID13_POSN 0x5 #define _TXB1EIDH_TXB1EID13_POSITION 0x5 #define _TXB1EIDH_TXB1EID13_SIZE 0x1 #define _TXB1EIDH_TXB1EID13_LENGTH 0x1 #define _TXB1EIDH_TXB1EID13_MASK 0x20 #define _TXB1EIDH_TXB1EID14_POSN 0x6 #define _TXB1EIDH_TXB1EID14_POSITION 0x6 #define _TXB1EIDH_TXB1EID14_SIZE 0x1 #define _TXB1EIDH_TXB1EID14_LENGTH 0x1 #define _TXB1EIDH_TXB1EID14_MASK 0x40 #define _TXB1EIDH_TXB1EID15_POSN 0x7 #define _TXB1EIDH_TXB1EID15_POSITION 0x7 #define _TXB1EIDH_TXB1EID15_SIZE 0x1 #define _TXB1EIDH_TXB1EID15_LENGTH 0x1 #define _TXB1EIDH_TXB1EID15_MASK 0x80 // Register: TXB1EIDL #define TXB1EIDL TXB1EIDL extern volatile unsigned char TXB1EIDL @ 0xF14; #ifndef _LIB_BUILD asm("TXB1EIDL equ 0F14h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned TXB1EID0 :1; unsigned TXB1EID1 :1; unsigned TXB1EID2 :1; unsigned TXB1EID3 :1; unsigned TXB1EID4 :1; unsigned TXB1EID5 :1; unsigned TXB1EID6 :1; unsigned TXB1EID7 :1; }; } TXB1EIDLbits_t; extern volatile TXB1EIDLbits_t TXB1EIDLbits @ 0xF14; // bitfield macros #define _TXB1EIDL_EID_POSN 0x0 #define _TXB1EIDL_EID_POSITION 0x0 #define _TXB1EIDL_EID_SIZE 0x8 #define _TXB1EIDL_EID_LENGTH 0x8 #define _TXB1EIDL_EID_MASK 0xFF #define _TXB1EIDL_EID0_POSN 0x0 #define _TXB1EIDL_EID0_POSITION 0x0 #define _TXB1EIDL_EID0_SIZE 0x1 #define _TXB1EIDL_EID0_LENGTH 0x1 #define _TXB1EIDL_EID0_MASK 0x1 #define _TXB1EIDL_EID1_POSN 0x1 #define _TXB1EIDL_EID1_POSITION 0x1 #define _TXB1EIDL_EID1_SIZE 0x1 #define _TXB1EIDL_EID1_LENGTH 0x1 #define _TXB1EIDL_EID1_MASK 0x2 #define _TXB1EIDL_EID2_POSN 0x2 #define _TXB1EIDL_EID2_POSITION 0x2 #define _TXB1EIDL_EID2_SIZE 0x1 #define _TXB1EIDL_EID2_LENGTH 0x1 #define _TXB1EIDL_EID2_MASK 0x4 #define _TXB1EIDL_EID3_POSN 0x3 #define _TXB1EIDL_EID3_POSITION 0x3 #define _TXB1EIDL_EID3_SIZE 0x1 #define _TXB1EIDL_EID3_LENGTH 0x1 #define _TXB1EIDL_EID3_MASK 0x8 #define _TXB1EIDL_EID4_POSN 0x4 #define _TXB1EIDL_EID4_POSITION 0x4 #define _TXB1EIDL_EID4_SIZE 0x1 #define _TXB1EIDL_EID4_LENGTH 0x1 #define _TXB1EIDL_EID4_MASK 0x10 #define _TXB1EIDL_EID5_POSN 0x5 #define _TXB1EIDL_EID5_POSITION 0x5 #define _TXB1EIDL_EID5_SIZE 0x1 #define _TXB1EIDL_EID5_LENGTH 0x1 #define _TXB1EIDL_EID5_MASK 0x20 #define _TXB1EIDL_EID6_POSN 0x6 #define _TXB1EIDL_EID6_POSITION 0x6 #define _TXB1EIDL_EID6_SIZE 0x1 #define _TXB1EIDL_EID6_LENGTH 0x1 #define _TXB1EIDL_EID6_MASK 0x40 #define _TXB1EIDL_EID7_POSN 0x7 #define _TXB1EIDL_EID7_POSITION 0x7 #define _TXB1EIDL_EID7_SIZE 0x1 #define _TXB1EIDL_EID7_LENGTH 0x1 #define _TXB1EIDL_EID7_MASK 0x80 #define _TXB1EIDL_TXB1EID0_POSN 0x0 #define _TXB1EIDL_TXB1EID0_POSITION 0x0 #define _TXB1EIDL_TXB1EID0_SIZE 0x1 #define _TXB1EIDL_TXB1EID0_LENGTH 0x1 #define _TXB1EIDL_TXB1EID0_MASK 0x1 #define _TXB1EIDL_TXB1EID1_POSN 0x1 #define _TXB1EIDL_TXB1EID1_POSITION 0x1 #define _TXB1EIDL_TXB1EID1_SIZE 0x1 #define _TXB1EIDL_TXB1EID1_LENGTH 0x1 #define _TXB1EIDL_TXB1EID1_MASK 0x2 #define _TXB1EIDL_TXB1EID2_POSN 0x2 #define _TXB1EIDL_TXB1EID2_POSITION 0x2 #define _TXB1EIDL_TXB1EID2_SIZE 0x1 #define _TXB1EIDL_TXB1EID2_LENGTH 0x1 #define _TXB1EIDL_TXB1EID2_MASK 0x4 #define _TXB1EIDL_TXB1EID3_POSN 0x3 #define _TXB1EIDL_TXB1EID3_POSITION 0x3 #define _TXB1EIDL_TXB1EID3_SIZE 0x1 #define _TXB1EIDL_TXB1EID3_LENGTH 0x1 #define _TXB1EIDL_TXB1EID3_MASK 0x8 #define _TXB1EIDL_TXB1EID4_POSN 0x4 #define _TXB1EIDL_TXB1EID4_POSITION 0x4 #define _TXB1EIDL_TXB1EID4_SIZE 0x1 #define _TXB1EIDL_TXB1EID4_LENGTH 0x1 #define _TXB1EIDL_TXB1EID4_MASK 0x10 #define _TXB1EIDL_TXB1EID5_POSN 0x5 #define _TXB1EIDL_TXB1EID5_POSITION 0x5 #define _TXB1EIDL_TXB1EID5_SIZE 0x1 #define _TXB1EIDL_TXB1EID5_LENGTH 0x1 #define _TXB1EIDL_TXB1EID5_MASK 0x20 #define _TXB1EIDL_TXB1EID6_POSN 0x6 #define _TXB1EIDL_TXB1EID6_POSITION 0x6 #define _TXB1EIDL_TXB1EID6_SIZE 0x1 #define _TXB1EIDL_TXB1EID6_LENGTH 0x1 #define _TXB1EIDL_TXB1EID6_MASK 0x40 #define _TXB1EIDL_TXB1EID7_POSN 0x7 #define _TXB1EIDL_TXB1EID7_POSITION 0x7 #define _TXB1EIDL_TXB1EID7_SIZE 0x1 #define _TXB1EIDL_TXB1EID7_LENGTH 0x1 #define _TXB1EIDL_TXB1EID7_MASK 0x80 // Register: TXB1DLC #define TXB1DLC TXB1DLC extern volatile unsigned char TXB1DLC @ 0xF15; #ifndef _LIB_BUILD asm("TXB1DLC equ 0F15h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned :2; unsigned TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; }; struct { unsigned TXB1DLC0 :1; unsigned TXB1DLC1 :1; unsigned TXB1DLC2 :1; unsigned TXB1DLC3 :1; unsigned :2; unsigned TXB1RTR :1; }; } TXB1DLCbits_t; extern volatile TXB1DLCbits_t TXB1DLCbits @ 0xF15; // bitfield macros #define _TXB1DLC_DLC_POSN 0x0 #define _TXB1DLC_DLC_POSITION 0x0 #define _TXB1DLC_DLC_SIZE 0x4 #define _TXB1DLC_DLC_LENGTH 0x4 #define _TXB1DLC_DLC_MASK 0xF #define _TXB1DLC_TXRTR_POSN 0x6 #define _TXB1DLC_TXRTR_POSITION 0x6 #define _TXB1DLC_TXRTR_SIZE 0x1 #define _TXB1DLC_TXRTR_LENGTH 0x1 #define _TXB1DLC_TXRTR_MASK 0x40 #define _TXB1DLC_DLC0_POSN 0x0 #define _TXB1DLC_DLC0_POSITION 0x0 #define _TXB1DLC_DLC0_SIZE 0x1 #define _TXB1DLC_DLC0_LENGTH 0x1 #define _TXB1DLC_DLC0_MASK 0x1 #define _TXB1DLC_DLC1_POSN 0x1 #define _TXB1DLC_DLC1_POSITION 0x1 #define _TXB1DLC_DLC1_SIZE 0x1 #define _TXB1DLC_DLC1_LENGTH 0x1 #define _TXB1DLC_DLC1_MASK 0x2 #define _TXB1DLC_DLC2_POSN 0x2 #define _TXB1DLC_DLC2_POSITION 0x2 #define _TXB1DLC_DLC2_SIZE 0x1 #define _TXB1DLC_DLC2_LENGTH 0x1 #define _TXB1DLC_DLC2_MASK 0x4 #define _TXB1DLC_DLC3_POSN 0x3 #define _TXB1DLC_DLC3_POSITION 0x3 #define _TXB1DLC_DLC3_SIZE 0x1 #define _TXB1DLC_DLC3_LENGTH 0x1 #define _TXB1DLC_DLC3_MASK 0x8 #define _TXB1DLC_TXB1DLC0_POSN 0x0 #define _TXB1DLC_TXB1DLC0_POSITION 0x0 #define _TXB1DLC_TXB1DLC0_SIZE 0x1 #define _TXB1DLC_TXB1DLC0_LENGTH 0x1 #define _TXB1DLC_TXB1DLC0_MASK 0x1 #define _TXB1DLC_TXB1DLC1_POSN 0x1 #define _TXB1DLC_TXB1DLC1_POSITION 0x1 #define _TXB1DLC_TXB1DLC1_SIZE 0x1 #define _TXB1DLC_TXB1DLC1_LENGTH 0x1 #define _TXB1DLC_TXB1DLC1_MASK 0x2 #define _TXB1DLC_TXB1DLC2_POSN 0x2 #define _TXB1DLC_TXB1DLC2_POSITION 0x2 #define _TXB1DLC_TXB1DLC2_SIZE 0x1 #define _TXB1DLC_TXB1DLC2_LENGTH 0x1 #define _TXB1DLC_TXB1DLC2_MASK 0x4 #define _TXB1DLC_TXB1DLC3_POSN 0x3 #define _TXB1DLC_TXB1DLC3_POSITION 0x3 #define _TXB1DLC_TXB1DLC3_SIZE 0x1 #define _TXB1DLC_TXB1DLC3_LENGTH 0x1 #define _TXB1DLC_TXB1DLC3_MASK 0x8 #define _TXB1DLC_TXB1RTR_POSN 0x6 #define _TXB1DLC_TXB1RTR_POSITION 0x6 #define _TXB1DLC_TXB1RTR_SIZE 0x1 #define _TXB1DLC_TXB1RTR_LENGTH 0x1 #define _TXB1DLC_TXB1RTR_MASK 0x40 // Register: TXB1D0 #define TXB1D0 TXB1D0 extern volatile unsigned char TXB1D0 @ 0xF16; #ifndef _LIB_BUILD asm("TXB1D0 equ 0F16h"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D0 :8; }; struct { unsigned TXB1D00 :1; unsigned TXB1D01 :1; unsigned TXB1D02 :1; unsigned TXB1D03 :1; unsigned TXB1D04 :1; unsigned TXB1D05 :1; unsigned TXB1D06 :1; unsigned TXB1D07 :1; }; } TXB1D0bits_t; extern volatile TXB1D0bits_t TXB1D0bits @ 0xF16; // bitfield macros #define _TXB1D0_TXB1D0_POSN 0x0 #define _TXB1D0_TXB1D0_POSITION 0x0 #define _TXB1D0_TXB1D0_SIZE 0x8 #define _TXB1D0_TXB1D0_LENGTH 0x8 #define _TXB1D0_TXB1D0_MASK 0xFF #define _TXB1D0_TXB1D00_POSN 0x0 #define _TXB1D0_TXB1D00_POSITION 0x0 #define _TXB1D0_TXB1D00_SIZE 0x1 #define _TXB1D0_TXB1D00_LENGTH 0x1 #define _TXB1D0_TXB1D00_MASK 0x1 #define _TXB1D0_TXB1D01_POSN 0x1 #define _TXB1D0_TXB1D01_POSITION 0x1 #define _TXB1D0_TXB1D01_SIZE 0x1 #define _TXB1D0_TXB1D01_LENGTH 0x1 #define _TXB1D0_TXB1D01_MASK 0x2 #define _TXB1D0_TXB1D02_POSN 0x2 #define _TXB1D0_TXB1D02_POSITION 0x2 #define _TXB1D0_TXB1D02_SIZE 0x1 #define _TXB1D0_TXB1D02_LENGTH 0x1 #define _TXB1D0_TXB1D02_MASK 0x4 #define _TXB1D0_TXB1D03_POSN 0x3 #define _TXB1D0_TXB1D03_POSITION 0x3 #define _TXB1D0_TXB1D03_SIZE 0x1 #define _TXB1D0_TXB1D03_LENGTH 0x1 #define _TXB1D0_TXB1D03_MASK 0x8 #define _TXB1D0_TXB1D04_POSN 0x4 #define _TXB1D0_TXB1D04_POSITION 0x4 #define _TXB1D0_TXB1D04_SIZE 0x1 #define _TXB1D0_TXB1D04_LENGTH 0x1 #define _TXB1D0_TXB1D04_MASK 0x10 #define _TXB1D0_TXB1D05_POSN 0x5 #define _TXB1D0_TXB1D05_POSITION 0x5 #define _TXB1D0_TXB1D05_SIZE 0x1 #define _TXB1D0_TXB1D05_LENGTH 0x1 #define _TXB1D0_TXB1D05_MASK 0x20 #define _TXB1D0_TXB1D06_POSN 0x6 #define _TXB1D0_TXB1D06_POSITION 0x6 #define _TXB1D0_TXB1D06_SIZE 0x1 #define _TXB1D0_TXB1D06_LENGTH 0x1 #define _TXB1D0_TXB1D06_MASK 0x40 #define _TXB1D0_TXB1D07_POSN 0x7 #define _TXB1D0_TXB1D07_POSITION 0x7 #define _TXB1D0_TXB1D07_SIZE 0x1 #define _TXB1D0_TXB1D07_LENGTH 0x1 #define _TXB1D0_TXB1D07_MASK 0x80 // Register: TXB1D1 #define TXB1D1 TXB1D1 extern volatile unsigned char TXB1D1 @ 0xF17; #ifndef _LIB_BUILD asm("TXB1D1 equ 0F17h"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D1 :8; }; struct { unsigned TXB1D10 :1; unsigned TXB1D11 :1; unsigned TXB1D12 :1; unsigned TXB1D13 :1; unsigned TXB1D14 :1; unsigned TXB1D15 :1; unsigned TXB1D16 :1; unsigned TXB1D17 :1; }; } TXB1D1bits_t; extern volatile TXB1D1bits_t TXB1D1bits @ 0xF17; // bitfield macros #define _TXB1D1_TXB1D1_POSN 0x0 #define _TXB1D1_TXB1D1_POSITION 0x0 #define _TXB1D1_TXB1D1_SIZE 0x8 #define _TXB1D1_TXB1D1_LENGTH 0x8 #define _TXB1D1_TXB1D1_MASK 0xFF #define _TXB1D1_TXB1D10_POSN 0x0 #define _TXB1D1_TXB1D10_POSITION 0x0 #define _TXB1D1_TXB1D10_SIZE 0x1 #define _TXB1D1_TXB1D10_LENGTH 0x1 #define _TXB1D1_TXB1D10_MASK 0x1 #define _TXB1D1_TXB1D11_POSN 0x1 #define _TXB1D1_TXB1D11_POSITION 0x1 #define _TXB1D1_TXB1D11_SIZE 0x1 #define _TXB1D1_TXB1D11_LENGTH 0x1 #define _TXB1D1_TXB1D11_MASK 0x2 #define _TXB1D1_TXB1D12_POSN 0x2 #define _TXB1D1_TXB1D12_POSITION 0x2 #define _TXB1D1_TXB1D12_SIZE 0x1 #define _TXB1D1_TXB1D12_LENGTH 0x1 #define _TXB1D1_TXB1D12_MASK 0x4 #define _TXB1D1_TXB1D13_POSN 0x3 #define _TXB1D1_TXB1D13_POSITION 0x3 #define _TXB1D1_TXB1D13_SIZE 0x1 #define _TXB1D1_TXB1D13_LENGTH 0x1 #define _TXB1D1_TXB1D13_MASK 0x8 #define _TXB1D1_TXB1D14_POSN 0x4 #define _TXB1D1_TXB1D14_POSITION 0x4 #define _TXB1D1_TXB1D14_SIZE 0x1 #define _TXB1D1_TXB1D14_LENGTH 0x1 #define _TXB1D1_TXB1D14_MASK 0x10 #define _TXB1D1_TXB1D15_POSN 0x5 #define _TXB1D1_TXB1D15_POSITION 0x5 #define _TXB1D1_TXB1D15_SIZE 0x1 #define _TXB1D1_TXB1D15_LENGTH 0x1 #define _TXB1D1_TXB1D15_MASK 0x20 #define _TXB1D1_TXB1D16_POSN 0x6 #define _TXB1D1_TXB1D16_POSITION 0x6 #define _TXB1D1_TXB1D16_SIZE 0x1 #define _TXB1D1_TXB1D16_LENGTH 0x1 #define _TXB1D1_TXB1D16_MASK 0x40 #define _TXB1D1_TXB1D17_POSN 0x7 #define _TXB1D1_TXB1D17_POSITION 0x7 #define _TXB1D1_TXB1D17_SIZE 0x1 #define _TXB1D1_TXB1D17_LENGTH 0x1 #define _TXB1D1_TXB1D17_MASK 0x80 // Register: TXB1D2 #define TXB1D2 TXB1D2 extern volatile unsigned char TXB1D2 @ 0xF18; #ifndef _LIB_BUILD asm("TXB1D2 equ 0F18h"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D2 :8; }; struct { unsigned TXB1D20 :1; unsigned TXB1D21 :1; unsigned TXB1D22 :1; unsigned TXB1D23 :1; unsigned TXB1D24 :1; unsigned TXB1D25 :1; unsigned TXB1D26 :1; unsigned TXB1D27 :1; }; } TXB1D2bits_t; extern volatile TXB1D2bits_t TXB1D2bits @ 0xF18; // bitfield macros #define _TXB1D2_TXB1D2_POSN 0x0 #define _TXB1D2_TXB1D2_POSITION 0x0 #define _TXB1D2_TXB1D2_SIZE 0x8 #define _TXB1D2_TXB1D2_LENGTH 0x8 #define _TXB1D2_TXB1D2_MASK 0xFF #define _TXB1D2_TXB1D20_POSN 0x0 #define _TXB1D2_TXB1D20_POSITION 0x0 #define _TXB1D2_TXB1D20_SIZE 0x1 #define _TXB1D2_TXB1D20_LENGTH 0x1 #define _TXB1D2_TXB1D20_MASK 0x1 #define _TXB1D2_TXB1D21_POSN 0x1 #define _TXB1D2_TXB1D21_POSITION 0x1 #define _TXB1D2_TXB1D21_SIZE 0x1 #define _TXB1D2_TXB1D21_LENGTH 0x1 #define _TXB1D2_TXB1D21_MASK 0x2 #define _TXB1D2_TXB1D22_POSN 0x2 #define _TXB1D2_TXB1D22_POSITION 0x2 #define _TXB1D2_TXB1D22_SIZE 0x1 #define _TXB1D2_TXB1D22_LENGTH 0x1 #define _TXB1D2_TXB1D22_MASK 0x4 #define _TXB1D2_TXB1D23_POSN 0x3 #define _TXB1D2_TXB1D23_POSITION 0x3 #define _TXB1D2_TXB1D23_SIZE 0x1 #define _TXB1D2_TXB1D23_LENGTH 0x1 #define _TXB1D2_TXB1D23_MASK 0x8 #define _TXB1D2_TXB1D24_POSN 0x4 #define _TXB1D2_TXB1D24_POSITION 0x4 #define _TXB1D2_TXB1D24_SIZE 0x1 #define _TXB1D2_TXB1D24_LENGTH 0x1 #define _TXB1D2_TXB1D24_MASK 0x10 #define _TXB1D2_TXB1D25_POSN 0x5 #define _TXB1D2_TXB1D25_POSITION 0x5 #define _TXB1D2_TXB1D25_SIZE 0x1 #define _TXB1D2_TXB1D25_LENGTH 0x1 #define _TXB1D2_TXB1D25_MASK 0x20 #define _TXB1D2_TXB1D26_POSN 0x6 #define _TXB1D2_TXB1D26_POSITION 0x6 #define _TXB1D2_TXB1D26_SIZE 0x1 #define _TXB1D2_TXB1D26_LENGTH 0x1 #define _TXB1D2_TXB1D26_MASK 0x40 #define _TXB1D2_TXB1D27_POSN 0x7 #define _TXB1D2_TXB1D27_POSITION 0x7 #define _TXB1D2_TXB1D27_SIZE 0x1 #define _TXB1D2_TXB1D27_LENGTH 0x1 #define _TXB1D2_TXB1D27_MASK 0x80 // Register: TXB1D3 #define TXB1D3 TXB1D3 extern volatile unsigned char TXB1D3 @ 0xF19; #ifndef _LIB_BUILD asm("TXB1D3 equ 0F19h"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D3 :8; }; struct { unsigned TXB1D30 :1; unsigned TXB1D31 :1; unsigned TXB1D32 :1; unsigned TXB1D33 :1; unsigned TXB1D34 :1; unsigned TXB1D35 :1; unsigned TXB1D36 :1; unsigned TXB1D37 :1; }; } TXB1D3bits_t; extern volatile TXB1D3bits_t TXB1D3bits @ 0xF19; // bitfield macros #define _TXB1D3_TXB1D3_POSN 0x0 #define _TXB1D3_TXB1D3_POSITION 0x0 #define _TXB1D3_TXB1D3_SIZE 0x8 #define _TXB1D3_TXB1D3_LENGTH 0x8 #define _TXB1D3_TXB1D3_MASK 0xFF #define _TXB1D3_TXB1D30_POSN 0x0 #define _TXB1D3_TXB1D30_POSITION 0x0 #define _TXB1D3_TXB1D30_SIZE 0x1 #define _TXB1D3_TXB1D30_LENGTH 0x1 #define _TXB1D3_TXB1D30_MASK 0x1 #define _TXB1D3_TXB1D31_POSN 0x1 #define _TXB1D3_TXB1D31_POSITION 0x1 #define _TXB1D3_TXB1D31_SIZE 0x1 #define _TXB1D3_TXB1D31_LENGTH 0x1 #define _TXB1D3_TXB1D31_MASK 0x2 #define _TXB1D3_TXB1D32_POSN 0x2 #define _TXB1D3_TXB1D32_POSITION 0x2 #define _TXB1D3_TXB1D32_SIZE 0x1 #define _TXB1D3_TXB1D32_LENGTH 0x1 #define _TXB1D3_TXB1D32_MASK 0x4 #define _TXB1D3_TXB1D33_POSN 0x3 #define _TXB1D3_TXB1D33_POSITION 0x3 #define _TXB1D3_TXB1D33_SIZE 0x1 #define _TXB1D3_TXB1D33_LENGTH 0x1 #define _TXB1D3_TXB1D33_MASK 0x8 #define _TXB1D3_TXB1D34_POSN 0x4 #define _TXB1D3_TXB1D34_POSITION 0x4 #define _TXB1D3_TXB1D34_SIZE 0x1 #define _TXB1D3_TXB1D34_LENGTH 0x1 #define _TXB1D3_TXB1D34_MASK 0x10 #define _TXB1D3_TXB1D35_POSN 0x5 #define _TXB1D3_TXB1D35_POSITION 0x5 #define _TXB1D3_TXB1D35_SIZE 0x1 #define _TXB1D3_TXB1D35_LENGTH 0x1 #define _TXB1D3_TXB1D35_MASK 0x20 #define _TXB1D3_TXB1D36_POSN 0x6 #define _TXB1D3_TXB1D36_POSITION 0x6 #define _TXB1D3_TXB1D36_SIZE 0x1 #define _TXB1D3_TXB1D36_LENGTH 0x1 #define _TXB1D3_TXB1D36_MASK 0x40 #define _TXB1D3_TXB1D37_POSN 0x7 #define _TXB1D3_TXB1D37_POSITION 0x7 #define _TXB1D3_TXB1D37_SIZE 0x1 #define _TXB1D3_TXB1D37_LENGTH 0x1 #define _TXB1D3_TXB1D37_MASK 0x80 // Register: TXB1D4 #define TXB1D4 TXB1D4 extern volatile unsigned char TXB1D4 @ 0xF1A; #ifndef _LIB_BUILD asm("TXB1D4 equ 0F1Ah"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D4 :8; }; struct { unsigned TXB1D40 :1; unsigned TXB1D41 :1; unsigned TXB1D42 :1; unsigned TXB1D43 :1; unsigned TXB1D44 :1; unsigned TXB1D45 :1; unsigned TXB1D46 :1; unsigned TXB1D47 :1; }; } TXB1D4bits_t; extern volatile TXB1D4bits_t TXB1D4bits @ 0xF1A; // bitfield macros #define _TXB1D4_TXB1D4_POSN 0x0 #define _TXB1D4_TXB1D4_POSITION 0x0 #define _TXB1D4_TXB1D4_SIZE 0x8 #define _TXB1D4_TXB1D4_LENGTH 0x8 #define _TXB1D4_TXB1D4_MASK 0xFF #define _TXB1D4_TXB1D40_POSN 0x0 #define _TXB1D4_TXB1D40_POSITION 0x0 #define _TXB1D4_TXB1D40_SIZE 0x1 #define _TXB1D4_TXB1D40_LENGTH 0x1 #define _TXB1D4_TXB1D40_MASK 0x1 #define _TXB1D4_TXB1D41_POSN 0x1 #define _TXB1D4_TXB1D41_POSITION 0x1 #define _TXB1D4_TXB1D41_SIZE 0x1 #define _TXB1D4_TXB1D41_LENGTH 0x1 #define _TXB1D4_TXB1D41_MASK 0x2 #define _TXB1D4_TXB1D42_POSN 0x2 #define _TXB1D4_TXB1D42_POSITION 0x2 #define _TXB1D4_TXB1D42_SIZE 0x1 #define _TXB1D4_TXB1D42_LENGTH 0x1 #define _TXB1D4_TXB1D42_MASK 0x4 #define _TXB1D4_TXB1D43_POSN 0x3 #define _TXB1D4_TXB1D43_POSITION 0x3 #define _TXB1D4_TXB1D43_SIZE 0x1 #define _TXB1D4_TXB1D43_LENGTH 0x1 #define _TXB1D4_TXB1D43_MASK 0x8 #define _TXB1D4_TXB1D44_POSN 0x4 #define _TXB1D4_TXB1D44_POSITION 0x4 #define _TXB1D4_TXB1D44_SIZE 0x1 #define _TXB1D4_TXB1D44_LENGTH 0x1 #define _TXB1D4_TXB1D44_MASK 0x10 #define _TXB1D4_TXB1D45_POSN 0x5 #define _TXB1D4_TXB1D45_POSITION 0x5 #define _TXB1D4_TXB1D45_SIZE 0x1 #define _TXB1D4_TXB1D45_LENGTH 0x1 #define _TXB1D4_TXB1D45_MASK 0x20 #define _TXB1D4_TXB1D46_POSN 0x6 #define _TXB1D4_TXB1D46_POSITION 0x6 #define _TXB1D4_TXB1D46_SIZE 0x1 #define _TXB1D4_TXB1D46_LENGTH 0x1 #define _TXB1D4_TXB1D46_MASK 0x40 #define _TXB1D4_TXB1D47_POSN 0x7 #define _TXB1D4_TXB1D47_POSITION 0x7 #define _TXB1D4_TXB1D47_SIZE 0x1 #define _TXB1D4_TXB1D47_LENGTH 0x1 #define _TXB1D4_TXB1D47_MASK 0x80 // Register: TXB1D5 #define TXB1D5 TXB1D5 extern volatile unsigned char TXB1D5 @ 0xF1B; #ifndef _LIB_BUILD asm("TXB1D5 equ 0F1Bh"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D5 :8; }; struct { unsigned TXB1D50 :1; unsigned TXB1D51 :1; unsigned TXB1D52 :1; unsigned TXB1D53 :1; unsigned TXB1D54 :1; unsigned TXB1D55 :1; unsigned TXB1D56 :1; unsigned TXB1D57 :1; }; } TXB1D5bits_t; extern volatile TXB1D5bits_t TXB1D5bits @ 0xF1B; // bitfield macros #define _TXB1D5_TXB1D5_POSN 0x0 #define _TXB1D5_TXB1D5_POSITION 0x0 #define _TXB1D5_TXB1D5_SIZE 0x8 #define _TXB1D5_TXB1D5_LENGTH 0x8 #define _TXB1D5_TXB1D5_MASK 0xFF #define _TXB1D5_TXB1D50_POSN 0x0 #define _TXB1D5_TXB1D50_POSITION 0x0 #define _TXB1D5_TXB1D50_SIZE 0x1 #define _TXB1D5_TXB1D50_LENGTH 0x1 #define _TXB1D5_TXB1D50_MASK 0x1 #define _TXB1D5_TXB1D51_POSN 0x1 #define _TXB1D5_TXB1D51_POSITION 0x1 #define _TXB1D5_TXB1D51_SIZE 0x1 #define _TXB1D5_TXB1D51_LENGTH 0x1 #define _TXB1D5_TXB1D51_MASK 0x2 #define _TXB1D5_TXB1D52_POSN 0x2 #define _TXB1D5_TXB1D52_POSITION 0x2 #define _TXB1D5_TXB1D52_SIZE 0x1 #define _TXB1D5_TXB1D52_LENGTH 0x1 #define _TXB1D5_TXB1D52_MASK 0x4 #define _TXB1D5_TXB1D53_POSN 0x3 #define _TXB1D5_TXB1D53_POSITION 0x3 #define _TXB1D5_TXB1D53_SIZE 0x1 #define _TXB1D5_TXB1D53_LENGTH 0x1 #define _TXB1D5_TXB1D53_MASK 0x8 #define _TXB1D5_TXB1D54_POSN 0x4 #define _TXB1D5_TXB1D54_POSITION 0x4 #define _TXB1D5_TXB1D54_SIZE 0x1 #define _TXB1D5_TXB1D54_LENGTH 0x1 #define _TXB1D5_TXB1D54_MASK 0x10 #define _TXB1D5_TXB1D55_POSN 0x5 #define _TXB1D5_TXB1D55_POSITION 0x5 #define _TXB1D5_TXB1D55_SIZE 0x1 #define _TXB1D5_TXB1D55_LENGTH 0x1 #define _TXB1D5_TXB1D55_MASK 0x20 #define _TXB1D5_TXB1D56_POSN 0x6 #define _TXB1D5_TXB1D56_POSITION 0x6 #define _TXB1D5_TXB1D56_SIZE 0x1 #define _TXB1D5_TXB1D56_LENGTH 0x1 #define _TXB1D5_TXB1D56_MASK 0x40 #define _TXB1D5_TXB1D57_POSN 0x7 #define _TXB1D5_TXB1D57_POSITION 0x7 #define _TXB1D5_TXB1D57_SIZE 0x1 #define _TXB1D5_TXB1D57_LENGTH 0x1 #define _TXB1D5_TXB1D57_MASK 0x80 // Register: TXB1D6 #define TXB1D6 TXB1D6 extern volatile unsigned char TXB1D6 @ 0xF1C; #ifndef _LIB_BUILD asm("TXB1D6 equ 0F1Ch"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D6 :8; }; struct { unsigned TXB1D60 :1; unsigned TXB1D61 :1; unsigned TXB1D62 :1; unsigned TXB1D63 :1; unsigned TXB1D64 :1; unsigned TXB1D65 :1; unsigned TXB1D66 :1; unsigned TXB1D67 :1; }; } TXB1D6bits_t; extern volatile TXB1D6bits_t TXB1D6bits @ 0xF1C; // bitfield macros #define _TXB1D6_TXB1D6_POSN 0x0 #define _TXB1D6_TXB1D6_POSITION 0x0 #define _TXB1D6_TXB1D6_SIZE 0x8 #define _TXB1D6_TXB1D6_LENGTH 0x8 #define _TXB1D6_TXB1D6_MASK 0xFF #define _TXB1D6_TXB1D60_POSN 0x0 #define _TXB1D6_TXB1D60_POSITION 0x0 #define _TXB1D6_TXB1D60_SIZE 0x1 #define _TXB1D6_TXB1D60_LENGTH 0x1 #define _TXB1D6_TXB1D60_MASK 0x1 #define _TXB1D6_TXB1D61_POSN 0x1 #define _TXB1D6_TXB1D61_POSITION 0x1 #define _TXB1D6_TXB1D61_SIZE 0x1 #define _TXB1D6_TXB1D61_LENGTH 0x1 #define _TXB1D6_TXB1D61_MASK 0x2 #define _TXB1D6_TXB1D62_POSN 0x2 #define _TXB1D6_TXB1D62_POSITION 0x2 #define _TXB1D6_TXB1D62_SIZE 0x1 #define _TXB1D6_TXB1D62_LENGTH 0x1 #define _TXB1D6_TXB1D62_MASK 0x4 #define _TXB1D6_TXB1D63_POSN 0x3 #define _TXB1D6_TXB1D63_POSITION 0x3 #define _TXB1D6_TXB1D63_SIZE 0x1 #define _TXB1D6_TXB1D63_LENGTH 0x1 #define _TXB1D6_TXB1D63_MASK 0x8 #define _TXB1D6_TXB1D64_POSN 0x4 #define _TXB1D6_TXB1D64_POSITION 0x4 #define _TXB1D6_TXB1D64_SIZE 0x1 #define _TXB1D6_TXB1D64_LENGTH 0x1 #define _TXB1D6_TXB1D64_MASK 0x10 #define _TXB1D6_TXB1D65_POSN 0x5 #define _TXB1D6_TXB1D65_POSITION 0x5 #define _TXB1D6_TXB1D65_SIZE 0x1 #define _TXB1D6_TXB1D65_LENGTH 0x1 #define _TXB1D6_TXB1D65_MASK 0x20 #define _TXB1D6_TXB1D66_POSN 0x6 #define _TXB1D6_TXB1D66_POSITION 0x6 #define _TXB1D6_TXB1D66_SIZE 0x1 #define _TXB1D6_TXB1D66_LENGTH 0x1 #define _TXB1D6_TXB1D66_MASK 0x40 #define _TXB1D6_TXB1D67_POSN 0x7 #define _TXB1D6_TXB1D67_POSITION 0x7 #define _TXB1D6_TXB1D67_SIZE 0x1 #define _TXB1D6_TXB1D67_LENGTH 0x1 #define _TXB1D6_TXB1D67_MASK 0x80 // Register: TXB1D7 #define TXB1D7 TXB1D7 extern volatile unsigned char TXB1D7 @ 0xF1D; #ifndef _LIB_BUILD asm("TXB1D7 equ 0F1Dh"); #endif // bitfield definitions typedef union { struct { unsigned TXB1D7 :8; }; struct { unsigned TXB1D70 :1; unsigned TXB1D71 :1; unsigned TXB1D72 :1; unsigned TXB1D73 :1; unsigned TXB1D74 :1; unsigned TXB1D75 :1; unsigned TXB1D76 :1; unsigned TXB1D77 :1; }; } TXB1D7bits_t; extern volatile TXB1D7bits_t TXB1D7bits @ 0xF1D; // bitfield macros #define _TXB1D7_TXB1D7_POSN 0x0 #define _TXB1D7_TXB1D7_POSITION 0x0 #define _TXB1D7_TXB1D7_SIZE 0x8 #define _TXB1D7_TXB1D7_LENGTH 0x8 #define _TXB1D7_TXB1D7_MASK 0xFF #define _TXB1D7_TXB1D70_POSN 0x0 #define _TXB1D7_TXB1D70_POSITION 0x0 #define _TXB1D7_TXB1D70_SIZE 0x1 #define _TXB1D7_TXB1D70_LENGTH 0x1 #define _TXB1D7_TXB1D70_MASK 0x1 #define _TXB1D7_TXB1D71_POSN 0x1 #define _TXB1D7_TXB1D71_POSITION 0x1 #define _TXB1D7_TXB1D71_SIZE 0x1 #define _TXB1D7_TXB1D71_LENGTH 0x1 #define _TXB1D7_TXB1D71_MASK 0x2 #define _TXB1D7_TXB1D72_POSN 0x2 #define _TXB1D7_TXB1D72_POSITION 0x2 #define _TXB1D7_TXB1D72_SIZE 0x1 #define _TXB1D7_TXB1D72_LENGTH 0x1 #define _TXB1D7_TXB1D72_MASK 0x4 #define _TXB1D7_TXB1D73_POSN 0x3 #define _TXB1D7_TXB1D73_POSITION 0x3 #define _TXB1D7_TXB1D73_SIZE 0x1 #define _TXB1D7_TXB1D73_LENGTH 0x1 #define _TXB1D7_TXB1D73_MASK 0x8 #define _TXB1D7_TXB1D74_POSN 0x4 #define _TXB1D7_TXB1D74_POSITION 0x4 #define _TXB1D7_TXB1D74_SIZE 0x1 #define _TXB1D7_TXB1D74_LENGTH 0x1 #define _TXB1D7_TXB1D74_MASK 0x10 #define _TXB1D7_TXB1D75_POSN 0x5 #define _TXB1D7_TXB1D75_POSITION 0x5 #define _TXB1D7_TXB1D75_SIZE 0x1 #define _TXB1D7_TXB1D75_LENGTH 0x1 #define _TXB1D7_TXB1D75_MASK 0x20 #define _TXB1D7_TXB1D76_POSN 0x6 #define _TXB1D7_TXB1D76_POSITION 0x6 #define _TXB1D7_TXB1D76_SIZE 0x1 #define _TXB1D7_TXB1D76_LENGTH 0x1 #define _TXB1D7_TXB1D76_MASK 0x40 #define _TXB1D7_TXB1D77_POSN 0x7 #define _TXB1D7_TXB1D77_POSITION 0x7 #define _TXB1D7_TXB1D77_SIZE 0x1 #define _TXB1D7_TXB1D77_LENGTH 0x1 #define _TXB1D7_TXB1D77_MASK 0x80 // Register: CANSTAT_RO2 #define CANSTAT_RO2 CANSTAT_RO2 extern volatile unsigned char CANSTAT_RO2 @ 0xF1E; #ifndef _LIB_BUILD asm("CANSTAT_RO2 equ 0F1Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE20 :1; unsigned ICODE21 :1; unsigned ICODE2 :1; }; } CANSTAT_RO2bits_t; extern volatile CANSTAT_RO2bits_t CANSTAT_RO2bits @ 0xF1E; // bitfield macros #define _CANSTAT_RO2_EICODE0_POSN 0x0 #define _CANSTAT_RO2_EICODE0_POSITION 0x0 #define _CANSTAT_RO2_EICODE0_SIZE 0x1 #define _CANSTAT_RO2_EICODE0_LENGTH 0x1 #define _CANSTAT_RO2_EICODE0_MASK 0x1 #define _CANSTAT_RO2_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO2_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO2_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO2_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO2_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO2_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO2_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO2_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO2_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO2_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO2_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO2_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO2_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO2_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO2_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO2_EICODE4_POSN 0x4 #define _CANSTAT_RO2_EICODE4_POSITION 0x4 #define _CANSTAT_RO2_EICODE4_SIZE 0x1 #define _CANSTAT_RO2_EICODE4_LENGTH 0x1 #define _CANSTAT_RO2_EICODE4_MASK 0x10 #define _CANSTAT_RO2_OPMODE_POSN 0x5 #define _CANSTAT_RO2_OPMODE_POSITION 0x5 #define _CANSTAT_RO2_OPMODE_SIZE 0x3 #define _CANSTAT_RO2_OPMODE_LENGTH 0x3 #define _CANSTAT_RO2_OPMODE_MASK 0xE0 #define _CANSTAT_RO2_EICODE1_POSN 0x1 #define _CANSTAT_RO2_EICODE1_POSITION 0x1 #define _CANSTAT_RO2_EICODE1_SIZE 0x1 #define _CANSTAT_RO2_EICODE1_LENGTH 0x1 #define _CANSTAT_RO2_EICODE1_MASK 0x2 #define _CANSTAT_RO2_EICODE2_POSN 0x2 #define _CANSTAT_RO2_EICODE2_POSITION 0x2 #define _CANSTAT_RO2_EICODE2_SIZE 0x1 #define _CANSTAT_RO2_EICODE2_LENGTH 0x1 #define _CANSTAT_RO2_EICODE2_MASK 0x4 #define _CANSTAT_RO2_EICODE3_POSN 0x3 #define _CANSTAT_RO2_EICODE3_POSITION 0x3 #define _CANSTAT_RO2_EICODE3_SIZE 0x1 #define _CANSTAT_RO2_EICODE3_LENGTH 0x1 #define _CANSTAT_RO2_EICODE3_MASK 0x8 #define _CANSTAT_RO2_OPMODE0_POSN 0x5 #define _CANSTAT_RO2_OPMODE0_POSITION 0x5 #define _CANSTAT_RO2_OPMODE0_SIZE 0x1 #define _CANSTAT_RO2_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO2_OPMODE0_MASK 0x20 #define _CANSTAT_RO2_OPMODE1_POSN 0x6 #define _CANSTAT_RO2_OPMODE1_POSITION 0x6 #define _CANSTAT_RO2_OPMODE1_SIZE 0x1 #define _CANSTAT_RO2_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO2_OPMODE1_MASK 0x40 #define _CANSTAT_RO2_OPMODE2_POSN 0x7 #define _CANSTAT_RO2_OPMODE2_POSITION 0x7 #define _CANSTAT_RO2_OPMODE2_SIZE 0x1 #define _CANSTAT_RO2_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO2_OPMODE2_MASK 0x80 #define _CANSTAT_RO2_ICODE20_POSN 0x1 #define _CANSTAT_RO2_ICODE20_POSITION 0x1 #define _CANSTAT_RO2_ICODE20_SIZE 0x1 #define _CANSTAT_RO2_ICODE20_LENGTH 0x1 #define _CANSTAT_RO2_ICODE20_MASK 0x2 #define _CANSTAT_RO2_ICODE21_POSN 0x2 #define _CANSTAT_RO2_ICODE21_POSITION 0x2 #define _CANSTAT_RO2_ICODE21_SIZE 0x1 #define _CANSTAT_RO2_ICODE21_LENGTH 0x1 #define _CANSTAT_RO2_ICODE21_MASK 0x4 #define _CANSTAT_RO2_ICODE2_POSN 0x3 #define _CANSTAT_RO2_ICODE2_POSITION 0x3 #define _CANSTAT_RO2_ICODE2_SIZE 0x1 #define _CANSTAT_RO2_ICODE2_LENGTH 0x1 #define _CANSTAT_RO2_ICODE2_MASK 0x8 // Register: CANCON_RO2 #define CANCON_RO2 CANCON_RO2 extern volatile unsigned char CANCON_RO2 @ 0xF1F; #ifndef _LIB_BUILD asm("CANCON_RO2 equ 0F1Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO2bits_t; extern volatile CANCON_RO2bits_t CANCON_RO2bits @ 0xF1F; // bitfield macros #define _CANCON_RO2_FP0_POSN 0x0 #define _CANCON_RO2_FP0_POSITION 0x0 #define _CANCON_RO2_FP0_SIZE 0x1 #define _CANCON_RO2_FP0_LENGTH 0x1 #define _CANCON_RO2_FP0_MASK 0x1 #define _CANCON_RO2_WIN0_FP1_POSN 0x1 #define _CANCON_RO2_WIN0_FP1_POSITION 0x1 #define _CANCON_RO2_WIN0_FP1_SIZE 0x1 #define _CANCON_RO2_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO2_WIN0_FP1_MASK 0x2 #define _CANCON_RO2_WIN1_FP2_POSN 0x2 #define _CANCON_RO2_WIN1_FP2_POSITION 0x2 #define _CANCON_RO2_WIN1_FP2_SIZE 0x1 #define _CANCON_RO2_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO2_WIN1_FP2_MASK 0x4 #define _CANCON_RO2_WIN2_FP3_POSN 0x3 #define _CANCON_RO2_WIN2_FP3_POSITION 0x3 #define _CANCON_RO2_WIN2_FP3_SIZE 0x1 #define _CANCON_RO2_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO2_WIN2_FP3_MASK 0x8 #define _CANCON_RO2_ABAT_POSN 0x4 #define _CANCON_RO2_ABAT_POSITION 0x4 #define _CANCON_RO2_ABAT_SIZE 0x1 #define _CANCON_RO2_ABAT_LENGTH 0x1 #define _CANCON_RO2_ABAT_MASK 0x10 #define _CANCON_RO2_REQOP_POSN 0x5 #define _CANCON_RO2_REQOP_POSITION 0x5 #define _CANCON_RO2_REQOP_SIZE 0x3 #define _CANCON_RO2_REQOP_LENGTH 0x3 #define _CANCON_RO2_REQOP_MASK 0xE0 #define _CANCON_RO2_WIN0_POSN 0x1 #define _CANCON_RO2_WIN0_POSITION 0x1 #define _CANCON_RO2_WIN0_SIZE 0x1 #define _CANCON_RO2_WIN0_LENGTH 0x1 #define _CANCON_RO2_WIN0_MASK 0x2 #define _CANCON_RO2_WIN1_POSN 0x2 #define _CANCON_RO2_WIN1_POSITION 0x2 #define _CANCON_RO2_WIN1_SIZE 0x1 #define _CANCON_RO2_WIN1_LENGTH 0x1 #define _CANCON_RO2_WIN1_MASK 0x4 #define _CANCON_RO2_WIN2_POSN 0x3 #define _CANCON_RO2_WIN2_POSITION 0x3 #define _CANCON_RO2_WIN2_SIZE 0x1 #define _CANCON_RO2_WIN2_LENGTH 0x1 #define _CANCON_RO2_WIN2_MASK 0x8 #define _CANCON_RO2_FP1_POSN 0x1 #define _CANCON_RO2_FP1_POSITION 0x1 #define _CANCON_RO2_FP1_SIZE 0x1 #define _CANCON_RO2_FP1_LENGTH 0x1 #define _CANCON_RO2_FP1_MASK 0x2 #define _CANCON_RO2_FP2_POSN 0x2 #define _CANCON_RO2_FP2_POSITION 0x2 #define _CANCON_RO2_FP2_SIZE 0x1 #define _CANCON_RO2_FP2_LENGTH 0x1 #define _CANCON_RO2_FP2_MASK 0x4 #define _CANCON_RO2_FP3_POSN 0x3 #define _CANCON_RO2_FP3_POSITION 0x3 #define _CANCON_RO2_FP3_SIZE 0x1 #define _CANCON_RO2_FP3_LENGTH 0x1 #define _CANCON_RO2_FP3_MASK 0x8 // Register: TXB0CON #define TXB0CON TXB0CON extern volatile unsigned char TXB0CON @ 0xF20; #ifndef _LIB_BUILD asm("TXB0CON equ 0F20h"); #endif // bitfield definitions typedef union { struct { unsigned TXPRI :2; unsigned :1; unsigned TXREQ :1; unsigned TXERR :1; unsigned TXLARB :1; unsigned TXABT :1; unsigned TXBIF :1; }; struct { unsigned TXPRI0 :1; unsigned TXPRI1 :1; }; struct { unsigned TXB0PRI0 :1; unsigned TXB0PRI1 :1; unsigned :1; unsigned TXB0REQ :1; unsigned TXB0ERR :1; unsigned TXB0LARB :1; unsigned TXB0ABT :1; unsigned TX0IF :1; }; } TXB0CONbits_t; extern volatile TXB0CONbits_t TXB0CONbits @ 0xF20; // bitfield macros #define _TXB0CON_TXPRI_POSN 0x0 #define _TXB0CON_TXPRI_POSITION 0x0 #define _TXB0CON_TXPRI_SIZE 0x2 #define _TXB0CON_TXPRI_LENGTH 0x2 #define _TXB0CON_TXPRI_MASK 0x3 #define _TXB0CON_TXREQ_POSN 0x3 #define _TXB0CON_TXREQ_POSITION 0x3 #define _TXB0CON_TXREQ_SIZE 0x1 #define _TXB0CON_TXREQ_LENGTH 0x1 #define _TXB0CON_TXREQ_MASK 0x8 #define _TXB0CON_TXERR_POSN 0x4 #define _TXB0CON_TXERR_POSITION 0x4 #define _TXB0CON_TXERR_SIZE 0x1 #define _TXB0CON_TXERR_LENGTH 0x1 #define _TXB0CON_TXERR_MASK 0x10 #define _TXB0CON_TXLARB_POSN 0x5 #define _TXB0CON_TXLARB_POSITION 0x5 #define _TXB0CON_TXLARB_SIZE 0x1 #define _TXB0CON_TXLARB_LENGTH 0x1 #define _TXB0CON_TXLARB_MASK 0x20 #define _TXB0CON_TXABT_POSN 0x6 #define _TXB0CON_TXABT_POSITION 0x6 #define _TXB0CON_TXABT_SIZE 0x1 #define _TXB0CON_TXABT_LENGTH 0x1 #define _TXB0CON_TXABT_MASK 0x40 #define _TXB0CON_TXBIF_POSN 0x7 #define _TXB0CON_TXBIF_POSITION 0x7 #define _TXB0CON_TXBIF_SIZE 0x1 #define _TXB0CON_TXBIF_LENGTH 0x1 #define _TXB0CON_TXBIF_MASK 0x80 #define _TXB0CON_TXPRI0_POSN 0x0 #define _TXB0CON_TXPRI0_POSITION 0x0 #define _TXB0CON_TXPRI0_SIZE 0x1 #define _TXB0CON_TXPRI0_LENGTH 0x1 #define _TXB0CON_TXPRI0_MASK 0x1 #define _TXB0CON_TXPRI1_POSN 0x1 #define _TXB0CON_TXPRI1_POSITION 0x1 #define _TXB0CON_TXPRI1_SIZE 0x1 #define _TXB0CON_TXPRI1_LENGTH 0x1 #define _TXB0CON_TXPRI1_MASK 0x2 #define _TXB0CON_TXB0PRI0_POSN 0x0 #define _TXB0CON_TXB0PRI0_POSITION 0x0 #define _TXB0CON_TXB0PRI0_SIZE 0x1 #define _TXB0CON_TXB0PRI0_LENGTH 0x1 #define _TXB0CON_TXB0PRI0_MASK 0x1 #define _TXB0CON_TXB0PRI1_POSN 0x1 #define _TXB0CON_TXB0PRI1_POSITION 0x1 #define _TXB0CON_TXB0PRI1_SIZE 0x1 #define _TXB0CON_TXB0PRI1_LENGTH 0x1 #define _TXB0CON_TXB0PRI1_MASK 0x2 #define _TXB0CON_TXB0REQ_POSN 0x3 #define _TXB0CON_TXB0REQ_POSITION 0x3 #define _TXB0CON_TXB0REQ_SIZE 0x1 #define _TXB0CON_TXB0REQ_LENGTH 0x1 #define _TXB0CON_TXB0REQ_MASK 0x8 #define _TXB0CON_TXB0ERR_POSN 0x4 #define _TXB0CON_TXB0ERR_POSITION 0x4 #define _TXB0CON_TXB0ERR_SIZE 0x1 #define _TXB0CON_TXB0ERR_LENGTH 0x1 #define _TXB0CON_TXB0ERR_MASK 0x10 #define _TXB0CON_TXB0LARB_POSN 0x5 #define _TXB0CON_TXB0LARB_POSITION 0x5 #define _TXB0CON_TXB0LARB_SIZE 0x1 #define _TXB0CON_TXB0LARB_LENGTH 0x1 #define _TXB0CON_TXB0LARB_MASK 0x20 #define _TXB0CON_TXB0ABT_POSN 0x6 #define _TXB0CON_TXB0ABT_POSITION 0x6 #define _TXB0CON_TXB0ABT_SIZE 0x1 #define _TXB0CON_TXB0ABT_LENGTH 0x1 #define _TXB0CON_TXB0ABT_MASK 0x40 #define _TXB0CON_TX0IF_POSN 0x7 #define _TXB0CON_TX0IF_POSITION 0x7 #define _TXB0CON_TX0IF_SIZE 0x1 #define _TXB0CON_TX0IF_LENGTH 0x1 #define _TXB0CON_TX0IF_MASK 0x80 // Register: TXB0SIDH #define TXB0SIDH TXB0SIDH extern volatile unsigned char TXB0SIDH @ 0xF21; #ifndef _LIB_BUILD asm("TXB0SIDH equ 0F21h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned TXB0SID3 :1; unsigned TXB0SID4 :1; unsigned TXB0SID5 :1; unsigned TXB0SID6 :1; unsigned TXB0SID7 :1; unsigned TXB0SID8 :1; unsigned TXB0SID9 :1; unsigned TXB0SID10 :1; }; } TXB0SIDHbits_t; extern volatile TXB0SIDHbits_t TXB0SIDHbits @ 0xF21; // bitfield macros #define _TXB0SIDH_SID_POSN 0x0 #define _TXB0SIDH_SID_POSITION 0x0 #define _TXB0SIDH_SID_SIZE 0x8 #define _TXB0SIDH_SID_LENGTH 0x8 #define _TXB0SIDH_SID_MASK 0xFF #define _TXB0SIDH_SID3_POSN 0x0 #define _TXB0SIDH_SID3_POSITION 0x0 #define _TXB0SIDH_SID3_SIZE 0x1 #define _TXB0SIDH_SID3_LENGTH 0x1 #define _TXB0SIDH_SID3_MASK 0x1 #define _TXB0SIDH_SID4_POSN 0x1 #define _TXB0SIDH_SID4_POSITION 0x1 #define _TXB0SIDH_SID4_SIZE 0x1 #define _TXB0SIDH_SID4_LENGTH 0x1 #define _TXB0SIDH_SID4_MASK 0x2 #define _TXB0SIDH_SID5_POSN 0x2 #define _TXB0SIDH_SID5_POSITION 0x2 #define _TXB0SIDH_SID5_SIZE 0x1 #define _TXB0SIDH_SID5_LENGTH 0x1 #define _TXB0SIDH_SID5_MASK 0x4 #define _TXB0SIDH_SID6_POSN 0x3 #define _TXB0SIDH_SID6_POSITION 0x3 #define _TXB0SIDH_SID6_SIZE 0x1 #define _TXB0SIDH_SID6_LENGTH 0x1 #define _TXB0SIDH_SID6_MASK 0x8 #define _TXB0SIDH_SID7_POSN 0x4 #define _TXB0SIDH_SID7_POSITION 0x4 #define _TXB0SIDH_SID7_SIZE 0x1 #define _TXB0SIDH_SID7_LENGTH 0x1 #define _TXB0SIDH_SID7_MASK 0x10 #define _TXB0SIDH_SID8_POSN 0x5 #define _TXB0SIDH_SID8_POSITION 0x5 #define _TXB0SIDH_SID8_SIZE 0x1 #define _TXB0SIDH_SID8_LENGTH 0x1 #define _TXB0SIDH_SID8_MASK 0x20 #define _TXB0SIDH_SID9_POSN 0x6 #define _TXB0SIDH_SID9_POSITION 0x6 #define _TXB0SIDH_SID9_SIZE 0x1 #define _TXB0SIDH_SID9_LENGTH 0x1 #define _TXB0SIDH_SID9_MASK 0x40 #define _TXB0SIDH_SID10_POSN 0x7 #define _TXB0SIDH_SID10_POSITION 0x7 #define _TXB0SIDH_SID10_SIZE 0x1 #define _TXB0SIDH_SID10_LENGTH 0x1 #define _TXB0SIDH_SID10_MASK 0x80 #define _TXB0SIDH_TXB0SID3_POSN 0x0 #define _TXB0SIDH_TXB0SID3_POSITION 0x0 #define _TXB0SIDH_TXB0SID3_SIZE 0x1 #define _TXB0SIDH_TXB0SID3_LENGTH 0x1 #define _TXB0SIDH_TXB0SID3_MASK 0x1 #define _TXB0SIDH_TXB0SID4_POSN 0x1 #define _TXB0SIDH_TXB0SID4_POSITION 0x1 #define _TXB0SIDH_TXB0SID4_SIZE 0x1 #define _TXB0SIDH_TXB0SID4_LENGTH 0x1 #define _TXB0SIDH_TXB0SID4_MASK 0x2 #define _TXB0SIDH_TXB0SID5_POSN 0x2 #define _TXB0SIDH_TXB0SID5_POSITION 0x2 #define _TXB0SIDH_TXB0SID5_SIZE 0x1 #define _TXB0SIDH_TXB0SID5_LENGTH 0x1 #define _TXB0SIDH_TXB0SID5_MASK 0x4 #define _TXB0SIDH_TXB0SID6_POSN 0x3 #define _TXB0SIDH_TXB0SID6_POSITION 0x3 #define _TXB0SIDH_TXB0SID6_SIZE 0x1 #define _TXB0SIDH_TXB0SID6_LENGTH 0x1 #define _TXB0SIDH_TXB0SID6_MASK 0x8 #define _TXB0SIDH_TXB0SID7_POSN 0x4 #define _TXB0SIDH_TXB0SID7_POSITION 0x4 #define _TXB0SIDH_TXB0SID7_SIZE 0x1 #define _TXB0SIDH_TXB0SID7_LENGTH 0x1 #define _TXB0SIDH_TXB0SID7_MASK 0x10 #define _TXB0SIDH_TXB0SID8_POSN 0x5 #define _TXB0SIDH_TXB0SID8_POSITION 0x5 #define _TXB0SIDH_TXB0SID8_SIZE 0x1 #define _TXB0SIDH_TXB0SID8_LENGTH 0x1 #define _TXB0SIDH_TXB0SID8_MASK 0x20 #define _TXB0SIDH_TXB0SID9_POSN 0x6 #define _TXB0SIDH_TXB0SID9_POSITION 0x6 #define _TXB0SIDH_TXB0SID9_SIZE 0x1 #define _TXB0SIDH_TXB0SID9_LENGTH 0x1 #define _TXB0SIDH_TXB0SID9_MASK 0x40 #define _TXB0SIDH_TXB0SID10_POSN 0x7 #define _TXB0SIDH_TXB0SID10_POSITION 0x7 #define _TXB0SIDH_TXB0SID10_SIZE 0x1 #define _TXB0SIDH_TXB0SID10_LENGTH 0x1 #define _TXB0SIDH_TXB0SID10_MASK 0x80 // Register: TXB0SIDL #define TXB0SIDL TXB0SIDL extern volatile unsigned char TXB0SIDL @ 0xF22; #ifndef _LIB_BUILD asm("TXB0SIDL equ 0F22h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXIDE :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned TXB0EID16 :1; unsigned TXB0EID17 :1; unsigned :1; unsigned TXB0EXIDE :1; unsigned :1; unsigned TXB0SID0 :1; unsigned TXB0SID1 :1; unsigned TXB0SID2 :1; }; } TXB0SIDLbits_t; extern volatile TXB0SIDLbits_t TXB0SIDLbits @ 0xF22; // bitfield macros #define _TXB0SIDL_EID_POSN 0x0 #define _TXB0SIDL_EID_POSITION 0x0 #define _TXB0SIDL_EID_SIZE 0x2 #define _TXB0SIDL_EID_LENGTH 0x2 #define _TXB0SIDL_EID_MASK 0x3 #define _TXB0SIDL_EXIDE_POSN 0x3 #define _TXB0SIDL_EXIDE_POSITION 0x3 #define _TXB0SIDL_EXIDE_SIZE 0x1 #define _TXB0SIDL_EXIDE_LENGTH 0x1 #define _TXB0SIDL_EXIDE_MASK 0x8 #define _TXB0SIDL_SRR_POSN 0x4 #define _TXB0SIDL_SRR_POSITION 0x4 #define _TXB0SIDL_SRR_SIZE 0x1 #define _TXB0SIDL_SRR_LENGTH 0x1 #define _TXB0SIDL_SRR_MASK 0x10 #define _TXB0SIDL_SID_POSN 0x5 #define _TXB0SIDL_SID_POSITION 0x5 #define _TXB0SIDL_SID_SIZE 0x3 #define _TXB0SIDL_SID_LENGTH 0x3 #define _TXB0SIDL_SID_MASK 0xE0 #define _TXB0SIDL_EID16_POSN 0x0 #define _TXB0SIDL_EID16_POSITION 0x0 #define _TXB0SIDL_EID16_SIZE 0x1 #define _TXB0SIDL_EID16_LENGTH 0x1 #define _TXB0SIDL_EID16_MASK 0x1 #define _TXB0SIDL_EID17_POSN 0x1 #define _TXB0SIDL_EID17_POSITION 0x1 #define _TXB0SIDL_EID17_SIZE 0x1 #define _TXB0SIDL_EID17_LENGTH 0x1 #define _TXB0SIDL_EID17_MASK 0x2 #define _TXB0SIDL_SID0_POSN 0x5 #define _TXB0SIDL_SID0_POSITION 0x5 #define _TXB0SIDL_SID0_SIZE 0x1 #define _TXB0SIDL_SID0_LENGTH 0x1 #define _TXB0SIDL_SID0_MASK 0x20 #define _TXB0SIDL_SID1_POSN 0x6 #define _TXB0SIDL_SID1_POSITION 0x6 #define _TXB0SIDL_SID1_SIZE 0x1 #define _TXB0SIDL_SID1_LENGTH 0x1 #define _TXB0SIDL_SID1_MASK 0x40 #define _TXB0SIDL_SID2_POSN 0x7 #define _TXB0SIDL_SID2_POSITION 0x7 #define _TXB0SIDL_SID2_SIZE 0x1 #define _TXB0SIDL_SID2_LENGTH 0x1 #define _TXB0SIDL_SID2_MASK 0x80 #define _TXB0SIDL_TXB0EID16_POSN 0x0 #define _TXB0SIDL_TXB0EID16_POSITION 0x0 #define _TXB0SIDL_TXB0EID16_SIZE 0x1 #define _TXB0SIDL_TXB0EID16_LENGTH 0x1 #define _TXB0SIDL_TXB0EID16_MASK 0x1 #define _TXB0SIDL_TXB0EID17_POSN 0x1 #define _TXB0SIDL_TXB0EID17_POSITION 0x1 #define _TXB0SIDL_TXB0EID17_SIZE 0x1 #define _TXB0SIDL_TXB0EID17_LENGTH 0x1 #define _TXB0SIDL_TXB0EID17_MASK 0x2 #define _TXB0SIDL_TXB0EXIDE_POSN 0x3 #define _TXB0SIDL_TXB0EXIDE_POSITION 0x3 #define _TXB0SIDL_TXB0EXIDE_SIZE 0x1 #define _TXB0SIDL_TXB0EXIDE_LENGTH 0x1 #define _TXB0SIDL_TXB0EXIDE_MASK 0x8 #define _TXB0SIDL_TXB0SID0_POSN 0x5 #define _TXB0SIDL_TXB0SID0_POSITION 0x5 #define _TXB0SIDL_TXB0SID0_SIZE 0x1 #define _TXB0SIDL_TXB0SID0_LENGTH 0x1 #define _TXB0SIDL_TXB0SID0_MASK 0x20 #define _TXB0SIDL_TXB0SID1_POSN 0x6 #define _TXB0SIDL_TXB0SID1_POSITION 0x6 #define _TXB0SIDL_TXB0SID1_SIZE 0x1 #define _TXB0SIDL_TXB0SID1_LENGTH 0x1 #define _TXB0SIDL_TXB0SID1_MASK 0x40 #define _TXB0SIDL_TXB0SID2_POSN 0x7 #define _TXB0SIDL_TXB0SID2_POSITION 0x7 #define _TXB0SIDL_TXB0SID2_SIZE 0x1 #define _TXB0SIDL_TXB0SID2_LENGTH 0x1 #define _TXB0SIDL_TXB0SID2_MASK 0x80 // Register: TXB0EIDH #define TXB0EIDH TXB0EIDH extern volatile unsigned char TXB0EIDH @ 0xF23; #ifndef _LIB_BUILD asm("TXB0EIDH equ 0F23h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned TXB0EID8 :1; unsigned TXB0EID9 :1; unsigned TXB0EID10 :1; unsigned TXB0EID11 :1; unsigned TXB0EID12 :1; unsigned TXB0EID13 :1; unsigned TXB0EID14 :1; unsigned TXB0EID15 :1; }; } TXB0EIDHbits_t; extern volatile TXB0EIDHbits_t TXB0EIDHbits @ 0xF23; // bitfield macros #define _TXB0EIDH_EID_POSN 0x0 #define _TXB0EIDH_EID_POSITION 0x0 #define _TXB0EIDH_EID_SIZE 0x8 #define _TXB0EIDH_EID_LENGTH 0x8 #define _TXB0EIDH_EID_MASK 0xFF #define _TXB0EIDH_EID8_POSN 0x0 #define _TXB0EIDH_EID8_POSITION 0x0 #define _TXB0EIDH_EID8_SIZE 0x1 #define _TXB0EIDH_EID8_LENGTH 0x1 #define _TXB0EIDH_EID8_MASK 0x1 #define _TXB0EIDH_EID9_POSN 0x1 #define _TXB0EIDH_EID9_POSITION 0x1 #define _TXB0EIDH_EID9_SIZE 0x1 #define _TXB0EIDH_EID9_LENGTH 0x1 #define _TXB0EIDH_EID9_MASK 0x2 #define _TXB0EIDH_EID10_POSN 0x2 #define _TXB0EIDH_EID10_POSITION 0x2 #define _TXB0EIDH_EID10_SIZE 0x1 #define _TXB0EIDH_EID10_LENGTH 0x1 #define _TXB0EIDH_EID10_MASK 0x4 #define _TXB0EIDH_EID11_POSN 0x3 #define _TXB0EIDH_EID11_POSITION 0x3 #define _TXB0EIDH_EID11_SIZE 0x1 #define _TXB0EIDH_EID11_LENGTH 0x1 #define _TXB0EIDH_EID11_MASK 0x8 #define _TXB0EIDH_EID12_POSN 0x4 #define _TXB0EIDH_EID12_POSITION 0x4 #define _TXB0EIDH_EID12_SIZE 0x1 #define _TXB0EIDH_EID12_LENGTH 0x1 #define _TXB0EIDH_EID12_MASK 0x10 #define _TXB0EIDH_EID13_POSN 0x5 #define _TXB0EIDH_EID13_POSITION 0x5 #define _TXB0EIDH_EID13_SIZE 0x1 #define _TXB0EIDH_EID13_LENGTH 0x1 #define _TXB0EIDH_EID13_MASK 0x20 #define _TXB0EIDH_EID14_POSN 0x6 #define _TXB0EIDH_EID14_POSITION 0x6 #define _TXB0EIDH_EID14_SIZE 0x1 #define _TXB0EIDH_EID14_LENGTH 0x1 #define _TXB0EIDH_EID14_MASK 0x40 #define _TXB0EIDH_EID15_POSN 0x7 #define _TXB0EIDH_EID15_POSITION 0x7 #define _TXB0EIDH_EID15_SIZE 0x1 #define _TXB0EIDH_EID15_LENGTH 0x1 #define _TXB0EIDH_EID15_MASK 0x80 #define _TXB0EIDH_TXB0EID8_POSN 0x0 #define _TXB0EIDH_TXB0EID8_POSITION 0x0 #define _TXB0EIDH_TXB0EID8_SIZE 0x1 #define _TXB0EIDH_TXB0EID8_LENGTH 0x1 #define _TXB0EIDH_TXB0EID8_MASK 0x1 #define _TXB0EIDH_TXB0EID9_POSN 0x1 #define _TXB0EIDH_TXB0EID9_POSITION 0x1 #define _TXB0EIDH_TXB0EID9_SIZE 0x1 #define _TXB0EIDH_TXB0EID9_LENGTH 0x1 #define _TXB0EIDH_TXB0EID9_MASK 0x2 #define _TXB0EIDH_TXB0EID10_POSN 0x2 #define _TXB0EIDH_TXB0EID10_POSITION 0x2 #define _TXB0EIDH_TXB0EID10_SIZE 0x1 #define _TXB0EIDH_TXB0EID10_LENGTH 0x1 #define _TXB0EIDH_TXB0EID10_MASK 0x4 #define _TXB0EIDH_TXB0EID11_POSN 0x3 #define _TXB0EIDH_TXB0EID11_POSITION 0x3 #define _TXB0EIDH_TXB0EID11_SIZE 0x1 #define _TXB0EIDH_TXB0EID11_LENGTH 0x1 #define _TXB0EIDH_TXB0EID11_MASK 0x8 #define _TXB0EIDH_TXB0EID12_POSN 0x4 #define _TXB0EIDH_TXB0EID12_POSITION 0x4 #define _TXB0EIDH_TXB0EID12_SIZE 0x1 #define _TXB0EIDH_TXB0EID12_LENGTH 0x1 #define _TXB0EIDH_TXB0EID12_MASK 0x10 #define _TXB0EIDH_TXB0EID13_POSN 0x5 #define _TXB0EIDH_TXB0EID13_POSITION 0x5 #define _TXB0EIDH_TXB0EID13_SIZE 0x1 #define _TXB0EIDH_TXB0EID13_LENGTH 0x1 #define _TXB0EIDH_TXB0EID13_MASK 0x20 #define _TXB0EIDH_TXB0EID14_POSN 0x6 #define _TXB0EIDH_TXB0EID14_POSITION 0x6 #define _TXB0EIDH_TXB0EID14_SIZE 0x1 #define _TXB0EIDH_TXB0EID14_LENGTH 0x1 #define _TXB0EIDH_TXB0EID14_MASK 0x40 #define _TXB0EIDH_TXB0EID15_POSN 0x7 #define _TXB0EIDH_TXB0EID15_POSITION 0x7 #define _TXB0EIDH_TXB0EID15_SIZE 0x1 #define _TXB0EIDH_TXB0EID15_LENGTH 0x1 #define _TXB0EIDH_TXB0EID15_MASK 0x80 // Register: TXB0EIDL #define TXB0EIDL TXB0EIDL extern volatile unsigned char TXB0EIDL @ 0xF24; #ifndef _LIB_BUILD asm("TXB0EIDL equ 0F24h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned TXB0EID0 :1; unsigned TXB0EID1 :1; unsigned TXB0EID2 :1; unsigned TXB0EID3 :1; unsigned TXB0EID4 :1; unsigned TXB0EID5 :1; unsigned TXB0EID6 :1; unsigned TXB0EID7 :1; }; } TXB0EIDLbits_t; extern volatile TXB0EIDLbits_t TXB0EIDLbits @ 0xF24; // bitfield macros #define _TXB0EIDL_EID_POSN 0x0 #define _TXB0EIDL_EID_POSITION 0x0 #define _TXB0EIDL_EID_SIZE 0x8 #define _TXB0EIDL_EID_LENGTH 0x8 #define _TXB0EIDL_EID_MASK 0xFF #define _TXB0EIDL_EID0_POSN 0x0 #define _TXB0EIDL_EID0_POSITION 0x0 #define _TXB0EIDL_EID0_SIZE 0x1 #define _TXB0EIDL_EID0_LENGTH 0x1 #define _TXB0EIDL_EID0_MASK 0x1 #define _TXB0EIDL_EID1_POSN 0x1 #define _TXB0EIDL_EID1_POSITION 0x1 #define _TXB0EIDL_EID1_SIZE 0x1 #define _TXB0EIDL_EID1_LENGTH 0x1 #define _TXB0EIDL_EID1_MASK 0x2 #define _TXB0EIDL_EID2_POSN 0x2 #define _TXB0EIDL_EID2_POSITION 0x2 #define _TXB0EIDL_EID2_SIZE 0x1 #define _TXB0EIDL_EID2_LENGTH 0x1 #define _TXB0EIDL_EID2_MASK 0x4 #define _TXB0EIDL_EID3_POSN 0x3 #define _TXB0EIDL_EID3_POSITION 0x3 #define _TXB0EIDL_EID3_SIZE 0x1 #define _TXB0EIDL_EID3_LENGTH 0x1 #define _TXB0EIDL_EID3_MASK 0x8 #define _TXB0EIDL_EID4_POSN 0x4 #define _TXB0EIDL_EID4_POSITION 0x4 #define _TXB0EIDL_EID4_SIZE 0x1 #define _TXB0EIDL_EID4_LENGTH 0x1 #define _TXB0EIDL_EID4_MASK 0x10 #define _TXB0EIDL_EID5_POSN 0x5 #define _TXB0EIDL_EID5_POSITION 0x5 #define _TXB0EIDL_EID5_SIZE 0x1 #define _TXB0EIDL_EID5_LENGTH 0x1 #define _TXB0EIDL_EID5_MASK 0x20 #define _TXB0EIDL_EID6_POSN 0x6 #define _TXB0EIDL_EID6_POSITION 0x6 #define _TXB0EIDL_EID6_SIZE 0x1 #define _TXB0EIDL_EID6_LENGTH 0x1 #define _TXB0EIDL_EID6_MASK 0x40 #define _TXB0EIDL_EID7_POSN 0x7 #define _TXB0EIDL_EID7_POSITION 0x7 #define _TXB0EIDL_EID7_SIZE 0x1 #define _TXB0EIDL_EID7_LENGTH 0x1 #define _TXB0EIDL_EID7_MASK 0x80 #define _TXB0EIDL_TXB0EID0_POSN 0x0 #define _TXB0EIDL_TXB0EID0_POSITION 0x0 #define _TXB0EIDL_TXB0EID0_SIZE 0x1 #define _TXB0EIDL_TXB0EID0_LENGTH 0x1 #define _TXB0EIDL_TXB0EID0_MASK 0x1 #define _TXB0EIDL_TXB0EID1_POSN 0x1 #define _TXB0EIDL_TXB0EID1_POSITION 0x1 #define _TXB0EIDL_TXB0EID1_SIZE 0x1 #define _TXB0EIDL_TXB0EID1_LENGTH 0x1 #define _TXB0EIDL_TXB0EID1_MASK 0x2 #define _TXB0EIDL_TXB0EID2_POSN 0x2 #define _TXB0EIDL_TXB0EID2_POSITION 0x2 #define _TXB0EIDL_TXB0EID2_SIZE 0x1 #define _TXB0EIDL_TXB0EID2_LENGTH 0x1 #define _TXB0EIDL_TXB0EID2_MASK 0x4 #define _TXB0EIDL_TXB0EID3_POSN 0x3 #define _TXB0EIDL_TXB0EID3_POSITION 0x3 #define _TXB0EIDL_TXB0EID3_SIZE 0x1 #define _TXB0EIDL_TXB0EID3_LENGTH 0x1 #define _TXB0EIDL_TXB0EID3_MASK 0x8 #define _TXB0EIDL_TXB0EID4_POSN 0x4 #define _TXB0EIDL_TXB0EID4_POSITION 0x4 #define _TXB0EIDL_TXB0EID4_SIZE 0x1 #define _TXB0EIDL_TXB0EID4_LENGTH 0x1 #define _TXB0EIDL_TXB0EID4_MASK 0x10 #define _TXB0EIDL_TXB0EID5_POSN 0x5 #define _TXB0EIDL_TXB0EID5_POSITION 0x5 #define _TXB0EIDL_TXB0EID5_SIZE 0x1 #define _TXB0EIDL_TXB0EID5_LENGTH 0x1 #define _TXB0EIDL_TXB0EID5_MASK 0x20 #define _TXB0EIDL_TXB0EID6_POSN 0x6 #define _TXB0EIDL_TXB0EID6_POSITION 0x6 #define _TXB0EIDL_TXB0EID6_SIZE 0x1 #define _TXB0EIDL_TXB0EID6_LENGTH 0x1 #define _TXB0EIDL_TXB0EID6_MASK 0x40 #define _TXB0EIDL_TXB0EID7_POSN 0x7 #define _TXB0EIDL_TXB0EID7_POSITION 0x7 #define _TXB0EIDL_TXB0EID7_SIZE 0x1 #define _TXB0EIDL_TXB0EID7_LENGTH 0x1 #define _TXB0EIDL_TXB0EID7_MASK 0x80 // Register: TXB0DLC #define TXB0DLC TXB0DLC extern volatile unsigned char TXB0DLC @ 0xF25; #ifndef _LIB_BUILD asm("TXB0DLC equ 0F25h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned :2; unsigned TXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; }; struct { unsigned TXB0DLC0 :1; unsigned TXB0DLC1 :1; unsigned TXB0DLC2 :1; unsigned TXB0DLC3 :1; unsigned :2; unsigned TXB0RTR :1; }; } TXB0DLCbits_t; extern volatile TXB0DLCbits_t TXB0DLCbits @ 0xF25; // bitfield macros #define _TXB0DLC_DLC_POSN 0x0 #define _TXB0DLC_DLC_POSITION 0x0 #define _TXB0DLC_DLC_SIZE 0x4 #define _TXB0DLC_DLC_LENGTH 0x4 #define _TXB0DLC_DLC_MASK 0xF #define _TXB0DLC_TXRTR_POSN 0x6 #define _TXB0DLC_TXRTR_POSITION 0x6 #define _TXB0DLC_TXRTR_SIZE 0x1 #define _TXB0DLC_TXRTR_LENGTH 0x1 #define _TXB0DLC_TXRTR_MASK 0x40 #define _TXB0DLC_DLC0_POSN 0x0 #define _TXB0DLC_DLC0_POSITION 0x0 #define _TXB0DLC_DLC0_SIZE 0x1 #define _TXB0DLC_DLC0_LENGTH 0x1 #define _TXB0DLC_DLC0_MASK 0x1 #define _TXB0DLC_DLC1_POSN 0x1 #define _TXB0DLC_DLC1_POSITION 0x1 #define _TXB0DLC_DLC1_SIZE 0x1 #define _TXB0DLC_DLC1_LENGTH 0x1 #define _TXB0DLC_DLC1_MASK 0x2 #define _TXB0DLC_DLC2_POSN 0x2 #define _TXB0DLC_DLC2_POSITION 0x2 #define _TXB0DLC_DLC2_SIZE 0x1 #define _TXB0DLC_DLC2_LENGTH 0x1 #define _TXB0DLC_DLC2_MASK 0x4 #define _TXB0DLC_DLC3_POSN 0x3 #define _TXB0DLC_DLC3_POSITION 0x3 #define _TXB0DLC_DLC3_SIZE 0x1 #define _TXB0DLC_DLC3_LENGTH 0x1 #define _TXB0DLC_DLC3_MASK 0x8 #define _TXB0DLC_TXB0DLC0_POSN 0x0 #define _TXB0DLC_TXB0DLC0_POSITION 0x0 #define _TXB0DLC_TXB0DLC0_SIZE 0x1 #define _TXB0DLC_TXB0DLC0_LENGTH 0x1 #define _TXB0DLC_TXB0DLC0_MASK 0x1 #define _TXB0DLC_TXB0DLC1_POSN 0x1 #define _TXB0DLC_TXB0DLC1_POSITION 0x1 #define _TXB0DLC_TXB0DLC1_SIZE 0x1 #define _TXB0DLC_TXB0DLC1_LENGTH 0x1 #define _TXB0DLC_TXB0DLC1_MASK 0x2 #define _TXB0DLC_TXB0DLC2_POSN 0x2 #define _TXB0DLC_TXB0DLC2_POSITION 0x2 #define _TXB0DLC_TXB0DLC2_SIZE 0x1 #define _TXB0DLC_TXB0DLC2_LENGTH 0x1 #define _TXB0DLC_TXB0DLC2_MASK 0x4 #define _TXB0DLC_TXB0DLC3_POSN 0x3 #define _TXB0DLC_TXB0DLC3_POSITION 0x3 #define _TXB0DLC_TXB0DLC3_SIZE 0x1 #define _TXB0DLC_TXB0DLC3_LENGTH 0x1 #define _TXB0DLC_TXB0DLC3_MASK 0x8 #define _TXB0DLC_TXB0RTR_POSN 0x6 #define _TXB0DLC_TXB0RTR_POSITION 0x6 #define _TXB0DLC_TXB0RTR_SIZE 0x1 #define _TXB0DLC_TXB0RTR_LENGTH 0x1 #define _TXB0DLC_TXB0RTR_MASK 0x40 // Register: TXB0D0 #define TXB0D0 TXB0D0 extern volatile unsigned char TXB0D0 @ 0xF26; #ifndef _LIB_BUILD asm("TXB0D0 equ 0F26h"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D0 :8; }; struct { unsigned TXB0D00 :1; unsigned TXB0D01 :1; unsigned TXB0D02 :1; unsigned TXB0D03 :1; unsigned TXB0D04 :1; unsigned TXB0D05 :1; unsigned TXB0D06 :1; unsigned TXB0D07 :1; }; } TXB0D0bits_t; extern volatile TXB0D0bits_t TXB0D0bits @ 0xF26; // bitfield macros #define _TXB0D0_TXB0D0_POSN 0x0 #define _TXB0D0_TXB0D0_POSITION 0x0 #define _TXB0D0_TXB0D0_SIZE 0x8 #define _TXB0D0_TXB0D0_LENGTH 0x8 #define _TXB0D0_TXB0D0_MASK 0xFF #define _TXB0D0_TXB0D00_POSN 0x0 #define _TXB0D0_TXB0D00_POSITION 0x0 #define _TXB0D0_TXB0D00_SIZE 0x1 #define _TXB0D0_TXB0D00_LENGTH 0x1 #define _TXB0D0_TXB0D00_MASK 0x1 #define _TXB0D0_TXB0D01_POSN 0x1 #define _TXB0D0_TXB0D01_POSITION 0x1 #define _TXB0D0_TXB0D01_SIZE 0x1 #define _TXB0D0_TXB0D01_LENGTH 0x1 #define _TXB0D0_TXB0D01_MASK 0x2 #define _TXB0D0_TXB0D02_POSN 0x2 #define _TXB0D0_TXB0D02_POSITION 0x2 #define _TXB0D0_TXB0D02_SIZE 0x1 #define _TXB0D0_TXB0D02_LENGTH 0x1 #define _TXB0D0_TXB0D02_MASK 0x4 #define _TXB0D0_TXB0D03_POSN 0x3 #define _TXB0D0_TXB0D03_POSITION 0x3 #define _TXB0D0_TXB0D03_SIZE 0x1 #define _TXB0D0_TXB0D03_LENGTH 0x1 #define _TXB0D0_TXB0D03_MASK 0x8 #define _TXB0D0_TXB0D04_POSN 0x4 #define _TXB0D0_TXB0D04_POSITION 0x4 #define _TXB0D0_TXB0D04_SIZE 0x1 #define _TXB0D0_TXB0D04_LENGTH 0x1 #define _TXB0D0_TXB0D04_MASK 0x10 #define _TXB0D0_TXB0D05_POSN 0x5 #define _TXB0D0_TXB0D05_POSITION 0x5 #define _TXB0D0_TXB0D05_SIZE 0x1 #define _TXB0D0_TXB0D05_LENGTH 0x1 #define _TXB0D0_TXB0D05_MASK 0x20 #define _TXB0D0_TXB0D06_POSN 0x6 #define _TXB0D0_TXB0D06_POSITION 0x6 #define _TXB0D0_TXB0D06_SIZE 0x1 #define _TXB0D0_TXB0D06_LENGTH 0x1 #define _TXB0D0_TXB0D06_MASK 0x40 #define _TXB0D0_TXB0D07_POSN 0x7 #define _TXB0D0_TXB0D07_POSITION 0x7 #define _TXB0D0_TXB0D07_SIZE 0x1 #define _TXB0D0_TXB0D07_LENGTH 0x1 #define _TXB0D0_TXB0D07_MASK 0x80 // Register: TXB0D1 #define TXB0D1 TXB0D1 extern volatile unsigned char TXB0D1 @ 0xF27; #ifndef _LIB_BUILD asm("TXB0D1 equ 0F27h"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D1 :8; }; struct { unsigned TXB0D10 :1; unsigned TXB0D11 :1; unsigned TXB0D12 :1; unsigned TXB0D13 :1; unsigned TXB0D14 :1; unsigned TXB0D15 :1; unsigned TXB0D16 :1; unsigned TXB0D17 :1; }; } TXB0D1bits_t; extern volatile TXB0D1bits_t TXB0D1bits @ 0xF27; // bitfield macros #define _TXB0D1_TXB0D1_POSN 0x0 #define _TXB0D1_TXB0D1_POSITION 0x0 #define _TXB0D1_TXB0D1_SIZE 0x8 #define _TXB0D1_TXB0D1_LENGTH 0x8 #define _TXB0D1_TXB0D1_MASK 0xFF #define _TXB0D1_TXB0D10_POSN 0x0 #define _TXB0D1_TXB0D10_POSITION 0x0 #define _TXB0D1_TXB0D10_SIZE 0x1 #define _TXB0D1_TXB0D10_LENGTH 0x1 #define _TXB0D1_TXB0D10_MASK 0x1 #define _TXB0D1_TXB0D11_POSN 0x1 #define _TXB0D1_TXB0D11_POSITION 0x1 #define _TXB0D1_TXB0D11_SIZE 0x1 #define _TXB0D1_TXB0D11_LENGTH 0x1 #define _TXB0D1_TXB0D11_MASK 0x2 #define _TXB0D1_TXB0D12_POSN 0x2 #define _TXB0D1_TXB0D12_POSITION 0x2 #define _TXB0D1_TXB0D12_SIZE 0x1 #define _TXB0D1_TXB0D12_LENGTH 0x1 #define _TXB0D1_TXB0D12_MASK 0x4 #define _TXB0D1_TXB0D13_POSN 0x3 #define _TXB0D1_TXB0D13_POSITION 0x3 #define _TXB0D1_TXB0D13_SIZE 0x1 #define _TXB0D1_TXB0D13_LENGTH 0x1 #define _TXB0D1_TXB0D13_MASK 0x8 #define _TXB0D1_TXB0D14_POSN 0x4 #define _TXB0D1_TXB0D14_POSITION 0x4 #define _TXB0D1_TXB0D14_SIZE 0x1 #define _TXB0D1_TXB0D14_LENGTH 0x1 #define _TXB0D1_TXB0D14_MASK 0x10 #define _TXB0D1_TXB0D15_POSN 0x5 #define _TXB0D1_TXB0D15_POSITION 0x5 #define _TXB0D1_TXB0D15_SIZE 0x1 #define _TXB0D1_TXB0D15_LENGTH 0x1 #define _TXB0D1_TXB0D15_MASK 0x20 #define _TXB0D1_TXB0D16_POSN 0x6 #define _TXB0D1_TXB0D16_POSITION 0x6 #define _TXB0D1_TXB0D16_SIZE 0x1 #define _TXB0D1_TXB0D16_LENGTH 0x1 #define _TXB0D1_TXB0D16_MASK 0x40 #define _TXB0D1_TXB0D17_POSN 0x7 #define _TXB0D1_TXB0D17_POSITION 0x7 #define _TXB0D1_TXB0D17_SIZE 0x1 #define _TXB0D1_TXB0D17_LENGTH 0x1 #define _TXB0D1_TXB0D17_MASK 0x80 // Register: TXB0D2 #define TXB0D2 TXB0D2 extern volatile unsigned char TXB0D2 @ 0xF28; #ifndef _LIB_BUILD asm("TXB0D2 equ 0F28h"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D2 :8; }; struct { unsigned TXB0D20 :1; unsigned TXB0D21 :1; unsigned TXB0D22 :1; unsigned TXB0D23 :1; unsigned TXB0D24 :1; unsigned TXB0D25 :1; unsigned TXB0D26 :1; unsigned TXB0D27 :1; }; } TXB0D2bits_t; extern volatile TXB0D2bits_t TXB0D2bits @ 0xF28; // bitfield macros #define _TXB0D2_TXB0D2_POSN 0x0 #define _TXB0D2_TXB0D2_POSITION 0x0 #define _TXB0D2_TXB0D2_SIZE 0x8 #define _TXB0D2_TXB0D2_LENGTH 0x8 #define _TXB0D2_TXB0D2_MASK 0xFF #define _TXB0D2_TXB0D20_POSN 0x0 #define _TXB0D2_TXB0D20_POSITION 0x0 #define _TXB0D2_TXB0D20_SIZE 0x1 #define _TXB0D2_TXB0D20_LENGTH 0x1 #define _TXB0D2_TXB0D20_MASK 0x1 #define _TXB0D2_TXB0D21_POSN 0x1 #define _TXB0D2_TXB0D21_POSITION 0x1 #define _TXB0D2_TXB0D21_SIZE 0x1 #define _TXB0D2_TXB0D21_LENGTH 0x1 #define _TXB0D2_TXB0D21_MASK 0x2 #define _TXB0D2_TXB0D22_POSN 0x2 #define _TXB0D2_TXB0D22_POSITION 0x2 #define _TXB0D2_TXB0D22_SIZE 0x1 #define _TXB0D2_TXB0D22_LENGTH 0x1 #define _TXB0D2_TXB0D22_MASK 0x4 #define _TXB0D2_TXB0D23_POSN 0x3 #define _TXB0D2_TXB0D23_POSITION 0x3 #define _TXB0D2_TXB0D23_SIZE 0x1 #define _TXB0D2_TXB0D23_LENGTH 0x1 #define _TXB0D2_TXB0D23_MASK 0x8 #define _TXB0D2_TXB0D24_POSN 0x4 #define _TXB0D2_TXB0D24_POSITION 0x4 #define _TXB0D2_TXB0D24_SIZE 0x1 #define _TXB0D2_TXB0D24_LENGTH 0x1 #define _TXB0D2_TXB0D24_MASK 0x10 #define _TXB0D2_TXB0D25_POSN 0x5 #define _TXB0D2_TXB0D25_POSITION 0x5 #define _TXB0D2_TXB0D25_SIZE 0x1 #define _TXB0D2_TXB0D25_LENGTH 0x1 #define _TXB0D2_TXB0D25_MASK 0x20 #define _TXB0D2_TXB0D26_POSN 0x6 #define _TXB0D2_TXB0D26_POSITION 0x6 #define _TXB0D2_TXB0D26_SIZE 0x1 #define _TXB0D2_TXB0D26_LENGTH 0x1 #define _TXB0D2_TXB0D26_MASK 0x40 #define _TXB0D2_TXB0D27_POSN 0x7 #define _TXB0D2_TXB0D27_POSITION 0x7 #define _TXB0D2_TXB0D27_SIZE 0x1 #define _TXB0D2_TXB0D27_LENGTH 0x1 #define _TXB0D2_TXB0D27_MASK 0x80 // Register: TXB0D3 #define TXB0D3 TXB0D3 extern volatile unsigned char TXB0D3 @ 0xF29; #ifndef _LIB_BUILD asm("TXB0D3 equ 0F29h"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D3 :8; }; struct { unsigned TXB0D30 :1; unsigned TXB0D31 :1; unsigned TXB0D32 :1; unsigned TXB0D33 :1; unsigned TXB0D34 :1; unsigned TXB0D35 :1; unsigned TXB0D36 :1; unsigned TXB0D37 :1; }; } TXB0D3bits_t; extern volatile TXB0D3bits_t TXB0D3bits @ 0xF29; // bitfield macros #define _TXB0D3_TXB0D3_POSN 0x0 #define _TXB0D3_TXB0D3_POSITION 0x0 #define _TXB0D3_TXB0D3_SIZE 0x8 #define _TXB0D3_TXB0D3_LENGTH 0x8 #define _TXB0D3_TXB0D3_MASK 0xFF #define _TXB0D3_TXB0D30_POSN 0x0 #define _TXB0D3_TXB0D30_POSITION 0x0 #define _TXB0D3_TXB0D30_SIZE 0x1 #define _TXB0D3_TXB0D30_LENGTH 0x1 #define _TXB0D3_TXB0D30_MASK 0x1 #define _TXB0D3_TXB0D31_POSN 0x1 #define _TXB0D3_TXB0D31_POSITION 0x1 #define _TXB0D3_TXB0D31_SIZE 0x1 #define _TXB0D3_TXB0D31_LENGTH 0x1 #define _TXB0D3_TXB0D31_MASK 0x2 #define _TXB0D3_TXB0D32_POSN 0x2 #define _TXB0D3_TXB0D32_POSITION 0x2 #define _TXB0D3_TXB0D32_SIZE 0x1 #define _TXB0D3_TXB0D32_LENGTH 0x1 #define _TXB0D3_TXB0D32_MASK 0x4 #define _TXB0D3_TXB0D33_POSN 0x3 #define _TXB0D3_TXB0D33_POSITION 0x3 #define _TXB0D3_TXB0D33_SIZE 0x1 #define _TXB0D3_TXB0D33_LENGTH 0x1 #define _TXB0D3_TXB0D33_MASK 0x8 #define _TXB0D3_TXB0D34_POSN 0x4 #define _TXB0D3_TXB0D34_POSITION 0x4 #define _TXB0D3_TXB0D34_SIZE 0x1 #define _TXB0D3_TXB0D34_LENGTH 0x1 #define _TXB0D3_TXB0D34_MASK 0x10 #define _TXB0D3_TXB0D35_POSN 0x5 #define _TXB0D3_TXB0D35_POSITION 0x5 #define _TXB0D3_TXB0D35_SIZE 0x1 #define _TXB0D3_TXB0D35_LENGTH 0x1 #define _TXB0D3_TXB0D35_MASK 0x20 #define _TXB0D3_TXB0D36_POSN 0x6 #define _TXB0D3_TXB0D36_POSITION 0x6 #define _TXB0D3_TXB0D36_SIZE 0x1 #define _TXB0D3_TXB0D36_LENGTH 0x1 #define _TXB0D3_TXB0D36_MASK 0x40 #define _TXB0D3_TXB0D37_POSN 0x7 #define _TXB0D3_TXB0D37_POSITION 0x7 #define _TXB0D3_TXB0D37_SIZE 0x1 #define _TXB0D3_TXB0D37_LENGTH 0x1 #define _TXB0D3_TXB0D37_MASK 0x80 // Register: TXB0D4 #define TXB0D4 TXB0D4 extern volatile unsigned char TXB0D4 @ 0xF2A; #ifndef _LIB_BUILD asm("TXB0D4 equ 0F2Ah"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D4 :8; }; struct { unsigned TXB0D40 :1; unsigned TXB0D41 :1; unsigned TXB0D42 :1; unsigned TXB0D43 :1; unsigned TXB0D44 :1; unsigned TXB0D45 :1; unsigned TXB0D46 :1; unsigned TXB0D47 :1; }; } TXB0D4bits_t; extern volatile TXB0D4bits_t TXB0D4bits @ 0xF2A; // bitfield macros #define _TXB0D4_TXB0D4_POSN 0x0 #define _TXB0D4_TXB0D4_POSITION 0x0 #define _TXB0D4_TXB0D4_SIZE 0x8 #define _TXB0D4_TXB0D4_LENGTH 0x8 #define _TXB0D4_TXB0D4_MASK 0xFF #define _TXB0D4_TXB0D40_POSN 0x0 #define _TXB0D4_TXB0D40_POSITION 0x0 #define _TXB0D4_TXB0D40_SIZE 0x1 #define _TXB0D4_TXB0D40_LENGTH 0x1 #define _TXB0D4_TXB0D40_MASK 0x1 #define _TXB0D4_TXB0D41_POSN 0x1 #define _TXB0D4_TXB0D41_POSITION 0x1 #define _TXB0D4_TXB0D41_SIZE 0x1 #define _TXB0D4_TXB0D41_LENGTH 0x1 #define _TXB0D4_TXB0D41_MASK 0x2 #define _TXB0D4_TXB0D42_POSN 0x2 #define _TXB0D4_TXB0D42_POSITION 0x2 #define _TXB0D4_TXB0D42_SIZE 0x1 #define _TXB0D4_TXB0D42_LENGTH 0x1 #define _TXB0D4_TXB0D42_MASK 0x4 #define _TXB0D4_TXB0D43_POSN 0x3 #define _TXB0D4_TXB0D43_POSITION 0x3 #define _TXB0D4_TXB0D43_SIZE 0x1 #define _TXB0D4_TXB0D43_LENGTH 0x1 #define _TXB0D4_TXB0D43_MASK 0x8 #define _TXB0D4_TXB0D44_POSN 0x4 #define _TXB0D4_TXB0D44_POSITION 0x4 #define _TXB0D4_TXB0D44_SIZE 0x1 #define _TXB0D4_TXB0D44_LENGTH 0x1 #define _TXB0D4_TXB0D44_MASK 0x10 #define _TXB0D4_TXB0D45_POSN 0x5 #define _TXB0D4_TXB0D45_POSITION 0x5 #define _TXB0D4_TXB0D45_SIZE 0x1 #define _TXB0D4_TXB0D45_LENGTH 0x1 #define _TXB0D4_TXB0D45_MASK 0x20 #define _TXB0D4_TXB0D46_POSN 0x6 #define _TXB0D4_TXB0D46_POSITION 0x6 #define _TXB0D4_TXB0D46_SIZE 0x1 #define _TXB0D4_TXB0D46_LENGTH 0x1 #define _TXB0D4_TXB0D46_MASK 0x40 #define _TXB0D4_TXB0D47_POSN 0x7 #define _TXB0D4_TXB0D47_POSITION 0x7 #define _TXB0D4_TXB0D47_SIZE 0x1 #define _TXB0D4_TXB0D47_LENGTH 0x1 #define _TXB0D4_TXB0D47_MASK 0x80 // Register: TXB0D5 #define TXB0D5 TXB0D5 extern volatile unsigned char TXB0D5 @ 0xF2B; #ifndef _LIB_BUILD asm("TXB0D5 equ 0F2Bh"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D5 :8; }; struct { unsigned TXB0D50 :1; unsigned TXB0D51 :1; unsigned TXB0D52 :1; unsigned TXB0D53 :1; unsigned TXB0D54 :1; unsigned TXB0D55 :1; unsigned TXB0D56 :1; unsigned TXB0D57 :1; }; } TXB0D5bits_t; extern volatile TXB0D5bits_t TXB0D5bits @ 0xF2B; // bitfield macros #define _TXB0D5_TXB0D5_POSN 0x0 #define _TXB0D5_TXB0D5_POSITION 0x0 #define _TXB0D5_TXB0D5_SIZE 0x8 #define _TXB0D5_TXB0D5_LENGTH 0x8 #define _TXB0D5_TXB0D5_MASK 0xFF #define _TXB0D5_TXB0D50_POSN 0x0 #define _TXB0D5_TXB0D50_POSITION 0x0 #define _TXB0D5_TXB0D50_SIZE 0x1 #define _TXB0D5_TXB0D50_LENGTH 0x1 #define _TXB0D5_TXB0D50_MASK 0x1 #define _TXB0D5_TXB0D51_POSN 0x1 #define _TXB0D5_TXB0D51_POSITION 0x1 #define _TXB0D5_TXB0D51_SIZE 0x1 #define _TXB0D5_TXB0D51_LENGTH 0x1 #define _TXB0D5_TXB0D51_MASK 0x2 #define _TXB0D5_TXB0D52_POSN 0x2 #define _TXB0D5_TXB0D52_POSITION 0x2 #define _TXB0D5_TXB0D52_SIZE 0x1 #define _TXB0D5_TXB0D52_LENGTH 0x1 #define _TXB0D5_TXB0D52_MASK 0x4 #define _TXB0D5_TXB0D53_POSN 0x3 #define _TXB0D5_TXB0D53_POSITION 0x3 #define _TXB0D5_TXB0D53_SIZE 0x1 #define _TXB0D5_TXB0D53_LENGTH 0x1 #define _TXB0D5_TXB0D53_MASK 0x8 #define _TXB0D5_TXB0D54_POSN 0x4 #define _TXB0D5_TXB0D54_POSITION 0x4 #define _TXB0D5_TXB0D54_SIZE 0x1 #define _TXB0D5_TXB0D54_LENGTH 0x1 #define _TXB0D5_TXB0D54_MASK 0x10 #define _TXB0D5_TXB0D55_POSN 0x5 #define _TXB0D5_TXB0D55_POSITION 0x5 #define _TXB0D5_TXB0D55_SIZE 0x1 #define _TXB0D5_TXB0D55_LENGTH 0x1 #define _TXB0D5_TXB0D55_MASK 0x20 #define _TXB0D5_TXB0D56_POSN 0x6 #define _TXB0D5_TXB0D56_POSITION 0x6 #define _TXB0D5_TXB0D56_SIZE 0x1 #define _TXB0D5_TXB0D56_LENGTH 0x1 #define _TXB0D5_TXB0D56_MASK 0x40 #define _TXB0D5_TXB0D57_POSN 0x7 #define _TXB0D5_TXB0D57_POSITION 0x7 #define _TXB0D5_TXB0D57_SIZE 0x1 #define _TXB0D5_TXB0D57_LENGTH 0x1 #define _TXB0D5_TXB0D57_MASK 0x80 // Register: TXB0D6 #define TXB0D6 TXB0D6 extern volatile unsigned char TXB0D6 @ 0xF2C; #ifndef _LIB_BUILD asm("TXB0D6 equ 0F2Ch"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D6 :8; }; struct { unsigned TXB0D60 :1; unsigned TXB0D61 :1; unsigned TXB0D62 :1; unsigned TXB0D63 :1; unsigned TXB0D64 :1; unsigned TXB0D65 :1; unsigned TXB0D66 :1; unsigned TXB0D67 :1; }; } TXB0D6bits_t; extern volatile TXB0D6bits_t TXB0D6bits @ 0xF2C; // bitfield macros #define _TXB0D6_TXB0D6_POSN 0x0 #define _TXB0D6_TXB0D6_POSITION 0x0 #define _TXB0D6_TXB0D6_SIZE 0x8 #define _TXB0D6_TXB0D6_LENGTH 0x8 #define _TXB0D6_TXB0D6_MASK 0xFF #define _TXB0D6_TXB0D60_POSN 0x0 #define _TXB0D6_TXB0D60_POSITION 0x0 #define _TXB0D6_TXB0D60_SIZE 0x1 #define _TXB0D6_TXB0D60_LENGTH 0x1 #define _TXB0D6_TXB0D60_MASK 0x1 #define _TXB0D6_TXB0D61_POSN 0x1 #define _TXB0D6_TXB0D61_POSITION 0x1 #define _TXB0D6_TXB0D61_SIZE 0x1 #define _TXB0D6_TXB0D61_LENGTH 0x1 #define _TXB0D6_TXB0D61_MASK 0x2 #define _TXB0D6_TXB0D62_POSN 0x2 #define _TXB0D6_TXB0D62_POSITION 0x2 #define _TXB0D6_TXB0D62_SIZE 0x1 #define _TXB0D6_TXB0D62_LENGTH 0x1 #define _TXB0D6_TXB0D62_MASK 0x4 #define _TXB0D6_TXB0D63_POSN 0x3 #define _TXB0D6_TXB0D63_POSITION 0x3 #define _TXB0D6_TXB0D63_SIZE 0x1 #define _TXB0D6_TXB0D63_LENGTH 0x1 #define _TXB0D6_TXB0D63_MASK 0x8 #define _TXB0D6_TXB0D64_POSN 0x4 #define _TXB0D6_TXB0D64_POSITION 0x4 #define _TXB0D6_TXB0D64_SIZE 0x1 #define _TXB0D6_TXB0D64_LENGTH 0x1 #define _TXB0D6_TXB0D64_MASK 0x10 #define _TXB0D6_TXB0D65_POSN 0x5 #define _TXB0D6_TXB0D65_POSITION 0x5 #define _TXB0D6_TXB0D65_SIZE 0x1 #define _TXB0D6_TXB0D65_LENGTH 0x1 #define _TXB0D6_TXB0D65_MASK 0x20 #define _TXB0D6_TXB0D66_POSN 0x6 #define _TXB0D6_TXB0D66_POSITION 0x6 #define _TXB0D6_TXB0D66_SIZE 0x1 #define _TXB0D6_TXB0D66_LENGTH 0x1 #define _TXB0D6_TXB0D66_MASK 0x40 #define _TXB0D6_TXB0D67_POSN 0x7 #define _TXB0D6_TXB0D67_POSITION 0x7 #define _TXB0D6_TXB0D67_SIZE 0x1 #define _TXB0D6_TXB0D67_LENGTH 0x1 #define _TXB0D6_TXB0D67_MASK 0x80 // Register: TXB0D7 #define TXB0D7 TXB0D7 extern volatile unsigned char TXB0D7 @ 0xF2D; #ifndef _LIB_BUILD asm("TXB0D7 equ 0F2Dh"); #endif // bitfield definitions typedef union { struct { unsigned TXB0D7 :8; }; struct { unsigned TXB0D70 :1; unsigned TXB0D71 :1; unsigned TXB0D72 :1; unsigned TXB0D73 :1; unsigned TXB0D74 :1; unsigned TXB0D75 :1; unsigned TXB0D76 :1; unsigned TXB0D77 :1; }; } TXB0D7bits_t; extern volatile TXB0D7bits_t TXB0D7bits @ 0xF2D; // bitfield macros #define _TXB0D7_TXB0D7_POSN 0x0 #define _TXB0D7_TXB0D7_POSITION 0x0 #define _TXB0D7_TXB0D7_SIZE 0x8 #define _TXB0D7_TXB0D7_LENGTH 0x8 #define _TXB0D7_TXB0D7_MASK 0xFF #define _TXB0D7_TXB0D70_POSN 0x0 #define _TXB0D7_TXB0D70_POSITION 0x0 #define _TXB0D7_TXB0D70_SIZE 0x1 #define _TXB0D7_TXB0D70_LENGTH 0x1 #define _TXB0D7_TXB0D70_MASK 0x1 #define _TXB0D7_TXB0D71_POSN 0x1 #define _TXB0D7_TXB0D71_POSITION 0x1 #define _TXB0D7_TXB0D71_SIZE 0x1 #define _TXB0D7_TXB0D71_LENGTH 0x1 #define _TXB0D7_TXB0D71_MASK 0x2 #define _TXB0D7_TXB0D72_POSN 0x2 #define _TXB0D7_TXB0D72_POSITION 0x2 #define _TXB0D7_TXB0D72_SIZE 0x1 #define _TXB0D7_TXB0D72_LENGTH 0x1 #define _TXB0D7_TXB0D72_MASK 0x4 #define _TXB0D7_TXB0D73_POSN 0x3 #define _TXB0D7_TXB0D73_POSITION 0x3 #define _TXB0D7_TXB0D73_SIZE 0x1 #define _TXB0D7_TXB0D73_LENGTH 0x1 #define _TXB0D7_TXB0D73_MASK 0x8 #define _TXB0D7_TXB0D74_POSN 0x4 #define _TXB0D7_TXB0D74_POSITION 0x4 #define _TXB0D7_TXB0D74_SIZE 0x1 #define _TXB0D7_TXB0D74_LENGTH 0x1 #define _TXB0D7_TXB0D74_MASK 0x10 #define _TXB0D7_TXB0D75_POSN 0x5 #define _TXB0D7_TXB0D75_POSITION 0x5 #define _TXB0D7_TXB0D75_SIZE 0x1 #define _TXB0D7_TXB0D75_LENGTH 0x1 #define _TXB0D7_TXB0D75_MASK 0x20 #define _TXB0D7_TXB0D76_POSN 0x6 #define _TXB0D7_TXB0D76_POSITION 0x6 #define _TXB0D7_TXB0D76_SIZE 0x1 #define _TXB0D7_TXB0D76_LENGTH 0x1 #define _TXB0D7_TXB0D76_MASK 0x40 #define _TXB0D7_TXB0D77_POSN 0x7 #define _TXB0D7_TXB0D77_POSITION 0x7 #define _TXB0D7_TXB0D77_SIZE 0x1 #define _TXB0D7_TXB0D77_LENGTH 0x1 #define _TXB0D7_TXB0D77_MASK 0x80 // Register: CANSTAT_RO1 #define CANSTAT_RO1 CANSTAT_RO1 extern volatile unsigned char CANSTAT_RO1 @ 0xF2E; #ifndef _LIB_BUILD asm("CANSTAT_RO1 equ 0F2Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO1bits_t; extern volatile CANSTAT_RO1bits_t CANSTAT_RO1bits @ 0xF2E; // bitfield macros #define _CANSTAT_RO1_EICODE0_POSN 0x0 #define _CANSTAT_RO1_EICODE0_POSITION 0x0 #define _CANSTAT_RO1_EICODE0_SIZE 0x1 #define _CANSTAT_RO1_EICODE0_LENGTH 0x1 #define _CANSTAT_RO1_EICODE0_MASK 0x1 #define _CANSTAT_RO1_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO1_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO1_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO1_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO1_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO1_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO1_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO1_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO1_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO1_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO1_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO1_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO1_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO1_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO1_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO1_EICODE4_POSN 0x4 #define _CANSTAT_RO1_EICODE4_POSITION 0x4 #define _CANSTAT_RO1_EICODE4_SIZE 0x1 #define _CANSTAT_RO1_EICODE4_LENGTH 0x1 #define _CANSTAT_RO1_EICODE4_MASK 0x10 #define _CANSTAT_RO1_OPMODE_POSN 0x5 #define _CANSTAT_RO1_OPMODE_POSITION 0x5 #define _CANSTAT_RO1_OPMODE_SIZE 0x3 #define _CANSTAT_RO1_OPMODE_LENGTH 0x3 #define _CANSTAT_RO1_OPMODE_MASK 0xE0 #define _CANSTAT_RO1_EICODE1_POSN 0x1 #define _CANSTAT_RO1_EICODE1_POSITION 0x1 #define _CANSTAT_RO1_EICODE1_SIZE 0x1 #define _CANSTAT_RO1_EICODE1_LENGTH 0x1 #define _CANSTAT_RO1_EICODE1_MASK 0x2 #define _CANSTAT_RO1_EICODE2_POSN 0x2 #define _CANSTAT_RO1_EICODE2_POSITION 0x2 #define _CANSTAT_RO1_EICODE2_SIZE 0x1 #define _CANSTAT_RO1_EICODE2_LENGTH 0x1 #define _CANSTAT_RO1_EICODE2_MASK 0x4 #define _CANSTAT_RO1_EICODE3_POSN 0x3 #define _CANSTAT_RO1_EICODE3_POSITION 0x3 #define _CANSTAT_RO1_EICODE3_SIZE 0x1 #define _CANSTAT_RO1_EICODE3_LENGTH 0x1 #define _CANSTAT_RO1_EICODE3_MASK 0x8 #define _CANSTAT_RO1_OPMODE0_POSN 0x5 #define _CANSTAT_RO1_OPMODE0_POSITION 0x5 #define _CANSTAT_RO1_OPMODE0_SIZE 0x1 #define _CANSTAT_RO1_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO1_OPMODE0_MASK 0x20 #define _CANSTAT_RO1_OPMODE1_POSN 0x6 #define _CANSTAT_RO1_OPMODE1_POSITION 0x6 #define _CANSTAT_RO1_OPMODE1_SIZE 0x1 #define _CANSTAT_RO1_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO1_OPMODE1_MASK 0x40 #define _CANSTAT_RO1_OPMODE2_POSN 0x7 #define _CANSTAT_RO1_OPMODE2_POSITION 0x7 #define _CANSTAT_RO1_OPMODE2_SIZE 0x1 #define _CANSTAT_RO1_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO1_OPMODE2_MASK 0x80 #define _CANSTAT_RO1_ICODE0_POSN 0x1 #define _CANSTAT_RO1_ICODE0_POSITION 0x1 #define _CANSTAT_RO1_ICODE0_SIZE 0x1 #define _CANSTAT_RO1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO1_ICODE0_MASK 0x2 #define _CANSTAT_RO1_ICODE1_POSN 0x2 #define _CANSTAT_RO1_ICODE1_POSITION 0x2 #define _CANSTAT_RO1_ICODE1_SIZE 0x1 #define _CANSTAT_RO1_ICODE1_LENGTH 0x1 #define _CANSTAT_RO1_ICODE1_MASK 0x4 #define _CANSTAT_RO1_ICODE2_POSN 0x3 #define _CANSTAT_RO1_ICODE2_POSITION 0x3 #define _CANSTAT_RO1_ICODE2_SIZE 0x1 #define _CANSTAT_RO1_ICODE2_LENGTH 0x1 #define _CANSTAT_RO1_ICODE2_MASK 0x8 // Register: CANCON_RO1 #define CANCON_RO1 CANCON_RO1 extern volatile unsigned char CANCON_RO1 @ 0xF2F; #ifndef _LIB_BUILD asm("CANCON_RO1 equ 0F2Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO1bits_t; extern volatile CANCON_RO1bits_t CANCON_RO1bits @ 0xF2F; // bitfield macros #define _CANCON_RO1_FP0_POSN 0x0 #define _CANCON_RO1_FP0_POSITION 0x0 #define _CANCON_RO1_FP0_SIZE 0x1 #define _CANCON_RO1_FP0_LENGTH 0x1 #define _CANCON_RO1_FP0_MASK 0x1 #define _CANCON_RO1_WIN0_FP1_POSN 0x1 #define _CANCON_RO1_WIN0_FP1_POSITION 0x1 #define _CANCON_RO1_WIN0_FP1_SIZE 0x1 #define _CANCON_RO1_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO1_WIN0_FP1_MASK 0x2 #define _CANCON_RO1_WIN1_FP2_POSN 0x2 #define _CANCON_RO1_WIN1_FP2_POSITION 0x2 #define _CANCON_RO1_WIN1_FP2_SIZE 0x1 #define _CANCON_RO1_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO1_WIN1_FP2_MASK 0x4 #define _CANCON_RO1_WIN2_FP3_POSN 0x3 #define _CANCON_RO1_WIN2_FP3_POSITION 0x3 #define _CANCON_RO1_WIN2_FP3_SIZE 0x1 #define _CANCON_RO1_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO1_WIN2_FP3_MASK 0x8 #define _CANCON_RO1_ABAT_POSN 0x4 #define _CANCON_RO1_ABAT_POSITION 0x4 #define _CANCON_RO1_ABAT_SIZE 0x1 #define _CANCON_RO1_ABAT_LENGTH 0x1 #define _CANCON_RO1_ABAT_MASK 0x10 #define _CANCON_RO1_REQOP_POSN 0x5 #define _CANCON_RO1_REQOP_POSITION 0x5 #define _CANCON_RO1_REQOP_SIZE 0x3 #define _CANCON_RO1_REQOP_LENGTH 0x3 #define _CANCON_RO1_REQOP_MASK 0xE0 #define _CANCON_RO1_WIN0_POSN 0x1 #define _CANCON_RO1_WIN0_POSITION 0x1 #define _CANCON_RO1_WIN0_SIZE 0x1 #define _CANCON_RO1_WIN0_LENGTH 0x1 #define _CANCON_RO1_WIN0_MASK 0x2 #define _CANCON_RO1_WIN1_POSN 0x2 #define _CANCON_RO1_WIN1_POSITION 0x2 #define _CANCON_RO1_WIN1_SIZE 0x1 #define _CANCON_RO1_WIN1_LENGTH 0x1 #define _CANCON_RO1_WIN1_MASK 0x4 #define _CANCON_RO1_WIN2_POSN 0x3 #define _CANCON_RO1_WIN2_POSITION 0x3 #define _CANCON_RO1_WIN2_SIZE 0x1 #define _CANCON_RO1_WIN2_LENGTH 0x1 #define _CANCON_RO1_WIN2_MASK 0x8 #define _CANCON_RO1_FP1_POSN 0x1 #define _CANCON_RO1_FP1_POSITION 0x1 #define _CANCON_RO1_FP1_SIZE 0x1 #define _CANCON_RO1_FP1_LENGTH 0x1 #define _CANCON_RO1_FP1_MASK 0x2 #define _CANCON_RO1_FP2_POSN 0x2 #define _CANCON_RO1_FP2_POSITION 0x2 #define _CANCON_RO1_FP2_SIZE 0x1 #define _CANCON_RO1_FP2_LENGTH 0x1 #define _CANCON_RO1_FP2_MASK 0x4 #define _CANCON_RO1_FP3_POSN 0x3 #define _CANCON_RO1_FP3_POSITION 0x3 #define _CANCON_RO1_FP3_SIZE 0x1 #define _CANCON_RO1_FP3_LENGTH 0x1 #define _CANCON_RO1_FP3_MASK 0x8 // Register: RXB1CON #define RXB1CON RXB1CON extern volatile unsigned char RXB1CON @ 0xF30; #ifndef _LIB_BUILD asm("RXB1CON equ 0F30h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0 :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned RXRTRRO_FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXM0_RTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned :3; unsigned RXRTRRO :1; unsigned :1; unsigned RXM0 :1; }; struct { unsigned :3; unsigned FILHIT3 :1; unsigned :1; unsigned RTRRO :1; }; struct { unsigned RXB1FILHIT0 :1; unsigned RXB1FILHIT1 :1; unsigned RXB1FILHIT2 :1; unsigned RXB1FILHIT3 :1; unsigned RXB1FILHIT4 :1; unsigned RXB1M0 :1; unsigned RXB1M1 :1; unsigned RXB1FUL :1; }; struct { unsigned :3; unsigned RXB1RTRR0 :1; unsigned :1; unsigned RXB1RTRRO :1; }; } RXB1CONbits_t; extern volatile RXB1CONbits_t RXB1CONbits @ 0xF30; // bitfield macros #define _RXB1CON_FILHIT0_POSN 0x0 #define _RXB1CON_FILHIT0_POSITION 0x0 #define _RXB1CON_FILHIT0_SIZE 0x1 #define _RXB1CON_FILHIT0_LENGTH 0x1 #define _RXB1CON_FILHIT0_MASK 0x1 #define _RXB1CON_FILHIT1_POSN 0x1 #define _RXB1CON_FILHIT1_POSITION 0x1 #define _RXB1CON_FILHIT1_SIZE 0x1 #define _RXB1CON_FILHIT1_LENGTH 0x1 #define _RXB1CON_FILHIT1_MASK 0x2 #define _RXB1CON_FILHIT2_POSN 0x2 #define _RXB1CON_FILHIT2_POSITION 0x2 #define _RXB1CON_FILHIT2_SIZE 0x1 #define _RXB1CON_FILHIT2_LENGTH 0x1 #define _RXB1CON_FILHIT2_MASK 0x4 #define _RXB1CON_RXRTRRO_FILHIT3_POSN 0x3 #define _RXB1CON_RXRTRRO_FILHIT3_POSITION 0x3 #define _RXB1CON_RXRTRRO_FILHIT3_SIZE 0x1 #define _RXB1CON_RXRTRRO_FILHIT3_LENGTH 0x1 #define _RXB1CON_RXRTRRO_FILHIT3_MASK 0x8 #define _RXB1CON_FILHIT4_POSN 0x4 #define _RXB1CON_FILHIT4_POSITION 0x4 #define _RXB1CON_FILHIT4_SIZE 0x1 #define _RXB1CON_FILHIT4_LENGTH 0x1 #define _RXB1CON_FILHIT4_MASK 0x10 #define _RXB1CON_RXM0_RTRRO_POSN 0x5 #define _RXB1CON_RXM0_RTRRO_POSITION 0x5 #define _RXB1CON_RXM0_RTRRO_SIZE 0x1 #define _RXB1CON_RXM0_RTRRO_LENGTH 0x1 #define _RXB1CON_RXM0_RTRRO_MASK 0x20 #define _RXB1CON_RXM1_POSN 0x6 #define _RXB1CON_RXM1_POSITION 0x6 #define _RXB1CON_RXM1_SIZE 0x1 #define _RXB1CON_RXM1_LENGTH 0x1 #define _RXB1CON_RXM1_MASK 0x40 #define _RXB1CON_RXFUL_POSN 0x7 #define _RXB1CON_RXFUL_POSITION 0x7 #define _RXB1CON_RXFUL_SIZE 0x1 #define _RXB1CON_RXFUL_LENGTH 0x1 #define _RXB1CON_RXFUL_MASK 0x80 #define _RXB1CON_RXRTRRO_POSN 0x3 #define _RXB1CON_RXRTRRO_POSITION 0x3 #define _RXB1CON_RXRTRRO_SIZE 0x1 #define _RXB1CON_RXRTRRO_LENGTH 0x1 #define _RXB1CON_RXRTRRO_MASK 0x8 #define _RXB1CON_RXM0_POSN 0x5 #define _RXB1CON_RXM0_POSITION 0x5 #define _RXB1CON_RXM0_SIZE 0x1 #define _RXB1CON_RXM0_LENGTH 0x1 #define _RXB1CON_RXM0_MASK 0x20 #define _RXB1CON_FILHIT3_POSN 0x3 #define _RXB1CON_FILHIT3_POSITION 0x3 #define _RXB1CON_FILHIT3_SIZE 0x1 #define _RXB1CON_FILHIT3_LENGTH 0x1 #define _RXB1CON_FILHIT3_MASK 0x8 #define _RXB1CON_RTRRO_POSN 0x5 #define _RXB1CON_RTRRO_POSITION 0x5 #define _RXB1CON_RTRRO_SIZE 0x1 #define _RXB1CON_RTRRO_LENGTH 0x1 #define _RXB1CON_RTRRO_MASK 0x20 #define _RXB1CON_RXB1FILHIT0_POSN 0x0 #define _RXB1CON_RXB1FILHIT0_POSITION 0x0 #define _RXB1CON_RXB1FILHIT0_SIZE 0x1 #define _RXB1CON_RXB1FILHIT0_LENGTH 0x1 #define _RXB1CON_RXB1FILHIT0_MASK 0x1 #define _RXB1CON_RXB1FILHIT1_POSN 0x1 #define _RXB1CON_RXB1FILHIT1_POSITION 0x1 #define _RXB1CON_RXB1FILHIT1_SIZE 0x1 #define _RXB1CON_RXB1FILHIT1_LENGTH 0x1 #define _RXB1CON_RXB1FILHIT1_MASK 0x2 #define _RXB1CON_RXB1FILHIT2_POSN 0x2 #define _RXB1CON_RXB1FILHIT2_POSITION 0x2 #define _RXB1CON_RXB1FILHIT2_SIZE 0x1 #define _RXB1CON_RXB1FILHIT2_LENGTH 0x1 #define _RXB1CON_RXB1FILHIT2_MASK 0x4 #define _RXB1CON_RXB1FILHIT3_POSN 0x3 #define _RXB1CON_RXB1FILHIT3_POSITION 0x3 #define _RXB1CON_RXB1FILHIT3_SIZE 0x1 #define _RXB1CON_RXB1FILHIT3_LENGTH 0x1 #define _RXB1CON_RXB1FILHIT3_MASK 0x8 #define _RXB1CON_RXB1FILHIT4_POSN 0x4 #define _RXB1CON_RXB1FILHIT4_POSITION 0x4 #define _RXB1CON_RXB1FILHIT4_SIZE 0x1 #define _RXB1CON_RXB1FILHIT4_LENGTH 0x1 #define _RXB1CON_RXB1FILHIT4_MASK 0x10 #define _RXB1CON_RXB1M0_POSN 0x5 #define _RXB1CON_RXB1M0_POSITION 0x5 #define _RXB1CON_RXB1M0_SIZE 0x1 #define _RXB1CON_RXB1M0_LENGTH 0x1 #define _RXB1CON_RXB1M0_MASK 0x20 #define _RXB1CON_RXB1M1_POSN 0x6 #define _RXB1CON_RXB1M1_POSITION 0x6 #define _RXB1CON_RXB1M1_SIZE 0x1 #define _RXB1CON_RXB1M1_LENGTH 0x1 #define _RXB1CON_RXB1M1_MASK 0x40 #define _RXB1CON_RXB1FUL_POSN 0x7 #define _RXB1CON_RXB1FUL_POSITION 0x7 #define _RXB1CON_RXB1FUL_SIZE 0x1 #define _RXB1CON_RXB1FUL_LENGTH 0x1 #define _RXB1CON_RXB1FUL_MASK 0x80 #define _RXB1CON_RXB1RTRR0_POSN 0x3 #define _RXB1CON_RXB1RTRR0_POSITION 0x3 #define _RXB1CON_RXB1RTRR0_SIZE 0x1 #define _RXB1CON_RXB1RTRR0_LENGTH 0x1 #define _RXB1CON_RXB1RTRR0_MASK 0x8 #define _RXB1CON_RXB1RTRRO_POSN 0x5 #define _RXB1CON_RXB1RTRRO_POSITION 0x5 #define _RXB1CON_RXB1RTRRO_SIZE 0x1 #define _RXB1CON_RXB1RTRRO_LENGTH 0x1 #define _RXB1CON_RXB1RTRRO_MASK 0x20 // Register: RXB1SIDH #define RXB1SIDH RXB1SIDH extern volatile unsigned char RXB1SIDH @ 0xF31; #ifndef _LIB_BUILD asm("RXB1SIDH equ 0F31h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXB1SID3 :1; unsigned RXB1SID4 :1; unsigned RXB1SID5 :1; unsigned RXB1SID6 :1; unsigned RXB1SID7 :1; unsigned RXB1SID8 :1; unsigned RXB1SID9 :1; unsigned RXB1SID10 :1; }; } RXB1SIDHbits_t; extern volatile RXB1SIDHbits_t RXB1SIDHbits @ 0xF31; // bitfield macros #define _RXB1SIDH_SID_POSN 0x0 #define _RXB1SIDH_SID_POSITION 0x0 #define _RXB1SIDH_SID_SIZE 0x8 #define _RXB1SIDH_SID_LENGTH 0x8 #define _RXB1SIDH_SID_MASK 0xFF #define _RXB1SIDH_SID3_POSN 0x0 #define _RXB1SIDH_SID3_POSITION 0x0 #define _RXB1SIDH_SID3_SIZE 0x1 #define _RXB1SIDH_SID3_LENGTH 0x1 #define _RXB1SIDH_SID3_MASK 0x1 #define _RXB1SIDH_SID4_POSN 0x1 #define _RXB1SIDH_SID4_POSITION 0x1 #define _RXB1SIDH_SID4_SIZE 0x1 #define _RXB1SIDH_SID4_LENGTH 0x1 #define _RXB1SIDH_SID4_MASK 0x2 #define _RXB1SIDH_SID5_POSN 0x2 #define _RXB1SIDH_SID5_POSITION 0x2 #define _RXB1SIDH_SID5_SIZE 0x1 #define _RXB1SIDH_SID5_LENGTH 0x1 #define _RXB1SIDH_SID5_MASK 0x4 #define _RXB1SIDH_SID6_POSN 0x3 #define _RXB1SIDH_SID6_POSITION 0x3 #define _RXB1SIDH_SID6_SIZE 0x1 #define _RXB1SIDH_SID6_LENGTH 0x1 #define _RXB1SIDH_SID6_MASK 0x8 #define _RXB1SIDH_SID7_POSN 0x4 #define _RXB1SIDH_SID7_POSITION 0x4 #define _RXB1SIDH_SID7_SIZE 0x1 #define _RXB1SIDH_SID7_LENGTH 0x1 #define _RXB1SIDH_SID7_MASK 0x10 #define _RXB1SIDH_SID8_POSN 0x5 #define _RXB1SIDH_SID8_POSITION 0x5 #define _RXB1SIDH_SID8_SIZE 0x1 #define _RXB1SIDH_SID8_LENGTH 0x1 #define _RXB1SIDH_SID8_MASK 0x20 #define _RXB1SIDH_SID9_POSN 0x6 #define _RXB1SIDH_SID9_POSITION 0x6 #define _RXB1SIDH_SID9_SIZE 0x1 #define _RXB1SIDH_SID9_LENGTH 0x1 #define _RXB1SIDH_SID9_MASK 0x40 #define _RXB1SIDH_SID10_POSN 0x7 #define _RXB1SIDH_SID10_POSITION 0x7 #define _RXB1SIDH_SID10_SIZE 0x1 #define _RXB1SIDH_SID10_LENGTH 0x1 #define _RXB1SIDH_SID10_MASK 0x80 #define _RXB1SIDH_RXB1SID3_POSN 0x0 #define _RXB1SIDH_RXB1SID3_POSITION 0x0 #define _RXB1SIDH_RXB1SID3_SIZE 0x1 #define _RXB1SIDH_RXB1SID3_LENGTH 0x1 #define _RXB1SIDH_RXB1SID3_MASK 0x1 #define _RXB1SIDH_RXB1SID4_POSN 0x1 #define _RXB1SIDH_RXB1SID4_POSITION 0x1 #define _RXB1SIDH_RXB1SID4_SIZE 0x1 #define _RXB1SIDH_RXB1SID4_LENGTH 0x1 #define _RXB1SIDH_RXB1SID4_MASK 0x2 #define _RXB1SIDH_RXB1SID5_POSN 0x2 #define _RXB1SIDH_RXB1SID5_POSITION 0x2 #define _RXB1SIDH_RXB1SID5_SIZE 0x1 #define _RXB1SIDH_RXB1SID5_LENGTH 0x1 #define _RXB1SIDH_RXB1SID5_MASK 0x4 #define _RXB1SIDH_RXB1SID6_POSN 0x3 #define _RXB1SIDH_RXB1SID6_POSITION 0x3 #define _RXB1SIDH_RXB1SID6_SIZE 0x1 #define _RXB1SIDH_RXB1SID6_LENGTH 0x1 #define _RXB1SIDH_RXB1SID6_MASK 0x8 #define _RXB1SIDH_RXB1SID7_POSN 0x4 #define _RXB1SIDH_RXB1SID7_POSITION 0x4 #define _RXB1SIDH_RXB1SID7_SIZE 0x1 #define _RXB1SIDH_RXB1SID7_LENGTH 0x1 #define _RXB1SIDH_RXB1SID7_MASK 0x10 #define _RXB1SIDH_RXB1SID8_POSN 0x5 #define _RXB1SIDH_RXB1SID8_POSITION 0x5 #define _RXB1SIDH_RXB1SID8_SIZE 0x1 #define _RXB1SIDH_RXB1SID8_LENGTH 0x1 #define _RXB1SIDH_RXB1SID8_MASK 0x20 #define _RXB1SIDH_RXB1SID9_POSN 0x6 #define _RXB1SIDH_RXB1SID9_POSITION 0x6 #define _RXB1SIDH_RXB1SID9_SIZE 0x1 #define _RXB1SIDH_RXB1SID9_LENGTH 0x1 #define _RXB1SIDH_RXB1SID9_MASK 0x40 #define _RXB1SIDH_RXB1SID10_POSN 0x7 #define _RXB1SIDH_RXB1SID10_POSITION 0x7 #define _RXB1SIDH_RXB1SID10_SIZE 0x1 #define _RXB1SIDH_RXB1SID10_LENGTH 0x1 #define _RXB1SIDH_RXB1SID10_MASK 0x80 // Register: RXB1SIDL #define RXB1SIDL RXB1SIDL extern volatile unsigned char RXB1SIDL @ 0xF32; #ifndef _LIB_BUILD asm("RXB1SIDL equ 0F32h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXID :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EDI16 :1; unsigned EDI17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXB1EID16 :1; unsigned RXB1EID17 :1; unsigned :1; unsigned RXB1EXID :1; unsigned RXB1SRR :1; unsigned RXB1SID0 :1; unsigned RXB1SID1 :1; unsigned RXB1SID2 :1; }; } RXB1SIDLbits_t; extern volatile RXB1SIDLbits_t RXB1SIDLbits @ 0xF32; // bitfield macros #define _RXB1SIDL_EID_POSN 0x0 #define _RXB1SIDL_EID_POSITION 0x0 #define _RXB1SIDL_EID_SIZE 0x2 #define _RXB1SIDL_EID_LENGTH 0x2 #define _RXB1SIDL_EID_MASK 0x3 #define _RXB1SIDL_EXID_POSN 0x3 #define _RXB1SIDL_EXID_POSITION 0x3 #define _RXB1SIDL_EXID_SIZE 0x1 #define _RXB1SIDL_EXID_LENGTH 0x1 #define _RXB1SIDL_EXID_MASK 0x8 #define _RXB1SIDL_SRR_POSN 0x4 #define _RXB1SIDL_SRR_POSITION 0x4 #define _RXB1SIDL_SRR_SIZE 0x1 #define _RXB1SIDL_SRR_LENGTH 0x1 #define _RXB1SIDL_SRR_MASK 0x10 #define _RXB1SIDL_SID_POSN 0x5 #define _RXB1SIDL_SID_POSITION 0x5 #define _RXB1SIDL_SID_SIZE 0x3 #define _RXB1SIDL_SID_LENGTH 0x3 #define _RXB1SIDL_SID_MASK 0xE0 #define _RXB1SIDL_EDI16_POSN 0x0 #define _RXB1SIDL_EDI16_POSITION 0x0 #define _RXB1SIDL_EDI16_SIZE 0x1 #define _RXB1SIDL_EDI16_LENGTH 0x1 #define _RXB1SIDL_EDI16_MASK 0x1 #define _RXB1SIDL_EDI17_POSN 0x1 #define _RXB1SIDL_EDI17_POSITION 0x1 #define _RXB1SIDL_EDI17_SIZE 0x1 #define _RXB1SIDL_EDI17_LENGTH 0x1 #define _RXB1SIDL_EDI17_MASK 0x2 #define _RXB1SIDL_SID0_POSN 0x5 #define _RXB1SIDL_SID0_POSITION 0x5 #define _RXB1SIDL_SID0_SIZE 0x1 #define _RXB1SIDL_SID0_LENGTH 0x1 #define _RXB1SIDL_SID0_MASK 0x20 #define _RXB1SIDL_SID1_POSN 0x6 #define _RXB1SIDL_SID1_POSITION 0x6 #define _RXB1SIDL_SID1_SIZE 0x1 #define _RXB1SIDL_SID1_LENGTH 0x1 #define _RXB1SIDL_SID1_MASK 0x40 #define _RXB1SIDL_SID2_POSN 0x7 #define _RXB1SIDL_SID2_POSITION 0x7 #define _RXB1SIDL_SID2_SIZE 0x1 #define _RXB1SIDL_SID2_LENGTH 0x1 #define _RXB1SIDL_SID2_MASK 0x80 #define _RXB1SIDL_RXB1EID16_POSN 0x0 #define _RXB1SIDL_RXB1EID16_POSITION 0x0 #define _RXB1SIDL_RXB1EID16_SIZE 0x1 #define _RXB1SIDL_RXB1EID16_LENGTH 0x1 #define _RXB1SIDL_RXB1EID16_MASK 0x1 #define _RXB1SIDL_RXB1EID17_POSN 0x1 #define _RXB1SIDL_RXB1EID17_POSITION 0x1 #define _RXB1SIDL_RXB1EID17_SIZE 0x1 #define _RXB1SIDL_RXB1EID17_LENGTH 0x1 #define _RXB1SIDL_RXB1EID17_MASK 0x2 #define _RXB1SIDL_RXB1EXID_POSN 0x3 #define _RXB1SIDL_RXB1EXID_POSITION 0x3 #define _RXB1SIDL_RXB1EXID_SIZE 0x1 #define _RXB1SIDL_RXB1EXID_LENGTH 0x1 #define _RXB1SIDL_RXB1EXID_MASK 0x8 #define _RXB1SIDL_RXB1SRR_POSN 0x4 #define _RXB1SIDL_RXB1SRR_POSITION 0x4 #define _RXB1SIDL_RXB1SRR_SIZE 0x1 #define _RXB1SIDL_RXB1SRR_LENGTH 0x1 #define _RXB1SIDL_RXB1SRR_MASK 0x10 #define _RXB1SIDL_RXB1SID0_POSN 0x5 #define _RXB1SIDL_RXB1SID0_POSITION 0x5 #define _RXB1SIDL_RXB1SID0_SIZE 0x1 #define _RXB1SIDL_RXB1SID0_LENGTH 0x1 #define _RXB1SIDL_RXB1SID0_MASK 0x20 #define _RXB1SIDL_RXB1SID1_POSN 0x6 #define _RXB1SIDL_RXB1SID1_POSITION 0x6 #define _RXB1SIDL_RXB1SID1_SIZE 0x1 #define _RXB1SIDL_RXB1SID1_LENGTH 0x1 #define _RXB1SIDL_RXB1SID1_MASK 0x40 #define _RXB1SIDL_RXB1SID2_POSN 0x7 #define _RXB1SIDL_RXB1SID2_POSITION 0x7 #define _RXB1SIDL_RXB1SID2_SIZE 0x1 #define _RXB1SIDL_RXB1SID2_LENGTH 0x1 #define _RXB1SIDL_RXB1SID2_MASK 0x80 // Register: RXB1EIDH #define RXB1EIDH RXB1EIDH extern volatile unsigned char RXB1EIDH @ 0xF33; #ifndef _LIB_BUILD asm("RXB1EIDH equ 0F33h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXB1EID8 :1; unsigned RXB1EID9 :1; unsigned RXB1EID10 :1; unsigned RXB1EID11 :1; unsigned RXB1EID12 :1; unsigned RXB1EID13 :1; unsigned RXB1EID14 :1; unsigned RXB1EID15 :1; }; } RXB1EIDHbits_t; extern volatile RXB1EIDHbits_t RXB1EIDHbits @ 0xF33; // bitfield macros #define _RXB1EIDH_EID_POSN 0x0 #define _RXB1EIDH_EID_POSITION 0x0 #define _RXB1EIDH_EID_SIZE 0x8 #define _RXB1EIDH_EID_LENGTH 0x8 #define _RXB1EIDH_EID_MASK 0xFF #define _RXB1EIDH_EID8_POSN 0x0 #define _RXB1EIDH_EID8_POSITION 0x0 #define _RXB1EIDH_EID8_SIZE 0x1 #define _RXB1EIDH_EID8_LENGTH 0x1 #define _RXB1EIDH_EID8_MASK 0x1 #define _RXB1EIDH_EID9_POSN 0x1 #define _RXB1EIDH_EID9_POSITION 0x1 #define _RXB1EIDH_EID9_SIZE 0x1 #define _RXB1EIDH_EID9_LENGTH 0x1 #define _RXB1EIDH_EID9_MASK 0x2 #define _RXB1EIDH_EID10_POSN 0x2 #define _RXB1EIDH_EID10_POSITION 0x2 #define _RXB1EIDH_EID10_SIZE 0x1 #define _RXB1EIDH_EID10_LENGTH 0x1 #define _RXB1EIDH_EID10_MASK 0x4 #define _RXB1EIDH_EID11_POSN 0x3 #define _RXB1EIDH_EID11_POSITION 0x3 #define _RXB1EIDH_EID11_SIZE 0x1 #define _RXB1EIDH_EID11_LENGTH 0x1 #define _RXB1EIDH_EID11_MASK 0x8 #define _RXB1EIDH_EID12_POSN 0x4 #define _RXB1EIDH_EID12_POSITION 0x4 #define _RXB1EIDH_EID12_SIZE 0x1 #define _RXB1EIDH_EID12_LENGTH 0x1 #define _RXB1EIDH_EID12_MASK 0x10 #define _RXB1EIDH_EID13_POSN 0x5 #define _RXB1EIDH_EID13_POSITION 0x5 #define _RXB1EIDH_EID13_SIZE 0x1 #define _RXB1EIDH_EID13_LENGTH 0x1 #define _RXB1EIDH_EID13_MASK 0x20 #define _RXB1EIDH_EID14_POSN 0x6 #define _RXB1EIDH_EID14_POSITION 0x6 #define _RXB1EIDH_EID14_SIZE 0x1 #define _RXB1EIDH_EID14_LENGTH 0x1 #define _RXB1EIDH_EID14_MASK 0x40 #define _RXB1EIDH_EID15_POSN 0x7 #define _RXB1EIDH_EID15_POSITION 0x7 #define _RXB1EIDH_EID15_SIZE 0x1 #define _RXB1EIDH_EID15_LENGTH 0x1 #define _RXB1EIDH_EID15_MASK 0x80 #define _RXB1EIDH_RXB1EID8_POSN 0x0 #define _RXB1EIDH_RXB1EID8_POSITION 0x0 #define _RXB1EIDH_RXB1EID8_SIZE 0x1 #define _RXB1EIDH_RXB1EID8_LENGTH 0x1 #define _RXB1EIDH_RXB1EID8_MASK 0x1 #define _RXB1EIDH_RXB1EID9_POSN 0x1 #define _RXB1EIDH_RXB1EID9_POSITION 0x1 #define _RXB1EIDH_RXB1EID9_SIZE 0x1 #define _RXB1EIDH_RXB1EID9_LENGTH 0x1 #define _RXB1EIDH_RXB1EID9_MASK 0x2 #define _RXB1EIDH_RXB1EID10_POSN 0x2 #define _RXB1EIDH_RXB1EID10_POSITION 0x2 #define _RXB1EIDH_RXB1EID10_SIZE 0x1 #define _RXB1EIDH_RXB1EID10_LENGTH 0x1 #define _RXB1EIDH_RXB1EID10_MASK 0x4 #define _RXB1EIDH_RXB1EID11_POSN 0x3 #define _RXB1EIDH_RXB1EID11_POSITION 0x3 #define _RXB1EIDH_RXB1EID11_SIZE 0x1 #define _RXB1EIDH_RXB1EID11_LENGTH 0x1 #define _RXB1EIDH_RXB1EID11_MASK 0x8 #define _RXB1EIDH_RXB1EID12_POSN 0x4 #define _RXB1EIDH_RXB1EID12_POSITION 0x4 #define _RXB1EIDH_RXB1EID12_SIZE 0x1 #define _RXB1EIDH_RXB1EID12_LENGTH 0x1 #define _RXB1EIDH_RXB1EID12_MASK 0x10 #define _RXB1EIDH_RXB1EID13_POSN 0x5 #define _RXB1EIDH_RXB1EID13_POSITION 0x5 #define _RXB1EIDH_RXB1EID13_SIZE 0x1 #define _RXB1EIDH_RXB1EID13_LENGTH 0x1 #define _RXB1EIDH_RXB1EID13_MASK 0x20 #define _RXB1EIDH_RXB1EID14_POSN 0x6 #define _RXB1EIDH_RXB1EID14_POSITION 0x6 #define _RXB1EIDH_RXB1EID14_SIZE 0x1 #define _RXB1EIDH_RXB1EID14_LENGTH 0x1 #define _RXB1EIDH_RXB1EID14_MASK 0x40 #define _RXB1EIDH_RXB1EID15_POSN 0x7 #define _RXB1EIDH_RXB1EID15_POSITION 0x7 #define _RXB1EIDH_RXB1EID15_SIZE 0x1 #define _RXB1EIDH_RXB1EID15_LENGTH 0x1 #define _RXB1EIDH_RXB1EID15_MASK 0x80 // Register: RXB1EIDL #define RXB1EIDL RXB1EIDL extern volatile unsigned char RXB1EIDL @ 0xF34; #ifndef _LIB_BUILD asm("RXB1EIDL equ 0F34h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXB1EID0 :1; unsigned RXB1EID1 :1; unsigned RXB1EID2 :1; unsigned RXB1EID3 :1; unsigned RXB1EID4 :1; unsigned RXB1EID5 :1; unsigned RXB1EID6 :1; unsigned RXB1EID7 :1; }; } RXB1EIDLbits_t; extern volatile RXB1EIDLbits_t RXB1EIDLbits @ 0xF34; // bitfield macros #define _RXB1EIDL_EID_POSN 0x0 #define _RXB1EIDL_EID_POSITION 0x0 #define _RXB1EIDL_EID_SIZE 0x8 #define _RXB1EIDL_EID_LENGTH 0x8 #define _RXB1EIDL_EID_MASK 0xFF #define _RXB1EIDL_EID0_POSN 0x0 #define _RXB1EIDL_EID0_POSITION 0x0 #define _RXB1EIDL_EID0_SIZE 0x1 #define _RXB1EIDL_EID0_LENGTH 0x1 #define _RXB1EIDL_EID0_MASK 0x1 #define _RXB1EIDL_EID1_POSN 0x1 #define _RXB1EIDL_EID1_POSITION 0x1 #define _RXB1EIDL_EID1_SIZE 0x1 #define _RXB1EIDL_EID1_LENGTH 0x1 #define _RXB1EIDL_EID1_MASK 0x2 #define _RXB1EIDL_EID2_POSN 0x2 #define _RXB1EIDL_EID2_POSITION 0x2 #define _RXB1EIDL_EID2_SIZE 0x1 #define _RXB1EIDL_EID2_LENGTH 0x1 #define _RXB1EIDL_EID2_MASK 0x4 #define _RXB1EIDL_EID3_POSN 0x3 #define _RXB1EIDL_EID3_POSITION 0x3 #define _RXB1EIDL_EID3_SIZE 0x1 #define _RXB1EIDL_EID3_LENGTH 0x1 #define _RXB1EIDL_EID3_MASK 0x8 #define _RXB1EIDL_EID4_POSN 0x4 #define _RXB1EIDL_EID4_POSITION 0x4 #define _RXB1EIDL_EID4_SIZE 0x1 #define _RXB1EIDL_EID4_LENGTH 0x1 #define _RXB1EIDL_EID4_MASK 0x10 #define _RXB1EIDL_EID5_POSN 0x5 #define _RXB1EIDL_EID5_POSITION 0x5 #define _RXB1EIDL_EID5_SIZE 0x1 #define _RXB1EIDL_EID5_LENGTH 0x1 #define _RXB1EIDL_EID5_MASK 0x20 #define _RXB1EIDL_EID6_POSN 0x6 #define _RXB1EIDL_EID6_POSITION 0x6 #define _RXB1EIDL_EID6_SIZE 0x1 #define _RXB1EIDL_EID6_LENGTH 0x1 #define _RXB1EIDL_EID6_MASK 0x40 #define _RXB1EIDL_EID7_POSN 0x7 #define _RXB1EIDL_EID7_POSITION 0x7 #define _RXB1EIDL_EID7_SIZE 0x1 #define _RXB1EIDL_EID7_LENGTH 0x1 #define _RXB1EIDL_EID7_MASK 0x80 #define _RXB1EIDL_RXB1EID0_POSN 0x0 #define _RXB1EIDL_RXB1EID0_POSITION 0x0 #define _RXB1EIDL_RXB1EID0_SIZE 0x1 #define _RXB1EIDL_RXB1EID0_LENGTH 0x1 #define _RXB1EIDL_RXB1EID0_MASK 0x1 #define _RXB1EIDL_RXB1EID1_POSN 0x1 #define _RXB1EIDL_RXB1EID1_POSITION 0x1 #define _RXB1EIDL_RXB1EID1_SIZE 0x1 #define _RXB1EIDL_RXB1EID1_LENGTH 0x1 #define _RXB1EIDL_RXB1EID1_MASK 0x2 #define _RXB1EIDL_RXB1EID2_POSN 0x2 #define _RXB1EIDL_RXB1EID2_POSITION 0x2 #define _RXB1EIDL_RXB1EID2_SIZE 0x1 #define _RXB1EIDL_RXB1EID2_LENGTH 0x1 #define _RXB1EIDL_RXB1EID2_MASK 0x4 #define _RXB1EIDL_RXB1EID3_POSN 0x3 #define _RXB1EIDL_RXB1EID3_POSITION 0x3 #define _RXB1EIDL_RXB1EID3_SIZE 0x1 #define _RXB1EIDL_RXB1EID3_LENGTH 0x1 #define _RXB1EIDL_RXB1EID3_MASK 0x8 #define _RXB1EIDL_RXB1EID4_POSN 0x4 #define _RXB1EIDL_RXB1EID4_POSITION 0x4 #define _RXB1EIDL_RXB1EID4_SIZE 0x1 #define _RXB1EIDL_RXB1EID4_LENGTH 0x1 #define _RXB1EIDL_RXB1EID4_MASK 0x10 #define _RXB1EIDL_RXB1EID5_POSN 0x5 #define _RXB1EIDL_RXB1EID5_POSITION 0x5 #define _RXB1EIDL_RXB1EID5_SIZE 0x1 #define _RXB1EIDL_RXB1EID5_LENGTH 0x1 #define _RXB1EIDL_RXB1EID5_MASK 0x20 #define _RXB1EIDL_RXB1EID6_POSN 0x6 #define _RXB1EIDL_RXB1EID6_POSITION 0x6 #define _RXB1EIDL_RXB1EID6_SIZE 0x1 #define _RXB1EIDL_RXB1EID6_LENGTH 0x1 #define _RXB1EIDL_RXB1EID6_MASK 0x40 #define _RXB1EIDL_RXB1EID7_POSN 0x7 #define _RXB1EIDL_RXB1EID7_POSITION 0x7 #define _RXB1EIDL_RXB1EID7_SIZE 0x1 #define _RXB1EIDL_RXB1EID7_LENGTH 0x1 #define _RXB1EIDL_RXB1EID7_MASK 0x80 // Register: RXB1DLC #define RXB1DLC RXB1DLC extern volatile unsigned char RXB1DLC @ 0xF35; #ifndef _LIB_BUILD asm("RXB1DLC equ 0F35h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; }; struct { unsigned RXB1DLC0 :1; unsigned RXB1DLC1 :1; unsigned RXB1DLC2 :1; unsigned RXB1DLC3 :1; unsigned RXB1RB0 :1; unsigned RXB1RB1 :1; unsigned RXB1RTR :1; }; } RXB1DLCbits_t; extern volatile RXB1DLCbits_t RXB1DLCbits @ 0xF35; // bitfield macros #define _RXB1DLC_DLC_POSN 0x0 #define _RXB1DLC_DLC_POSITION 0x0 #define _RXB1DLC_DLC_SIZE 0x4 #define _RXB1DLC_DLC_LENGTH 0x4 #define _RXB1DLC_DLC_MASK 0xF #define _RXB1DLC_RB_POSN 0x4 #define _RXB1DLC_RB_POSITION 0x4 #define _RXB1DLC_RB_SIZE 0x2 #define _RXB1DLC_RB_LENGTH 0x2 #define _RXB1DLC_RB_MASK 0x30 #define _RXB1DLC_RXRTR_POSN 0x6 #define _RXB1DLC_RXRTR_POSITION 0x6 #define _RXB1DLC_RXRTR_SIZE 0x1 #define _RXB1DLC_RXRTR_LENGTH 0x1 #define _RXB1DLC_RXRTR_MASK 0x40 #define _RXB1DLC_DLC0_POSN 0x0 #define _RXB1DLC_DLC0_POSITION 0x0 #define _RXB1DLC_DLC0_SIZE 0x1 #define _RXB1DLC_DLC0_LENGTH 0x1 #define _RXB1DLC_DLC0_MASK 0x1 #define _RXB1DLC_DLC1_POSN 0x1 #define _RXB1DLC_DLC1_POSITION 0x1 #define _RXB1DLC_DLC1_SIZE 0x1 #define _RXB1DLC_DLC1_LENGTH 0x1 #define _RXB1DLC_DLC1_MASK 0x2 #define _RXB1DLC_DLC2_POSN 0x2 #define _RXB1DLC_DLC2_POSITION 0x2 #define _RXB1DLC_DLC2_SIZE 0x1 #define _RXB1DLC_DLC2_LENGTH 0x1 #define _RXB1DLC_DLC2_MASK 0x4 #define _RXB1DLC_DLC3_POSN 0x3 #define _RXB1DLC_DLC3_POSITION 0x3 #define _RXB1DLC_DLC3_SIZE 0x1 #define _RXB1DLC_DLC3_LENGTH 0x1 #define _RXB1DLC_DLC3_MASK 0x8 #define _RXB1DLC_RB0_POSN 0x4 #define _RXB1DLC_RB0_POSITION 0x4 #define _RXB1DLC_RB0_SIZE 0x1 #define _RXB1DLC_RB0_LENGTH 0x1 #define _RXB1DLC_RB0_MASK 0x10 #define _RXB1DLC_RB1_POSN 0x5 #define _RXB1DLC_RB1_POSITION 0x5 #define _RXB1DLC_RB1_SIZE 0x1 #define _RXB1DLC_RB1_LENGTH 0x1 #define _RXB1DLC_RB1_MASK 0x20 #define _RXB1DLC_RXB1DLC0_POSN 0x0 #define _RXB1DLC_RXB1DLC0_POSITION 0x0 #define _RXB1DLC_RXB1DLC0_SIZE 0x1 #define _RXB1DLC_RXB1DLC0_LENGTH 0x1 #define _RXB1DLC_RXB1DLC0_MASK 0x1 #define _RXB1DLC_RXB1DLC1_POSN 0x1 #define _RXB1DLC_RXB1DLC1_POSITION 0x1 #define _RXB1DLC_RXB1DLC1_SIZE 0x1 #define _RXB1DLC_RXB1DLC1_LENGTH 0x1 #define _RXB1DLC_RXB1DLC1_MASK 0x2 #define _RXB1DLC_RXB1DLC2_POSN 0x2 #define _RXB1DLC_RXB1DLC2_POSITION 0x2 #define _RXB1DLC_RXB1DLC2_SIZE 0x1 #define _RXB1DLC_RXB1DLC2_LENGTH 0x1 #define _RXB1DLC_RXB1DLC2_MASK 0x4 #define _RXB1DLC_RXB1DLC3_POSN 0x3 #define _RXB1DLC_RXB1DLC3_POSITION 0x3 #define _RXB1DLC_RXB1DLC3_SIZE 0x1 #define _RXB1DLC_RXB1DLC3_LENGTH 0x1 #define _RXB1DLC_RXB1DLC3_MASK 0x8 #define _RXB1DLC_RXB1RB0_POSN 0x4 #define _RXB1DLC_RXB1RB0_POSITION 0x4 #define _RXB1DLC_RXB1RB0_SIZE 0x1 #define _RXB1DLC_RXB1RB0_LENGTH 0x1 #define _RXB1DLC_RXB1RB0_MASK 0x10 #define _RXB1DLC_RXB1RB1_POSN 0x5 #define _RXB1DLC_RXB1RB1_POSITION 0x5 #define _RXB1DLC_RXB1RB1_SIZE 0x1 #define _RXB1DLC_RXB1RB1_LENGTH 0x1 #define _RXB1DLC_RXB1RB1_MASK 0x20 #define _RXB1DLC_RXB1RTR_POSN 0x6 #define _RXB1DLC_RXB1RTR_POSITION 0x6 #define _RXB1DLC_RXB1RTR_SIZE 0x1 #define _RXB1DLC_RXB1RTR_LENGTH 0x1 #define _RXB1DLC_RXB1RTR_MASK 0x40 // Register: RXB1D0 #define RXB1D0 RXB1D0 extern volatile unsigned char RXB1D0 @ 0xF36; #ifndef _LIB_BUILD asm("RXB1D0 equ 0F36h"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D0 :8; }; struct { unsigned RXB1D00 :1; unsigned RXB1D01 :1; unsigned RXB1D02 :1; unsigned RXB1D03 :1; unsigned RXB1D04 :1; unsigned RXB1D05 :1; unsigned RXB1D06 :1; unsigned RXB1D07 :1; }; } RXB1D0bits_t; extern volatile RXB1D0bits_t RXB1D0bits @ 0xF36; // bitfield macros #define _RXB1D0_RXB1D0_POSN 0x0 #define _RXB1D0_RXB1D0_POSITION 0x0 #define _RXB1D0_RXB1D0_SIZE 0x8 #define _RXB1D0_RXB1D0_LENGTH 0x8 #define _RXB1D0_RXB1D0_MASK 0xFF #define _RXB1D0_RXB1D00_POSN 0x0 #define _RXB1D0_RXB1D00_POSITION 0x0 #define _RXB1D0_RXB1D00_SIZE 0x1 #define _RXB1D0_RXB1D00_LENGTH 0x1 #define _RXB1D0_RXB1D00_MASK 0x1 #define _RXB1D0_RXB1D01_POSN 0x1 #define _RXB1D0_RXB1D01_POSITION 0x1 #define _RXB1D0_RXB1D01_SIZE 0x1 #define _RXB1D0_RXB1D01_LENGTH 0x1 #define _RXB1D0_RXB1D01_MASK 0x2 #define _RXB1D0_RXB1D02_POSN 0x2 #define _RXB1D0_RXB1D02_POSITION 0x2 #define _RXB1D0_RXB1D02_SIZE 0x1 #define _RXB1D0_RXB1D02_LENGTH 0x1 #define _RXB1D0_RXB1D02_MASK 0x4 #define _RXB1D0_RXB1D03_POSN 0x3 #define _RXB1D0_RXB1D03_POSITION 0x3 #define _RXB1D0_RXB1D03_SIZE 0x1 #define _RXB1D0_RXB1D03_LENGTH 0x1 #define _RXB1D0_RXB1D03_MASK 0x8 #define _RXB1D0_RXB1D04_POSN 0x4 #define _RXB1D0_RXB1D04_POSITION 0x4 #define _RXB1D0_RXB1D04_SIZE 0x1 #define _RXB1D0_RXB1D04_LENGTH 0x1 #define _RXB1D0_RXB1D04_MASK 0x10 #define _RXB1D0_RXB1D05_POSN 0x5 #define _RXB1D0_RXB1D05_POSITION 0x5 #define _RXB1D0_RXB1D05_SIZE 0x1 #define _RXB1D0_RXB1D05_LENGTH 0x1 #define _RXB1D0_RXB1D05_MASK 0x20 #define _RXB1D0_RXB1D06_POSN 0x6 #define _RXB1D0_RXB1D06_POSITION 0x6 #define _RXB1D0_RXB1D06_SIZE 0x1 #define _RXB1D0_RXB1D06_LENGTH 0x1 #define _RXB1D0_RXB1D06_MASK 0x40 #define _RXB1D0_RXB1D07_POSN 0x7 #define _RXB1D0_RXB1D07_POSITION 0x7 #define _RXB1D0_RXB1D07_SIZE 0x1 #define _RXB1D0_RXB1D07_LENGTH 0x1 #define _RXB1D0_RXB1D07_MASK 0x80 // Register: RXB1D1 #define RXB1D1 RXB1D1 extern volatile unsigned char RXB1D1 @ 0xF37; #ifndef _LIB_BUILD asm("RXB1D1 equ 0F37h"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D1 :8; }; struct { unsigned RXB1D10 :1; unsigned RXB1D11 :1; unsigned RXB1D12 :1; unsigned RXB1D13 :1; unsigned RXB1D14 :1; unsigned RXB1D15 :1; unsigned RXB1D16 :1; unsigned RXB1D17 :1; }; } RXB1D1bits_t; extern volatile RXB1D1bits_t RXB1D1bits @ 0xF37; // bitfield macros #define _RXB1D1_RXB1D1_POSN 0x0 #define _RXB1D1_RXB1D1_POSITION 0x0 #define _RXB1D1_RXB1D1_SIZE 0x8 #define _RXB1D1_RXB1D1_LENGTH 0x8 #define _RXB1D1_RXB1D1_MASK 0xFF #define _RXB1D1_RXB1D10_POSN 0x0 #define _RXB1D1_RXB1D10_POSITION 0x0 #define _RXB1D1_RXB1D10_SIZE 0x1 #define _RXB1D1_RXB1D10_LENGTH 0x1 #define _RXB1D1_RXB1D10_MASK 0x1 #define _RXB1D1_RXB1D11_POSN 0x1 #define _RXB1D1_RXB1D11_POSITION 0x1 #define _RXB1D1_RXB1D11_SIZE 0x1 #define _RXB1D1_RXB1D11_LENGTH 0x1 #define _RXB1D1_RXB1D11_MASK 0x2 #define _RXB1D1_RXB1D12_POSN 0x2 #define _RXB1D1_RXB1D12_POSITION 0x2 #define _RXB1D1_RXB1D12_SIZE 0x1 #define _RXB1D1_RXB1D12_LENGTH 0x1 #define _RXB1D1_RXB1D12_MASK 0x4 #define _RXB1D1_RXB1D13_POSN 0x3 #define _RXB1D1_RXB1D13_POSITION 0x3 #define _RXB1D1_RXB1D13_SIZE 0x1 #define _RXB1D1_RXB1D13_LENGTH 0x1 #define _RXB1D1_RXB1D13_MASK 0x8 #define _RXB1D1_RXB1D14_POSN 0x4 #define _RXB1D1_RXB1D14_POSITION 0x4 #define _RXB1D1_RXB1D14_SIZE 0x1 #define _RXB1D1_RXB1D14_LENGTH 0x1 #define _RXB1D1_RXB1D14_MASK 0x10 #define _RXB1D1_RXB1D15_POSN 0x5 #define _RXB1D1_RXB1D15_POSITION 0x5 #define _RXB1D1_RXB1D15_SIZE 0x1 #define _RXB1D1_RXB1D15_LENGTH 0x1 #define _RXB1D1_RXB1D15_MASK 0x20 #define _RXB1D1_RXB1D16_POSN 0x6 #define _RXB1D1_RXB1D16_POSITION 0x6 #define _RXB1D1_RXB1D16_SIZE 0x1 #define _RXB1D1_RXB1D16_LENGTH 0x1 #define _RXB1D1_RXB1D16_MASK 0x40 #define _RXB1D1_RXB1D17_POSN 0x7 #define _RXB1D1_RXB1D17_POSITION 0x7 #define _RXB1D1_RXB1D17_SIZE 0x1 #define _RXB1D1_RXB1D17_LENGTH 0x1 #define _RXB1D1_RXB1D17_MASK 0x80 // Register: RXB1D2 #define RXB1D2 RXB1D2 extern volatile unsigned char RXB1D2 @ 0xF38; #ifndef _LIB_BUILD asm("RXB1D2 equ 0F38h"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D2 :8; }; struct { unsigned RXB1D20 :1; unsigned RXB1D21 :1; unsigned RXB1D22 :1; unsigned RXB1D23 :1; unsigned RXB1D24 :1; unsigned RXB1D25 :1; unsigned RXB1D26 :1; unsigned RXB1D27 :1; }; } RXB1D2bits_t; extern volatile RXB1D2bits_t RXB1D2bits @ 0xF38; // bitfield macros #define _RXB1D2_RXB1D2_POSN 0x0 #define _RXB1D2_RXB1D2_POSITION 0x0 #define _RXB1D2_RXB1D2_SIZE 0x8 #define _RXB1D2_RXB1D2_LENGTH 0x8 #define _RXB1D2_RXB1D2_MASK 0xFF #define _RXB1D2_RXB1D20_POSN 0x0 #define _RXB1D2_RXB1D20_POSITION 0x0 #define _RXB1D2_RXB1D20_SIZE 0x1 #define _RXB1D2_RXB1D20_LENGTH 0x1 #define _RXB1D2_RXB1D20_MASK 0x1 #define _RXB1D2_RXB1D21_POSN 0x1 #define _RXB1D2_RXB1D21_POSITION 0x1 #define _RXB1D2_RXB1D21_SIZE 0x1 #define _RXB1D2_RXB1D21_LENGTH 0x1 #define _RXB1D2_RXB1D21_MASK 0x2 #define _RXB1D2_RXB1D22_POSN 0x2 #define _RXB1D2_RXB1D22_POSITION 0x2 #define _RXB1D2_RXB1D22_SIZE 0x1 #define _RXB1D2_RXB1D22_LENGTH 0x1 #define _RXB1D2_RXB1D22_MASK 0x4 #define _RXB1D2_RXB1D23_POSN 0x3 #define _RXB1D2_RXB1D23_POSITION 0x3 #define _RXB1D2_RXB1D23_SIZE 0x1 #define _RXB1D2_RXB1D23_LENGTH 0x1 #define _RXB1D2_RXB1D23_MASK 0x8 #define _RXB1D2_RXB1D24_POSN 0x4 #define _RXB1D2_RXB1D24_POSITION 0x4 #define _RXB1D2_RXB1D24_SIZE 0x1 #define _RXB1D2_RXB1D24_LENGTH 0x1 #define _RXB1D2_RXB1D24_MASK 0x10 #define _RXB1D2_RXB1D25_POSN 0x5 #define _RXB1D2_RXB1D25_POSITION 0x5 #define _RXB1D2_RXB1D25_SIZE 0x1 #define _RXB1D2_RXB1D25_LENGTH 0x1 #define _RXB1D2_RXB1D25_MASK 0x20 #define _RXB1D2_RXB1D26_POSN 0x6 #define _RXB1D2_RXB1D26_POSITION 0x6 #define _RXB1D2_RXB1D26_SIZE 0x1 #define _RXB1D2_RXB1D26_LENGTH 0x1 #define _RXB1D2_RXB1D26_MASK 0x40 #define _RXB1D2_RXB1D27_POSN 0x7 #define _RXB1D2_RXB1D27_POSITION 0x7 #define _RXB1D2_RXB1D27_SIZE 0x1 #define _RXB1D2_RXB1D27_LENGTH 0x1 #define _RXB1D2_RXB1D27_MASK 0x80 // Register: RXB1D3 #define RXB1D3 RXB1D3 extern volatile unsigned char RXB1D3 @ 0xF39; #ifndef _LIB_BUILD asm("RXB1D3 equ 0F39h"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D3 :8; }; struct { unsigned RXB1D30 :1; unsigned RXB1D31 :1; unsigned RXB1D32 :1; unsigned RXB1D33 :1; unsigned RXB1D34 :1; unsigned RXB1D35 :1; unsigned RXB1D36 :1; unsigned RXB1D37 :1; }; } RXB1D3bits_t; extern volatile RXB1D3bits_t RXB1D3bits @ 0xF39; // bitfield macros #define _RXB1D3_RXB1D3_POSN 0x0 #define _RXB1D3_RXB1D3_POSITION 0x0 #define _RXB1D3_RXB1D3_SIZE 0x8 #define _RXB1D3_RXB1D3_LENGTH 0x8 #define _RXB1D3_RXB1D3_MASK 0xFF #define _RXB1D3_RXB1D30_POSN 0x0 #define _RXB1D3_RXB1D30_POSITION 0x0 #define _RXB1D3_RXB1D30_SIZE 0x1 #define _RXB1D3_RXB1D30_LENGTH 0x1 #define _RXB1D3_RXB1D30_MASK 0x1 #define _RXB1D3_RXB1D31_POSN 0x1 #define _RXB1D3_RXB1D31_POSITION 0x1 #define _RXB1D3_RXB1D31_SIZE 0x1 #define _RXB1D3_RXB1D31_LENGTH 0x1 #define _RXB1D3_RXB1D31_MASK 0x2 #define _RXB1D3_RXB1D32_POSN 0x2 #define _RXB1D3_RXB1D32_POSITION 0x2 #define _RXB1D3_RXB1D32_SIZE 0x1 #define _RXB1D3_RXB1D32_LENGTH 0x1 #define _RXB1D3_RXB1D32_MASK 0x4 #define _RXB1D3_RXB1D33_POSN 0x3 #define _RXB1D3_RXB1D33_POSITION 0x3 #define _RXB1D3_RXB1D33_SIZE 0x1 #define _RXB1D3_RXB1D33_LENGTH 0x1 #define _RXB1D3_RXB1D33_MASK 0x8 #define _RXB1D3_RXB1D34_POSN 0x4 #define _RXB1D3_RXB1D34_POSITION 0x4 #define _RXB1D3_RXB1D34_SIZE 0x1 #define _RXB1D3_RXB1D34_LENGTH 0x1 #define _RXB1D3_RXB1D34_MASK 0x10 #define _RXB1D3_RXB1D35_POSN 0x5 #define _RXB1D3_RXB1D35_POSITION 0x5 #define _RXB1D3_RXB1D35_SIZE 0x1 #define _RXB1D3_RXB1D35_LENGTH 0x1 #define _RXB1D3_RXB1D35_MASK 0x20 #define _RXB1D3_RXB1D36_POSN 0x6 #define _RXB1D3_RXB1D36_POSITION 0x6 #define _RXB1D3_RXB1D36_SIZE 0x1 #define _RXB1D3_RXB1D36_LENGTH 0x1 #define _RXB1D3_RXB1D36_MASK 0x40 #define _RXB1D3_RXB1D37_POSN 0x7 #define _RXB1D3_RXB1D37_POSITION 0x7 #define _RXB1D3_RXB1D37_SIZE 0x1 #define _RXB1D3_RXB1D37_LENGTH 0x1 #define _RXB1D3_RXB1D37_MASK 0x80 // Register: RXB1D4 #define RXB1D4 RXB1D4 extern volatile unsigned char RXB1D4 @ 0xF3A; #ifndef _LIB_BUILD asm("RXB1D4 equ 0F3Ah"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D4 :8; }; struct { unsigned RXB1D40 :1; unsigned RXB1D41 :1; unsigned RXB1D42 :1; unsigned RXB1D43 :1; unsigned RXB1D44 :1; unsigned RXB1D45 :1; unsigned RXB1D46 :1; unsigned RXB1D47 :1; }; } RXB1D4bits_t; extern volatile RXB1D4bits_t RXB1D4bits @ 0xF3A; // bitfield macros #define _RXB1D4_RXB1D4_POSN 0x0 #define _RXB1D4_RXB1D4_POSITION 0x0 #define _RXB1D4_RXB1D4_SIZE 0x8 #define _RXB1D4_RXB1D4_LENGTH 0x8 #define _RXB1D4_RXB1D4_MASK 0xFF #define _RXB1D4_RXB1D40_POSN 0x0 #define _RXB1D4_RXB1D40_POSITION 0x0 #define _RXB1D4_RXB1D40_SIZE 0x1 #define _RXB1D4_RXB1D40_LENGTH 0x1 #define _RXB1D4_RXB1D40_MASK 0x1 #define _RXB1D4_RXB1D41_POSN 0x1 #define _RXB1D4_RXB1D41_POSITION 0x1 #define _RXB1D4_RXB1D41_SIZE 0x1 #define _RXB1D4_RXB1D41_LENGTH 0x1 #define _RXB1D4_RXB1D41_MASK 0x2 #define _RXB1D4_RXB1D42_POSN 0x2 #define _RXB1D4_RXB1D42_POSITION 0x2 #define _RXB1D4_RXB1D42_SIZE 0x1 #define _RXB1D4_RXB1D42_LENGTH 0x1 #define _RXB1D4_RXB1D42_MASK 0x4 #define _RXB1D4_RXB1D43_POSN 0x3 #define _RXB1D4_RXB1D43_POSITION 0x3 #define _RXB1D4_RXB1D43_SIZE 0x1 #define _RXB1D4_RXB1D43_LENGTH 0x1 #define _RXB1D4_RXB1D43_MASK 0x8 #define _RXB1D4_RXB1D44_POSN 0x4 #define _RXB1D4_RXB1D44_POSITION 0x4 #define _RXB1D4_RXB1D44_SIZE 0x1 #define _RXB1D4_RXB1D44_LENGTH 0x1 #define _RXB1D4_RXB1D44_MASK 0x10 #define _RXB1D4_RXB1D45_POSN 0x5 #define _RXB1D4_RXB1D45_POSITION 0x5 #define _RXB1D4_RXB1D45_SIZE 0x1 #define _RXB1D4_RXB1D45_LENGTH 0x1 #define _RXB1D4_RXB1D45_MASK 0x20 #define _RXB1D4_RXB1D46_POSN 0x6 #define _RXB1D4_RXB1D46_POSITION 0x6 #define _RXB1D4_RXB1D46_SIZE 0x1 #define _RXB1D4_RXB1D46_LENGTH 0x1 #define _RXB1D4_RXB1D46_MASK 0x40 #define _RXB1D4_RXB1D47_POSN 0x7 #define _RXB1D4_RXB1D47_POSITION 0x7 #define _RXB1D4_RXB1D47_SIZE 0x1 #define _RXB1D4_RXB1D47_LENGTH 0x1 #define _RXB1D4_RXB1D47_MASK 0x80 // Register: RXB1D5 #define RXB1D5 RXB1D5 extern volatile unsigned char RXB1D5 @ 0xF3B; #ifndef _LIB_BUILD asm("RXB1D5 equ 0F3Bh"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D5 :8; }; struct { unsigned RXB1D50 :1; unsigned RXB1D51 :1; unsigned RXB1D52 :1; unsigned RXB1D53 :1; unsigned RXB1D54 :1; unsigned RXB1D55 :1; unsigned RXB1D56 :1; unsigned RXB1D57 :1; }; } RXB1D5bits_t; extern volatile RXB1D5bits_t RXB1D5bits @ 0xF3B; // bitfield macros #define _RXB1D5_RXB1D5_POSN 0x0 #define _RXB1D5_RXB1D5_POSITION 0x0 #define _RXB1D5_RXB1D5_SIZE 0x8 #define _RXB1D5_RXB1D5_LENGTH 0x8 #define _RXB1D5_RXB1D5_MASK 0xFF #define _RXB1D5_RXB1D50_POSN 0x0 #define _RXB1D5_RXB1D50_POSITION 0x0 #define _RXB1D5_RXB1D50_SIZE 0x1 #define _RXB1D5_RXB1D50_LENGTH 0x1 #define _RXB1D5_RXB1D50_MASK 0x1 #define _RXB1D5_RXB1D51_POSN 0x1 #define _RXB1D5_RXB1D51_POSITION 0x1 #define _RXB1D5_RXB1D51_SIZE 0x1 #define _RXB1D5_RXB1D51_LENGTH 0x1 #define _RXB1D5_RXB1D51_MASK 0x2 #define _RXB1D5_RXB1D52_POSN 0x2 #define _RXB1D5_RXB1D52_POSITION 0x2 #define _RXB1D5_RXB1D52_SIZE 0x1 #define _RXB1D5_RXB1D52_LENGTH 0x1 #define _RXB1D5_RXB1D52_MASK 0x4 #define _RXB1D5_RXB1D53_POSN 0x3 #define _RXB1D5_RXB1D53_POSITION 0x3 #define _RXB1D5_RXB1D53_SIZE 0x1 #define _RXB1D5_RXB1D53_LENGTH 0x1 #define _RXB1D5_RXB1D53_MASK 0x8 #define _RXB1D5_RXB1D54_POSN 0x4 #define _RXB1D5_RXB1D54_POSITION 0x4 #define _RXB1D5_RXB1D54_SIZE 0x1 #define _RXB1D5_RXB1D54_LENGTH 0x1 #define _RXB1D5_RXB1D54_MASK 0x10 #define _RXB1D5_RXB1D55_POSN 0x5 #define _RXB1D5_RXB1D55_POSITION 0x5 #define _RXB1D5_RXB1D55_SIZE 0x1 #define _RXB1D5_RXB1D55_LENGTH 0x1 #define _RXB1D5_RXB1D55_MASK 0x20 #define _RXB1D5_RXB1D56_POSN 0x6 #define _RXB1D5_RXB1D56_POSITION 0x6 #define _RXB1D5_RXB1D56_SIZE 0x1 #define _RXB1D5_RXB1D56_LENGTH 0x1 #define _RXB1D5_RXB1D56_MASK 0x40 #define _RXB1D5_RXB1D57_POSN 0x7 #define _RXB1D5_RXB1D57_POSITION 0x7 #define _RXB1D5_RXB1D57_SIZE 0x1 #define _RXB1D5_RXB1D57_LENGTH 0x1 #define _RXB1D5_RXB1D57_MASK 0x80 // Register: RXB1D6 #define RXB1D6 RXB1D6 extern volatile unsigned char RXB1D6 @ 0xF3C; #ifndef _LIB_BUILD asm("RXB1D6 equ 0F3Ch"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D6 :8; }; struct { unsigned RXB1D60 :1; unsigned RXB1D61 :1; unsigned RXB1D62 :1; unsigned RXB1D63 :1; unsigned RXB1D64 :1; unsigned RXB1D65 :1; unsigned RXB1D66 :1; unsigned RXB1D67 :1; }; } RXB1D6bits_t; extern volatile RXB1D6bits_t RXB1D6bits @ 0xF3C; // bitfield macros #define _RXB1D6_RXB1D6_POSN 0x0 #define _RXB1D6_RXB1D6_POSITION 0x0 #define _RXB1D6_RXB1D6_SIZE 0x8 #define _RXB1D6_RXB1D6_LENGTH 0x8 #define _RXB1D6_RXB1D6_MASK 0xFF #define _RXB1D6_RXB1D60_POSN 0x0 #define _RXB1D6_RXB1D60_POSITION 0x0 #define _RXB1D6_RXB1D60_SIZE 0x1 #define _RXB1D6_RXB1D60_LENGTH 0x1 #define _RXB1D6_RXB1D60_MASK 0x1 #define _RXB1D6_RXB1D61_POSN 0x1 #define _RXB1D6_RXB1D61_POSITION 0x1 #define _RXB1D6_RXB1D61_SIZE 0x1 #define _RXB1D6_RXB1D61_LENGTH 0x1 #define _RXB1D6_RXB1D61_MASK 0x2 #define _RXB1D6_RXB1D62_POSN 0x2 #define _RXB1D6_RXB1D62_POSITION 0x2 #define _RXB1D6_RXB1D62_SIZE 0x1 #define _RXB1D6_RXB1D62_LENGTH 0x1 #define _RXB1D6_RXB1D62_MASK 0x4 #define _RXB1D6_RXB1D63_POSN 0x3 #define _RXB1D6_RXB1D63_POSITION 0x3 #define _RXB1D6_RXB1D63_SIZE 0x1 #define _RXB1D6_RXB1D63_LENGTH 0x1 #define _RXB1D6_RXB1D63_MASK 0x8 #define _RXB1D6_RXB1D64_POSN 0x4 #define _RXB1D6_RXB1D64_POSITION 0x4 #define _RXB1D6_RXB1D64_SIZE 0x1 #define _RXB1D6_RXB1D64_LENGTH 0x1 #define _RXB1D6_RXB1D64_MASK 0x10 #define _RXB1D6_RXB1D65_POSN 0x5 #define _RXB1D6_RXB1D65_POSITION 0x5 #define _RXB1D6_RXB1D65_SIZE 0x1 #define _RXB1D6_RXB1D65_LENGTH 0x1 #define _RXB1D6_RXB1D65_MASK 0x20 #define _RXB1D6_RXB1D66_POSN 0x6 #define _RXB1D6_RXB1D66_POSITION 0x6 #define _RXB1D6_RXB1D66_SIZE 0x1 #define _RXB1D6_RXB1D66_LENGTH 0x1 #define _RXB1D6_RXB1D66_MASK 0x40 #define _RXB1D6_RXB1D67_POSN 0x7 #define _RXB1D6_RXB1D67_POSITION 0x7 #define _RXB1D6_RXB1D67_SIZE 0x1 #define _RXB1D6_RXB1D67_LENGTH 0x1 #define _RXB1D6_RXB1D67_MASK 0x80 // Register: RXB1D7 #define RXB1D7 RXB1D7 extern volatile unsigned char RXB1D7 @ 0xF3D; #ifndef _LIB_BUILD asm("RXB1D7 equ 0F3Dh"); #endif // bitfield definitions typedef union { struct { unsigned RXB1D7 :8; }; struct { unsigned RXB1D70 :1; unsigned RXB1D71 :1; unsigned RXB1D72 :1; unsigned RXB1D73 :1; unsigned RXB1D74 :1; unsigned RXB1D75 :1; unsigned RXB1D76 :1; unsigned RXB1D77 :1; }; } RXB1D7bits_t; extern volatile RXB1D7bits_t RXB1D7bits @ 0xF3D; // bitfield macros #define _RXB1D7_RXB1D7_POSN 0x0 #define _RXB1D7_RXB1D7_POSITION 0x0 #define _RXB1D7_RXB1D7_SIZE 0x8 #define _RXB1D7_RXB1D7_LENGTH 0x8 #define _RXB1D7_RXB1D7_MASK 0xFF #define _RXB1D7_RXB1D70_POSN 0x0 #define _RXB1D7_RXB1D70_POSITION 0x0 #define _RXB1D7_RXB1D70_SIZE 0x1 #define _RXB1D7_RXB1D70_LENGTH 0x1 #define _RXB1D7_RXB1D70_MASK 0x1 #define _RXB1D7_RXB1D71_POSN 0x1 #define _RXB1D7_RXB1D71_POSITION 0x1 #define _RXB1D7_RXB1D71_SIZE 0x1 #define _RXB1D7_RXB1D71_LENGTH 0x1 #define _RXB1D7_RXB1D71_MASK 0x2 #define _RXB1D7_RXB1D72_POSN 0x2 #define _RXB1D7_RXB1D72_POSITION 0x2 #define _RXB1D7_RXB1D72_SIZE 0x1 #define _RXB1D7_RXB1D72_LENGTH 0x1 #define _RXB1D7_RXB1D72_MASK 0x4 #define _RXB1D7_RXB1D73_POSN 0x3 #define _RXB1D7_RXB1D73_POSITION 0x3 #define _RXB1D7_RXB1D73_SIZE 0x1 #define _RXB1D7_RXB1D73_LENGTH 0x1 #define _RXB1D7_RXB1D73_MASK 0x8 #define _RXB1D7_RXB1D74_POSN 0x4 #define _RXB1D7_RXB1D74_POSITION 0x4 #define _RXB1D7_RXB1D74_SIZE 0x1 #define _RXB1D7_RXB1D74_LENGTH 0x1 #define _RXB1D7_RXB1D74_MASK 0x10 #define _RXB1D7_RXB1D75_POSN 0x5 #define _RXB1D7_RXB1D75_POSITION 0x5 #define _RXB1D7_RXB1D75_SIZE 0x1 #define _RXB1D7_RXB1D75_LENGTH 0x1 #define _RXB1D7_RXB1D75_MASK 0x20 #define _RXB1D7_RXB1D76_POSN 0x6 #define _RXB1D7_RXB1D76_POSITION 0x6 #define _RXB1D7_RXB1D76_SIZE 0x1 #define _RXB1D7_RXB1D76_LENGTH 0x1 #define _RXB1D7_RXB1D76_MASK 0x40 #define _RXB1D7_RXB1D77_POSN 0x7 #define _RXB1D7_RXB1D77_POSITION 0x7 #define _RXB1D7_RXB1D77_SIZE 0x1 #define _RXB1D7_RXB1D77_LENGTH 0x1 #define _RXB1D7_RXB1D77_MASK 0x80 // Register: CANSTAT_RO0 #define CANSTAT_RO0 CANSTAT_RO0 extern volatile unsigned char CANSTAT_RO0 @ 0xF3E; #ifndef _LIB_BUILD asm("CANSTAT_RO0 equ 0F3Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTAT_RO0bits_t; extern volatile CANSTAT_RO0bits_t CANSTAT_RO0bits @ 0xF3E; // bitfield macros #define _CANSTAT_RO0_EICODE0_POSN 0x0 #define _CANSTAT_RO0_EICODE0_POSITION 0x0 #define _CANSTAT_RO0_EICODE0_SIZE 0x1 #define _CANSTAT_RO0_EICODE0_LENGTH 0x1 #define _CANSTAT_RO0_EICODE0_MASK 0x1 #define _CANSTAT_RO0_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_RO0_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_RO0_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_RO0_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_RO0_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_RO0_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_RO0_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_RO0_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_RO0_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_RO0_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_RO0_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_RO0_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_RO0_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_RO0_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_RO0_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_RO0_EICODE4_POSN 0x4 #define _CANSTAT_RO0_EICODE4_POSITION 0x4 #define _CANSTAT_RO0_EICODE4_SIZE 0x1 #define _CANSTAT_RO0_EICODE4_LENGTH 0x1 #define _CANSTAT_RO0_EICODE4_MASK 0x10 #define _CANSTAT_RO0_OPMODE_POSN 0x5 #define _CANSTAT_RO0_OPMODE_POSITION 0x5 #define _CANSTAT_RO0_OPMODE_SIZE 0x3 #define _CANSTAT_RO0_OPMODE_LENGTH 0x3 #define _CANSTAT_RO0_OPMODE_MASK 0xE0 #define _CANSTAT_RO0_EICODE1_POSN 0x1 #define _CANSTAT_RO0_EICODE1_POSITION 0x1 #define _CANSTAT_RO0_EICODE1_SIZE 0x1 #define _CANSTAT_RO0_EICODE1_LENGTH 0x1 #define _CANSTAT_RO0_EICODE1_MASK 0x2 #define _CANSTAT_RO0_EICODE2_POSN 0x2 #define _CANSTAT_RO0_EICODE2_POSITION 0x2 #define _CANSTAT_RO0_EICODE2_SIZE 0x1 #define _CANSTAT_RO0_EICODE2_LENGTH 0x1 #define _CANSTAT_RO0_EICODE2_MASK 0x4 #define _CANSTAT_RO0_EICODE3_POSN 0x3 #define _CANSTAT_RO0_EICODE3_POSITION 0x3 #define _CANSTAT_RO0_EICODE3_SIZE 0x1 #define _CANSTAT_RO0_EICODE3_LENGTH 0x1 #define _CANSTAT_RO0_EICODE3_MASK 0x8 #define _CANSTAT_RO0_OPMODE0_POSN 0x5 #define _CANSTAT_RO0_OPMODE0_POSITION 0x5 #define _CANSTAT_RO0_OPMODE0_SIZE 0x1 #define _CANSTAT_RO0_OPMODE0_LENGTH 0x1 #define _CANSTAT_RO0_OPMODE0_MASK 0x20 #define _CANSTAT_RO0_OPMODE1_POSN 0x6 #define _CANSTAT_RO0_OPMODE1_POSITION 0x6 #define _CANSTAT_RO0_OPMODE1_SIZE 0x1 #define _CANSTAT_RO0_OPMODE1_LENGTH 0x1 #define _CANSTAT_RO0_OPMODE1_MASK 0x40 #define _CANSTAT_RO0_OPMODE2_POSN 0x7 #define _CANSTAT_RO0_OPMODE2_POSITION 0x7 #define _CANSTAT_RO0_OPMODE2_SIZE 0x1 #define _CANSTAT_RO0_OPMODE2_LENGTH 0x1 #define _CANSTAT_RO0_OPMODE2_MASK 0x80 #define _CANSTAT_RO0_ICODE0_POSN 0x1 #define _CANSTAT_RO0_ICODE0_POSITION 0x1 #define _CANSTAT_RO0_ICODE0_SIZE 0x1 #define _CANSTAT_RO0_ICODE0_LENGTH 0x1 #define _CANSTAT_RO0_ICODE0_MASK 0x2 #define _CANSTAT_RO0_ICODE1_POSN 0x2 #define _CANSTAT_RO0_ICODE1_POSITION 0x2 #define _CANSTAT_RO0_ICODE1_SIZE 0x1 #define _CANSTAT_RO0_ICODE1_LENGTH 0x1 #define _CANSTAT_RO0_ICODE1_MASK 0x4 #define _CANSTAT_RO0_ICODE2_POSN 0x3 #define _CANSTAT_RO0_ICODE2_POSITION 0x3 #define _CANSTAT_RO0_ICODE2_SIZE 0x1 #define _CANSTAT_RO0_ICODE2_LENGTH 0x1 #define _CANSTAT_RO0_ICODE2_MASK 0x8 // Register: CANCON_RO0 #define CANCON_RO0 CANCON_RO0 extern volatile unsigned char CANCON_RO0 @ 0xF3F; #ifndef _LIB_BUILD asm("CANCON_RO0 equ 0F3Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCON_RO0bits_t; extern volatile CANCON_RO0bits_t CANCON_RO0bits @ 0xF3F; // bitfield macros #define _CANCON_RO0_FP0_POSN 0x0 #define _CANCON_RO0_FP0_POSITION 0x0 #define _CANCON_RO0_FP0_SIZE 0x1 #define _CANCON_RO0_FP0_LENGTH 0x1 #define _CANCON_RO0_FP0_MASK 0x1 #define _CANCON_RO0_WIN0_FP1_POSN 0x1 #define _CANCON_RO0_WIN0_FP1_POSITION 0x1 #define _CANCON_RO0_WIN0_FP1_SIZE 0x1 #define _CANCON_RO0_WIN0_FP1_LENGTH 0x1 #define _CANCON_RO0_WIN0_FP1_MASK 0x2 #define _CANCON_RO0_WIN1_FP2_POSN 0x2 #define _CANCON_RO0_WIN1_FP2_POSITION 0x2 #define _CANCON_RO0_WIN1_FP2_SIZE 0x1 #define _CANCON_RO0_WIN1_FP2_LENGTH 0x1 #define _CANCON_RO0_WIN1_FP2_MASK 0x4 #define _CANCON_RO0_WIN2_FP3_POSN 0x3 #define _CANCON_RO0_WIN2_FP3_POSITION 0x3 #define _CANCON_RO0_WIN2_FP3_SIZE 0x1 #define _CANCON_RO0_WIN2_FP3_LENGTH 0x1 #define _CANCON_RO0_WIN2_FP3_MASK 0x8 #define _CANCON_RO0_ABAT_POSN 0x4 #define _CANCON_RO0_ABAT_POSITION 0x4 #define _CANCON_RO0_ABAT_SIZE 0x1 #define _CANCON_RO0_ABAT_LENGTH 0x1 #define _CANCON_RO0_ABAT_MASK 0x10 #define _CANCON_RO0_REQOP_POSN 0x5 #define _CANCON_RO0_REQOP_POSITION 0x5 #define _CANCON_RO0_REQOP_SIZE 0x3 #define _CANCON_RO0_REQOP_LENGTH 0x3 #define _CANCON_RO0_REQOP_MASK 0xE0 #define _CANCON_RO0_WIN0_POSN 0x1 #define _CANCON_RO0_WIN0_POSITION 0x1 #define _CANCON_RO0_WIN0_SIZE 0x1 #define _CANCON_RO0_WIN0_LENGTH 0x1 #define _CANCON_RO0_WIN0_MASK 0x2 #define _CANCON_RO0_WIN1_POSN 0x2 #define _CANCON_RO0_WIN1_POSITION 0x2 #define _CANCON_RO0_WIN1_SIZE 0x1 #define _CANCON_RO0_WIN1_LENGTH 0x1 #define _CANCON_RO0_WIN1_MASK 0x4 #define _CANCON_RO0_WIN2_POSN 0x3 #define _CANCON_RO0_WIN2_POSITION 0x3 #define _CANCON_RO0_WIN2_SIZE 0x1 #define _CANCON_RO0_WIN2_LENGTH 0x1 #define _CANCON_RO0_WIN2_MASK 0x8 #define _CANCON_RO0_FP1_POSN 0x1 #define _CANCON_RO0_FP1_POSITION 0x1 #define _CANCON_RO0_FP1_SIZE 0x1 #define _CANCON_RO0_FP1_LENGTH 0x1 #define _CANCON_RO0_FP1_MASK 0x2 #define _CANCON_RO0_FP2_POSN 0x2 #define _CANCON_RO0_FP2_POSITION 0x2 #define _CANCON_RO0_FP2_SIZE 0x1 #define _CANCON_RO0_FP2_LENGTH 0x1 #define _CANCON_RO0_FP2_MASK 0x4 #define _CANCON_RO0_FP3_POSN 0x3 #define _CANCON_RO0_FP3_POSITION 0x3 #define _CANCON_RO0_FP3_SIZE 0x1 #define _CANCON_RO0_FP3_LENGTH 0x1 #define _CANCON_RO0_FP3_MASK 0x8 // Register: CCP5CON #define CCP5CON CCP5CON extern volatile unsigned char CCP5CON @ 0xF47; #ifndef _LIB_BUILD asm("CCP5CON equ 0F47h"); #endif // bitfield definitions typedef union { struct { unsigned CCP5M :4; unsigned DC5B :2; }; struct { unsigned CCP5M0 :1; unsigned CCP5M1 :1; unsigned CCP5M2 :1; unsigned CCP5M3 :1; unsigned DC5B0 :1; unsigned DC5B1 :1; }; struct { unsigned :4; unsigned CCP5Y :1; unsigned CCP5X :1; }; } CCP5CONbits_t; extern volatile CCP5CONbits_t CCP5CONbits @ 0xF47; // bitfield macros #define _CCP5CON_CCP5M_POSN 0x0 #define _CCP5CON_CCP5M_POSITION 0x0 #define _CCP5CON_CCP5M_SIZE 0x4 #define _CCP5CON_CCP5M_LENGTH 0x4 #define _CCP5CON_CCP5M_MASK 0xF #define _CCP5CON_DC5B_POSN 0x4 #define _CCP5CON_DC5B_POSITION 0x4 #define _CCP5CON_DC5B_SIZE 0x2 #define _CCP5CON_DC5B_LENGTH 0x2 #define _CCP5CON_DC5B_MASK 0x30 #define _CCP5CON_CCP5M0_POSN 0x0 #define _CCP5CON_CCP5M0_POSITION 0x0 #define _CCP5CON_CCP5M0_SIZE 0x1 #define _CCP5CON_CCP5M0_LENGTH 0x1 #define _CCP5CON_CCP5M0_MASK 0x1 #define _CCP5CON_CCP5M1_POSN 0x1 #define _CCP5CON_CCP5M1_POSITION 0x1 #define _CCP5CON_CCP5M1_SIZE 0x1 #define _CCP5CON_CCP5M1_LENGTH 0x1 #define _CCP5CON_CCP5M1_MASK 0x2 #define _CCP5CON_CCP5M2_POSN 0x2 #define _CCP5CON_CCP5M2_POSITION 0x2 #define _CCP5CON_CCP5M2_SIZE 0x1 #define _CCP5CON_CCP5M2_LENGTH 0x1 #define _CCP5CON_CCP5M2_MASK 0x4 #define _CCP5CON_CCP5M3_POSN 0x3 #define _CCP5CON_CCP5M3_POSITION 0x3 #define _CCP5CON_CCP5M3_SIZE 0x1 #define _CCP5CON_CCP5M3_LENGTH 0x1 #define _CCP5CON_CCP5M3_MASK 0x8 #define _CCP5CON_DC5B0_POSN 0x4 #define _CCP5CON_DC5B0_POSITION 0x4 #define _CCP5CON_DC5B0_SIZE 0x1 #define _CCP5CON_DC5B0_LENGTH 0x1 #define _CCP5CON_DC5B0_MASK 0x10 #define _CCP5CON_DC5B1_POSN 0x5 #define _CCP5CON_DC5B1_POSITION 0x5 #define _CCP5CON_DC5B1_SIZE 0x1 #define _CCP5CON_DC5B1_LENGTH 0x1 #define _CCP5CON_DC5B1_MASK 0x20 #define _CCP5CON_CCP5Y_POSN 0x4 #define _CCP5CON_CCP5Y_POSITION 0x4 #define _CCP5CON_CCP5Y_SIZE 0x1 #define _CCP5CON_CCP5Y_LENGTH 0x1 #define _CCP5CON_CCP5Y_MASK 0x10 #define _CCP5CON_CCP5X_POSN 0x5 #define _CCP5CON_CCP5X_POSITION 0x5 #define _CCP5CON_CCP5X_SIZE 0x1 #define _CCP5CON_CCP5X_LENGTH 0x1 #define _CCP5CON_CCP5X_MASK 0x20 // Register: CCPR5 #define CCPR5 CCPR5 extern volatile unsigned short CCPR5 @ 0xF48; #ifndef _LIB_BUILD asm("CCPR5 equ 0F48h"); #endif // Register: CCPR5L #define CCPR5L CCPR5L extern volatile unsigned char CCPR5L @ 0xF48; #ifndef _LIB_BUILD asm("CCPR5L equ 0F48h"); #endif // bitfield definitions typedef union { struct { unsigned CCPR5L :8; }; } CCPR5Lbits_t; extern volatile CCPR5Lbits_t CCPR5Lbits @ 0xF48; // bitfield macros #define _CCPR5L_CCPR5L_POSN 0x0 #define _CCPR5L_CCPR5L_POSITION 0x0 #define _CCPR5L_CCPR5L_SIZE 0x8 #define _CCPR5L_CCPR5L_LENGTH 0x8 #define _CCPR5L_CCPR5L_MASK 0xFF // Register: CCPR5H #define CCPR5H CCPR5H extern volatile unsigned char CCPR5H @ 0xF49; #ifndef _LIB_BUILD asm("CCPR5H equ 0F49h"); #endif // bitfield definitions typedef union { struct { unsigned CCPR5H :8; }; } CCPR5Hbits_t; extern volatile CCPR5Hbits_t CCPR5Hbits @ 0xF49; // bitfield macros #define _CCPR5H_CCPR5H_POSN 0x0 #define _CCPR5H_CCPR5H_POSITION 0x0 #define _CCPR5H_CCPR5H_SIZE 0x8 #define _CCPR5H_CCPR5H_LENGTH 0x8 #define _CCPR5H_CCPR5H_MASK 0xFF // Register: CCP4CON #define CCP4CON CCP4CON extern volatile unsigned char CCP4CON @ 0xF4A; #ifndef _LIB_BUILD asm("CCP4CON equ 0F4Ah"); #endif // bitfield definitions typedef union { struct { unsigned CCP4M :4; unsigned DC4B :2; }; struct { unsigned CCP4M0 :1; unsigned CCP4M1 :1; unsigned CCP4M2 :1; unsigned CCP4M3 :1; unsigned DC4B0 :1; unsigned DC4B1 :1; }; struct { unsigned :4; unsigned CCP4Y :1; unsigned CCP4X :1; }; } CCP4CONbits_t; extern volatile CCP4CONbits_t CCP4CONbits @ 0xF4A; // bitfield macros #define _CCP4CON_CCP4M_POSN 0x0 #define _CCP4CON_CCP4M_POSITION 0x0 #define _CCP4CON_CCP4M_SIZE 0x4 #define _CCP4CON_CCP4M_LENGTH 0x4 #define _CCP4CON_CCP4M_MASK 0xF #define _CCP4CON_DC4B_POSN 0x4 #define _CCP4CON_DC4B_POSITION 0x4 #define _CCP4CON_DC4B_SIZE 0x2 #define _CCP4CON_DC4B_LENGTH 0x2 #define _CCP4CON_DC4B_MASK 0x30 #define _CCP4CON_CCP4M0_POSN 0x0 #define _CCP4CON_CCP4M0_POSITION 0x0 #define _CCP4CON_CCP4M0_SIZE 0x1 #define _CCP4CON_CCP4M0_LENGTH 0x1 #define _CCP4CON_CCP4M0_MASK 0x1 #define _CCP4CON_CCP4M1_POSN 0x1 #define _CCP4CON_CCP4M1_POSITION 0x1 #define _CCP4CON_CCP4M1_SIZE 0x1 #define _CCP4CON_CCP4M1_LENGTH 0x1 #define _CCP4CON_CCP4M1_MASK 0x2 #define _CCP4CON_CCP4M2_POSN 0x2 #define _CCP4CON_CCP4M2_POSITION 0x2 #define _CCP4CON_CCP4M2_SIZE 0x1 #define _CCP4CON_CCP4M2_LENGTH 0x1 #define _CCP4CON_CCP4M2_MASK 0x4 #define _CCP4CON_CCP4M3_POSN 0x3 #define _CCP4CON_CCP4M3_POSITION 0x3 #define _CCP4CON_CCP4M3_SIZE 0x1 #define _CCP4CON_CCP4M3_LENGTH 0x1 #define _CCP4CON_CCP4M3_MASK 0x8 #define _CCP4CON_DC4B0_POSN 0x4 #define _CCP4CON_DC4B0_POSITION 0x4 #define _CCP4CON_DC4B0_SIZE 0x1 #define _CCP4CON_DC4B0_LENGTH 0x1 #define _CCP4CON_DC4B0_MASK 0x10 #define _CCP4CON_DC4B1_POSN 0x5 #define _CCP4CON_DC4B1_POSITION 0x5 #define _CCP4CON_DC4B1_SIZE 0x1 #define _CCP4CON_DC4B1_LENGTH 0x1 #define _CCP4CON_DC4B1_MASK 0x20 #define _CCP4CON_CCP4Y_POSN 0x4 #define _CCP4CON_CCP4Y_POSITION 0x4 #define _CCP4CON_CCP4Y_SIZE 0x1 #define _CCP4CON_CCP4Y_LENGTH 0x1 #define _CCP4CON_CCP4Y_MASK 0x10 #define _CCP4CON_CCP4X_POSN 0x5 #define _CCP4CON_CCP4X_POSITION 0x5 #define _CCP4CON_CCP4X_SIZE 0x1 #define _CCP4CON_CCP4X_LENGTH 0x1 #define _CCP4CON_CCP4X_MASK 0x20 // Register: CCPR4 #define CCPR4 CCPR4 extern volatile unsigned short CCPR4 @ 0xF4B; #ifndef _LIB_BUILD asm("CCPR4 equ 0F4Bh"); #endif // Register: CCPR4L #define CCPR4L CCPR4L extern volatile unsigned char CCPR4L @ 0xF4B; #ifndef _LIB_BUILD asm("CCPR4L equ 0F4Bh"); #endif // bitfield definitions typedef union { struct { unsigned CCPR4L :8; }; } CCPR4Lbits_t; extern volatile CCPR4Lbits_t CCPR4Lbits @ 0xF4B; // bitfield macros #define _CCPR4L_CCPR4L_POSN 0x0 #define _CCPR4L_CCPR4L_POSITION 0x0 #define _CCPR4L_CCPR4L_SIZE 0x8 #define _CCPR4L_CCPR4L_LENGTH 0x8 #define _CCPR4L_CCPR4L_MASK 0xFF // Register: CCPR4H #define CCPR4H CCPR4H extern volatile unsigned char CCPR4H @ 0xF4C; #ifndef _LIB_BUILD asm("CCPR4H equ 0F4Ch"); #endif // bitfield definitions typedef union { struct { unsigned CCPR4H :8; }; } CCPR4Hbits_t; extern volatile CCPR4Hbits_t CCPR4Hbits @ 0xF4C; // bitfield macros #define _CCPR4H_CCPR4H_POSN 0x0 #define _CCPR4H_CCPR4H_POSITION 0x0 #define _CCPR4H_CCPR4H_SIZE 0x8 #define _CCPR4H_CCPR4H_LENGTH 0x8 #define _CCPR4H_CCPR4H_MASK 0xFF // Register: CCP3CON #define CCP3CON CCP3CON extern volatile unsigned char CCP3CON @ 0xF4D; #ifndef _LIB_BUILD asm("CCP3CON equ 0F4Dh"); #endif // bitfield definitions typedef union { struct { unsigned CCP3M :4; unsigned DC3B :2; }; struct { unsigned CCP3M0 :1; unsigned CCP3M1 :1; unsigned CCP3M2 :1; unsigned CCP3M3 :1; unsigned DC3B0 :1; unsigned DC3B1 :1; }; struct { unsigned :4; unsigned CCP3Y :1; unsigned CCP3X :1; }; } CCP3CONbits_t; extern volatile CCP3CONbits_t CCP3CONbits @ 0xF4D; // bitfield macros #define _CCP3CON_CCP3M_POSN 0x0 #define _CCP3CON_CCP3M_POSITION 0x0 #define _CCP3CON_CCP3M_SIZE 0x4 #define _CCP3CON_CCP3M_LENGTH 0x4 #define _CCP3CON_CCP3M_MASK 0xF #define _CCP3CON_DC3B_POSN 0x4 #define _CCP3CON_DC3B_POSITION 0x4 #define _CCP3CON_DC3B_SIZE 0x2 #define _CCP3CON_DC3B_LENGTH 0x2 #define _CCP3CON_DC3B_MASK 0x30 #define _CCP3CON_CCP3M0_POSN 0x0 #define _CCP3CON_CCP3M0_POSITION 0x0 #define _CCP3CON_CCP3M0_SIZE 0x1 #define _CCP3CON_CCP3M0_LENGTH 0x1 #define _CCP3CON_CCP3M0_MASK 0x1 #define _CCP3CON_CCP3M1_POSN 0x1 #define _CCP3CON_CCP3M1_POSITION 0x1 #define _CCP3CON_CCP3M1_SIZE 0x1 #define _CCP3CON_CCP3M1_LENGTH 0x1 #define _CCP3CON_CCP3M1_MASK 0x2 #define _CCP3CON_CCP3M2_POSN 0x2 #define _CCP3CON_CCP3M2_POSITION 0x2 #define _CCP3CON_CCP3M2_SIZE 0x1 #define _CCP3CON_CCP3M2_LENGTH 0x1 #define _CCP3CON_CCP3M2_MASK 0x4 #define _CCP3CON_CCP3M3_POSN 0x3 #define _CCP3CON_CCP3M3_POSITION 0x3 #define _CCP3CON_CCP3M3_SIZE 0x1 #define _CCP3CON_CCP3M3_LENGTH 0x1 #define _CCP3CON_CCP3M3_MASK 0x8 #define _CCP3CON_DC3B0_POSN 0x4 #define _CCP3CON_DC3B0_POSITION 0x4 #define _CCP3CON_DC3B0_SIZE 0x1 #define _CCP3CON_DC3B0_LENGTH 0x1 #define _CCP3CON_DC3B0_MASK 0x10 #define _CCP3CON_DC3B1_POSN 0x5 #define _CCP3CON_DC3B1_POSITION 0x5 #define _CCP3CON_DC3B1_SIZE 0x1 #define _CCP3CON_DC3B1_LENGTH 0x1 #define _CCP3CON_DC3B1_MASK 0x20 #define _CCP3CON_CCP3Y_POSN 0x4 #define _CCP3CON_CCP3Y_POSITION 0x4 #define _CCP3CON_CCP3Y_SIZE 0x1 #define _CCP3CON_CCP3Y_LENGTH 0x1 #define _CCP3CON_CCP3Y_MASK 0x10 #define _CCP3CON_CCP3X_POSN 0x5 #define _CCP3CON_CCP3X_POSITION 0x5 #define _CCP3CON_CCP3X_SIZE 0x1 #define _CCP3CON_CCP3X_LENGTH 0x1 #define _CCP3CON_CCP3X_MASK 0x20 // Register: CCPR3 #define CCPR3 CCPR3 extern volatile unsigned short CCPR3 @ 0xF4E; #ifndef _LIB_BUILD asm("CCPR3 equ 0F4Eh"); #endif // Register: CCPR3L #define CCPR3L CCPR3L extern volatile unsigned char CCPR3L @ 0xF4E; #ifndef _LIB_BUILD asm("CCPR3L equ 0F4Eh"); #endif // bitfield definitions typedef union { struct { unsigned CCPR3L :8; }; } CCPR3Lbits_t; extern volatile CCPR3Lbits_t CCPR3Lbits @ 0xF4E; // bitfield macros #define _CCPR3L_CCPR3L_POSN 0x0 #define _CCPR3L_CCPR3L_POSITION 0x0 #define _CCPR3L_CCPR3L_SIZE 0x8 #define _CCPR3L_CCPR3L_LENGTH 0x8 #define _CCPR3L_CCPR3L_MASK 0xFF // Register: CCPR3H #define CCPR3H CCPR3H extern volatile unsigned char CCPR3H @ 0xF4F; #ifndef _LIB_BUILD asm("CCPR3H equ 0F4Fh"); #endif // bitfield definitions typedef union { struct { unsigned CCPR3H :8; }; } CCPR3Hbits_t; extern volatile CCPR3Hbits_t CCPR3Hbits @ 0xF4F; // bitfield macros #define _CCPR3H_CCPR3H_POSN 0x0 #define _CCPR3H_CCPR3H_POSITION 0x0 #define _CCPR3H_CCPR3H_SIZE 0x8 #define _CCPR3H_CCPR3H_LENGTH 0x8 #define _CCPR3H_CCPR3H_MASK 0xFF // Register: CCP2CON #define CCP2CON CCP2CON extern volatile unsigned char CCP2CON @ 0xF50; #ifndef _LIB_BUILD asm("CCP2CON equ 0F50h"); #endif // aliases extern volatile unsigned char ECCP2CON @ 0xF50; #ifndef _LIB_BUILD asm("ECCP2CON equ 0F50h"); #endif // bitfield definitions typedef union { struct { unsigned CCP2M :4; unsigned DC2B :2; }; struct { unsigned CCP2M0 :1; unsigned CCP2M1 :1; unsigned CCP2M2 :1; unsigned CCP2M3 :1; unsigned DC2B0 :1; unsigned DC2B1 :1; }; struct { unsigned :4; unsigned CCP2Y :1; unsigned CCP2X :1; }; } CCP2CONbits_t; extern volatile CCP2CONbits_t CCP2CONbits @ 0xF50; // bitfield macros #define _CCP2CON_CCP2M_POSN 0x0 #define _CCP2CON_CCP2M_POSITION 0x0 #define _CCP2CON_CCP2M_SIZE 0x4 #define _CCP2CON_CCP2M_LENGTH 0x4 #define _CCP2CON_CCP2M_MASK 0xF #define _CCP2CON_DC2B_POSN 0x4 #define _CCP2CON_DC2B_POSITION 0x4 #define _CCP2CON_DC2B_SIZE 0x2 #define _CCP2CON_DC2B_LENGTH 0x2 #define _CCP2CON_DC2B_MASK 0x30 #define _CCP2CON_CCP2M0_POSN 0x0 #define _CCP2CON_CCP2M0_POSITION 0x0 #define _CCP2CON_CCP2M0_SIZE 0x1 #define _CCP2CON_CCP2M0_LENGTH 0x1 #define _CCP2CON_CCP2M0_MASK 0x1 #define _CCP2CON_CCP2M1_POSN 0x1 #define _CCP2CON_CCP2M1_POSITION 0x1 #define _CCP2CON_CCP2M1_SIZE 0x1 #define _CCP2CON_CCP2M1_LENGTH 0x1 #define _CCP2CON_CCP2M1_MASK 0x2 #define _CCP2CON_CCP2M2_POSN 0x2 #define _CCP2CON_CCP2M2_POSITION 0x2 #define _CCP2CON_CCP2M2_SIZE 0x1 #define _CCP2CON_CCP2M2_LENGTH 0x1 #define _CCP2CON_CCP2M2_MASK 0x4 #define _CCP2CON_CCP2M3_POSN 0x3 #define _CCP2CON_CCP2M3_POSITION 0x3 #define _CCP2CON_CCP2M3_SIZE 0x1 #define _CCP2CON_CCP2M3_LENGTH 0x1 #define _CCP2CON_CCP2M3_MASK 0x8 #define _CCP2CON_DC2B0_POSN 0x4 #define _CCP2CON_DC2B0_POSITION 0x4 #define _CCP2CON_DC2B0_SIZE 0x1 #define _CCP2CON_DC2B0_LENGTH 0x1 #define _CCP2CON_DC2B0_MASK 0x10 #define _CCP2CON_DC2B1_POSN 0x5 #define _CCP2CON_DC2B1_POSITION 0x5 #define _CCP2CON_DC2B1_SIZE 0x1 #define _CCP2CON_DC2B1_LENGTH 0x1 #define _CCP2CON_DC2B1_MASK 0x20 #define _CCP2CON_CCP2Y_POSN 0x4 #define _CCP2CON_CCP2Y_POSITION 0x4 #define _CCP2CON_CCP2Y_SIZE 0x1 #define _CCP2CON_CCP2Y_LENGTH 0x1 #define _CCP2CON_CCP2Y_MASK 0x10 #define _CCP2CON_CCP2X_POSN 0x5 #define _CCP2CON_CCP2X_POSITION 0x5 #define _CCP2CON_CCP2X_SIZE 0x1 #define _CCP2CON_CCP2X_LENGTH 0x1 #define _CCP2CON_CCP2X_MASK 0x20 // alias bitfield definitions typedef union { struct { unsigned CCP2M :4; unsigned DC2B :2; }; struct { unsigned CCP2M0 :1; unsigned CCP2M1 :1; unsigned CCP2M2 :1; unsigned CCP2M3 :1; unsigned DC2B0 :1; unsigned DC2B1 :1; }; struct { unsigned :4; unsigned CCP2Y :1; unsigned CCP2X :1; }; } ECCP2CONbits_t; extern volatile ECCP2CONbits_t ECCP2CONbits @ 0xF50; // bitfield macros #define _ECCP2CON_CCP2M_POSN 0x0 #define _ECCP2CON_CCP2M_POSITION 0x0 #define _ECCP2CON_CCP2M_SIZE 0x4 #define _ECCP2CON_CCP2M_LENGTH 0x4 #define _ECCP2CON_CCP2M_MASK 0xF #define _ECCP2CON_DC2B_POSN 0x4 #define _ECCP2CON_DC2B_POSITION 0x4 #define _ECCP2CON_DC2B_SIZE 0x2 #define _ECCP2CON_DC2B_LENGTH 0x2 #define _ECCP2CON_DC2B_MASK 0x30 #define _ECCP2CON_CCP2M0_POSN 0x0 #define _ECCP2CON_CCP2M0_POSITION 0x0 #define _ECCP2CON_CCP2M0_SIZE 0x1 #define _ECCP2CON_CCP2M0_LENGTH 0x1 #define _ECCP2CON_CCP2M0_MASK 0x1 #define _ECCP2CON_CCP2M1_POSN 0x1 #define _ECCP2CON_CCP2M1_POSITION 0x1 #define _ECCP2CON_CCP2M1_SIZE 0x1 #define _ECCP2CON_CCP2M1_LENGTH 0x1 #define _ECCP2CON_CCP2M1_MASK 0x2 #define _ECCP2CON_CCP2M2_POSN 0x2 #define _ECCP2CON_CCP2M2_POSITION 0x2 #define _ECCP2CON_CCP2M2_SIZE 0x1 #define _ECCP2CON_CCP2M2_LENGTH 0x1 #define _ECCP2CON_CCP2M2_MASK 0x4 #define _ECCP2CON_CCP2M3_POSN 0x3 #define _ECCP2CON_CCP2M3_POSITION 0x3 #define _ECCP2CON_CCP2M3_SIZE 0x1 #define _ECCP2CON_CCP2M3_LENGTH 0x1 #define _ECCP2CON_CCP2M3_MASK 0x8 #define _ECCP2CON_DC2B0_POSN 0x4 #define _ECCP2CON_DC2B0_POSITION 0x4 #define _ECCP2CON_DC2B0_SIZE 0x1 #define _ECCP2CON_DC2B0_LENGTH 0x1 #define _ECCP2CON_DC2B0_MASK 0x10 #define _ECCP2CON_DC2B1_POSN 0x5 #define _ECCP2CON_DC2B1_POSITION 0x5 #define _ECCP2CON_DC2B1_SIZE 0x1 #define _ECCP2CON_DC2B1_LENGTH 0x1 #define _ECCP2CON_DC2B1_MASK 0x20 #define _ECCP2CON_CCP2Y_POSN 0x4 #define _ECCP2CON_CCP2Y_POSITION 0x4 #define _ECCP2CON_CCP2Y_SIZE 0x1 #define _ECCP2CON_CCP2Y_LENGTH 0x1 #define _ECCP2CON_CCP2Y_MASK 0x10 #define _ECCP2CON_CCP2X_POSN 0x5 #define _ECCP2CON_CCP2X_POSITION 0x5 #define _ECCP2CON_CCP2X_SIZE 0x1 #define _ECCP2CON_CCP2X_LENGTH 0x1 #define _ECCP2CON_CCP2X_MASK 0x20 // Register: CCPR2 #define CCPR2 CCPR2 extern volatile unsigned short CCPR2 @ 0xF51; #ifndef _LIB_BUILD asm("CCPR2 equ 0F51h"); #endif // Register: CCPR2L #define CCPR2L CCPR2L extern volatile unsigned char CCPR2L @ 0xF51; #ifndef _LIB_BUILD asm("CCPR2L equ 0F51h"); #endif // bitfield definitions typedef union { struct { unsigned CCPR2L :8; }; } CCPR2Lbits_t; extern volatile CCPR2Lbits_t CCPR2Lbits @ 0xF51; // bitfield macros #define _CCPR2L_CCPR2L_POSN 0x0 #define _CCPR2L_CCPR2L_POSITION 0x0 #define _CCPR2L_CCPR2L_SIZE 0x8 #define _CCPR2L_CCPR2L_LENGTH 0x8 #define _CCPR2L_CCPR2L_MASK 0xFF // Register: CCPR2H #define CCPR2H CCPR2H extern volatile unsigned char CCPR2H @ 0xF52; #ifndef _LIB_BUILD asm("CCPR2H equ 0F52h"); #endif // bitfield definitions typedef union { struct { unsigned CCPR2H :8; }; } CCPR2Hbits_t; extern volatile CCPR2Hbits_t CCPR2Hbits @ 0xF52; // bitfield macros #define _CCPR2H_CCPR2H_POSN 0x0 #define _CCPR2H_CCPR2H_POSITION 0x0 #define _CCPR2H_CCPR2H_SIZE 0x8 #define _CCPR2H_CCPR2H_LENGTH 0x8 #define _CCPR2H_CCPR2H_MASK 0xFF // Register: CTMUICON #define CTMUICON CTMUICON extern volatile unsigned char CTMUICON @ 0xF53; #ifndef _LIB_BUILD asm("CTMUICON equ 0F53h"); #endif // bitfield definitions typedef union { struct { unsigned IRNG :2; unsigned ITRIM :6; }; struct { unsigned IRNG0 :1; unsigned IRNG1 :1; unsigned ITRIM0 :1; unsigned ITRIM1 :1; unsigned ITRIM2 :1; unsigned ITRIM3 :1; unsigned ITRIM4 :1; unsigned ITRIM5 :1; }; } CTMUICONbits_t; extern volatile CTMUICONbits_t CTMUICONbits @ 0xF53; // bitfield macros #define _CTMUICON_IRNG_POSN 0x0 #define _CTMUICON_IRNG_POSITION 0x0 #define _CTMUICON_IRNG_SIZE 0x2 #define _CTMUICON_IRNG_LENGTH 0x2 #define _CTMUICON_IRNG_MASK 0x3 #define _CTMUICON_ITRIM_POSN 0x2 #define _CTMUICON_ITRIM_POSITION 0x2 #define _CTMUICON_ITRIM_SIZE 0x6 #define _CTMUICON_ITRIM_LENGTH 0x6 #define _CTMUICON_ITRIM_MASK 0xFC #define _CTMUICON_IRNG0_POSN 0x0 #define _CTMUICON_IRNG0_POSITION 0x0 #define _CTMUICON_IRNG0_SIZE 0x1 #define _CTMUICON_IRNG0_LENGTH 0x1 #define _CTMUICON_IRNG0_MASK 0x1 #define _CTMUICON_IRNG1_POSN 0x1 #define _CTMUICON_IRNG1_POSITION 0x1 #define _CTMUICON_IRNG1_SIZE 0x1 #define _CTMUICON_IRNG1_LENGTH 0x1 #define _CTMUICON_IRNG1_MASK 0x2 #define _CTMUICON_ITRIM0_POSN 0x2 #define _CTMUICON_ITRIM0_POSITION 0x2 #define _CTMUICON_ITRIM0_SIZE 0x1 #define _CTMUICON_ITRIM0_LENGTH 0x1 #define _CTMUICON_ITRIM0_MASK 0x4 #define _CTMUICON_ITRIM1_POSN 0x3 #define _CTMUICON_ITRIM1_POSITION 0x3 #define _CTMUICON_ITRIM1_SIZE 0x1 #define _CTMUICON_ITRIM1_LENGTH 0x1 #define _CTMUICON_ITRIM1_MASK 0x8 #define _CTMUICON_ITRIM2_POSN 0x4 #define _CTMUICON_ITRIM2_POSITION 0x4 #define _CTMUICON_ITRIM2_SIZE 0x1 #define _CTMUICON_ITRIM2_LENGTH 0x1 #define _CTMUICON_ITRIM2_MASK 0x10 #define _CTMUICON_ITRIM3_POSN 0x5 #define _CTMUICON_ITRIM3_POSITION 0x5 #define _CTMUICON_ITRIM3_SIZE 0x1 #define _CTMUICON_ITRIM3_LENGTH 0x1 #define _CTMUICON_ITRIM3_MASK 0x20 #define _CTMUICON_ITRIM4_POSN 0x6 #define _CTMUICON_ITRIM4_POSITION 0x6 #define _CTMUICON_ITRIM4_SIZE 0x1 #define _CTMUICON_ITRIM4_LENGTH 0x1 #define _CTMUICON_ITRIM4_MASK 0x40 #define _CTMUICON_ITRIM5_POSN 0x7 #define _CTMUICON_ITRIM5_POSITION 0x7 #define _CTMUICON_ITRIM5_SIZE 0x1 #define _CTMUICON_ITRIM5_LENGTH 0x1 #define _CTMUICON_ITRIM5_MASK 0x80 // Register: CTMUCONL #define CTMUCONL CTMUCONL extern volatile unsigned char CTMUCONL @ 0xF54; #ifndef _LIB_BUILD asm("CTMUCONL equ 0F54h"); #endif // bitfield definitions typedef union { struct { unsigned EDG1STAT :1; unsigned EDG2STAT :1; unsigned EDG1SEL :2; unsigned EDG1POL :1; unsigned EDG2SEL :2; unsigned EDG2POL :1; }; struct { unsigned :2; unsigned EDG1SEL0 :1; unsigned EDG1SEL1 :1; unsigned :1; unsigned EDG2SEL0 :1; unsigned EDG2SEL1 :1; }; } CTMUCONLbits_t; extern volatile CTMUCONLbits_t CTMUCONLbits @ 0xF54; // bitfield macros #define _CTMUCONL_EDG1STAT_POSN 0x0 #define _CTMUCONL_EDG1STAT_POSITION 0x0 #define _CTMUCONL_EDG1STAT_SIZE 0x1 #define _CTMUCONL_EDG1STAT_LENGTH 0x1 #define _CTMUCONL_EDG1STAT_MASK 0x1 #define _CTMUCONL_EDG2STAT_POSN 0x1 #define _CTMUCONL_EDG2STAT_POSITION 0x1 #define _CTMUCONL_EDG2STAT_SIZE 0x1 #define _CTMUCONL_EDG2STAT_LENGTH 0x1 #define _CTMUCONL_EDG2STAT_MASK 0x2 #define _CTMUCONL_EDG1SEL_POSN 0x2 #define _CTMUCONL_EDG1SEL_POSITION 0x2 #define _CTMUCONL_EDG1SEL_SIZE 0x2 #define _CTMUCONL_EDG1SEL_LENGTH 0x2 #define _CTMUCONL_EDG1SEL_MASK 0xC #define _CTMUCONL_EDG1POL_POSN 0x4 #define _CTMUCONL_EDG1POL_POSITION 0x4 #define _CTMUCONL_EDG1POL_SIZE 0x1 #define _CTMUCONL_EDG1POL_LENGTH 0x1 #define _CTMUCONL_EDG1POL_MASK 0x10 #define _CTMUCONL_EDG2SEL_POSN 0x5 #define _CTMUCONL_EDG2SEL_POSITION 0x5 #define _CTMUCONL_EDG2SEL_SIZE 0x2 #define _CTMUCONL_EDG2SEL_LENGTH 0x2 #define _CTMUCONL_EDG2SEL_MASK 0x60 #define _CTMUCONL_EDG2POL_POSN 0x7 #define _CTMUCONL_EDG2POL_POSITION 0x7 #define _CTMUCONL_EDG2POL_SIZE 0x1 #define _CTMUCONL_EDG2POL_LENGTH 0x1 #define _CTMUCONL_EDG2POL_MASK 0x80 #define _CTMUCONL_EDG1SEL0_POSN 0x2 #define _CTMUCONL_EDG1SEL0_POSITION 0x2 #define _CTMUCONL_EDG1SEL0_SIZE 0x1 #define _CTMUCONL_EDG1SEL0_LENGTH 0x1 #define _CTMUCONL_EDG1SEL0_MASK 0x4 #define _CTMUCONL_EDG1SEL1_POSN 0x3 #define _CTMUCONL_EDG1SEL1_POSITION 0x3 #define _CTMUCONL_EDG1SEL1_SIZE 0x1 #define _CTMUCONL_EDG1SEL1_LENGTH 0x1 #define _CTMUCONL_EDG1SEL1_MASK 0x8 #define _CTMUCONL_EDG2SEL0_POSN 0x5 #define _CTMUCONL_EDG2SEL0_POSITION 0x5 #define _CTMUCONL_EDG2SEL0_SIZE 0x1 #define _CTMUCONL_EDG2SEL0_LENGTH 0x1 #define _CTMUCONL_EDG2SEL0_MASK 0x20 #define _CTMUCONL_EDG2SEL1_POSN 0x6 #define _CTMUCONL_EDG2SEL1_POSITION 0x6 #define _CTMUCONL_EDG2SEL1_SIZE 0x1 #define _CTMUCONL_EDG2SEL1_LENGTH 0x1 #define _CTMUCONL_EDG2SEL1_MASK 0x40 // Register: CTMUCONH #define CTMUCONH CTMUCONH extern volatile unsigned char CTMUCONH @ 0xF55; #ifndef _LIB_BUILD asm("CTMUCONH equ 0F55h"); #endif // bitfield definitions typedef union { struct { unsigned CTTRIG :1; unsigned IDISSEN :1; unsigned EDGSEQEN :1; unsigned EDGEN :1; unsigned TGEN :1; unsigned CTMUSIDL :1; unsigned :1; unsigned CTMUEN :1; }; } CTMUCONHbits_t; extern volatile CTMUCONHbits_t CTMUCONHbits @ 0xF55; // bitfield macros #define _CTMUCONH_CTTRIG_POSN 0x0 #define _CTMUCONH_CTTRIG_POSITION 0x0 #define _CTMUCONH_CTTRIG_SIZE 0x1 #define _CTMUCONH_CTTRIG_LENGTH 0x1 #define _CTMUCONH_CTTRIG_MASK 0x1 #define _CTMUCONH_IDISSEN_POSN 0x1 #define _CTMUCONH_IDISSEN_POSITION 0x1 #define _CTMUCONH_IDISSEN_SIZE 0x1 #define _CTMUCONH_IDISSEN_LENGTH 0x1 #define _CTMUCONH_IDISSEN_MASK 0x2 #define _CTMUCONH_EDGSEQEN_POSN 0x2 #define _CTMUCONH_EDGSEQEN_POSITION 0x2 #define _CTMUCONH_EDGSEQEN_SIZE 0x1 #define _CTMUCONH_EDGSEQEN_LENGTH 0x1 #define _CTMUCONH_EDGSEQEN_MASK 0x4 #define _CTMUCONH_EDGEN_POSN 0x3 #define _CTMUCONH_EDGEN_POSITION 0x3 #define _CTMUCONH_EDGEN_SIZE 0x1 #define _CTMUCONH_EDGEN_LENGTH 0x1 #define _CTMUCONH_EDGEN_MASK 0x8 #define _CTMUCONH_TGEN_POSN 0x4 #define _CTMUCONH_TGEN_POSITION 0x4 #define _CTMUCONH_TGEN_SIZE 0x1 #define _CTMUCONH_TGEN_LENGTH 0x1 #define _CTMUCONH_TGEN_MASK 0x10 #define _CTMUCONH_CTMUSIDL_POSN 0x5 #define _CTMUCONH_CTMUSIDL_POSITION 0x5 #define _CTMUCONH_CTMUSIDL_SIZE 0x1 #define _CTMUCONH_CTMUSIDL_LENGTH 0x1 #define _CTMUCONH_CTMUSIDL_MASK 0x20 #define _CTMUCONH_CTMUEN_POSN 0x7 #define _CTMUCONH_CTMUEN_POSITION 0x7 #define _CTMUCONH_CTMUEN_SIZE 0x1 #define _CTMUCONH_CTMUEN_LENGTH 0x1 #define _CTMUCONH_CTMUEN_MASK 0x80 // Register: PADCFG1 #define PADCFG1 PADCFG1 extern volatile unsigned char PADCFG1 @ 0xF56; #ifndef _LIB_BUILD asm("PADCFG1 equ 0F56h"); #endif // bitfield definitions typedef union { struct { unsigned CTMUDS :1; }; struct { unsigned PMPTTL :1; }; } PADCFG1bits_t; extern volatile PADCFG1bits_t PADCFG1bits @ 0xF56; // bitfield macros #define _PADCFG1_CTMUDS_POSN 0x0 #define _PADCFG1_CTMUDS_POSITION 0x0 #define _PADCFG1_CTMUDS_SIZE 0x1 #define _PADCFG1_CTMUDS_LENGTH 0x1 #define _PADCFG1_CTMUDS_MASK 0x1 #define _PADCFG1_PMPTTL_POSN 0x0 #define _PADCFG1_PMPTTL_POSITION 0x0 #define _PADCFG1_PMPTTL_SIZE 0x1 #define _PADCFG1_PMPTTL_LENGTH 0x1 #define _PADCFG1_PMPTTL_MASK 0x1 // Register: PMD2 #define PMD2 PMD2 extern volatile unsigned char PMD2 @ 0xF57; #ifndef _LIB_BUILD asm("PMD2 equ 0F57h"); #endif // bitfield definitions typedef union { struct { unsigned CMP1MD :1; unsigned CMP2MD :1; unsigned ECANMD :1; }; } PMD2bits_t; extern volatile PMD2bits_t PMD2bits @ 0xF57; // bitfield macros #define _PMD2_CMP1MD_POSN 0x0 #define _PMD2_CMP1MD_POSITION 0x0 #define _PMD2_CMP1MD_SIZE 0x1 #define _PMD2_CMP1MD_LENGTH 0x1 #define _PMD2_CMP1MD_MASK 0x1 #define _PMD2_CMP2MD_POSN 0x1 #define _PMD2_CMP2MD_POSITION 0x1 #define _PMD2_CMP2MD_SIZE 0x1 #define _PMD2_CMP2MD_LENGTH 0x1 #define _PMD2_CMP2MD_MASK 0x2 #define _PMD2_ECANMD_POSN 0x2 #define _PMD2_ECANMD_POSITION 0x2 #define _PMD2_ECANMD_SIZE 0x1 #define _PMD2_ECANMD_LENGTH 0x1 #define _PMD2_ECANMD_MASK 0x4 // Register: PMD1 #define PMD1 PMD1 extern volatile unsigned char PMD1 @ 0xF58; #ifndef _LIB_BUILD asm("PMD1 equ 0F58h"); #endif // bitfield definitions typedef union { struct { unsigned TMR0MD :1; unsigned TMR1MD :1; unsigned TMR2MD :1; unsigned TMR3MD :1; unsigned TMR4MD :1; unsigned ADCMD :1; unsigned CTMUMD :1; unsigned PSPMD :1; }; struct { unsigned EMBMD :1; }; } PMD1bits_t; extern volatile PMD1bits_t PMD1bits @ 0xF58; // bitfield macros #define _PMD1_TMR0MD_POSN 0x0 #define _PMD1_TMR0MD_POSITION 0x0 #define _PMD1_TMR0MD_SIZE 0x1 #define _PMD1_TMR0MD_LENGTH 0x1 #define _PMD1_TMR0MD_MASK 0x1 #define _PMD1_TMR1MD_POSN 0x1 #define _PMD1_TMR1MD_POSITION 0x1 #define _PMD1_TMR1MD_SIZE 0x1 #define _PMD1_TMR1MD_LENGTH 0x1 #define _PMD1_TMR1MD_MASK 0x2 #define _PMD1_TMR2MD_POSN 0x2 #define _PMD1_TMR2MD_POSITION 0x2 #define _PMD1_TMR2MD_SIZE 0x1 #define _PMD1_TMR2MD_LENGTH 0x1 #define _PMD1_TMR2MD_MASK 0x4 #define _PMD1_TMR3MD_POSN 0x3 #define _PMD1_TMR3MD_POSITION 0x3 #define _PMD1_TMR3MD_SIZE 0x1 #define _PMD1_TMR3MD_LENGTH 0x1 #define _PMD1_TMR3MD_MASK 0x8 #define _PMD1_TMR4MD_POSN 0x4 #define _PMD1_TMR4MD_POSITION 0x4 #define _PMD1_TMR4MD_SIZE 0x1 #define _PMD1_TMR4MD_LENGTH 0x1 #define _PMD1_TMR4MD_MASK 0x10 #define _PMD1_ADCMD_POSN 0x5 #define _PMD1_ADCMD_POSITION 0x5 #define _PMD1_ADCMD_SIZE 0x1 #define _PMD1_ADCMD_LENGTH 0x1 #define _PMD1_ADCMD_MASK 0x20 #define _PMD1_CTMUMD_POSN 0x6 #define _PMD1_CTMUMD_POSITION 0x6 #define _PMD1_CTMUMD_SIZE 0x1 #define _PMD1_CTMUMD_LENGTH 0x1 #define _PMD1_CTMUMD_MASK 0x40 #define _PMD1_PSPMD_POSN 0x7 #define _PMD1_PSPMD_POSITION 0x7 #define _PMD1_PSPMD_SIZE 0x1 #define _PMD1_PSPMD_LENGTH 0x1 #define _PMD1_PSPMD_MASK 0x80 #define _PMD1_EMBMD_POSN 0x0 #define _PMD1_EMBMD_POSITION 0x0 #define _PMD1_EMBMD_SIZE 0x1 #define _PMD1_EMBMD_LENGTH 0x1 #define _PMD1_EMBMD_MASK 0x1 // Register: PMD0 #define PMD0 PMD0 extern volatile unsigned char PMD0 @ 0xF59; #ifndef _LIB_BUILD asm("PMD0 equ 0F59h"); #endif // bitfield definitions typedef union { struct { unsigned SSPMD :1; unsigned UART1MD :1; unsigned UART2MD :1; unsigned CCP1MD :1; unsigned CCP2MD :1; unsigned CCP3MD :1; unsigned CCP4MD :1; unsigned CCP5MD :1; }; struct { unsigned :1; unsigned SPI1MD :1; unsigned SPI2MD :1; }; } PMD0bits_t; extern volatile PMD0bits_t PMD0bits @ 0xF59; // bitfield macros #define _PMD0_SSPMD_POSN 0x0 #define _PMD0_SSPMD_POSITION 0x0 #define _PMD0_SSPMD_SIZE 0x1 #define _PMD0_SSPMD_LENGTH 0x1 #define _PMD0_SSPMD_MASK 0x1 #define _PMD0_UART1MD_POSN 0x1 #define _PMD0_UART1MD_POSITION 0x1 #define _PMD0_UART1MD_SIZE 0x1 #define _PMD0_UART1MD_LENGTH 0x1 #define _PMD0_UART1MD_MASK 0x2 #define _PMD0_UART2MD_POSN 0x2 #define _PMD0_UART2MD_POSITION 0x2 #define _PMD0_UART2MD_SIZE 0x1 #define _PMD0_UART2MD_LENGTH 0x1 #define _PMD0_UART2MD_MASK 0x4 #define _PMD0_CCP1MD_POSN 0x3 #define _PMD0_CCP1MD_POSITION 0x3 #define _PMD0_CCP1MD_SIZE 0x1 #define _PMD0_CCP1MD_LENGTH 0x1 #define _PMD0_CCP1MD_MASK 0x8 #define _PMD0_CCP2MD_POSN 0x4 #define _PMD0_CCP2MD_POSITION 0x4 #define _PMD0_CCP2MD_SIZE 0x1 #define _PMD0_CCP2MD_LENGTH 0x1 #define _PMD0_CCP2MD_MASK 0x10 #define _PMD0_CCP3MD_POSN 0x5 #define _PMD0_CCP3MD_POSITION 0x5 #define _PMD0_CCP3MD_SIZE 0x1 #define _PMD0_CCP3MD_LENGTH 0x1 #define _PMD0_CCP3MD_MASK 0x20 #define _PMD0_CCP4MD_POSN 0x6 #define _PMD0_CCP4MD_POSITION 0x6 #define _PMD0_CCP4MD_SIZE 0x1 #define _PMD0_CCP4MD_LENGTH 0x1 #define _PMD0_CCP4MD_MASK 0x40 #define _PMD0_CCP5MD_POSN 0x7 #define _PMD0_CCP5MD_POSITION 0x7 #define _PMD0_CCP5MD_SIZE 0x1 #define _PMD0_CCP5MD_LENGTH 0x1 #define _PMD0_CCP5MD_MASK 0x80 #define _PMD0_SPI1MD_POSN 0x1 #define _PMD0_SPI1MD_POSITION 0x1 #define _PMD0_SPI1MD_SIZE 0x1 #define _PMD0_SPI1MD_LENGTH 0x1 #define _PMD0_SPI1MD_MASK 0x2 #define _PMD0_SPI2MD_POSN 0x2 #define _PMD0_SPI2MD_POSITION 0x2 #define _PMD0_SPI2MD_SIZE 0x1 #define _PMD0_SPI2MD_LENGTH 0x1 #define _PMD0_SPI2MD_MASK 0x4 // Register: IOCB #define IOCB IOCB extern volatile unsigned char IOCB @ 0xF5A; #ifndef _LIB_BUILD asm("IOCB equ 0F5Ah"); #endif // bitfield definitions typedef union { struct { unsigned :4; unsigned IOCB4 :1; unsigned IOCB5 :1; unsigned IOCB6 :1; unsigned IOCB7 :1; }; } IOCBbits_t; extern volatile IOCBbits_t IOCBbits @ 0xF5A; // bitfield macros #define _IOCB_IOCB4_POSN 0x4 #define _IOCB_IOCB4_POSITION 0x4 #define _IOCB_IOCB4_SIZE 0x1 #define _IOCB_IOCB4_LENGTH 0x1 #define _IOCB_IOCB4_MASK 0x10 #define _IOCB_IOCB5_POSN 0x5 #define _IOCB_IOCB5_POSITION 0x5 #define _IOCB_IOCB5_SIZE 0x1 #define _IOCB_IOCB5_LENGTH 0x1 #define _IOCB_IOCB5_MASK 0x20 #define _IOCB_IOCB6_POSN 0x6 #define _IOCB_IOCB6_POSITION 0x6 #define _IOCB_IOCB6_SIZE 0x1 #define _IOCB_IOCB6_LENGTH 0x1 #define _IOCB_IOCB6_MASK 0x40 #define _IOCB_IOCB7_POSN 0x7 #define _IOCB_IOCB7_POSITION 0x7 #define _IOCB_IOCB7_SIZE 0x1 #define _IOCB_IOCB7_LENGTH 0x1 #define _IOCB_IOCB7_MASK 0x80 // Register: WPUB #define WPUB WPUB extern volatile unsigned char WPUB @ 0xF5B; #ifndef _LIB_BUILD asm("WPUB equ 0F5Bh"); #endif // bitfield definitions typedef union { struct { unsigned WPUB0 :1; unsigned WPUB1 :1; unsigned WPUB2 :1; unsigned WPUB3 :1; unsigned WPUB4 :1; unsigned WPUB5 :1; unsigned WPUB6 :1; unsigned WPUB7 :1; }; } WPUBbits_t; extern volatile WPUBbits_t WPUBbits @ 0xF5B; // bitfield macros #define _WPUB_WPUB0_POSN 0x0 #define _WPUB_WPUB0_POSITION 0x0 #define _WPUB_WPUB0_SIZE 0x1 #define _WPUB_WPUB0_LENGTH 0x1 #define _WPUB_WPUB0_MASK 0x1 #define _WPUB_WPUB1_POSN 0x1 #define _WPUB_WPUB1_POSITION 0x1 #define _WPUB_WPUB1_SIZE 0x1 #define _WPUB_WPUB1_LENGTH 0x1 #define _WPUB_WPUB1_MASK 0x2 #define _WPUB_WPUB2_POSN 0x2 #define _WPUB_WPUB2_POSITION 0x2 #define _WPUB_WPUB2_SIZE 0x1 #define _WPUB_WPUB2_LENGTH 0x1 #define _WPUB_WPUB2_MASK 0x4 #define _WPUB_WPUB3_POSN 0x3 #define _WPUB_WPUB3_POSITION 0x3 #define _WPUB_WPUB3_SIZE 0x1 #define _WPUB_WPUB3_LENGTH 0x1 #define _WPUB_WPUB3_MASK 0x8 #define _WPUB_WPUB4_POSN 0x4 #define _WPUB_WPUB4_POSITION 0x4 #define _WPUB_WPUB4_SIZE 0x1 #define _WPUB_WPUB4_LENGTH 0x1 #define _WPUB_WPUB4_MASK 0x10 #define _WPUB_WPUB5_POSN 0x5 #define _WPUB_WPUB5_POSITION 0x5 #define _WPUB_WPUB5_SIZE 0x1 #define _WPUB_WPUB5_LENGTH 0x1 #define _WPUB_WPUB5_MASK 0x20 #define _WPUB_WPUB6_POSN 0x6 #define _WPUB_WPUB6_POSITION 0x6 #define _WPUB_WPUB6_SIZE 0x1 #define _WPUB_WPUB6_LENGTH 0x1 #define _WPUB_WPUB6_MASK 0x40 #define _WPUB_WPUB7_POSN 0x7 #define _WPUB_WPUB7_POSITION 0x7 #define _WPUB_WPUB7_SIZE 0x1 #define _WPUB_WPUB7_LENGTH 0x1 #define _WPUB_WPUB7_MASK 0x80 // Register: ANCON1 #define ANCON1 ANCON1 extern volatile unsigned char ANCON1 @ 0xF5C; #ifndef _LIB_BUILD asm("ANCON1 equ 0F5Ch"); #endif // bitfield definitions typedef union { struct { unsigned ANSEL8 :1; unsigned ANSEL9 :1; unsigned ANSEL10 :1; }; struct { unsigned PCFG8 :1; unsigned PCFG9 :1; unsigned PCFG10 :1; }; } ANCON1bits_t; extern volatile ANCON1bits_t ANCON1bits @ 0xF5C; // bitfield macros #define _ANCON1_ANSEL8_POSN 0x0 #define _ANCON1_ANSEL8_POSITION 0x0 #define _ANCON1_ANSEL8_SIZE 0x1 #define _ANCON1_ANSEL8_LENGTH 0x1 #define _ANCON1_ANSEL8_MASK 0x1 #define _ANCON1_ANSEL9_POSN 0x1 #define _ANCON1_ANSEL9_POSITION 0x1 #define _ANCON1_ANSEL9_SIZE 0x1 #define _ANCON1_ANSEL9_LENGTH 0x1 #define _ANCON1_ANSEL9_MASK 0x2 #define _ANCON1_ANSEL10_POSN 0x2 #define _ANCON1_ANSEL10_POSITION 0x2 #define _ANCON1_ANSEL10_SIZE 0x1 #define _ANCON1_ANSEL10_LENGTH 0x1 #define _ANCON1_ANSEL10_MASK 0x4 #define _ANCON1_PCFG8_POSN 0x0 #define _ANCON1_PCFG8_POSITION 0x0 #define _ANCON1_PCFG8_SIZE 0x1 #define _ANCON1_PCFG8_LENGTH 0x1 #define _ANCON1_PCFG8_MASK 0x1 #define _ANCON1_PCFG9_POSN 0x1 #define _ANCON1_PCFG9_POSITION 0x1 #define _ANCON1_PCFG9_SIZE 0x1 #define _ANCON1_PCFG9_LENGTH 0x1 #define _ANCON1_PCFG9_MASK 0x2 #define _ANCON1_PCFG10_POSN 0x2 #define _ANCON1_PCFG10_POSITION 0x2 #define _ANCON1_PCFG10_SIZE 0x1 #define _ANCON1_PCFG10_LENGTH 0x1 #define _ANCON1_PCFG10_MASK 0x4 // Register: ANCON0 #define ANCON0 ANCON0 extern volatile unsigned char ANCON0 @ 0xF5D; #ifndef _LIB_BUILD asm("ANCON0 equ 0F5Dh"); #endif // bitfield definitions typedef union { struct { unsigned ANSEL0 :1; unsigned ANSEL1 :1; unsigned ANSEL2 :1; unsigned ANSEL3 :1; unsigned ANSEL4 :1; }; struct { unsigned PCFG0 :1; unsigned PCFG1 :1; unsigned PCFG2 :1; unsigned PCFG3 :1; unsigned PCFG4 :1; }; } ANCON0bits_t; extern volatile ANCON0bits_t ANCON0bits @ 0xF5D; // bitfield macros #define _ANCON0_ANSEL0_POSN 0x0 #define _ANCON0_ANSEL0_POSITION 0x0 #define _ANCON0_ANSEL0_SIZE 0x1 #define _ANCON0_ANSEL0_LENGTH 0x1 #define _ANCON0_ANSEL0_MASK 0x1 #define _ANCON0_ANSEL1_POSN 0x1 #define _ANCON0_ANSEL1_POSITION 0x1 #define _ANCON0_ANSEL1_SIZE 0x1 #define _ANCON0_ANSEL1_LENGTH 0x1 #define _ANCON0_ANSEL1_MASK 0x2 #define _ANCON0_ANSEL2_POSN 0x2 #define _ANCON0_ANSEL2_POSITION 0x2 #define _ANCON0_ANSEL2_SIZE 0x1 #define _ANCON0_ANSEL2_LENGTH 0x1 #define _ANCON0_ANSEL2_MASK 0x4 #define _ANCON0_ANSEL3_POSN 0x3 #define _ANCON0_ANSEL3_POSITION 0x3 #define _ANCON0_ANSEL3_SIZE 0x1 #define _ANCON0_ANSEL3_LENGTH 0x1 #define _ANCON0_ANSEL3_MASK 0x8 #define _ANCON0_ANSEL4_POSN 0x4 #define _ANCON0_ANSEL4_POSITION 0x4 #define _ANCON0_ANSEL4_SIZE 0x1 #define _ANCON0_ANSEL4_LENGTH 0x1 #define _ANCON0_ANSEL4_MASK 0x10 #define _ANCON0_PCFG0_POSN 0x0 #define _ANCON0_PCFG0_POSITION 0x0 #define _ANCON0_PCFG0_SIZE 0x1 #define _ANCON0_PCFG0_LENGTH 0x1 #define _ANCON0_PCFG0_MASK 0x1 #define _ANCON0_PCFG1_POSN 0x1 #define _ANCON0_PCFG1_POSITION 0x1 #define _ANCON0_PCFG1_SIZE 0x1 #define _ANCON0_PCFG1_LENGTH 0x1 #define _ANCON0_PCFG1_MASK 0x2 #define _ANCON0_PCFG2_POSN 0x2 #define _ANCON0_PCFG2_POSITION 0x2 #define _ANCON0_PCFG2_SIZE 0x1 #define _ANCON0_PCFG2_LENGTH 0x1 #define _ANCON0_PCFG2_MASK 0x4 #define _ANCON0_PCFG3_POSN 0x3 #define _ANCON0_PCFG3_POSITION 0x3 #define _ANCON0_PCFG3_SIZE 0x1 #define _ANCON0_PCFG3_LENGTH 0x1 #define _ANCON0_PCFG3_MASK 0x8 #define _ANCON0_PCFG4_POSN 0x4 #define _ANCON0_PCFG4_POSITION 0x4 #define _ANCON0_PCFG4_SIZE 0x1 #define _ANCON0_PCFG4_LENGTH 0x1 #define _ANCON0_PCFG4_MASK 0x10 // Register: CM2CON #define CM2CON CM2CON extern volatile unsigned char CM2CON @ 0xF5E; #ifndef _LIB_BUILD asm("CM2CON equ 0F5Eh"); #endif // aliases extern volatile unsigned char CM2CON1 @ 0xF5E; #ifndef _LIB_BUILD asm("CM2CON1 equ 0F5Eh"); #endif // bitfield definitions typedef union { struct { unsigned CCH :2; unsigned CREF :1; unsigned EVPOL :2; unsigned CPOL :1; unsigned COE :1; unsigned CON :1; }; struct { unsigned CCH0 :1; unsigned CCH1 :1; unsigned :1; unsigned EVPOL0 :1; unsigned EVPOL1 :1; }; struct { unsigned CCH02 :1; unsigned CCH12 :1; unsigned CREF2 :1; unsigned EVPOL02 :1; unsigned EVPOL12 :1; unsigned CPOL2 :1; unsigned COE2 :1; unsigned CON2 :1; }; } CM2CONbits_t; extern volatile CM2CONbits_t CM2CONbits @ 0xF5E; // bitfield macros #define _CM2CON_CCH_POSN 0x0 #define _CM2CON_CCH_POSITION 0x0 #define _CM2CON_CCH_SIZE 0x2 #define _CM2CON_CCH_LENGTH 0x2 #define _CM2CON_CCH_MASK 0x3 #define _CM2CON_CREF_POSN 0x2 #define _CM2CON_CREF_POSITION 0x2 #define _CM2CON_CREF_SIZE 0x1 #define _CM2CON_CREF_LENGTH 0x1 #define _CM2CON_CREF_MASK 0x4 #define _CM2CON_EVPOL_POSN 0x3 #define _CM2CON_EVPOL_POSITION 0x3 #define _CM2CON_EVPOL_SIZE 0x2 #define _CM2CON_EVPOL_LENGTH 0x2 #define _CM2CON_EVPOL_MASK 0x18 #define _CM2CON_CPOL_POSN 0x5 #define _CM2CON_CPOL_POSITION 0x5 #define _CM2CON_CPOL_SIZE 0x1 #define _CM2CON_CPOL_LENGTH 0x1 #define _CM2CON_CPOL_MASK 0x20 #define _CM2CON_COE_POSN 0x6 #define _CM2CON_COE_POSITION 0x6 #define _CM2CON_COE_SIZE 0x1 #define _CM2CON_COE_LENGTH 0x1 #define _CM2CON_COE_MASK 0x40 #define _CM2CON_CON_POSN 0x7 #define _CM2CON_CON_POSITION 0x7 #define _CM2CON_CON_SIZE 0x1 #define _CM2CON_CON_LENGTH 0x1 #define _CM2CON_CON_MASK 0x80 #define _CM2CON_CCH0_POSN 0x0 #define _CM2CON_CCH0_POSITION 0x0 #define _CM2CON_CCH0_SIZE 0x1 #define _CM2CON_CCH0_LENGTH 0x1 #define _CM2CON_CCH0_MASK 0x1 #define _CM2CON_CCH1_POSN 0x1 #define _CM2CON_CCH1_POSITION 0x1 #define _CM2CON_CCH1_SIZE 0x1 #define _CM2CON_CCH1_LENGTH 0x1 #define _CM2CON_CCH1_MASK 0x2 #define _CM2CON_EVPOL0_POSN 0x3 #define _CM2CON_EVPOL0_POSITION 0x3 #define _CM2CON_EVPOL0_SIZE 0x1 #define _CM2CON_EVPOL0_LENGTH 0x1 #define _CM2CON_EVPOL0_MASK 0x8 #define _CM2CON_EVPOL1_POSN 0x4 #define _CM2CON_EVPOL1_POSITION 0x4 #define _CM2CON_EVPOL1_SIZE 0x1 #define _CM2CON_EVPOL1_LENGTH 0x1 #define _CM2CON_EVPOL1_MASK 0x10 #define _CM2CON_CCH02_POSN 0x0 #define _CM2CON_CCH02_POSITION 0x0 #define _CM2CON_CCH02_SIZE 0x1 #define _CM2CON_CCH02_LENGTH 0x1 #define _CM2CON_CCH02_MASK 0x1 #define _CM2CON_CCH12_POSN 0x1 #define _CM2CON_CCH12_POSITION 0x1 #define _CM2CON_CCH12_SIZE 0x1 #define _CM2CON_CCH12_LENGTH 0x1 #define _CM2CON_CCH12_MASK 0x2 #define _CM2CON_CREF2_POSN 0x2 #define _CM2CON_CREF2_POSITION 0x2 #define _CM2CON_CREF2_SIZE 0x1 #define _CM2CON_CREF2_LENGTH 0x1 #define _CM2CON_CREF2_MASK 0x4 #define _CM2CON_EVPOL02_POSN 0x3 #define _CM2CON_EVPOL02_POSITION 0x3 #define _CM2CON_EVPOL02_SIZE 0x1 #define _CM2CON_EVPOL02_LENGTH 0x1 #define _CM2CON_EVPOL02_MASK 0x8 #define _CM2CON_EVPOL12_POSN 0x4 #define _CM2CON_EVPOL12_POSITION 0x4 #define _CM2CON_EVPOL12_SIZE 0x1 #define _CM2CON_EVPOL12_LENGTH 0x1 #define _CM2CON_EVPOL12_MASK 0x10 #define _CM2CON_CPOL2_POSN 0x5 #define _CM2CON_CPOL2_POSITION 0x5 #define _CM2CON_CPOL2_SIZE 0x1 #define _CM2CON_CPOL2_LENGTH 0x1 #define _CM2CON_CPOL2_MASK 0x20 #define _CM2CON_COE2_POSN 0x6 #define _CM2CON_COE2_POSITION 0x6 #define _CM2CON_COE2_SIZE 0x1 #define _CM2CON_COE2_LENGTH 0x1 #define _CM2CON_COE2_MASK 0x40 #define _CM2CON_CON2_POSN 0x7 #define _CM2CON_CON2_POSITION 0x7 #define _CM2CON_CON2_SIZE 0x1 #define _CM2CON_CON2_LENGTH 0x1 #define _CM2CON_CON2_MASK 0x80 // alias bitfield definitions typedef union { struct { unsigned CCH :2; unsigned CREF :1; unsigned EVPOL :2; unsigned CPOL :1; unsigned COE :1; unsigned CON :1; }; struct { unsigned CCH0 :1; unsigned CCH1 :1; unsigned :1; unsigned EVPOL0 :1; unsigned EVPOL1 :1; }; struct { unsigned CCH02 :1; unsigned CCH12 :1; unsigned CREF2 :1; unsigned EVPOL02 :1; unsigned EVPOL12 :1; unsigned CPOL2 :1; unsigned COE2 :1; unsigned CON2 :1; }; } CM2CON1bits_t; extern volatile CM2CON1bits_t CM2CON1bits @ 0xF5E; // bitfield macros #define _CM2CON1_CCH_POSN 0x0 #define _CM2CON1_CCH_POSITION 0x0 #define _CM2CON1_CCH_SIZE 0x2 #define _CM2CON1_CCH_LENGTH 0x2 #define _CM2CON1_CCH_MASK 0x3 #define _CM2CON1_CREF_POSN 0x2 #define _CM2CON1_CREF_POSITION 0x2 #define _CM2CON1_CREF_SIZE 0x1 #define _CM2CON1_CREF_LENGTH 0x1 #define _CM2CON1_CREF_MASK 0x4 #define _CM2CON1_EVPOL_POSN 0x3 #define _CM2CON1_EVPOL_POSITION 0x3 #define _CM2CON1_EVPOL_SIZE 0x2 #define _CM2CON1_EVPOL_LENGTH 0x2 #define _CM2CON1_EVPOL_MASK 0x18 #define _CM2CON1_CPOL_POSN 0x5 #define _CM2CON1_CPOL_POSITION 0x5 #define _CM2CON1_CPOL_SIZE 0x1 #define _CM2CON1_CPOL_LENGTH 0x1 #define _CM2CON1_CPOL_MASK 0x20 #define _CM2CON1_COE_POSN 0x6 #define _CM2CON1_COE_POSITION 0x6 #define _CM2CON1_COE_SIZE 0x1 #define _CM2CON1_COE_LENGTH 0x1 #define _CM2CON1_COE_MASK 0x40 #define _CM2CON1_CON_POSN 0x7 #define _CM2CON1_CON_POSITION 0x7 #define _CM2CON1_CON_SIZE 0x1 #define _CM2CON1_CON_LENGTH 0x1 #define _CM2CON1_CON_MASK 0x80 #define _CM2CON1_CCH0_POSN 0x0 #define _CM2CON1_CCH0_POSITION 0x0 #define _CM2CON1_CCH0_SIZE 0x1 #define _CM2CON1_CCH0_LENGTH 0x1 #define _CM2CON1_CCH0_MASK 0x1 #define _CM2CON1_CCH1_POSN 0x1 #define _CM2CON1_CCH1_POSITION 0x1 #define _CM2CON1_CCH1_SIZE 0x1 #define _CM2CON1_CCH1_LENGTH 0x1 #define _CM2CON1_CCH1_MASK 0x2 #define _CM2CON1_EVPOL0_POSN 0x3 #define _CM2CON1_EVPOL0_POSITION 0x3 #define _CM2CON1_EVPOL0_SIZE 0x1 #define _CM2CON1_EVPOL0_LENGTH 0x1 #define _CM2CON1_EVPOL0_MASK 0x8 #define _CM2CON1_EVPOL1_POSN 0x4 #define _CM2CON1_EVPOL1_POSITION 0x4 #define _CM2CON1_EVPOL1_SIZE 0x1 #define _CM2CON1_EVPOL1_LENGTH 0x1 #define _CM2CON1_EVPOL1_MASK 0x10 #define _CM2CON1_CCH02_POSN 0x0 #define _CM2CON1_CCH02_POSITION 0x0 #define _CM2CON1_CCH02_SIZE 0x1 #define _CM2CON1_CCH02_LENGTH 0x1 #define _CM2CON1_CCH02_MASK 0x1 #define _CM2CON1_CCH12_POSN 0x1 #define _CM2CON1_CCH12_POSITION 0x1 #define _CM2CON1_CCH12_SIZE 0x1 #define _CM2CON1_CCH12_LENGTH 0x1 #define _CM2CON1_CCH12_MASK 0x2 #define _CM2CON1_CREF2_POSN 0x2 #define _CM2CON1_CREF2_POSITION 0x2 #define _CM2CON1_CREF2_SIZE 0x1 #define _CM2CON1_CREF2_LENGTH 0x1 #define _CM2CON1_CREF2_MASK 0x4 #define _CM2CON1_EVPOL02_POSN 0x3 #define _CM2CON1_EVPOL02_POSITION 0x3 #define _CM2CON1_EVPOL02_SIZE 0x1 #define _CM2CON1_EVPOL02_LENGTH 0x1 #define _CM2CON1_EVPOL02_MASK 0x8 #define _CM2CON1_EVPOL12_POSN 0x4 #define _CM2CON1_EVPOL12_POSITION 0x4 #define _CM2CON1_EVPOL12_SIZE 0x1 #define _CM2CON1_EVPOL12_LENGTH 0x1 #define _CM2CON1_EVPOL12_MASK 0x10 #define _CM2CON1_CPOL2_POSN 0x5 #define _CM2CON1_CPOL2_POSITION 0x5 #define _CM2CON1_CPOL2_SIZE 0x1 #define _CM2CON1_CPOL2_LENGTH 0x1 #define _CM2CON1_CPOL2_MASK 0x20 #define _CM2CON1_COE2_POSN 0x6 #define _CM2CON1_COE2_POSITION 0x6 #define _CM2CON1_COE2_SIZE 0x1 #define _CM2CON1_COE2_LENGTH 0x1 #define _CM2CON1_COE2_MASK 0x40 #define _CM2CON1_CON2_POSN 0x7 #define _CM2CON1_CON2_POSITION 0x7 #define _CM2CON1_CON2_SIZE 0x1 #define _CM2CON1_CON2_LENGTH 0x1 #define _CM2CON1_CON2_MASK 0x80 // Register: CM1CON #define CM1CON CM1CON extern volatile unsigned char CM1CON @ 0xF5F; #ifndef _LIB_BUILD asm("CM1CON equ 0F5Fh"); #endif // aliases extern volatile unsigned char CM1CON1 @ 0xF5F; #ifndef _LIB_BUILD asm("CM1CON1 equ 0F5Fh"); #endif // bitfield definitions typedef union { struct { unsigned CCH :2; unsigned CREF :1; unsigned EVPOL :2; unsigned CPOL :1; unsigned COE :1; unsigned CON :1; }; struct { unsigned CCH0 :1; unsigned CCH1 :1; unsigned :1; unsigned EVPOL0 :1; unsigned EVPOL1 :1; }; struct { unsigned C1CH0 :1; unsigned C1CH1 :1; unsigned CREF1 :1; unsigned EVPOL01 :1; unsigned EVPOL11 :1; unsigned CPOL1 :1; unsigned COE1 :1; unsigned CON1 :1; }; struct { unsigned CCH01 :1; unsigned CCH11 :1; }; } CM1CONbits_t; extern volatile CM1CONbits_t CM1CONbits @ 0xF5F; // bitfield macros #define _CM1CON_CCH_POSN 0x0 #define _CM1CON_CCH_POSITION 0x0 #define _CM1CON_CCH_SIZE 0x2 #define _CM1CON_CCH_LENGTH 0x2 #define _CM1CON_CCH_MASK 0x3 #define _CM1CON_CREF_POSN 0x2 #define _CM1CON_CREF_POSITION 0x2 #define _CM1CON_CREF_SIZE 0x1 #define _CM1CON_CREF_LENGTH 0x1 #define _CM1CON_CREF_MASK 0x4 #define _CM1CON_EVPOL_POSN 0x3 #define _CM1CON_EVPOL_POSITION 0x3 #define _CM1CON_EVPOL_SIZE 0x2 #define _CM1CON_EVPOL_LENGTH 0x2 #define _CM1CON_EVPOL_MASK 0x18 #define _CM1CON_CPOL_POSN 0x5 #define _CM1CON_CPOL_POSITION 0x5 #define _CM1CON_CPOL_SIZE 0x1 #define _CM1CON_CPOL_LENGTH 0x1 #define _CM1CON_CPOL_MASK 0x20 #define _CM1CON_COE_POSN 0x6 #define _CM1CON_COE_POSITION 0x6 #define _CM1CON_COE_SIZE 0x1 #define _CM1CON_COE_LENGTH 0x1 #define _CM1CON_COE_MASK 0x40 #define _CM1CON_CON_POSN 0x7 #define _CM1CON_CON_POSITION 0x7 #define _CM1CON_CON_SIZE 0x1 #define _CM1CON_CON_LENGTH 0x1 #define _CM1CON_CON_MASK 0x80 #define _CM1CON_CCH0_POSN 0x0 #define _CM1CON_CCH0_POSITION 0x0 #define _CM1CON_CCH0_SIZE 0x1 #define _CM1CON_CCH0_LENGTH 0x1 #define _CM1CON_CCH0_MASK 0x1 #define _CM1CON_CCH1_POSN 0x1 #define _CM1CON_CCH1_POSITION 0x1 #define _CM1CON_CCH1_SIZE 0x1 #define _CM1CON_CCH1_LENGTH 0x1 #define _CM1CON_CCH1_MASK 0x2 #define _CM1CON_EVPOL0_POSN 0x3 #define _CM1CON_EVPOL0_POSITION 0x3 #define _CM1CON_EVPOL0_SIZE 0x1 #define _CM1CON_EVPOL0_LENGTH 0x1 #define _CM1CON_EVPOL0_MASK 0x8 #define _CM1CON_EVPOL1_POSN 0x4 #define _CM1CON_EVPOL1_POSITION 0x4 #define _CM1CON_EVPOL1_SIZE 0x1 #define _CM1CON_EVPOL1_LENGTH 0x1 #define _CM1CON_EVPOL1_MASK 0x10 #define _CM1CON_C1CH0_POSN 0x0 #define _CM1CON_C1CH0_POSITION 0x0 #define _CM1CON_C1CH0_SIZE 0x1 #define _CM1CON_C1CH0_LENGTH 0x1 #define _CM1CON_C1CH0_MASK 0x1 #define _CM1CON_C1CH1_POSN 0x1 #define _CM1CON_C1CH1_POSITION 0x1 #define _CM1CON_C1CH1_SIZE 0x1 #define _CM1CON_C1CH1_LENGTH 0x1 #define _CM1CON_C1CH1_MASK 0x2 #define _CM1CON_CREF1_POSN 0x2 #define _CM1CON_CREF1_POSITION 0x2 #define _CM1CON_CREF1_SIZE 0x1 #define _CM1CON_CREF1_LENGTH 0x1 #define _CM1CON_CREF1_MASK 0x4 #define _CM1CON_EVPOL01_POSN 0x3 #define _CM1CON_EVPOL01_POSITION 0x3 #define _CM1CON_EVPOL01_SIZE 0x1 #define _CM1CON_EVPOL01_LENGTH 0x1 #define _CM1CON_EVPOL01_MASK 0x8 #define _CM1CON_EVPOL11_POSN 0x4 #define _CM1CON_EVPOL11_POSITION 0x4 #define _CM1CON_EVPOL11_SIZE 0x1 #define _CM1CON_EVPOL11_LENGTH 0x1 #define _CM1CON_EVPOL11_MASK 0x10 #define _CM1CON_CPOL1_POSN 0x5 #define _CM1CON_CPOL1_POSITION 0x5 #define _CM1CON_CPOL1_SIZE 0x1 #define _CM1CON_CPOL1_LENGTH 0x1 #define _CM1CON_CPOL1_MASK 0x20 #define _CM1CON_COE1_POSN 0x6 #define _CM1CON_COE1_POSITION 0x6 #define _CM1CON_COE1_SIZE 0x1 #define _CM1CON_COE1_LENGTH 0x1 #define _CM1CON_COE1_MASK 0x40 #define _CM1CON_CON1_POSN 0x7 #define _CM1CON_CON1_POSITION 0x7 #define _CM1CON_CON1_SIZE 0x1 #define _CM1CON_CON1_LENGTH 0x1 #define _CM1CON_CON1_MASK 0x80 #define _CM1CON_CCH01_POSN 0x0 #define _CM1CON_CCH01_POSITION 0x0 #define _CM1CON_CCH01_SIZE 0x1 #define _CM1CON_CCH01_LENGTH 0x1 #define _CM1CON_CCH01_MASK 0x1 #define _CM1CON_CCH11_POSN 0x1 #define _CM1CON_CCH11_POSITION 0x1 #define _CM1CON_CCH11_SIZE 0x1 #define _CM1CON_CCH11_LENGTH 0x1 #define _CM1CON_CCH11_MASK 0x2 // alias bitfield definitions typedef union { struct { unsigned CCH :2; unsigned CREF :1; unsigned EVPOL :2; unsigned CPOL :1; unsigned COE :1; unsigned CON :1; }; struct { unsigned CCH0 :1; unsigned CCH1 :1; unsigned :1; unsigned EVPOL0 :1; unsigned EVPOL1 :1; }; struct { unsigned C1CH0 :1; unsigned C1CH1 :1; unsigned CREF1 :1; unsigned EVPOL01 :1; unsigned EVPOL11 :1; unsigned CPOL1 :1; unsigned COE1 :1; unsigned CON1 :1; }; struct { unsigned CCH01 :1; unsigned CCH11 :1; }; } CM1CON1bits_t; extern volatile CM1CON1bits_t CM1CON1bits @ 0xF5F; // bitfield macros #define _CM1CON1_CCH_POSN 0x0 #define _CM1CON1_CCH_POSITION 0x0 #define _CM1CON1_CCH_SIZE 0x2 #define _CM1CON1_CCH_LENGTH 0x2 #define _CM1CON1_CCH_MASK 0x3 #define _CM1CON1_CREF_POSN 0x2 #define _CM1CON1_CREF_POSITION 0x2 #define _CM1CON1_CREF_SIZE 0x1 #define _CM1CON1_CREF_LENGTH 0x1 #define _CM1CON1_CREF_MASK 0x4 #define _CM1CON1_EVPOL_POSN 0x3 #define _CM1CON1_EVPOL_POSITION 0x3 #define _CM1CON1_EVPOL_SIZE 0x2 #define _CM1CON1_EVPOL_LENGTH 0x2 #define _CM1CON1_EVPOL_MASK 0x18 #define _CM1CON1_CPOL_POSN 0x5 #define _CM1CON1_CPOL_POSITION 0x5 #define _CM1CON1_CPOL_SIZE 0x1 #define _CM1CON1_CPOL_LENGTH 0x1 #define _CM1CON1_CPOL_MASK 0x20 #define _CM1CON1_COE_POSN 0x6 #define _CM1CON1_COE_POSITION 0x6 #define _CM1CON1_COE_SIZE 0x1 #define _CM1CON1_COE_LENGTH 0x1 #define _CM1CON1_COE_MASK 0x40 #define _CM1CON1_CON_POSN 0x7 #define _CM1CON1_CON_POSITION 0x7 #define _CM1CON1_CON_SIZE 0x1 #define _CM1CON1_CON_LENGTH 0x1 #define _CM1CON1_CON_MASK 0x80 #define _CM1CON1_CCH0_POSN 0x0 #define _CM1CON1_CCH0_POSITION 0x0 #define _CM1CON1_CCH0_SIZE 0x1 #define _CM1CON1_CCH0_LENGTH 0x1 #define _CM1CON1_CCH0_MASK 0x1 #define _CM1CON1_CCH1_POSN 0x1 #define _CM1CON1_CCH1_POSITION 0x1 #define _CM1CON1_CCH1_SIZE 0x1 #define _CM1CON1_CCH1_LENGTH 0x1 #define _CM1CON1_CCH1_MASK 0x2 #define _CM1CON1_EVPOL0_POSN 0x3 #define _CM1CON1_EVPOL0_POSITION 0x3 #define _CM1CON1_EVPOL0_SIZE 0x1 #define _CM1CON1_EVPOL0_LENGTH 0x1 #define _CM1CON1_EVPOL0_MASK 0x8 #define _CM1CON1_EVPOL1_POSN 0x4 #define _CM1CON1_EVPOL1_POSITION 0x4 #define _CM1CON1_EVPOL1_SIZE 0x1 #define _CM1CON1_EVPOL1_LENGTH 0x1 #define _CM1CON1_EVPOL1_MASK 0x10 #define _CM1CON1_C1CH0_POSN 0x0 #define _CM1CON1_C1CH0_POSITION 0x0 #define _CM1CON1_C1CH0_SIZE 0x1 #define _CM1CON1_C1CH0_LENGTH 0x1 #define _CM1CON1_C1CH0_MASK 0x1 #define _CM1CON1_C1CH1_POSN 0x1 #define _CM1CON1_C1CH1_POSITION 0x1 #define _CM1CON1_C1CH1_SIZE 0x1 #define _CM1CON1_C1CH1_LENGTH 0x1 #define _CM1CON1_C1CH1_MASK 0x2 #define _CM1CON1_CREF1_POSN 0x2 #define _CM1CON1_CREF1_POSITION 0x2 #define _CM1CON1_CREF1_SIZE 0x1 #define _CM1CON1_CREF1_LENGTH 0x1 #define _CM1CON1_CREF1_MASK 0x4 #define _CM1CON1_EVPOL01_POSN 0x3 #define _CM1CON1_EVPOL01_POSITION 0x3 #define _CM1CON1_EVPOL01_SIZE 0x1 #define _CM1CON1_EVPOL01_LENGTH 0x1 #define _CM1CON1_EVPOL01_MASK 0x8 #define _CM1CON1_EVPOL11_POSN 0x4 #define _CM1CON1_EVPOL11_POSITION 0x4 #define _CM1CON1_EVPOL11_SIZE 0x1 #define _CM1CON1_EVPOL11_LENGTH 0x1 #define _CM1CON1_EVPOL11_MASK 0x10 #define _CM1CON1_CPOL1_POSN 0x5 #define _CM1CON1_CPOL1_POSITION 0x5 #define _CM1CON1_CPOL1_SIZE 0x1 #define _CM1CON1_CPOL1_LENGTH 0x1 #define _CM1CON1_CPOL1_MASK 0x20 #define _CM1CON1_COE1_POSN 0x6 #define _CM1CON1_COE1_POSITION 0x6 #define _CM1CON1_COE1_SIZE 0x1 #define _CM1CON1_COE1_LENGTH 0x1 #define _CM1CON1_COE1_MASK 0x40 #define _CM1CON1_CON1_POSN 0x7 #define _CM1CON1_CON1_POSITION 0x7 #define _CM1CON1_CON1_SIZE 0x1 #define _CM1CON1_CON1_LENGTH 0x1 #define _CM1CON1_CON1_MASK 0x80 #define _CM1CON1_CCH01_POSN 0x0 #define _CM1CON1_CCH01_POSITION 0x0 #define _CM1CON1_CCH01_SIZE 0x1 #define _CM1CON1_CCH01_LENGTH 0x1 #define _CM1CON1_CCH01_MASK 0x1 #define _CM1CON1_CCH11_POSN 0x1 #define _CM1CON1_CCH11_POSITION 0x1 #define _CM1CON1_CCH11_SIZE 0x1 #define _CM1CON1_CCH11_LENGTH 0x1 #define _CM1CON1_CCH11_MASK 0x2 // Register: RXB0CON #define RXB0CON RXB0CON extern volatile unsigned char RXB0CON @ 0xF60; #ifndef _LIB_BUILD asm("RXB0CON equ 0F60h"); #endif // bitfield definitions typedef union { struct { unsigned FILHIT0 :1; unsigned JTOFF_FILHIT1 :1; unsigned RB0DBEN_FILHIT2 :1; unsigned RXRTRRO_FILHIT3 :1; unsigned FILHIT4 :1; unsigned RXM0_RTRRO :1; unsigned RXM1 :1; unsigned RXFUL :1; }; struct { unsigned :1; unsigned JTOFF :1; unsigned RB0DBEN :1; unsigned RXRTRRO :1; unsigned :1; unsigned RTRRO :1; }; struct { unsigned :1; unsigned FILHIT1 :1; unsigned FILHIT2 :1; unsigned FILHIT3 :1; unsigned :1; unsigned RXM0 :1; }; struct { unsigned RXB0FILHIT0 :1; unsigned RXB0FILHIT1 :1; unsigned RXB0FILHIT2 :1; unsigned RXB0FILHIT3 :1; unsigned RXB0FILHIT4 :1; unsigned RXB0M0 :1; unsigned RXB0M1 :1; unsigned RXB0FUL :1; }; struct { unsigned :3; unsigned RXB0RTRR0 :1; unsigned :1; unsigned RXB0RTRRO :1; }; } RXB0CONbits_t; extern volatile RXB0CONbits_t RXB0CONbits @ 0xF60; // bitfield macros #define _RXB0CON_FILHIT0_POSN 0x0 #define _RXB0CON_FILHIT0_POSITION 0x0 #define _RXB0CON_FILHIT0_SIZE 0x1 #define _RXB0CON_FILHIT0_LENGTH 0x1 #define _RXB0CON_FILHIT0_MASK 0x1 #define _RXB0CON_JTOFF_FILHIT1_POSN 0x1 #define _RXB0CON_JTOFF_FILHIT1_POSITION 0x1 #define _RXB0CON_JTOFF_FILHIT1_SIZE 0x1 #define _RXB0CON_JTOFF_FILHIT1_LENGTH 0x1 #define _RXB0CON_JTOFF_FILHIT1_MASK 0x2 #define _RXB0CON_RB0DBEN_FILHIT2_POSN 0x2 #define _RXB0CON_RB0DBEN_FILHIT2_POSITION 0x2 #define _RXB0CON_RB0DBEN_FILHIT2_SIZE 0x1 #define _RXB0CON_RB0DBEN_FILHIT2_LENGTH 0x1 #define _RXB0CON_RB0DBEN_FILHIT2_MASK 0x4 #define _RXB0CON_RXRTRRO_FILHIT3_POSN 0x3 #define _RXB0CON_RXRTRRO_FILHIT3_POSITION 0x3 #define _RXB0CON_RXRTRRO_FILHIT3_SIZE 0x1 #define _RXB0CON_RXRTRRO_FILHIT3_LENGTH 0x1 #define _RXB0CON_RXRTRRO_FILHIT3_MASK 0x8 #define _RXB0CON_FILHIT4_POSN 0x4 #define _RXB0CON_FILHIT4_POSITION 0x4 #define _RXB0CON_FILHIT4_SIZE 0x1 #define _RXB0CON_FILHIT4_LENGTH 0x1 #define _RXB0CON_FILHIT4_MASK 0x10 #define _RXB0CON_RXM0_RTRRO_POSN 0x5 #define _RXB0CON_RXM0_RTRRO_POSITION 0x5 #define _RXB0CON_RXM0_RTRRO_SIZE 0x1 #define _RXB0CON_RXM0_RTRRO_LENGTH 0x1 #define _RXB0CON_RXM0_RTRRO_MASK 0x20 #define _RXB0CON_RXM1_POSN 0x6 #define _RXB0CON_RXM1_POSITION 0x6 #define _RXB0CON_RXM1_SIZE 0x1 #define _RXB0CON_RXM1_LENGTH 0x1 #define _RXB0CON_RXM1_MASK 0x40 #define _RXB0CON_RXFUL_POSN 0x7 #define _RXB0CON_RXFUL_POSITION 0x7 #define _RXB0CON_RXFUL_SIZE 0x1 #define _RXB0CON_RXFUL_LENGTH 0x1 #define _RXB0CON_RXFUL_MASK 0x80 #define _RXB0CON_JTOFF_POSN 0x1 #define _RXB0CON_JTOFF_POSITION 0x1 #define _RXB0CON_JTOFF_SIZE 0x1 #define _RXB0CON_JTOFF_LENGTH 0x1 #define _RXB0CON_JTOFF_MASK 0x2 #define _RXB0CON_RB0DBEN_POSN 0x2 #define _RXB0CON_RB0DBEN_POSITION 0x2 #define _RXB0CON_RB0DBEN_SIZE 0x1 #define _RXB0CON_RB0DBEN_LENGTH 0x1 #define _RXB0CON_RB0DBEN_MASK 0x4 #define _RXB0CON_RXRTRRO_POSN 0x3 #define _RXB0CON_RXRTRRO_POSITION 0x3 #define _RXB0CON_RXRTRRO_SIZE 0x1 #define _RXB0CON_RXRTRRO_LENGTH 0x1 #define _RXB0CON_RXRTRRO_MASK 0x8 #define _RXB0CON_RTRRO_POSN 0x5 #define _RXB0CON_RTRRO_POSITION 0x5 #define _RXB0CON_RTRRO_SIZE 0x1 #define _RXB0CON_RTRRO_LENGTH 0x1 #define _RXB0CON_RTRRO_MASK 0x20 #define _RXB0CON_FILHIT1_POSN 0x1 #define _RXB0CON_FILHIT1_POSITION 0x1 #define _RXB0CON_FILHIT1_SIZE 0x1 #define _RXB0CON_FILHIT1_LENGTH 0x1 #define _RXB0CON_FILHIT1_MASK 0x2 #define _RXB0CON_FILHIT2_POSN 0x2 #define _RXB0CON_FILHIT2_POSITION 0x2 #define _RXB0CON_FILHIT2_SIZE 0x1 #define _RXB0CON_FILHIT2_LENGTH 0x1 #define _RXB0CON_FILHIT2_MASK 0x4 #define _RXB0CON_FILHIT3_POSN 0x3 #define _RXB0CON_FILHIT3_POSITION 0x3 #define _RXB0CON_FILHIT3_SIZE 0x1 #define _RXB0CON_FILHIT3_LENGTH 0x1 #define _RXB0CON_FILHIT3_MASK 0x8 #define _RXB0CON_RXM0_POSN 0x5 #define _RXB0CON_RXM0_POSITION 0x5 #define _RXB0CON_RXM0_SIZE 0x1 #define _RXB0CON_RXM0_LENGTH 0x1 #define _RXB0CON_RXM0_MASK 0x20 #define _RXB0CON_RXB0FILHIT0_POSN 0x0 #define _RXB0CON_RXB0FILHIT0_POSITION 0x0 #define _RXB0CON_RXB0FILHIT0_SIZE 0x1 #define _RXB0CON_RXB0FILHIT0_LENGTH 0x1 #define _RXB0CON_RXB0FILHIT0_MASK 0x1 #define _RXB0CON_RXB0FILHIT1_POSN 0x1 #define _RXB0CON_RXB0FILHIT1_POSITION 0x1 #define _RXB0CON_RXB0FILHIT1_SIZE 0x1 #define _RXB0CON_RXB0FILHIT1_LENGTH 0x1 #define _RXB0CON_RXB0FILHIT1_MASK 0x2 #define _RXB0CON_RXB0FILHIT2_POSN 0x2 #define _RXB0CON_RXB0FILHIT2_POSITION 0x2 #define _RXB0CON_RXB0FILHIT2_SIZE 0x1 #define _RXB0CON_RXB0FILHIT2_LENGTH 0x1 #define _RXB0CON_RXB0FILHIT2_MASK 0x4 #define _RXB0CON_RXB0FILHIT3_POSN 0x3 #define _RXB0CON_RXB0FILHIT3_POSITION 0x3 #define _RXB0CON_RXB0FILHIT3_SIZE 0x1 #define _RXB0CON_RXB0FILHIT3_LENGTH 0x1 #define _RXB0CON_RXB0FILHIT3_MASK 0x8 #define _RXB0CON_RXB0FILHIT4_POSN 0x4 #define _RXB0CON_RXB0FILHIT4_POSITION 0x4 #define _RXB0CON_RXB0FILHIT4_SIZE 0x1 #define _RXB0CON_RXB0FILHIT4_LENGTH 0x1 #define _RXB0CON_RXB0FILHIT4_MASK 0x10 #define _RXB0CON_RXB0M0_POSN 0x5 #define _RXB0CON_RXB0M0_POSITION 0x5 #define _RXB0CON_RXB0M0_SIZE 0x1 #define _RXB0CON_RXB0M0_LENGTH 0x1 #define _RXB0CON_RXB0M0_MASK 0x20 #define _RXB0CON_RXB0M1_POSN 0x6 #define _RXB0CON_RXB0M1_POSITION 0x6 #define _RXB0CON_RXB0M1_SIZE 0x1 #define _RXB0CON_RXB0M1_LENGTH 0x1 #define _RXB0CON_RXB0M1_MASK 0x40 #define _RXB0CON_RXB0FUL_POSN 0x7 #define _RXB0CON_RXB0FUL_POSITION 0x7 #define _RXB0CON_RXB0FUL_SIZE 0x1 #define _RXB0CON_RXB0FUL_LENGTH 0x1 #define _RXB0CON_RXB0FUL_MASK 0x80 #define _RXB0CON_RXB0RTRR0_POSN 0x3 #define _RXB0CON_RXB0RTRR0_POSITION 0x3 #define _RXB0CON_RXB0RTRR0_SIZE 0x1 #define _RXB0CON_RXB0RTRR0_LENGTH 0x1 #define _RXB0CON_RXB0RTRR0_MASK 0x8 #define _RXB0CON_RXB0RTRRO_POSN 0x5 #define _RXB0CON_RXB0RTRRO_POSITION 0x5 #define _RXB0CON_RXB0RTRRO_SIZE 0x1 #define _RXB0CON_RXB0RTRRO_LENGTH 0x1 #define _RXB0CON_RXB0RTRRO_MASK 0x20 // Register: RXB0SIDH #define RXB0SIDH RXB0SIDH extern volatile unsigned char RXB0SIDH @ 0xF61; #ifndef _LIB_BUILD asm("RXB0SIDH equ 0F61h"); #endif // bitfield definitions typedef union { struct { unsigned SID :8; }; struct { unsigned SID3 :1; unsigned SID4 :1; unsigned SID5 :1; unsigned SID6 :1; unsigned SID7 :1; unsigned SID8 :1; unsigned SID9 :1; unsigned SID10 :1; }; struct { unsigned RXB0SID3 :1; unsigned RXB0SID4 :1; unsigned RXB0SID5 :1; unsigned RXB0SID6 :1; unsigned RXB0SID7 :1; unsigned RXB0SID8 :1; unsigned RXB0SID9 :1; unsigned RXB0SID10 :1; }; } RXB0SIDHbits_t; extern volatile RXB0SIDHbits_t RXB0SIDHbits @ 0xF61; // bitfield macros #define _RXB0SIDH_SID_POSN 0x0 #define _RXB0SIDH_SID_POSITION 0x0 #define _RXB0SIDH_SID_SIZE 0x8 #define _RXB0SIDH_SID_LENGTH 0x8 #define _RXB0SIDH_SID_MASK 0xFF #define _RXB0SIDH_SID3_POSN 0x0 #define _RXB0SIDH_SID3_POSITION 0x0 #define _RXB0SIDH_SID3_SIZE 0x1 #define _RXB0SIDH_SID3_LENGTH 0x1 #define _RXB0SIDH_SID3_MASK 0x1 #define _RXB0SIDH_SID4_POSN 0x1 #define _RXB0SIDH_SID4_POSITION 0x1 #define _RXB0SIDH_SID4_SIZE 0x1 #define _RXB0SIDH_SID4_LENGTH 0x1 #define _RXB0SIDH_SID4_MASK 0x2 #define _RXB0SIDH_SID5_POSN 0x2 #define _RXB0SIDH_SID5_POSITION 0x2 #define _RXB0SIDH_SID5_SIZE 0x1 #define _RXB0SIDH_SID5_LENGTH 0x1 #define _RXB0SIDH_SID5_MASK 0x4 #define _RXB0SIDH_SID6_POSN 0x3 #define _RXB0SIDH_SID6_POSITION 0x3 #define _RXB0SIDH_SID6_SIZE 0x1 #define _RXB0SIDH_SID6_LENGTH 0x1 #define _RXB0SIDH_SID6_MASK 0x8 #define _RXB0SIDH_SID7_POSN 0x4 #define _RXB0SIDH_SID7_POSITION 0x4 #define _RXB0SIDH_SID7_SIZE 0x1 #define _RXB0SIDH_SID7_LENGTH 0x1 #define _RXB0SIDH_SID7_MASK 0x10 #define _RXB0SIDH_SID8_POSN 0x5 #define _RXB0SIDH_SID8_POSITION 0x5 #define _RXB0SIDH_SID8_SIZE 0x1 #define _RXB0SIDH_SID8_LENGTH 0x1 #define _RXB0SIDH_SID8_MASK 0x20 #define _RXB0SIDH_SID9_POSN 0x6 #define _RXB0SIDH_SID9_POSITION 0x6 #define _RXB0SIDH_SID9_SIZE 0x1 #define _RXB0SIDH_SID9_LENGTH 0x1 #define _RXB0SIDH_SID9_MASK 0x40 #define _RXB0SIDH_SID10_POSN 0x7 #define _RXB0SIDH_SID10_POSITION 0x7 #define _RXB0SIDH_SID10_SIZE 0x1 #define _RXB0SIDH_SID10_LENGTH 0x1 #define _RXB0SIDH_SID10_MASK 0x80 #define _RXB0SIDH_RXB0SID3_POSN 0x0 #define _RXB0SIDH_RXB0SID3_POSITION 0x0 #define _RXB0SIDH_RXB0SID3_SIZE 0x1 #define _RXB0SIDH_RXB0SID3_LENGTH 0x1 #define _RXB0SIDH_RXB0SID3_MASK 0x1 #define _RXB0SIDH_RXB0SID4_POSN 0x1 #define _RXB0SIDH_RXB0SID4_POSITION 0x1 #define _RXB0SIDH_RXB0SID4_SIZE 0x1 #define _RXB0SIDH_RXB0SID4_LENGTH 0x1 #define _RXB0SIDH_RXB0SID4_MASK 0x2 #define _RXB0SIDH_RXB0SID5_POSN 0x2 #define _RXB0SIDH_RXB0SID5_POSITION 0x2 #define _RXB0SIDH_RXB0SID5_SIZE 0x1 #define _RXB0SIDH_RXB0SID5_LENGTH 0x1 #define _RXB0SIDH_RXB0SID5_MASK 0x4 #define _RXB0SIDH_RXB0SID6_POSN 0x3 #define _RXB0SIDH_RXB0SID6_POSITION 0x3 #define _RXB0SIDH_RXB0SID6_SIZE 0x1 #define _RXB0SIDH_RXB0SID6_LENGTH 0x1 #define _RXB0SIDH_RXB0SID6_MASK 0x8 #define _RXB0SIDH_RXB0SID7_POSN 0x4 #define _RXB0SIDH_RXB0SID7_POSITION 0x4 #define _RXB0SIDH_RXB0SID7_SIZE 0x1 #define _RXB0SIDH_RXB0SID7_LENGTH 0x1 #define _RXB0SIDH_RXB0SID7_MASK 0x10 #define _RXB0SIDH_RXB0SID8_POSN 0x5 #define _RXB0SIDH_RXB0SID8_POSITION 0x5 #define _RXB0SIDH_RXB0SID8_SIZE 0x1 #define _RXB0SIDH_RXB0SID8_LENGTH 0x1 #define _RXB0SIDH_RXB0SID8_MASK 0x20 #define _RXB0SIDH_RXB0SID9_POSN 0x6 #define _RXB0SIDH_RXB0SID9_POSITION 0x6 #define _RXB0SIDH_RXB0SID9_SIZE 0x1 #define _RXB0SIDH_RXB0SID9_LENGTH 0x1 #define _RXB0SIDH_RXB0SID9_MASK 0x40 #define _RXB0SIDH_RXB0SID10_POSN 0x7 #define _RXB0SIDH_RXB0SID10_POSITION 0x7 #define _RXB0SIDH_RXB0SID10_SIZE 0x1 #define _RXB0SIDH_RXB0SID10_LENGTH 0x1 #define _RXB0SIDH_RXB0SID10_MASK 0x80 // Register: RXB0SIDL #define RXB0SIDL RXB0SIDL extern volatile unsigned char RXB0SIDL @ 0xF62; #ifndef _LIB_BUILD asm("RXB0SIDL equ 0F62h"); #endif // bitfield definitions typedef union { struct { unsigned EID :2; unsigned :1; unsigned EXID :1; unsigned SRR :1; unsigned SID :3; }; struct { unsigned EID16 :1; unsigned EID17 :1; unsigned :3; unsigned SID0 :1; unsigned SID1 :1; unsigned SID2 :1; }; struct { unsigned RXB0EID16 :1; unsigned RXB0EID17 :1; unsigned :1; unsigned RXB0EXID :1; unsigned RXB0SRR :1; unsigned RXB0SID0 :1; unsigned RXB0SID1 :1; unsigned RXB0SID2 :1; }; } RXB0SIDLbits_t; extern volatile RXB0SIDLbits_t RXB0SIDLbits @ 0xF62; // bitfield macros #define _RXB0SIDL_EID_POSN 0x0 #define _RXB0SIDL_EID_POSITION 0x0 #define _RXB0SIDL_EID_SIZE 0x2 #define _RXB0SIDL_EID_LENGTH 0x2 #define _RXB0SIDL_EID_MASK 0x3 #define _RXB0SIDL_EXID_POSN 0x3 #define _RXB0SIDL_EXID_POSITION 0x3 #define _RXB0SIDL_EXID_SIZE 0x1 #define _RXB0SIDL_EXID_LENGTH 0x1 #define _RXB0SIDL_EXID_MASK 0x8 #define _RXB0SIDL_SRR_POSN 0x4 #define _RXB0SIDL_SRR_POSITION 0x4 #define _RXB0SIDL_SRR_SIZE 0x1 #define _RXB0SIDL_SRR_LENGTH 0x1 #define _RXB0SIDL_SRR_MASK 0x10 #define _RXB0SIDL_SID_POSN 0x5 #define _RXB0SIDL_SID_POSITION 0x5 #define _RXB0SIDL_SID_SIZE 0x3 #define _RXB0SIDL_SID_LENGTH 0x3 #define _RXB0SIDL_SID_MASK 0xE0 #define _RXB0SIDL_EID16_POSN 0x0 #define _RXB0SIDL_EID16_POSITION 0x0 #define _RXB0SIDL_EID16_SIZE 0x1 #define _RXB0SIDL_EID16_LENGTH 0x1 #define _RXB0SIDL_EID16_MASK 0x1 #define _RXB0SIDL_EID17_POSN 0x1 #define _RXB0SIDL_EID17_POSITION 0x1 #define _RXB0SIDL_EID17_SIZE 0x1 #define _RXB0SIDL_EID17_LENGTH 0x1 #define _RXB0SIDL_EID17_MASK 0x2 #define _RXB0SIDL_SID0_POSN 0x5 #define _RXB0SIDL_SID0_POSITION 0x5 #define _RXB0SIDL_SID0_SIZE 0x1 #define _RXB0SIDL_SID0_LENGTH 0x1 #define _RXB0SIDL_SID0_MASK 0x20 #define _RXB0SIDL_SID1_POSN 0x6 #define _RXB0SIDL_SID1_POSITION 0x6 #define _RXB0SIDL_SID1_SIZE 0x1 #define _RXB0SIDL_SID1_LENGTH 0x1 #define _RXB0SIDL_SID1_MASK 0x40 #define _RXB0SIDL_SID2_POSN 0x7 #define _RXB0SIDL_SID2_POSITION 0x7 #define _RXB0SIDL_SID2_SIZE 0x1 #define _RXB0SIDL_SID2_LENGTH 0x1 #define _RXB0SIDL_SID2_MASK 0x80 #define _RXB0SIDL_RXB0EID16_POSN 0x0 #define _RXB0SIDL_RXB0EID16_POSITION 0x0 #define _RXB0SIDL_RXB0EID16_SIZE 0x1 #define _RXB0SIDL_RXB0EID16_LENGTH 0x1 #define _RXB0SIDL_RXB0EID16_MASK 0x1 #define _RXB0SIDL_RXB0EID17_POSN 0x1 #define _RXB0SIDL_RXB0EID17_POSITION 0x1 #define _RXB0SIDL_RXB0EID17_SIZE 0x1 #define _RXB0SIDL_RXB0EID17_LENGTH 0x1 #define _RXB0SIDL_RXB0EID17_MASK 0x2 #define _RXB0SIDL_RXB0EXID_POSN 0x3 #define _RXB0SIDL_RXB0EXID_POSITION 0x3 #define _RXB0SIDL_RXB0EXID_SIZE 0x1 #define _RXB0SIDL_RXB0EXID_LENGTH 0x1 #define _RXB0SIDL_RXB0EXID_MASK 0x8 #define _RXB0SIDL_RXB0SRR_POSN 0x4 #define _RXB0SIDL_RXB0SRR_POSITION 0x4 #define _RXB0SIDL_RXB0SRR_SIZE 0x1 #define _RXB0SIDL_RXB0SRR_LENGTH 0x1 #define _RXB0SIDL_RXB0SRR_MASK 0x10 #define _RXB0SIDL_RXB0SID0_POSN 0x5 #define _RXB0SIDL_RXB0SID0_POSITION 0x5 #define _RXB0SIDL_RXB0SID0_SIZE 0x1 #define _RXB0SIDL_RXB0SID0_LENGTH 0x1 #define _RXB0SIDL_RXB0SID0_MASK 0x20 #define _RXB0SIDL_RXB0SID1_POSN 0x6 #define _RXB0SIDL_RXB0SID1_POSITION 0x6 #define _RXB0SIDL_RXB0SID1_SIZE 0x1 #define _RXB0SIDL_RXB0SID1_LENGTH 0x1 #define _RXB0SIDL_RXB0SID1_MASK 0x40 #define _RXB0SIDL_RXB0SID2_POSN 0x7 #define _RXB0SIDL_RXB0SID2_POSITION 0x7 #define _RXB0SIDL_RXB0SID2_SIZE 0x1 #define _RXB0SIDL_RXB0SID2_LENGTH 0x1 #define _RXB0SIDL_RXB0SID2_MASK 0x80 // Register: RXB0EIDH #define RXB0EIDH RXB0EIDH extern volatile unsigned char RXB0EIDH @ 0xF63; #ifndef _LIB_BUILD asm("RXB0EIDH equ 0F63h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID8 :1; unsigned EID9 :1; unsigned EID10 :1; unsigned EID11 :1; unsigned EID12 :1; unsigned EID13 :1; unsigned EID14 :1; unsigned EID15 :1; }; struct { unsigned RXB0EID8 :1; unsigned RXB0EID9 :1; unsigned RXB0EID10 :1; unsigned RXB0EID11 :1; unsigned RXB0EID12 :1; unsigned RXB0EID13 :1; unsigned RXB0EID14 :1; unsigned RXB0EID15 :1; }; } RXB0EIDHbits_t; extern volatile RXB0EIDHbits_t RXB0EIDHbits @ 0xF63; // bitfield macros #define _RXB0EIDH_EID_POSN 0x0 #define _RXB0EIDH_EID_POSITION 0x0 #define _RXB0EIDH_EID_SIZE 0x8 #define _RXB0EIDH_EID_LENGTH 0x8 #define _RXB0EIDH_EID_MASK 0xFF #define _RXB0EIDH_EID8_POSN 0x0 #define _RXB0EIDH_EID8_POSITION 0x0 #define _RXB0EIDH_EID8_SIZE 0x1 #define _RXB0EIDH_EID8_LENGTH 0x1 #define _RXB0EIDH_EID8_MASK 0x1 #define _RXB0EIDH_EID9_POSN 0x1 #define _RXB0EIDH_EID9_POSITION 0x1 #define _RXB0EIDH_EID9_SIZE 0x1 #define _RXB0EIDH_EID9_LENGTH 0x1 #define _RXB0EIDH_EID9_MASK 0x2 #define _RXB0EIDH_EID10_POSN 0x2 #define _RXB0EIDH_EID10_POSITION 0x2 #define _RXB0EIDH_EID10_SIZE 0x1 #define _RXB0EIDH_EID10_LENGTH 0x1 #define _RXB0EIDH_EID10_MASK 0x4 #define _RXB0EIDH_EID11_POSN 0x3 #define _RXB0EIDH_EID11_POSITION 0x3 #define _RXB0EIDH_EID11_SIZE 0x1 #define _RXB0EIDH_EID11_LENGTH 0x1 #define _RXB0EIDH_EID11_MASK 0x8 #define _RXB0EIDH_EID12_POSN 0x4 #define _RXB0EIDH_EID12_POSITION 0x4 #define _RXB0EIDH_EID12_SIZE 0x1 #define _RXB0EIDH_EID12_LENGTH 0x1 #define _RXB0EIDH_EID12_MASK 0x10 #define _RXB0EIDH_EID13_POSN 0x5 #define _RXB0EIDH_EID13_POSITION 0x5 #define _RXB0EIDH_EID13_SIZE 0x1 #define _RXB0EIDH_EID13_LENGTH 0x1 #define _RXB0EIDH_EID13_MASK 0x20 #define _RXB0EIDH_EID14_POSN 0x6 #define _RXB0EIDH_EID14_POSITION 0x6 #define _RXB0EIDH_EID14_SIZE 0x1 #define _RXB0EIDH_EID14_LENGTH 0x1 #define _RXB0EIDH_EID14_MASK 0x40 #define _RXB0EIDH_EID15_POSN 0x7 #define _RXB0EIDH_EID15_POSITION 0x7 #define _RXB0EIDH_EID15_SIZE 0x1 #define _RXB0EIDH_EID15_LENGTH 0x1 #define _RXB0EIDH_EID15_MASK 0x80 #define _RXB0EIDH_RXB0EID8_POSN 0x0 #define _RXB0EIDH_RXB0EID8_POSITION 0x0 #define _RXB0EIDH_RXB0EID8_SIZE 0x1 #define _RXB0EIDH_RXB0EID8_LENGTH 0x1 #define _RXB0EIDH_RXB0EID8_MASK 0x1 #define _RXB0EIDH_RXB0EID9_POSN 0x1 #define _RXB0EIDH_RXB0EID9_POSITION 0x1 #define _RXB0EIDH_RXB0EID9_SIZE 0x1 #define _RXB0EIDH_RXB0EID9_LENGTH 0x1 #define _RXB0EIDH_RXB0EID9_MASK 0x2 #define _RXB0EIDH_RXB0EID10_POSN 0x2 #define _RXB0EIDH_RXB0EID10_POSITION 0x2 #define _RXB0EIDH_RXB0EID10_SIZE 0x1 #define _RXB0EIDH_RXB0EID10_LENGTH 0x1 #define _RXB0EIDH_RXB0EID10_MASK 0x4 #define _RXB0EIDH_RXB0EID11_POSN 0x3 #define _RXB0EIDH_RXB0EID11_POSITION 0x3 #define _RXB0EIDH_RXB0EID11_SIZE 0x1 #define _RXB0EIDH_RXB0EID11_LENGTH 0x1 #define _RXB0EIDH_RXB0EID11_MASK 0x8 #define _RXB0EIDH_RXB0EID12_POSN 0x4 #define _RXB0EIDH_RXB0EID12_POSITION 0x4 #define _RXB0EIDH_RXB0EID12_SIZE 0x1 #define _RXB0EIDH_RXB0EID12_LENGTH 0x1 #define _RXB0EIDH_RXB0EID12_MASK 0x10 #define _RXB0EIDH_RXB0EID13_POSN 0x5 #define _RXB0EIDH_RXB0EID13_POSITION 0x5 #define _RXB0EIDH_RXB0EID13_SIZE 0x1 #define _RXB0EIDH_RXB0EID13_LENGTH 0x1 #define _RXB0EIDH_RXB0EID13_MASK 0x20 #define _RXB0EIDH_RXB0EID14_POSN 0x6 #define _RXB0EIDH_RXB0EID14_POSITION 0x6 #define _RXB0EIDH_RXB0EID14_SIZE 0x1 #define _RXB0EIDH_RXB0EID14_LENGTH 0x1 #define _RXB0EIDH_RXB0EID14_MASK 0x40 #define _RXB0EIDH_RXB0EID15_POSN 0x7 #define _RXB0EIDH_RXB0EID15_POSITION 0x7 #define _RXB0EIDH_RXB0EID15_SIZE 0x1 #define _RXB0EIDH_RXB0EID15_LENGTH 0x1 #define _RXB0EIDH_RXB0EID15_MASK 0x80 // Register: RXB0EIDL #define RXB0EIDL RXB0EIDL extern volatile unsigned char RXB0EIDL @ 0xF64; #ifndef _LIB_BUILD asm("RXB0EIDL equ 0F64h"); #endif // bitfield definitions typedef union { struct { unsigned EID :8; }; struct { unsigned EID0 :1; unsigned EID1 :1; unsigned EID2 :1; unsigned EID3 :1; unsigned EID4 :1; unsigned EID5 :1; unsigned EID6 :1; unsigned EID7 :1; }; struct { unsigned RXB0EID0 :1; unsigned RXB0EID1 :1; unsigned RXB0EID2 :1; unsigned RXB0EID3 :1; unsigned RXB0EID4 :1; unsigned RXB0EID5 :1; unsigned RXB0EID6 :1; unsigned RXB0EID7 :1; }; } RXB0EIDLbits_t; extern volatile RXB0EIDLbits_t RXB0EIDLbits @ 0xF64; // bitfield macros #define _RXB0EIDL_EID_POSN 0x0 #define _RXB0EIDL_EID_POSITION 0x0 #define _RXB0EIDL_EID_SIZE 0x8 #define _RXB0EIDL_EID_LENGTH 0x8 #define _RXB0EIDL_EID_MASK 0xFF #define _RXB0EIDL_EID0_POSN 0x0 #define _RXB0EIDL_EID0_POSITION 0x0 #define _RXB0EIDL_EID0_SIZE 0x1 #define _RXB0EIDL_EID0_LENGTH 0x1 #define _RXB0EIDL_EID0_MASK 0x1 #define _RXB0EIDL_EID1_POSN 0x1 #define _RXB0EIDL_EID1_POSITION 0x1 #define _RXB0EIDL_EID1_SIZE 0x1 #define _RXB0EIDL_EID1_LENGTH 0x1 #define _RXB0EIDL_EID1_MASK 0x2 #define _RXB0EIDL_EID2_POSN 0x2 #define _RXB0EIDL_EID2_POSITION 0x2 #define _RXB0EIDL_EID2_SIZE 0x1 #define _RXB0EIDL_EID2_LENGTH 0x1 #define _RXB0EIDL_EID2_MASK 0x4 #define _RXB0EIDL_EID3_POSN 0x3 #define _RXB0EIDL_EID3_POSITION 0x3 #define _RXB0EIDL_EID3_SIZE 0x1 #define _RXB0EIDL_EID3_LENGTH 0x1 #define _RXB0EIDL_EID3_MASK 0x8 #define _RXB0EIDL_EID4_POSN 0x4 #define _RXB0EIDL_EID4_POSITION 0x4 #define _RXB0EIDL_EID4_SIZE 0x1 #define _RXB0EIDL_EID4_LENGTH 0x1 #define _RXB0EIDL_EID4_MASK 0x10 #define _RXB0EIDL_EID5_POSN 0x5 #define _RXB0EIDL_EID5_POSITION 0x5 #define _RXB0EIDL_EID5_SIZE 0x1 #define _RXB0EIDL_EID5_LENGTH 0x1 #define _RXB0EIDL_EID5_MASK 0x20 #define _RXB0EIDL_EID6_POSN 0x6 #define _RXB0EIDL_EID6_POSITION 0x6 #define _RXB0EIDL_EID6_SIZE 0x1 #define _RXB0EIDL_EID6_LENGTH 0x1 #define _RXB0EIDL_EID6_MASK 0x40 #define _RXB0EIDL_EID7_POSN 0x7 #define _RXB0EIDL_EID7_POSITION 0x7 #define _RXB0EIDL_EID7_SIZE 0x1 #define _RXB0EIDL_EID7_LENGTH 0x1 #define _RXB0EIDL_EID7_MASK 0x80 #define _RXB0EIDL_RXB0EID0_POSN 0x0 #define _RXB0EIDL_RXB0EID0_POSITION 0x0 #define _RXB0EIDL_RXB0EID0_SIZE 0x1 #define _RXB0EIDL_RXB0EID0_LENGTH 0x1 #define _RXB0EIDL_RXB0EID0_MASK 0x1 #define _RXB0EIDL_RXB0EID1_POSN 0x1 #define _RXB0EIDL_RXB0EID1_POSITION 0x1 #define _RXB0EIDL_RXB0EID1_SIZE 0x1 #define _RXB0EIDL_RXB0EID1_LENGTH 0x1 #define _RXB0EIDL_RXB0EID1_MASK 0x2 #define _RXB0EIDL_RXB0EID2_POSN 0x2 #define _RXB0EIDL_RXB0EID2_POSITION 0x2 #define _RXB0EIDL_RXB0EID2_SIZE 0x1 #define _RXB0EIDL_RXB0EID2_LENGTH 0x1 #define _RXB0EIDL_RXB0EID2_MASK 0x4 #define _RXB0EIDL_RXB0EID3_POSN 0x3 #define _RXB0EIDL_RXB0EID3_POSITION 0x3 #define _RXB0EIDL_RXB0EID3_SIZE 0x1 #define _RXB0EIDL_RXB0EID3_LENGTH 0x1 #define _RXB0EIDL_RXB0EID3_MASK 0x8 #define _RXB0EIDL_RXB0EID4_POSN 0x4 #define _RXB0EIDL_RXB0EID4_POSITION 0x4 #define _RXB0EIDL_RXB0EID4_SIZE 0x1 #define _RXB0EIDL_RXB0EID4_LENGTH 0x1 #define _RXB0EIDL_RXB0EID4_MASK 0x10 #define _RXB0EIDL_RXB0EID5_POSN 0x5 #define _RXB0EIDL_RXB0EID5_POSITION 0x5 #define _RXB0EIDL_RXB0EID5_SIZE 0x1 #define _RXB0EIDL_RXB0EID5_LENGTH 0x1 #define _RXB0EIDL_RXB0EID5_MASK 0x20 #define _RXB0EIDL_RXB0EID6_POSN 0x6 #define _RXB0EIDL_RXB0EID6_POSITION 0x6 #define _RXB0EIDL_RXB0EID6_SIZE 0x1 #define _RXB0EIDL_RXB0EID6_LENGTH 0x1 #define _RXB0EIDL_RXB0EID6_MASK 0x40 #define _RXB0EIDL_RXB0EID7_POSN 0x7 #define _RXB0EIDL_RXB0EID7_POSITION 0x7 #define _RXB0EIDL_RXB0EID7_SIZE 0x1 #define _RXB0EIDL_RXB0EID7_LENGTH 0x1 #define _RXB0EIDL_RXB0EID7_MASK 0x80 // Register: RXB0DLC #define RXB0DLC RXB0DLC extern volatile unsigned char RXB0DLC @ 0xF65; #ifndef _LIB_BUILD asm("RXB0DLC equ 0F65h"); #endif // bitfield definitions typedef union { struct { unsigned DLC :4; unsigned RB :2; unsigned RXRTR :1; }; struct { unsigned DLC0 :1; unsigned DLC1 :1; unsigned DLC2 :1; unsigned DLC3 :1; unsigned RB0 :1; unsigned RB1 :1; }; struct { unsigned RXB0DLC0 :1; unsigned RXB0DLC1 :1; unsigned RXB0DLC2 :1; unsigned RXB0DLC3 :1; unsigned RXB0RB0 :1; unsigned RXB0RB1 :1; unsigned RXB0RTR :1; }; } RXB0DLCbits_t; extern volatile RXB0DLCbits_t RXB0DLCbits @ 0xF65; // bitfield macros #define _RXB0DLC_DLC_POSN 0x0 #define _RXB0DLC_DLC_POSITION 0x0 #define _RXB0DLC_DLC_SIZE 0x4 #define _RXB0DLC_DLC_LENGTH 0x4 #define _RXB0DLC_DLC_MASK 0xF #define _RXB0DLC_RB_POSN 0x4 #define _RXB0DLC_RB_POSITION 0x4 #define _RXB0DLC_RB_SIZE 0x2 #define _RXB0DLC_RB_LENGTH 0x2 #define _RXB0DLC_RB_MASK 0x30 #define _RXB0DLC_RXRTR_POSN 0x6 #define _RXB0DLC_RXRTR_POSITION 0x6 #define _RXB0DLC_RXRTR_SIZE 0x1 #define _RXB0DLC_RXRTR_LENGTH 0x1 #define _RXB0DLC_RXRTR_MASK 0x40 #define _RXB0DLC_DLC0_POSN 0x0 #define _RXB0DLC_DLC0_POSITION 0x0 #define _RXB0DLC_DLC0_SIZE 0x1 #define _RXB0DLC_DLC0_LENGTH 0x1 #define _RXB0DLC_DLC0_MASK 0x1 #define _RXB0DLC_DLC1_POSN 0x1 #define _RXB0DLC_DLC1_POSITION 0x1 #define _RXB0DLC_DLC1_SIZE 0x1 #define _RXB0DLC_DLC1_LENGTH 0x1 #define _RXB0DLC_DLC1_MASK 0x2 #define _RXB0DLC_DLC2_POSN 0x2 #define _RXB0DLC_DLC2_POSITION 0x2 #define _RXB0DLC_DLC2_SIZE 0x1 #define _RXB0DLC_DLC2_LENGTH 0x1 #define _RXB0DLC_DLC2_MASK 0x4 #define _RXB0DLC_DLC3_POSN 0x3 #define _RXB0DLC_DLC3_POSITION 0x3 #define _RXB0DLC_DLC3_SIZE 0x1 #define _RXB0DLC_DLC3_LENGTH 0x1 #define _RXB0DLC_DLC3_MASK 0x8 #define _RXB0DLC_RB0_POSN 0x4 #define _RXB0DLC_RB0_POSITION 0x4 #define _RXB0DLC_RB0_SIZE 0x1 #define _RXB0DLC_RB0_LENGTH 0x1 #define _RXB0DLC_RB0_MASK 0x10 #define _RXB0DLC_RB1_POSN 0x5 #define _RXB0DLC_RB1_POSITION 0x5 #define _RXB0DLC_RB1_SIZE 0x1 #define _RXB0DLC_RB1_LENGTH 0x1 #define _RXB0DLC_RB1_MASK 0x20 #define _RXB0DLC_RXB0DLC0_POSN 0x0 #define _RXB0DLC_RXB0DLC0_POSITION 0x0 #define _RXB0DLC_RXB0DLC0_SIZE 0x1 #define _RXB0DLC_RXB0DLC0_LENGTH 0x1 #define _RXB0DLC_RXB0DLC0_MASK 0x1 #define _RXB0DLC_RXB0DLC1_POSN 0x1 #define _RXB0DLC_RXB0DLC1_POSITION 0x1 #define _RXB0DLC_RXB0DLC1_SIZE 0x1 #define _RXB0DLC_RXB0DLC1_LENGTH 0x1 #define _RXB0DLC_RXB0DLC1_MASK 0x2 #define _RXB0DLC_RXB0DLC2_POSN 0x2 #define _RXB0DLC_RXB0DLC2_POSITION 0x2 #define _RXB0DLC_RXB0DLC2_SIZE 0x1 #define _RXB0DLC_RXB0DLC2_LENGTH 0x1 #define _RXB0DLC_RXB0DLC2_MASK 0x4 #define _RXB0DLC_RXB0DLC3_POSN 0x3 #define _RXB0DLC_RXB0DLC3_POSITION 0x3 #define _RXB0DLC_RXB0DLC3_SIZE 0x1 #define _RXB0DLC_RXB0DLC3_LENGTH 0x1 #define _RXB0DLC_RXB0DLC3_MASK 0x8 #define _RXB0DLC_RXB0RB0_POSN 0x4 #define _RXB0DLC_RXB0RB0_POSITION 0x4 #define _RXB0DLC_RXB0RB0_SIZE 0x1 #define _RXB0DLC_RXB0RB0_LENGTH 0x1 #define _RXB0DLC_RXB0RB0_MASK 0x10 #define _RXB0DLC_RXB0RB1_POSN 0x5 #define _RXB0DLC_RXB0RB1_POSITION 0x5 #define _RXB0DLC_RXB0RB1_SIZE 0x1 #define _RXB0DLC_RXB0RB1_LENGTH 0x1 #define _RXB0DLC_RXB0RB1_MASK 0x20 #define _RXB0DLC_RXB0RTR_POSN 0x6 #define _RXB0DLC_RXB0RTR_POSITION 0x6 #define _RXB0DLC_RXB0RTR_SIZE 0x1 #define _RXB0DLC_RXB0RTR_LENGTH 0x1 #define _RXB0DLC_RXB0RTR_MASK 0x40 // Register: RXB0D0 #define RXB0D0 RXB0D0 extern volatile unsigned char RXB0D0 @ 0xF66; #ifndef _LIB_BUILD asm("RXB0D0 equ 0F66h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D0 :8; }; struct { unsigned RXB0D00 :1; unsigned RXB0D01 :1; unsigned RXB0D02 :1; unsigned RXB0D03 :1; unsigned RXB0D04 :1; unsigned RXB0D05 :1; unsigned RXB0D06 :1; unsigned RXB0D07 :1; }; } RXB0D0bits_t; extern volatile RXB0D0bits_t RXB0D0bits @ 0xF66; // bitfield macros #define _RXB0D0_RXB0D0_POSN 0x0 #define _RXB0D0_RXB0D0_POSITION 0x0 #define _RXB0D0_RXB0D0_SIZE 0x8 #define _RXB0D0_RXB0D0_LENGTH 0x8 #define _RXB0D0_RXB0D0_MASK 0xFF #define _RXB0D0_RXB0D00_POSN 0x0 #define _RXB0D0_RXB0D00_POSITION 0x0 #define _RXB0D0_RXB0D00_SIZE 0x1 #define _RXB0D0_RXB0D00_LENGTH 0x1 #define _RXB0D0_RXB0D00_MASK 0x1 #define _RXB0D0_RXB0D01_POSN 0x1 #define _RXB0D0_RXB0D01_POSITION 0x1 #define _RXB0D0_RXB0D01_SIZE 0x1 #define _RXB0D0_RXB0D01_LENGTH 0x1 #define _RXB0D0_RXB0D01_MASK 0x2 #define _RXB0D0_RXB0D02_POSN 0x2 #define _RXB0D0_RXB0D02_POSITION 0x2 #define _RXB0D0_RXB0D02_SIZE 0x1 #define _RXB0D0_RXB0D02_LENGTH 0x1 #define _RXB0D0_RXB0D02_MASK 0x4 #define _RXB0D0_RXB0D03_POSN 0x3 #define _RXB0D0_RXB0D03_POSITION 0x3 #define _RXB0D0_RXB0D03_SIZE 0x1 #define _RXB0D0_RXB0D03_LENGTH 0x1 #define _RXB0D0_RXB0D03_MASK 0x8 #define _RXB0D0_RXB0D04_POSN 0x4 #define _RXB0D0_RXB0D04_POSITION 0x4 #define _RXB0D0_RXB0D04_SIZE 0x1 #define _RXB0D0_RXB0D04_LENGTH 0x1 #define _RXB0D0_RXB0D04_MASK 0x10 #define _RXB0D0_RXB0D05_POSN 0x5 #define _RXB0D0_RXB0D05_POSITION 0x5 #define _RXB0D0_RXB0D05_SIZE 0x1 #define _RXB0D0_RXB0D05_LENGTH 0x1 #define _RXB0D0_RXB0D05_MASK 0x20 #define _RXB0D0_RXB0D06_POSN 0x6 #define _RXB0D0_RXB0D06_POSITION 0x6 #define _RXB0D0_RXB0D06_SIZE 0x1 #define _RXB0D0_RXB0D06_LENGTH 0x1 #define _RXB0D0_RXB0D06_MASK 0x40 #define _RXB0D0_RXB0D07_POSN 0x7 #define _RXB0D0_RXB0D07_POSITION 0x7 #define _RXB0D0_RXB0D07_SIZE 0x1 #define _RXB0D0_RXB0D07_LENGTH 0x1 #define _RXB0D0_RXB0D07_MASK 0x80 // Register: RXB0D1 #define RXB0D1 RXB0D1 extern volatile unsigned char RXB0D1 @ 0xF67; #ifndef _LIB_BUILD asm("RXB0D1 equ 0F67h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D1 :8; }; struct { unsigned RXB0D10 :1; unsigned RXB0D11 :1; unsigned RXB0D12 :1; unsigned RXB0D13 :1; unsigned RXB0D14 :1; unsigned RXB0D15 :1; unsigned RXB0D16 :1; unsigned RXB0D17 :1; }; } RXB0D1bits_t; extern volatile RXB0D1bits_t RXB0D1bits @ 0xF67; // bitfield macros #define _RXB0D1_RXB0D1_POSN 0x0 #define _RXB0D1_RXB0D1_POSITION 0x0 #define _RXB0D1_RXB0D1_SIZE 0x8 #define _RXB0D1_RXB0D1_LENGTH 0x8 #define _RXB0D1_RXB0D1_MASK 0xFF #define _RXB0D1_RXB0D10_POSN 0x0 #define _RXB0D1_RXB0D10_POSITION 0x0 #define _RXB0D1_RXB0D10_SIZE 0x1 #define _RXB0D1_RXB0D10_LENGTH 0x1 #define _RXB0D1_RXB0D10_MASK 0x1 #define _RXB0D1_RXB0D11_POSN 0x1 #define _RXB0D1_RXB0D11_POSITION 0x1 #define _RXB0D1_RXB0D11_SIZE 0x1 #define _RXB0D1_RXB0D11_LENGTH 0x1 #define _RXB0D1_RXB0D11_MASK 0x2 #define _RXB0D1_RXB0D12_POSN 0x2 #define _RXB0D1_RXB0D12_POSITION 0x2 #define _RXB0D1_RXB0D12_SIZE 0x1 #define _RXB0D1_RXB0D12_LENGTH 0x1 #define _RXB0D1_RXB0D12_MASK 0x4 #define _RXB0D1_RXB0D13_POSN 0x3 #define _RXB0D1_RXB0D13_POSITION 0x3 #define _RXB0D1_RXB0D13_SIZE 0x1 #define _RXB0D1_RXB0D13_LENGTH 0x1 #define _RXB0D1_RXB0D13_MASK 0x8 #define _RXB0D1_RXB0D14_POSN 0x4 #define _RXB0D1_RXB0D14_POSITION 0x4 #define _RXB0D1_RXB0D14_SIZE 0x1 #define _RXB0D1_RXB0D14_LENGTH 0x1 #define _RXB0D1_RXB0D14_MASK 0x10 #define _RXB0D1_RXB0D15_POSN 0x5 #define _RXB0D1_RXB0D15_POSITION 0x5 #define _RXB0D1_RXB0D15_SIZE 0x1 #define _RXB0D1_RXB0D15_LENGTH 0x1 #define _RXB0D1_RXB0D15_MASK 0x20 #define _RXB0D1_RXB0D16_POSN 0x6 #define _RXB0D1_RXB0D16_POSITION 0x6 #define _RXB0D1_RXB0D16_SIZE 0x1 #define _RXB0D1_RXB0D16_LENGTH 0x1 #define _RXB0D1_RXB0D16_MASK 0x40 #define _RXB0D1_RXB0D17_POSN 0x7 #define _RXB0D1_RXB0D17_POSITION 0x7 #define _RXB0D1_RXB0D17_SIZE 0x1 #define _RXB0D1_RXB0D17_LENGTH 0x1 #define _RXB0D1_RXB0D17_MASK 0x80 // Register: RXB0D2 #define RXB0D2 RXB0D2 extern volatile unsigned char RXB0D2 @ 0xF68; #ifndef _LIB_BUILD asm("RXB0D2 equ 0F68h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D2 :8; }; struct { unsigned RXB0D20 :1; unsigned RXB0D21 :1; unsigned RXB0D22 :1; unsigned RXB0D23 :1; unsigned RXB0D24 :1; unsigned RXB0D25 :1; unsigned RXB0D26 :1; unsigned RXB0D27 :1; }; } RXB0D2bits_t; extern volatile RXB0D2bits_t RXB0D2bits @ 0xF68; // bitfield macros #define _RXB0D2_RXB0D2_POSN 0x0 #define _RXB0D2_RXB0D2_POSITION 0x0 #define _RXB0D2_RXB0D2_SIZE 0x8 #define _RXB0D2_RXB0D2_LENGTH 0x8 #define _RXB0D2_RXB0D2_MASK 0xFF #define _RXB0D2_RXB0D20_POSN 0x0 #define _RXB0D2_RXB0D20_POSITION 0x0 #define _RXB0D2_RXB0D20_SIZE 0x1 #define _RXB0D2_RXB0D20_LENGTH 0x1 #define _RXB0D2_RXB0D20_MASK 0x1 #define _RXB0D2_RXB0D21_POSN 0x1 #define _RXB0D2_RXB0D21_POSITION 0x1 #define _RXB0D2_RXB0D21_SIZE 0x1 #define _RXB0D2_RXB0D21_LENGTH 0x1 #define _RXB0D2_RXB0D21_MASK 0x2 #define _RXB0D2_RXB0D22_POSN 0x2 #define _RXB0D2_RXB0D22_POSITION 0x2 #define _RXB0D2_RXB0D22_SIZE 0x1 #define _RXB0D2_RXB0D22_LENGTH 0x1 #define _RXB0D2_RXB0D22_MASK 0x4 #define _RXB0D2_RXB0D23_POSN 0x3 #define _RXB0D2_RXB0D23_POSITION 0x3 #define _RXB0D2_RXB0D23_SIZE 0x1 #define _RXB0D2_RXB0D23_LENGTH 0x1 #define _RXB0D2_RXB0D23_MASK 0x8 #define _RXB0D2_RXB0D24_POSN 0x4 #define _RXB0D2_RXB0D24_POSITION 0x4 #define _RXB0D2_RXB0D24_SIZE 0x1 #define _RXB0D2_RXB0D24_LENGTH 0x1 #define _RXB0D2_RXB0D24_MASK 0x10 #define _RXB0D2_RXB0D25_POSN 0x5 #define _RXB0D2_RXB0D25_POSITION 0x5 #define _RXB0D2_RXB0D25_SIZE 0x1 #define _RXB0D2_RXB0D25_LENGTH 0x1 #define _RXB0D2_RXB0D25_MASK 0x20 #define _RXB0D2_RXB0D26_POSN 0x6 #define _RXB0D2_RXB0D26_POSITION 0x6 #define _RXB0D2_RXB0D26_SIZE 0x1 #define _RXB0D2_RXB0D26_LENGTH 0x1 #define _RXB0D2_RXB0D26_MASK 0x40 #define _RXB0D2_RXB0D27_POSN 0x7 #define _RXB0D2_RXB0D27_POSITION 0x7 #define _RXB0D2_RXB0D27_SIZE 0x1 #define _RXB0D2_RXB0D27_LENGTH 0x1 #define _RXB0D2_RXB0D27_MASK 0x80 // Register: RXB0D3 #define RXB0D3 RXB0D3 extern volatile unsigned char RXB0D3 @ 0xF69; #ifndef _LIB_BUILD asm("RXB0D3 equ 0F69h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D3 :8; }; struct { unsigned RXB0D30 :1; unsigned RXB0D31 :1; unsigned RXB0D32 :1; unsigned RXB0D33 :1; unsigned RXB0D34 :1; unsigned RXB0D35 :1; unsigned RXB0D36 :1; unsigned RXB0D37 :1; }; } RXB0D3bits_t; extern volatile RXB0D3bits_t RXB0D3bits @ 0xF69; // bitfield macros #define _RXB0D3_RXB0D3_POSN 0x0 #define _RXB0D3_RXB0D3_POSITION 0x0 #define _RXB0D3_RXB0D3_SIZE 0x8 #define _RXB0D3_RXB0D3_LENGTH 0x8 #define _RXB0D3_RXB0D3_MASK 0xFF #define _RXB0D3_RXB0D30_POSN 0x0 #define _RXB0D3_RXB0D30_POSITION 0x0 #define _RXB0D3_RXB0D30_SIZE 0x1 #define _RXB0D3_RXB0D30_LENGTH 0x1 #define _RXB0D3_RXB0D30_MASK 0x1 #define _RXB0D3_RXB0D31_POSN 0x1 #define _RXB0D3_RXB0D31_POSITION 0x1 #define _RXB0D3_RXB0D31_SIZE 0x1 #define _RXB0D3_RXB0D31_LENGTH 0x1 #define _RXB0D3_RXB0D31_MASK 0x2 #define _RXB0D3_RXB0D32_POSN 0x2 #define _RXB0D3_RXB0D32_POSITION 0x2 #define _RXB0D3_RXB0D32_SIZE 0x1 #define _RXB0D3_RXB0D32_LENGTH 0x1 #define _RXB0D3_RXB0D32_MASK 0x4 #define _RXB0D3_RXB0D33_POSN 0x3 #define _RXB0D3_RXB0D33_POSITION 0x3 #define _RXB0D3_RXB0D33_SIZE 0x1 #define _RXB0D3_RXB0D33_LENGTH 0x1 #define _RXB0D3_RXB0D33_MASK 0x8 #define _RXB0D3_RXB0D34_POSN 0x4 #define _RXB0D3_RXB0D34_POSITION 0x4 #define _RXB0D3_RXB0D34_SIZE 0x1 #define _RXB0D3_RXB0D34_LENGTH 0x1 #define _RXB0D3_RXB0D34_MASK 0x10 #define _RXB0D3_RXB0D35_POSN 0x5 #define _RXB0D3_RXB0D35_POSITION 0x5 #define _RXB0D3_RXB0D35_SIZE 0x1 #define _RXB0D3_RXB0D35_LENGTH 0x1 #define _RXB0D3_RXB0D35_MASK 0x20 #define _RXB0D3_RXB0D36_POSN 0x6 #define _RXB0D3_RXB0D36_POSITION 0x6 #define _RXB0D3_RXB0D36_SIZE 0x1 #define _RXB0D3_RXB0D36_LENGTH 0x1 #define _RXB0D3_RXB0D36_MASK 0x40 #define _RXB0D3_RXB0D37_POSN 0x7 #define _RXB0D3_RXB0D37_POSITION 0x7 #define _RXB0D3_RXB0D37_SIZE 0x1 #define _RXB0D3_RXB0D37_LENGTH 0x1 #define _RXB0D3_RXB0D37_MASK 0x80 // Register: RXB0D4 #define RXB0D4 RXB0D4 extern volatile unsigned char RXB0D4 @ 0xF6A; #ifndef _LIB_BUILD asm("RXB0D4 equ 0F6Ah"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D4 :8; }; struct { unsigned RXB0D40 :1; unsigned RXB0D41 :1; unsigned RXB0D42 :1; unsigned RXB0D43 :1; unsigned RXB0D44 :1; unsigned RXB0D45 :1; unsigned RXB0D46 :1; unsigned RXB0D47 :1; }; } RXB0D4bits_t; extern volatile RXB0D4bits_t RXB0D4bits @ 0xF6A; // bitfield macros #define _RXB0D4_RXB0D4_POSN 0x0 #define _RXB0D4_RXB0D4_POSITION 0x0 #define _RXB0D4_RXB0D4_SIZE 0x8 #define _RXB0D4_RXB0D4_LENGTH 0x8 #define _RXB0D4_RXB0D4_MASK 0xFF #define _RXB0D4_RXB0D40_POSN 0x0 #define _RXB0D4_RXB0D40_POSITION 0x0 #define _RXB0D4_RXB0D40_SIZE 0x1 #define _RXB0D4_RXB0D40_LENGTH 0x1 #define _RXB0D4_RXB0D40_MASK 0x1 #define _RXB0D4_RXB0D41_POSN 0x1 #define _RXB0D4_RXB0D41_POSITION 0x1 #define _RXB0D4_RXB0D41_SIZE 0x1 #define _RXB0D4_RXB0D41_LENGTH 0x1 #define _RXB0D4_RXB0D41_MASK 0x2 #define _RXB0D4_RXB0D42_POSN 0x2 #define _RXB0D4_RXB0D42_POSITION 0x2 #define _RXB0D4_RXB0D42_SIZE 0x1 #define _RXB0D4_RXB0D42_LENGTH 0x1 #define _RXB0D4_RXB0D42_MASK 0x4 #define _RXB0D4_RXB0D43_POSN 0x3 #define _RXB0D4_RXB0D43_POSITION 0x3 #define _RXB0D4_RXB0D43_SIZE 0x1 #define _RXB0D4_RXB0D43_LENGTH 0x1 #define _RXB0D4_RXB0D43_MASK 0x8 #define _RXB0D4_RXB0D44_POSN 0x4 #define _RXB0D4_RXB0D44_POSITION 0x4 #define _RXB0D4_RXB0D44_SIZE 0x1 #define _RXB0D4_RXB0D44_LENGTH 0x1 #define _RXB0D4_RXB0D44_MASK 0x10 #define _RXB0D4_RXB0D45_POSN 0x5 #define _RXB0D4_RXB0D45_POSITION 0x5 #define _RXB0D4_RXB0D45_SIZE 0x1 #define _RXB0D4_RXB0D45_LENGTH 0x1 #define _RXB0D4_RXB0D45_MASK 0x20 #define _RXB0D4_RXB0D46_POSN 0x6 #define _RXB0D4_RXB0D46_POSITION 0x6 #define _RXB0D4_RXB0D46_SIZE 0x1 #define _RXB0D4_RXB0D46_LENGTH 0x1 #define _RXB0D4_RXB0D46_MASK 0x40 #define _RXB0D4_RXB0D47_POSN 0x7 #define _RXB0D4_RXB0D47_POSITION 0x7 #define _RXB0D4_RXB0D47_SIZE 0x1 #define _RXB0D4_RXB0D47_LENGTH 0x1 #define _RXB0D4_RXB0D47_MASK 0x80 // Register: RXB0D5 #define RXB0D5 RXB0D5 extern volatile unsigned char RXB0D5 @ 0xF6B; #ifndef _LIB_BUILD asm("RXB0D5 equ 0F6Bh"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D5 :8; }; struct { unsigned RXB0D50 :1; unsigned RXB0D51 :1; unsigned RXB0D52 :1; unsigned RXB0D53 :1; unsigned RXB0D54 :1; unsigned RXB0D55 :1; unsigned RXB0D56 :1; unsigned RXB0D57 :1; }; } RXB0D5bits_t; extern volatile RXB0D5bits_t RXB0D5bits @ 0xF6B; // bitfield macros #define _RXB0D5_RXB0D5_POSN 0x0 #define _RXB0D5_RXB0D5_POSITION 0x0 #define _RXB0D5_RXB0D5_SIZE 0x8 #define _RXB0D5_RXB0D5_LENGTH 0x8 #define _RXB0D5_RXB0D5_MASK 0xFF #define _RXB0D5_RXB0D50_POSN 0x0 #define _RXB0D5_RXB0D50_POSITION 0x0 #define _RXB0D5_RXB0D50_SIZE 0x1 #define _RXB0D5_RXB0D50_LENGTH 0x1 #define _RXB0D5_RXB0D50_MASK 0x1 #define _RXB0D5_RXB0D51_POSN 0x1 #define _RXB0D5_RXB0D51_POSITION 0x1 #define _RXB0D5_RXB0D51_SIZE 0x1 #define _RXB0D5_RXB0D51_LENGTH 0x1 #define _RXB0D5_RXB0D51_MASK 0x2 #define _RXB0D5_RXB0D52_POSN 0x2 #define _RXB0D5_RXB0D52_POSITION 0x2 #define _RXB0D5_RXB0D52_SIZE 0x1 #define _RXB0D5_RXB0D52_LENGTH 0x1 #define _RXB0D5_RXB0D52_MASK 0x4 #define _RXB0D5_RXB0D53_POSN 0x3 #define _RXB0D5_RXB0D53_POSITION 0x3 #define _RXB0D5_RXB0D53_SIZE 0x1 #define _RXB0D5_RXB0D53_LENGTH 0x1 #define _RXB0D5_RXB0D53_MASK 0x8 #define _RXB0D5_RXB0D54_POSN 0x4 #define _RXB0D5_RXB0D54_POSITION 0x4 #define _RXB0D5_RXB0D54_SIZE 0x1 #define _RXB0D5_RXB0D54_LENGTH 0x1 #define _RXB0D5_RXB0D54_MASK 0x10 #define _RXB0D5_RXB0D55_POSN 0x5 #define _RXB0D5_RXB0D55_POSITION 0x5 #define _RXB0D5_RXB0D55_SIZE 0x1 #define _RXB0D5_RXB0D55_LENGTH 0x1 #define _RXB0D5_RXB0D55_MASK 0x20 #define _RXB0D5_RXB0D56_POSN 0x6 #define _RXB0D5_RXB0D56_POSITION 0x6 #define _RXB0D5_RXB0D56_SIZE 0x1 #define _RXB0D5_RXB0D56_LENGTH 0x1 #define _RXB0D5_RXB0D56_MASK 0x40 #define _RXB0D5_RXB0D57_POSN 0x7 #define _RXB0D5_RXB0D57_POSITION 0x7 #define _RXB0D5_RXB0D57_SIZE 0x1 #define _RXB0D5_RXB0D57_LENGTH 0x1 #define _RXB0D5_RXB0D57_MASK 0x80 // Register: RXB0D6 #define RXB0D6 RXB0D6 extern volatile unsigned char RXB0D6 @ 0xF6C; #ifndef _LIB_BUILD asm("RXB0D6 equ 0F6Ch"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D6 :8; }; struct { unsigned RXB0D60 :1; unsigned RXB0D61 :1; unsigned RXB0D62 :1; unsigned RXB0D63 :1; unsigned RXB0D64 :1; unsigned RXB0D65 :1; unsigned RXB0D66 :1; unsigned RXB0D67 :1; }; } RXB0D6bits_t; extern volatile RXB0D6bits_t RXB0D6bits @ 0xF6C; // bitfield macros #define _RXB0D6_RXB0D6_POSN 0x0 #define _RXB0D6_RXB0D6_POSITION 0x0 #define _RXB0D6_RXB0D6_SIZE 0x8 #define _RXB0D6_RXB0D6_LENGTH 0x8 #define _RXB0D6_RXB0D6_MASK 0xFF #define _RXB0D6_RXB0D60_POSN 0x0 #define _RXB0D6_RXB0D60_POSITION 0x0 #define _RXB0D6_RXB0D60_SIZE 0x1 #define _RXB0D6_RXB0D60_LENGTH 0x1 #define _RXB0D6_RXB0D60_MASK 0x1 #define _RXB0D6_RXB0D61_POSN 0x1 #define _RXB0D6_RXB0D61_POSITION 0x1 #define _RXB0D6_RXB0D61_SIZE 0x1 #define _RXB0D6_RXB0D61_LENGTH 0x1 #define _RXB0D6_RXB0D61_MASK 0x2 #define _RXB0D6_RXB0D62_POSN 0x2 #define _RXB0D6_RXB0D62_POSITION 0x2 #define _RXB0D6_RXB0D62_SIZE 0x1 #define _RXB0D6_RXB0D62_LENGTH 0x1 #define _RXB0D6_RXB0D62_MASK 0x4 #define _RXB0D6_RXB0D63_POSN 0x3 #define _RXB0D6_RXB0D63_POSITION 0x3 #define _RXB0D6_RXB0D63_SIZE 0x1 #define _RXB0D6_RXB0D63_LENGTH 0x1 #define _RXB0D6_RXB0D63_MASK 0x8 #define _RXB0D6_RXB0D64_POSN 0x4 #define _RXB0D6_RXB0D64_POSITION 0x4 #define _RXB0D6_RXB0D64_SIZE 0x1 #define _RXB0D6_RXB0D64_LENGTH 0x1 #define _RXB0D6_RXB0D64_MASK 0x10 #define _RXB0D6_RXB0D65_POSN 0x5 #define _RXB0D6_RXB0D65_POSITION 0x5 #define _RXB0D6_RXB0D65_SIZE 0x1 #define _RXB0D6_RXB0D65_LENGTH 0x1 #define _RXB0D6_RXB0D65_MASK 0x20 #define _RXB0D6_RXB0D66_POSN 0x6 #define _RXB0D6_RXB0D66_POSITION 0x6 #define _RXB0D6_RXB0D66_SIZE 0x1 #define _RXB0D6_RXB0D66_LENGTH 0x1 #define _RXB0D6_RXB0D66_MASK 0x40 #define _RXB0D6_RXB0D67_POSN 0x7 #define _RXB0D6_RXB0D67_POSITION 0x7 #define _RXB0D6_RXB0D67_SIZE 0x1 #define _RXB0D6_RXB0D67_LENGTH 0x1 #define _RXB0D6_RXB0D67_MASK 0x80 // Register: RXB0D7 #define RXB0D7 RXB0D7 extern volatile unsigned char RXB0D7 @ 0xF6D; #ifndef _LIB_BUILD asm("RXB0D7 equ 0F6Dh"); #endif // bitfield definitions typedef union { struct { unsigned RXB0D7 :8; }; struct { unsigned RXB0D70 :1; unsigned RXB0D71 :1; unsigned RXB0D72 :1; unsigned RXB0D73 :1; unsigned RXB0D74 :1; unsigned RXB0D75 :1; unsigned RXB0D76 :1; unsigned RXB0D77 :1; }; } RXB0D7bits_t; extern volatile RXB0D7bits_t RXB0D7bits @ 0xF6D; // bitfield macros #define _RXB0D7_RXB0D7_POSN 0x0 #define _RXB0D7_RXB0D7_POSITION 0x0 #define _RXB0D7_RXB0D7_SIZE 0x8 #define _RXB0D7_RXB0D7_LENGTH 0x8 #define _RXB0D7_RXB0D7_MASK 0xFF #define _RXB0D7_RXB0D70_POSN 0x0 #define _RXB0D7_RXB0D70_POSITION 0x0 #define _RXB0D7_RXB0D70_SIZE 0x1 #define _RXB0D7_RXB0D70_LENGTH 0x1 #define _RXB0D7_RXB0D70_MASK 0x1 #define _RXB0D7_RXB0D71_POSN 0x1 #define _RXB0D7_RXB0D71_POSITION 0x1 #define _RXB0D7_RXB0D71_SIZE 0x1 #define _RXB0D7_RXB0D71_LENGTH 0x1 #define _RXB0D7_RXB0D71_MASK 0x2 #define _RXB0D7_RXB0D72_POSN 0x2 #define _RXB0D7_RXB0D72_POSITION 0x2 #define _RXB0D7_RXB0D72_SIZE 0x1 #define _RXB0D7_RXB0D72_LENGTH 0x1 #define _RXB0D7_RXB0D72_MASK 0x4 #define _RXB0D7_RXB0D73_POSN 0x3 #define _RXB0D7_RXB0D73_POSITION 0x3 #define _RXB0D7_RXB0D73_SIZE 0x1 #define _RXB0D7_RXB0D73_LENGTH 0x1 #define _RXB0D7_RXB0D73_MASK 0x8 #define _RXB0D7_RXB0D74_POSN 0x4 #define _RXB0D7_RXB0D74_POSITION 0x4 #define _RXB0D7_RXB0D74_SIZE 0x1 #define _RXB0D7_RXB0D74_LENGTH 0x1 #define _RXB0D7_RXB0D74_MASK 0x10 #define _RXB0D7_RXB0D75_POSN 0x5 #define _RXB0D7_RXB0D75_POSITION 0x5 #define _RXB0D7_RXB0D75_SIZE 0x1 #define _RXB0D7_RXB0D75_LENGTH 0x1 #define _RXB0D7_RXB0D75_MASK 0x20 #define _RXB0D7_RXB0D76_POSN 0x6 #define _RXB0D7_RXB0D76_POSITION 0x6 #define _RXB0D7_RXB0D76_SIZE 0x1 #define _RXB0D7_RXB0D76_LENGTH 0x1 #define _RXB0D7_RXB0D76_MASK 0x40 #define _RXB0D7_RXB0D77_POSN 0x7 #define _RXB0D7_RXB0D77_POSITION 0x7 #define _RXB0D7_RXB0D77_SIZE 0x1 #define _RXB0D7_RXB0D77_LENGTH 0x1 #define _RXB0D7_RXB0D77_MASK 0x80 // Register: CANSTAT #define CANSTAT CANSTAT extern volatile unsigned char CANSTAT @ 0xF6E; #ifndef _LIB_BUILD asm("CANSTAT equ 0F6Eh"); #endif // bitfield definitions typedef union { struct { unsigned EICODE0 :1; unsigned EICODE1_ICODE0 :1; unsigned EICODE2_ICODE1 :1; unsigned EICODE3_ICODE2 :1; unsigned EICODE4 :1; unsigned OPMODE :3; }; struct { unsigned :1; unsigned EICODE1 :1; unsigned EICODE2 :1; unsigned EICODE3 :1; unsigned :1; unsigned OPMODE0 :1; unsigned OPMODE1 :1; unsigned OPMODE2 :1; }; struct { unsigned :1; unsigned ICODE0 :1; unsigned ICODE1 :1; unsigned ICODE2 :1; }; } CANSTATbits_t; extern volatile CANSTATbits_t CANSTATbits @ 0xF6E; // bitfield macros #define _CANSTAT_EICODE0_POSN 0x0 #define _CANSTAT_EICODE0_POSITION 0x0 #define _CANSTAT_EICODE0_SIZE 0x1 #define _CANSTAT_EICODE0_LENGTH 0x1 #define _CANSTAT_EICODE0_MASK 0x1 #define _CANSTAT_EICODE1_ICODE0_POSN 0x1 #define _CANSTAT_EICODE1_ICODE0_POSITION 0x1 #define _CANSTAT_EICODE1_ICODE0_SIZE 0x1 #define _CANSTAT_EICODE1_ICODE0_LENGTH 0x1 #define _CANSTAT_EICODE1_ICODE0_MASK 0x2 #define _CANSTAT_EICODE2_ICODE1_POSN 0x2 #define _CANSTAT_EICODE2_ICODE1_POSITION 0x2 #define _CANSTAT_EICODE2_ICODE1_SIZE 0x1 #define _CANSTAT_EICODE2_ICODE1_LENGTH 0x1 #define _CANSTAT_EICODE2_ICODE1_MASK 0x4 #define _CANSTAT_EICODE3_ICODE2_POSN 0x3 #define _CANSTAT_EICODE3_ICODE2_POSITION 0x3 #define _CANSTAT_EICODE3_ICODE2_SIZE 0x1 #define _CANSTAT_EICODE3_ICODE2_LENGTH 0x1 #define _CANSTAT_EICODE3_ICODE2_MASK 0x8 #define _CANSTAT_EICODE4_POSN 0x4 #define _CANSTAT_EICODE4_POSITION 0x4 #define _CANSTAT_EICODE4_SIZE 0x1 #define _CANSTAT_EICODE4_LENGTH 0x1 #define _CANSTAT_EICODE4_MASK 0x10 #define _CANSTAT_OPMODE_POSN 0x5 #define _CANSTAT_OPMODE_POSITION 0x5 #define _CANSTAT_OPMODE_SIZE 0x3 #define _CANSTAT_OPMODE_LENGTH 0x3 #define _CANSTAT_OPMODE_MASK 0xE0 #define _CANSTAT_EICODE1_POSN 0x1 #define _CANSTAT_EICODE1_POSITION 0x1 #define _CANSTAT_EICODE1_SIZE 0x1 #define _CANSTAT_EICODE1_LENGTH 0x1 #define _CANSTAT_EICODE1_MASK 0x2 #define _CANSTAT_EICODE2_POSN 0x2 #define _CANSTAT_EICODE2_POSITION 0x2 #define _CANSTAT_EICODE2_SIZE 0x1 #define _CANSTAT_EICODE2_LENGTH 0x1 #define _CANSTAT_EICODE2_MASK 0x4 #define _CANSTAT_EICODE3_POSN 0x3 #define _CANSTAT_EICODE3_POSITION 0x3 #define _CANSTAT_EICODE3_SIZE 0x1 #define _CANSTAT_EICODE3_LENGTH 0x1 #define _CANSTAT_EICODE3_MASK 0x8 #define _CANSTAT_OPMODE0_POSN 0x5 #define _CANSTAT_OPMODE0_POSITION 0x5 #define _CANSTAT_OPMODE0_SIZE 0x1 #define _CANSTAT_OPMODE0_LENGTH 0x1 #define _CANSTAT_OPMODE0_MASK 0x20 #define _CANSTAT_OPMODE1_POSN 0x6 #define _CANSTAT_OPMODE1_POSITION 0x6 #define _CANSTAT_OPMODE1_SIZE 0x1 #define _CANSTAT_OPMODE1_LENGTH 0x1 #define _CANSTAT_OPMODE1_MASK 0x40 #define _CANSTAT_OPMODE2_POSN 0x7 #define _CANSTAT_OPMODE2_POSITION 0x7 #define _CANSTAT_OPMODE2_SIZE 0x1 #define _CANSTAT_OPMODE2_LENGTH 0x1 #define _CANSTAT_OPMODE2_MASK 0x80 #define _CANSTAT_ICODE0_POSN 0x1 #define _CANSTAT_ICODE0_POSITION 0x1 #define _CANSTAT_ICODE0_SIZE 0x1 #define _CANSTAT_ICODE0_LENGTH 0x1 #define _CANSTAT_ICODE0_MASK 0x2 #define _CANSTAT_ICODE1_POSN 0x2 #define _CANSTAT_ICODE1_POSITION 0x2 #define _CANSTAT_ICODE1_SIZE 0x1 #define _CANSTAT_ICODE1_LENGTH 0x1 #define _CANSTAT_ICODE1_MASK 0x4 #define _CANSTAT_ICODE2_POSN 0x3 #define _CANSTAT_ICODE2_POSITION 0x3 #define _CANSTAT_ICODE2_SIZE 0x1 #define _CANSTAT_ICODE2_LENGTH 0x1 #define _CANSTAT_ICODE2_MASK 0x8 // Register: CANCON #define CANCON CANCON extern volatile unsigned char CANCON @ 0xF6F; #ifndef _LIB_BUILD asm("CANCON equ 0F6Fh"); #endif // bitfield definitions typedef union { struct { unsigned FP0 :1; unsigned WIN0_FP1 :1; unsigned WIN1_FP2 :1; unsigned WIN2_FP3 :1; unsigned ABAT :1; unsigned REQOP :3; }; struct { unsigned :1; unsigned WIN0 :1; unsigned WIN1 :1; unsigned WIN2 :1; }; struct { unsigned :1; unsigned FP1 :1; unsigned FP2 :1; unsigned FP3 :1; }; } CANCONbits_t; extern volatile CANCONbits_t CANCONbits @ 0xF6F; // bitfield macros #define _CANCON_FP0_POSN 0x0 #define _CANCON_FP0_POSITION 0x0 #define _CANCON_FP0_SIZE 0x1 #define _CANCON_FP0_LENGTH 0x1 #define _CANCON_FP0_MASK 0x1 #define _CANCON_WIN0_FP1_POSN 0x1 #define _CANCON_WIN0_FP1_POSITION 0x1 #define _CANCON_WIN0_FP1_SIZE 0x1 #define _CANCON_WIN0_FP1_LENGTH 0x1 #define _CANCON_WIN0_FP1_MASK 0x2 #define _CANCON_WIN1_FP2_POSN 0x2 #define _CANCON_WIN1_FP2_POSITION 0x2 #define _CANCON_WIN1_FP2_SIZE 0x1 #define _CANCON_WIN1_FP2_LENGTH 0x1 #define _CANCON_WIN1_FP2_MASK 0x4 #define _CANCON_WIN2_FP3_POSN 0x3 #define _CANCON_WIN2_FP3_POSITION 0x3 #define _CANCON_WIN2_FP3_SIZE 0x1 #define _CANCON_WIN2_FP3_LENGTH 0x1 #define _CANCON_WIN2_FP3_MASK 0x8 #define _CANCON_ABAT_POSN 0x4 #define _CANCON_ABAT_POSITION 0x4 #define _CANCON_ABAT_SIZE 0x1 #define _CANCON_ABAT_LENGTH 0x1 #define _CANCON_ABAT_MASK 0x10 #define _CANCON_REQOP_POSN 0x5 #define _CANCON_REQOP_POSITION 0x5 #define _CANCON_REQOP_SIZE 0x3 #define _CANCON_REQOP_LENGTH 0x3 #define _CANCON_REQOP_MASK 0xE0 #define _CANCON_WIN0_POSN 0x1 #define _CANCON_WIN0_POSITION 0x1 #define _CANCON_WIN0_SIZE 0x1 #define _CANCON_WIN0_LENGTH 0x1 #define _CANCON_WIN0_MASK 0x2 #define _CANCON_WIN1_POSN 0x2 #define _CANCON_WIN1_POSITION 0x2 #define _CANCON_WIN1_SIZE 0x1 #define _CANCON_WIN1_LENGTH 0x1 #define _CANCON_WIN1_MASK 0x4 #define _CANCON_WIN2_POSN 0x3 #define _CANCON_WIN2_POSITION 0x3 #define _CANCON_WIN2_SIZE 0x1 #define _CANCON_WIN2_LENGTH 0x1 #define _CANCON_WIN2_MASK 0x8 #define _CANCON_FP1_POSN 0x1 #define _CANCON_FP1_POSITION 0x1 #define _CANCON_FP1_SIZE 0x1 #define _CANCON_FP1_LENGTH 0x1 #define _CANCON_FP1_MASK 0x2 #define _CANCON_FP2_POSN 0x2 #define _CANCON_FP2_POSITION 0x2 #define _CANCON_FP2_SIZE 0x1 #define _CANCON_FP2_LENGTH 0x1 #define _CANCON_FP2_MASK 0x4 #define _CANCON_FP3_POSN 0x3 #define _CANCON_FP3_POSITION 0x3 #define _CANCON_FP3_SIZE 0x1 #define _CANCON_FP3_LENGTH 0x1 #define _CANCON_FP3_MASK 0x8 // Register: CIOCON #define CIOCON CIOCON extern volatile unsigned char CIOCON @ 0xF70; #ifndef _LIB_BUILD asm("CIOCON equ 0F70h"); #endif // bitfield definitions typedef union { struct { unsigned CLKSEL :1; unsigned :3; unsigned CANCAP :1; unsigned ENDRHI :1; unsigned TX2EN :1; unsigned TX2SRC :1; }; } CIOCONbits_t; extern volatile CIOCONbits_t CIOCONbits @ 0xF70; // bitfield macros #define _CIOCON_CLKSEL_POSN 0x0 #define _CIOCON_CLKSEL_POSITION 0x0 #define _CIOCON_CLKSEL_SIZE 0x1 #define _CIOCON_CLKSEL_LENGTH 0x1 #define _CIOCON_CLKSEL_MASK 0x1 #define _CIOCON_CANCAP_POSN 0x4 #define _CIOCON_CANCAP_POSITION 0x4 #define _CIOCON_CANCAP_SIZE 0x1 #define _CIOCON_CANCAP_LENGTH 0x1 #define _CIOCON_CANCAP_MASK 0x10 #define _CIOCON_ENDRHI_POSN 0x5 #define _CIOCON_ENDRHI_POSITION 0x5 #define _CIOCON_ENDRHI_SIZE 0x1 #define _CIOCON_ENDRHI_LENGTH 0x1 #define _CIOCON_ENDRHI_MASK 0x20 #define _CIOCON_TX2EN_POSN 0x6 #define _CIOCON_TX2EN_POSITION 0x6 #define _CIOCON_TX2EN_SIZE 0x1 #define _CIOCON_TX2EN_LENGTH 0x1 #define _CIOCON_TX2EN_MASK 0x40 #define _CIOCON_TX2SRC_POSN 0x7 #define _CIOCON_TX2SRC_POSITION 0x7 #define _CIOCON_TX2SRC_SIZE 0x1 #define _CIOCON_TX2SRC_LENGTH 0x1 #define _CIOCON_TX2SRC_MASK 0x80 // Register: COMSTAT #define COMSTAT COMSTAT extern volatile unsigned char COMSTAT @ 0xF71; #ifndef _LIB_BUILD asm("COMSTAT equ 0F71h"); #endif // bitfield definitions typedef union { struct { unsigned EWARN :1; unsigned RXWARN :1; unsigned TXWARN :1; unsigned RXBP :1; unsigned TXBP :1; unsigned TXBO :1; unsigned RXB1OVFL :1; unsigned RXB0OVFL :1; }; struct { unsigned :7; unsigned NOT_FIFOEMPTY :1; }; struct { unsigned :7; unsigned nFIFOEMPTY :1; }; struct { unsigned :6; unsigned RXBNOVFL :1; unsigned FIFOEMPTY :1; }; } COMSTATbits_t; extern volatile COMSTATbits_t COMSTATbits @ 0xF71; // bitfield macros #define _COMSTAT_EWARN_POSN 0x0 #define _COMSTAT_EWARN_POSITION 0x0 #define _COMSTAT_EWARN_SIZE 0x1 #define _COMSTAT_EWARN_LENGTH 0x1 #define _COMSTAT_EWARN_MASK 0x1 #define _COMSTAT_RXWARN_POSN 0x1 #define _COMSTAT_RXWARN_POSITION 0x1 #define _COMSTAT_RXWARN_SIZE 0x1 #define _COMSTAT_RXWARN_LENGTH 0x1 #define _COMSTAT_RXWARN_MASK 0x2 #define _COMSTAT_TXWARN_POSN 0x2 #define _COMSTAT_TXWARN_POSITION 0x2 #define _COMSTAT_TXWARN_SIZE 0x1 #define _COMSTAT_TXWARN_LENGTH 0x1 #define _COMSTAT_TXWARN_MASK 0x4 #define _COMSTAT_RXBP_POSN 0x3 #define _COMSTAT_RXBP_POSITION 0x3 #define _COMSTAT_RXBP_SIZE 0x1 #define _COMSTAT_RXBP_LENGTH 0x1 #define _COMSTAT_RXBP_MASK 0x8 #define _COMSTAT_TXBP_POSN 0x4 #define _COMSTAT_TXBP_POSITION 0x4 #define _COMSTAT_TXBP_SIZE 0x1 #define _COMSTAT_TXBP_LENGTH 0x1 #define _COMSTAT_TXBP_MASK 0x10 #define _COMSTAT_TXBO_POSN 0x5 #define _COMSTAT_TXBO_POSITION 0x5 #define _COMSTAT_TXBO_SIZE 0x1 #define _COMSTAT_TXBO_LENGTH 0x1 #define _COMSTAT_TXBO_MASK 0x20 #define _COMSTAT_RXB1OVFL_POSN 0x6 #define _COMSTAT_RXB1OVFL_POSITION 0x6 #define _COMSTAT_RXB1OVFL_SIZE 0x1 #define _COMSTAT_RXB1OVFL_LENGTH 0x1 #define _COMSTAT_RXB1OVFL_MASK 0x40 #define _COMSTAT_RXB0OVFL_POSN 0x7 #define _COMSTAT_RXB0OVFL_POSITION 0x7 #define _COMSTAT_RXB0OVFL_SIZE 0x1 #define _COMSTAT_RXB0OVFL_LENGTH 0x1 #define _COMSTAT_RXB0OVFL_MASK 0x80 #define _COMSTAT_NOT_FIFOEMPTY_POSN 0x7 #define _COMSTAT_NOT_FIFOEMPTY_POSITION 0x7 #define _COMSTAT_NOT_FIFOEMPTY_SIZE 0x1 #define _COMSTAT_NOT_FIFOEMPTY_LENGTH 0x1 #define _COMSTAT_NOT_FIFOEMPTY_MASK 0x80 #define _COMSTAT_nFIFOEMPTY_POSN 0x7 #define _COMSTAT_nFIFOEMPTY_POSITION 0x7 #define _COMSTAT_nFIFOEMPTY_SIZE 0x1 #define _COMSTAT_nFIFOEMPTY_LENGTH 0x1 #define _COMSTAT_nFIFOEMPTY_MASK 0x80 #define _COMSTAT_RXBNOVFL_POSN 0x6 #define _COMSTAT_RXBNOVFL_POSITION 0x6 #define _COMSTAT_RXBNOVFL_SIZE 0x1 #define _COMSTAT_RXBNOVFL_LENGTH 0x1 #define _COMSTAT_RXBNOVFL_MASK 0x40 #define _COMSTAT_FIFOEMPTY_POSN 0x7 #define _COMSTAT_FIFOEMPTY_POSITION 0x7 #define _COMSTAT_FIFOEMPTY_SIZE 0x1 #define _COMSTAT_FIFOEMPTY_LENGTH 0x1 #define _COMSTAT_FIFOEMPTY_MASK 0x80 // Register: ECANCON #define ECANCON ECANCON extern volatile unsigned char ECANCON @ 0xF72; #ifndef _LIB_BUILD asm("ECANCON equ 0F72h"); #endif // bitfield definitions typedef union { struct { unsigned EWIN :5; unsigned FIFOWM :1; unsigned MDSEL :2; }; struct { unsigned EWIN0 :1; unsigned EWIN1 :1; unsigned EWIN2 :1; unsigned EWIN3 :1; unsigned EWIN4 :1; unsigned :1; unsigned MDSEL0 :1; unsigned MDSEL1 :1; }; } ECANCONbits_t; extern volatile ECANCONbits_t ECANCONbits @ 0xF72; // bitfield macros #define _ECANCON_EWIN_POSN 0x0 #define _ECANCON_EWIN_POSITION 0x0 #define _ECANCON_EWIN_SIZE 0x5 #define _ECANCON_EWIN_LENGTH 0x5 #define _ECANCON_EWIN_MASK 0x1F #define _ECANCON_FIFOWM_POSN 0x5 #define _ECANCON_FIFOWM_POSITION 0x5 #define _ECANCON_FIFOWM_SIZE 0x1 #define _ECANCON_FIFOWM_LENGTH 0x1 #define _ECANCON_FIFOWM_MASK 0x20 #define _ECANCON_MDSEL_POSN 0x6 #define _ECANCON_MDSEL_POSITION 0x6 #define _ECANCON_MDSEL_SIZE 0x2 #define _ECANCON_MDSEL_LENGTH 0x2 #define _ECANCON_MDSEL_MASK 0xC0 #define _ECANCON_EWIN0_POSN 0x0 #define _ECANCON_EWIN0_POSITION 0x0 #define _ECANCON_EWIN0_SIZE 0x1 #define _ECANCON_EWIN0_LENGTH 0x1 #define _ECANCON_EWIN0_MASK 0x1 #define _ECANCON_EWIN1_POSN 0x1 #define _ECANCON_EWIN1_POSITION 0x1 #define _ECANCON_EWIN1_SIZE 0x1 #define _ECANCON_EWIN1_LENGTH 0x1 #define _ECANCON_EWIN1_MASK 0x2 #define _ECANCON_EWIN2_POSN 0x2 #define _ECANCON_EWIN2_POSITION 0x2 #define _ECANCON_EWIN2_SIZE 0x1 #define _ECANCON_EWIN2_LENGTH 0x1 #define _ECANCON_EWIN2_MASK 0x4 #define _ECANCON_EWIN3_POSN 0x3 #define _ECANCON_EWIN3_POSITION 0x3 #define _ECANCON_EWIN3_SIZE 0x1 #define _ECANCON_EWIN3_LENGTH 0x1 #define _ECANCON_EWIN3_MASK 0x8 #define _ECANCON_EWIN4_POSN 0x4 #define _ECANCON_EWIN4_POSITION 0x4 #define _ECANCON_EWIN4_SIZE 0x1 #define _ECANCON_EWIN4_LENGTH 0x1 #define _ECANCON_EWIN4_MASK 0x10 #define _ECANCON_MDSEL0_POSN 0x6 #define _ECANCON_MDSEL0_POSITION 0x6 #define _ECANCON_MDSEL0_SIZE 0x1 #define _ECANCON_MDSEL0_LENGTH 0x1 #define _ECANCON_MDSEL0_MASK 0x40 #define _ECANCON_MDSEL1_POSN 0x7 #define _ECANCON_MDSEL1_POSITION 0x7 #define _ECANCON_MDSEL1_SIZE 0x1 #define _ECANCON_MDSEL1_LENGTH 0x1 #define _ECANCON_MDSEL1_MASK 0x80 // Register: EEDATA #define EEDATA EEDATA extern volatile unsigned char EEDATA @ 0xF73; #ifndef _LIB_BUILD asm("EEDATA equ 0F73h"); #endif // bitfield definitions typedef union { struct { unsigned EEDATA :8; }; } EEDATAbits_t; extern volatile EEDATAbits_t EEDATAbits @ 0xF73; // bitfield macros #define _EEDATA_EEDATA_POSN 0x0 #define _EEDATA_EEDATA_POSITION 0x0 #define _EEDATA_EEDATA_SIZE 0x8 #define _EEDATA_EEDATA_LENGTH 0x8 #define _EEDATA_EEDATA_MASK 0xFF // Register: EEADR #define EEADR EEADR extern volatile unsigned char EEADR @ 0xF74; #ifndef _LIB_BUILD asm("EEADR equ 0F74h"); #endif // bitfield definitions typedef union { struct { unsigned EEADR :8; }; } EEADRbits_t; extern volatile EEADRbits_t EEADRbits @ 0xF74; // bitfield macros #define _EEADR_EEADR_POSN 0x0 #define _EEADR_EEADR_POSITION 0x0 #define _EEADR_EEADR_SIZE 0x8 #define _EEADR_EEADR_LENGTH 0x8 #define _EEADR_EEADR_MASK 0xFF // Register: EEADRH #define EEADRH EEADRH extern volatile unsigned char EEADRH @ 0xF75; #ifndef _LIB_BUILD asm("EEADRH equ 0F75h"); #endif // bitfield definitions typedef union { struct { unsigned EEADRH :8; }; } EEADRHbits_t; extern volatile EEADRHbits_t EEADRHbits @ 0xF75; // bitfield macros #define _EEADRH_EEADRH_POSN 0x0 #define _EEADRH_EEADRH_POSITION 0x0 #define _EEADRH_EEADRH_SIZE 0x8 #define _EEADRH_EEADRH_LENGTH 0x8 #define _EEADRH_EEADRH_MASK 0xFF // Register: PIE5 #define PIE5 PIE5 extern volatile unsigned char PIE5 @ 0xF76; #ifndef _LIB_BUILD asm("PIE5 equ 0F76h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0IE :1; unsigned RXB1IE :1; unsigned TXB0IE :1; unsigned TXB1IE :1; unsigned TXB2IE :1; unsigned ERRIE :1; unsigned WAKIE :1; unsigned IRXIE :1; }; struct { unsigned FIFOWMIE :1; unsigned RXBnIE :1; unsigned :2; unsigned TXBnIE :1; }; } PIE5bits_t; extern volatile PIE5bits_t PIE5bits @ 0xF76; // bitfield macros #define _PIE5_RXB0IE_POSN 0x0 #define _PIE5_RXB0IE_POSITION 0x0 #define _PIE5_RXB0IE_SIZE 0x1 #define _PIE5_RXB0IE_LENGTH 0x1 #define _PIE5_RXB0IE_MASK 0x1 #define _PIE5_RXB1IE_POSN 0x1 #define _PIE5_RXB1IE_POSITION 0x1 #define _PIE5_RXB1IE_SIZE 0x1 #define _PIE5_RXB1IE_LENGTH 0x1 #define _PIE5_RXB1IE_MASK 0x2 #define _PIE5_TXB0IE_POSN 0x2 #define _PIE5_TXB0IE_POSITION 0x2 #define _PIE5_TXB0IE_SIZE 0x1 #define _PIE5_TXB0IE_LENGTH 0x1 #define _PIE5_TXB0IE_MASK 0x4 #define _PIE5_TXB1IE_POSN 0x3 #define _PIE5_TXB1IE_POSITION 0x3 #define _PIE5_TXB1IE_SIZE 0x1 #define _PIE5_TXB1IE_LENGTH 0x1 #define _PIE5_TXB1IE_MASK 0x8 #define _PIE5_TXB2IE_POSN 0x4 #define _PIE5_TXB2IE_POSITION 0x4 #define _PIE5_TXB2IE_SIZE 0x1 #define _PIE5_TXB2IE_LENGTH 0x1 #define _PIE5_TXB2IE_MASK 0x10 #define _PIE5_ERRIE_POSN 0x5 #define _PIE5_ERRIE_POSITION 0x5 #define _PIE5_ERRIE_SIZE 0x1 #define _PIE5_ERRIE_LENGTH 0x1 #define _PIE5_ERRIE_MASK 0x20 #define _PIE5_WAKIE_POSN 0x6 #define _PIE5_WAKIE_POSITION 0x6 #define _PIE5_WAKIE_SIZE 0x1 #define _PIE5_WAKIE_LENGTH 0x1 #define _PIE5_WAKIE_MASK 0x40 #define _PIE5_IRXIE_POSN 0x7 #define _PIE5_IRXIE_POSITION 0x7 #define _PIE5_IRXIE_SIZE 0x1 #define _PIE5_IRXIE_LENGTH 0x1 #define _PIE5_IRXIE_MASK 0x80 #define _PIE5_FIFOWMIE_POSN 0x0 #define _PIE5_FIFOWMIE_POSITION 0x0 #define _PIE5_FIFOWMIE_SIZE 0x1 #define _PIE5_FIFOWMIE_LENGTH 0x1 #define _PIE5_FIFOWMIE_MASK 0x1 #define _PIE5_RXBnIE_POSN 0x1 #define _PIE5_RXBnIE_POSITION 0x1 #define _PIE5_RXBnIE_SIZE 0x1 #define _PIE5_RXBnIE_LENGTH 0x1 #define _PIE5_RXBnIE_MASK 0x2 #define _PIE5_TXBnIE_POSN 0x4 #define _PIE5_TXBnIE_POSITION 0x4 #define _PIE5_TXBnIE_SIZE 0x1 #define _PIE5_TXBnIE_LENGTH 0x1 #define _PIE5_TXBnIE_MASK 0x10 // Register: PIR5 #define PIR5 PIR5 extern volatile unsigned char PIR5 @ 0xF77; #ifndef _LIB_BUILD asm("PIR5 equ 0F77h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0IF :1; unsigned RXB1IF :1; unsigned TXB0IF :1; unsigned TXB1IF :1; unsigned TXB2IF :1; unsigned ERRIF :1; unsigned WAKIF :1; unsigned IRXIF :1; }; struct { unsigned FIFOWMIF :1; unsigned RXBnIF :1; unsigned :2; unsigned TXBnIF :1; }; } PIR5bits_t; extern volatile PIR5bits_t PIR5bits @ 0xF77; // bitfield macros #define _PIR5_RXB0IF_POSN 0x0 #define _PIR5_RXB0IF_POSITION 0x0 #define _PIR5_RXB0IF_SIZE 0x1 #define _PIR5_RXB0IF_LENGTH 0x1 #define _PIR5_RXB0IF_MASK 0x1 #define _PIR5_RXB1IF_POSN 0x1 #define _PIR5_RXB1IF_POSITION 0x1 #define _PIR5_RXB1IF_SIZE 0x1 #define _PIR5_RXB1IF_LENGTH 0x1 #define _PIR5_RXB1IF_MASK 0x2 #define _PIR5_TXB0IF_POSN 0x2 #define _PIR5_TXB0IF_POSITION 0x2 #define _PIR5_TXB0IF_SIZE 0x1 #define _PIR5_TXB0IF_LENGTH 0x1 #define _PIR5_TXB0IF_MASK 0x4 #define _PIR5_TXB1IF_POSN 0x3 #define _PIR5_TXB1IF_POSITION 0x3 #define _PIR5_TXB1IF_SIZE 0x1 #define _PIR5_TXB1IF_LENGTH 0x1 #define _PIR5_TXB1IF_MASK 0x8 #define _PIR5_TXB2IF_POSN 0x4 #define _PIR5_TXB2IF_POSITION 0x4 #define _PIR5_TXB2IF_SIZE 0x1 #define _PIR5_TXB2IF_LENGTH 0x1 #define _PIR5_TXB2IF_MASK 0x10 #define _PIR5_ERRIF_POSN 0x5 #define _PIR5_ERRIF_POSITION 0x5 #define _PIR5_ERRIF_SIZE 0x1 #define _PIR5_ERRIF_LENGTH 0x1 #define _PIR5_ERRIF_MASK 0x20 #define _PIR5_WAKIF_POSN 0x6 #define _PIR5_WAKIF_POSITION 0x6 #define _PIR5_WAKIF_SIZE 0x1 #define _PIR5_WAKIF_LENGTH 0x1 #define _PIR5_WAKIF_MASK 0x40 #define _PIR5_IRXIF_POSN 0x7 #define _PIR5_IRXIF_POSITION 0x7 #define _PIR5_IRXIF_SIZE 0x1 #define _PIR5_IRXIF_LENGTH 0x1 #define _PIR5_IRXIF_MASK 0x80 #define _PIR5_FIFOWMIF_POSN 0x0 #define _PIR5_FIFOWMIF_POSITION 0x0 #define _PIR5_FIFOWMIF_SIZE 0x1 #define _PIR5_FIFOWMIF_LENGTH 0x1 #define _PIR5_FIFOWMIF_MASK 0x1 #define _PIR5_RXBnIF_POSN 0x1 #define _PIR5_RXBnIF_POSITION 0x1 #define _PIR5_RXBnIF_SIZE 0x1 #define _PIR5_RXBnIF_LENGTH 0x1 #define _PIR5_RXBnIF_MASK 0x2 #define _PIR5_TXBnIF_POSN 0x4 #define _PIR5_TXBnIF_POSITION 0x4 #define _PIR5_TXBnIF_SIZE 0x1 #define _PIR5_TXBnIF_LENGTH 0x1 #define _PIR5_TXBnIF_MASK 0x10 // Register: IPR5 #define IPR5 IPR5 extern volatile unsigned char IPR5 @ 0xF78; #ifndef _LIB_BUILD asm("IPR5 equ 0F78h"); #endif // bitfield definitions typedef union { struct { unsigned RXB0IP :1; unsigned RXB1IP :1; unsigned TXB0IP :1; unsigned TXB1IP :1; unsigned TXB2IP :1; unsigned ERRIP :1; unsigned WAKIP :1; unsigned IRXIP :1; }; struct { unsigned FIFOWMIP :1; unsigned RXBnIP :1; unsigned :2; unsigned TXBnIP :1; }; struct { unsigned CCH05 :1; unsigned CCH15 :1; unsigned :1; unsigned EVPOL05 :1; unsigned EVPOL15 :1; }; } IPR5bits_t; extern volatile IPR5bits_t IPR5bits @ 0xF78; // bitfield macros #define _IPR5_RXB0IP_POSN 0x0 #define _IPR5_RXB0IP_POSITION 0x0 #define _IPR5_RXB0IP_SIZE 0x1 #define _IPR5_RXB0IP_LENGTH 0x1 #define _IPR5_RXB0IP_MASK 0x1 #define _IPR5_RXB1IP_POSN 0x1 #define _IPR5_RXB1IP_POSITION 0x1 #define _IPR5_RXB1IP_SIZE 0x1 #define _IPR5_RXB1IP_LENGTH 0x1 #define _IPR5_RXB1IP_MASK 0x2 #define _IPR5_TXB0IP_POSN 0x2 #define _IPR5_TXB0IP_POSITION 0x2 #define _IPR5_TXB0IP_SIZE 0x1 #define _IPR5_TXB0IP_LENGTH 0x1 #define _IPR5_TXB0IP_MASK 0x4 #define _IPR5_TXB1IP_POSN 0x3 #define _IPR5_TXB1IP_POSITION 0x3 #define _IPR5_TXB1IP_SIZE 0x1 #define _IPR5_TXB1IP_LENGTH 0x1 #define _IPR5_TXB1IP_MASK 0x8 #define _IPR5_TXB2IP_POSN 0x4 #define _IPR5_TXB2IP_POSITION 0x4 #define _IPR5_TXB2IP_SIZE 0x1 #define _IPR5_TXB2IP_LENGTH 0x1 #define _IPR5_TXB2IP_MASK 0x10 #define _IPR5_ERRIP_POSN 0x5 #define _IPR5_ERRIP_POSITION 0x5 #define _IPR5_ERRIP_SIZE 0x1 #define _IPR5_ERRIP_LENGTH 0x1 #define _IPR5_ERRIP_MASK 0x20 #define _IPR5_WAKIP_POSN 0x6 #define _IPR5_WAKIP_POSITION 0x6 #define _IPR5_WAKIP_SIZE 0x1 #define _IPR5_WAKIP_LENGTH 0x1 #define _IPR5_WAKIP_MASK 0x40 #define _IPR5_IRXIP_POSN 0x7 #define _IPR5_IRXIP_POSITION 0x7 #define _IPR5_IRXIP_SIZE 0x1 #define _IPR5_IRXIP_LENGTH 0x1 #define _IPR5_IRXIP_MASK 0x80 #define _IPR5_FIFOWMIP_POSN 0x0 #define _IPR5_FIFOWMIP_POSITION 0x0 #define _IPR5_FIFOWMIP_SIZE 0x1 #define _IPR5_FIFOWMIP_LENGTH 0x1 #define _IPR5_FIFOWMIP_MASK 0x1 #define _IPR5_RXBnIP_POSN 0x1 #define _IPR5_RXBnIP_POSITION 0x1 #define _IPR5_RXBnIP_SIZE 0x1 #define _IPR5_RXBnIP_LENGTH 0x1 #define _IPR5_RXBnIP_MASK 0x2 #define _IPR5_TXBnIP_POSN 0x4 #define _IPR5_TXBnIP_POSITION 0x4 #define _IPR5_TXBnIP_SIZE 0x1 #define _IPR5_TXBnIP_LENGTH 0x1 #define _IPR5_TXBnIP_MASK 0x10 #define _IPR5_CCH05_POSN 0x0 #define _IPR5_CCH05_POSITION 0x0 #define _IPR5_CCH05_SIZE 0x1 #define _IPR5_CCH05_LENGTH 0x1 #define _IPR5_CCH05_MASK 0x1 #define _IPR5_CCH15_POSN 0x1 #define _IPR5_CCH15_POSITION 0x1 #define _IPR5_CCH15_SIZE 0x1 #define _IPR5_CCH15_LENGTH 0x1 #define _IPR5_CCH15_MASK 0x2 #define _IPR5_EVPOL05_POSN 0x3 #define _IPR5_EVPOL05_POSITION 0x3 #define _IPR5_EVPOL05_SIZE 0x1 #define _IPR5_EVPOL05_LENGTH 0x1 #define _IPR5_EVPOL05_MASK 0x8 #define _IPR5_EVPOL15_POSN 0x4 #define _IPR5_EVPOL15_POSITION 0x4 #define _IPR5_EVPOL15_SIZE 0x1 #define _IPR5_EVPOL15_LENGTH 0x1 #define _IPR5_EVPOL15_MASK 0x10 // Register: TXREG2 #define TXREG2 TXREG2 extern volatile unsigned char TXREG2 @ 0xF79; #ifndef _LIB_BUILD asm("TXREG2 equ 0F79h"); #endif // bitfield definitions typedef union { struct { unsigned TXREG2 :8; }; } TXREG2bits_t; extern volatile TXREG2bits_t TXREG2bits @ 0xF79; // bitfield macros #define _TXREG2_TXREG2_POSN 0x0 #define _TXREG2_TXREG2_POSITION 0x0 #define _TXREG2_TXREG2_SIZE 0x8 #define _TXREG2_TXREG2_LENGTH 0x8 #define _TXREG2_TXREG2_MASK 0xFF // Register: RCREG2 #define RCREG2 RCREG2 extern volatile unsigned char RCREG2 @ 0xF7A; #ifndef _LIB_BUILD asm("RCREG2 equ 0F7Ah"); #endif // bitfield definitions typedef union { struct { unsigned RCREG2 :8; }; } RCREG2bits_t; extern volatile RCREG2bits_t RCREG2bits @ 0xF7A; // bitfield macros #define _RCREG2_RCREG2_POSN 0x0 #define _RCREG2_RCREG2_POSITION 0x0 #define _RCREG2_RCREG2_SIZE 0x8 #define _RCREG2_RCREG2_LENGTH 0x8 #define _RCREG2_RCREG2_MASK 0xFF // Register: SPBRG2 #define SPBRG2 SPBRG2 extern volatile unsigned char SPBRG2 @ 0xF7B; #ifndef _LIB_BUILD asm("SPBRG2 equ 0F7Bh"); #endif // bitfield definitions typedef union { struct { unsigned SPBRG2 :8; }; } SPBRG2bits_t; extern volatile SPBRG2bits_t SPBRG2bits @ 0xF7B; // bitfield macros #define _SPBRG2_SPBRG2_POSN 0x0 #define _SPBRG2_SPBRG2_POSITION 0x0 #define _SPBRG2_SPBRG2_SIZE 0x8 #define _SPBRG2_SPBRG2_LENGTH 0x8 #define _SPBRG2_SPBRG2_MASK 0xFF // Register: SPBRGH2 #define SPBRGH2 SPBRGH2 extern volatile unsigned char SPBRGH2 @ 0xF7C; #ifndef _LIB_BUILD asm("SPBRGH2 equ 0F7Ch"); #endif // bitfield definitions typedef union { struct { unsigned SPBRGH2 :8; }; } SPBRGH2bits_t; extern volatile SPBRGH2bits_t SPBRGH2bits @ 0xF7C; // bitfield macros #define _SPBRGH2_SPBRGH2_POSN 0x0 #define _SPBRGH2_SPBRGH2_POSITION 0x0 #define _SPBRGH2_SPBRGH2_SIZE 0x8 #define _SPBRGH2_SPBRGH2_LENGTH 0x8 #define _SPBRGH2_SPBRGH2_MASK 0xFF // Register: SPBRGH1 #define SPBRGH1 SPBRGH1 extern volatile unsigned char SPBRGH1 @ 0xF7D; #ifndef _LIB_BUILD asm("SPBRGH1 equ 0F7Dh"); #endif // bitfield definitions typedef union { struct { unsigned SPBRGH1 :8; }; } SPBRGH1bits_t; extern volatile SPBRGH1bits_t SPBRGH1bits @ 0xF7D; // bitfield macros #define _SPBRGH1_SPBRGH1_POSN 0x0 #define _SPBRGH1_SPBRGH1_POSITION 0x0 #define _SPBRGH1_SPBRGH1_SIZE 0x8 #define _SPBRGH1_SPBRGH1_LENGTH 0x8 #define _SPBRGH1_SPBRGH1_MASK 0xFF // Register: EECON2 #define EECON2 EECON2 extern volatile unsigned char EECON2 @ 0xF7E; #ifndef _LIB_BUILD asm("EECON2 equ 0F7Eh"); #endif // bitfield definitions typedef union { struct { unsigned EECON2 :8; }; } EECON2bits_t; extern volatile EECON2bits_t EECON2bits @ 0xF7E; // bitfield macros #define _EECON2_EECON2_POSN 0x0 #define _EECON2_EECON2_POSITION 0x0 #define _EECON2_EECON2_SIZE 0x8 #define _EECON2_EECON2_LENGTH 0x8 #define _EECON2_EECON2_MASK 0xFF // Register: EECON1 #define EECON1 EECON1 extern volatile unsigned char EECON1 @ 0xF7F; #ifndef _LIB_BUILD asm("EECON1 equ 0F7Fh"); #endif // bitfield definitions typedef union { struct { unsigned RD :1; unsigned WR :1; unsigned WREN :1; unsigned WRERR :1; unsigned FREE :1; unsigned :1; unsigned CFGS :1; unsigned EEPGD :1; }; struct { unsigned :6; unsigned EEFS :1; }; } EECON1bits_t; extern volatile EECON1bits_t EECON1bits @ 0xF7F; // bitfield macros #define _EECON1_RD_POSN 0x0 #define _EECON1_RD_POSITION 0x0 #define _EECON1_RD_SIZE 0x1 #define _EECON1_RD_LENGTH 0x1 #define _EECON1_RD_MASK 0x1 #define _EECON1_WR_POSN 0x1 #define _EECON1_WR_POSITION 0x1 #define _EECON1_WR_SIZE 0x1 #define _EECON1_WR_LENGTH 0x1 #define _EECON1_WR_MASK 0x2 #define _EECON1_WREN_POSN 0x2 #define _EECON1_WREN_POSITION 0x2 #define _EECON1_WREN_SIZE 0x1 #define _EECON1_WREN_LENGTH 0x1 #define _EECON1_WREN_MASK 0x4 #define _EECON1_WRERR_POSN 0x3 #define _EECON1_WRERR_POSITION 0x3 #define _EECON1_WRERR_SIZE 0x1 #define _EECON1_WRERR_LENGTH 0x1 #define _EECON1_WRERR_MASK 0x8 #define _EECON1_FREE_POSN 0x4 #define _EECON1_FREE_POSITION 0x4 #define _EECON1_FREE_SIZE 0x1 #define _EECON1_FREE_LENGTH 0x1 #define _EECON1_FREE_MASK 0x10 #define _EECON1_CFGS_POSN 0x6 #define _EECON1_CFGS_POSITION 0x6 #define _EECON1_CFGS_SIZE 0x1 #define _EECON1_CFGS_LENGTH 0x1 #define _EECON1_CFGS_MASK 0x40 #define _EECON1_EEPGD_POSN 0x7 #define _EECON1_EEPGD_POSITION 0x7 #define _EECON1_EEPGD_SIZE 0x1 #define _EECON1_EEPGD_LENGTH 0x1 #define _EECON1_EEPGD_MASK 0x80 #define _EECON1_EEFS_POSN 0x6 #define _EECON1_EEFS_POSITION 0x6 #define _EECON1_EEFS_SIZE 0x1 #define _EECON1_EEFS_LENGTH 0x1 #define _EECON1_EEFS_MASK 0x40 // Register: PORTA #define PORTA PORTA extern volatile unsigned char PORTA @ 0xF80; #ifndef _LIB_BUILD asm("PORTA equ 0F80h"); #endif // bitfield definitions typedef union { struct { unsigned RA0 :1; unsigned RA1 :1; unsigned RA2 :1; unsigned RA3 :1; unsigned :1; unsigned RA5 :1; unsigned RA6 :1; unsigned RA7 :1; }; struct { unsigned ULPWUIN :1; unsigned :4; unsigned LVDIN :1; unsigned :1; unsigned RJPU :1; }; } PORTAbits_t; extern volatile PORTAbits_t PORTAbits @ 0xF80; // bitfield macros #define _PORTA_RA0_POSN 0x0 #define _PORTA_RA0_POSITION 0x0 #define _PORTA_RA0_SIZE 0x1 #define _PORTA_RA0_LENGTH 0x1 #define _PORTA_RA0_MASK 0x1 #define _PORTA_RA1_POSN 0x1 #define _PORTA_RA1_POSITION 0x1 #define _PORTA_RA1_SIZE 0x1 #define _PORTA_RA1_LENGTH 0x1 #define _PORTA_RA1_MASK 0x2 #define _PORTA_RA2_POSN 0x2 #define _PORTA_RA2_POSITION 0x2 #define _PORTA_RA2_SIZE 0x1 #define _PORTA_RA2_LENGTH 0x1 #define _PORTA_RA2_MASK 0x4 #define _PORTA_RA3_POSN 0x3 #define _PORTA_RA3_POSITION 0x3 #define _PORTA_RA3_SIZE 0x1 #define _PORTA_RA3_LENGTH 0x1 #define _PORTA_RA3_MASK 0x8 #define _PORTA_RA5_POSN 0x5 #define _PORTA_RA5_POSITION 0x5 #define _PORTA_RA5_SIZE 0x1 #define _PORTA_RA5_LENGTH 0x1 #define _PORTA_RA5_MASK 0x20 #define _PORTA_RA6_POSN 0x6 #define _PORTA_RA6_POSITION 0x6 #define _PORTA_RA6_SIZE 0x1 #define _PORTA_RA6_LENGTH 0x1 #define _PORTA_RA6_MASK 0x40 #define _PORTA_RA7_POSN 0x7 #define _PORTA_RA7_POSITION 0x7 #define _PORTA_RA7_SIZE 0x1 #define _PORTA_RA7_LENGTH 0x1 #define _PORTA_RA7_MASK 0x80 #define _PORTA_ULPWUIN_POSN 0x0 #define _PORTA_ULPWUIN_POSITION 0x0 #define _PORTA_ULPWUIN_SIZE 0x1 #define _PORTA_ULPWUIN_LENGTH 0x1 #define _PORTA_ULPWUIN_MASK 0x1 #define _PORTA_LVDIN_POSN 0x5 #define _PORTA_LVDIN_POSITION 0x5 #define _PORTA_LVDIN_SIZE 0x1 #define _PORTA_LVDIN_LENGTH 0x1 #define _PORTA_LVDIN_MASK 0x20 #define _PORTA_RJPU_POSN 0x7 #define _PORTA_RJPU_POSITION 0x7 #define _PORTA_RJPU_SIZE 0x1 #define _PORTA_RJPU_LENGTH 0x1 #define _PORTA_RJPU_MASK 0x80 // Register: PORTB #define PORTB PORTB extern volatile unsigned char PORTB @ 0xF81; #ifndef _LIB_BUILD asm("PORTB equ 0F81h"); #endif // bitfield definitions typedef union { struct { unsigned RB0 :1; unsigned RB1 :1; unsigned RB2 :1; unsigned RB3 :1; unsigned RB4 :1; unsigned RB5 :1; unsigned RB6 :1; unsigned RB7 :1; }; struct { unsigned :3; unsigned CCP2_PA2 :1; }; } PORTBbits_t; extern volatile PORTBbits_t PORTBbits @ 0xF81; // bitfield macros #define _PORTB_RB0_POSN 0x0 #define _PORTB_RB0_POSITION 0x0 #define _PORTB_RB0_SIZE 0x1 #define _PORTB_RB0_LENGTH 0x1 #define _PORTB_RB0_MASK 0x1 #define _PORTB_RB1_POSN 0x1 #define _PORTB_RB1_POSITION 0x1 #define _PORTB_RB1_SIZE 0x1 #define _PORTB_RB1_LENGTH 0x1 #define _PORTB_RB1_MASK 0x2 #define _PORTB_RB2_POSN 0x2 #define _PORTB_RB2_POSITION 0x2 #define _PORTB_RB2_SIZE 0x1 #define _PORTB_RB2_LENGTH 0x1 #define _PORTB_RB2_MASK 0x4 #define _PORTB_RB3_POSN 0x3 #define _PORTB_RB3_POSITION 0x3 #define _PORTB_RB3_SIZE 0x1 #define _PORTB_RB3_LENGTH 0x1 #define _PORTB_RB3_MASK 0x8 #define _PORTB_RB4_POSN 0x4 #define _PORTB_RB4_POSITION 0x4 #define _PORTB_RB4_SIZE 0x1 #define _PORTB_RB4_LENGTH 0x1 #define _PORTB_RB4_MASK 0x10 #define _PORTB_RB5_POSN 0x5 #define _PORTB_RB5_POSITION 0x5 #define _PORTB_RB5_SIZE 0x1 #define _PORTB_RB5_LENGTH 0x1 #define _PORTB_RB5_MASK 0x20 #define _PORTB_RB6_POSN 0x6 #define _PORTB_RB6_POSITION 0x6 #define _PORTB_RB6_SIZE 0x1 #define _PORTB_RB6_LENGTH 0x1 #define _PORTB_RB6_MASK 0x40 #define _PORTB_RB7_POSN 0x7 #define _PORTB_RB7_POSITION 0x7 #define _PORTB_RB7_SIZE 0x1 #define _PORTB_RB7_LENGTH 0x1 #define _PORTB_RB7_MASK 0x80 #define _PORTB_CCP2_PA2_POSN 0x3 #define _PORTB_CCP2_PA2_POSITION 0x3 #define _PORTB_CCP2_PA2_SIZE 0x1 #define _PORTB_CCP2_PA2_LENGTH 0x1 #define _PORTB_CCP2_PA2_MASK 0x8 // Register: PORTC #define PORTC PORTC extern volatile unsigned char PORTC @ 0xF82; #ifndef _LIB_BUILD asm("PORTC equ 0F82h"); #endif // bitfield definitions typedef union { struct { unsigned RC0 :1; unsigned RC1 :1; unsigned RC2 :1; unsigned RC3 :1; unsigned RC4 :1; unsigned RC5 :1; unsigned RC6 :1; unsigned RC7 :1; }; struct { unsigned :1; unsigned CCP2 :1; unsigned PA1 :1; }; struct { unsigned :1; unsigned PA2 :1; }; } PORTCbits_t; extern volatile PORTCbits_t PORTCbits @ 0xF82; // bitfield macros #define _PORTC_RC0_POSN 0x0 #define _PORTC_RC0_POSITION 0x0 #define _PORTC_RC0_SIZE 0x1 #define _PORTC_RC0_LENGTH 0x1 #define _PORTC_RC0_MASK 0x1 #define _PORTC_RC1_POSN 0x1 #define _PORTC_RC1_POSITION 0x1 #define _PORTC_RC1_SIZE 0x1 #define _PORTC_RC1_LENGTH 0x1 #define _PORTC_RC1_MASK 0x2 #define _PORTC_RC2_POSN 0x2 #define _PORTC_RC2_POSITION 0x2 #define _PORTC_RC2_SIZE 0x1 #define _PORTC_RC2_LENGTH 0x1 #define _PORTC_RC2_MASK 0x4 #define _PORTC_RC3_POSN 0x3 #define _PORTC_RC3_POSITION 0x3 #define _PORTC_RC3_SIZE 0x1 #define _PORTC_RC3_LENGTH 0x1 #define _PORTC_RC3_MASK 0x8 #define _PORTC_RC4_POSN 0x4 #define _PORTC_RC4_POSITION 0x4 #define _PORTC_RC4_SIZE 0x1 #define _PORTC_RC4_LENGTH 0x1 #define _PORTC_RC4_MASK 0x10 #define _PORTC_RC5_POSN 0x5 #define _PORTC_RC5_POSITION 0x5 #define _PORTC_RC5_SIZE 0x1 #define _PORTC_RC5_LENGTH 0x1 #define _PORTC_RC5_MASK 0x20 #define _PORTC_RC6_POSN 0x6 #define _PORTC_RC6_POSITION 0x6 #define _PORTC_RC6_SIZE 0x1 #define _PORTC_RC6_LENGTH 0x1 #define _PORTC_RC6_MASK 0x40 #define _PORTC_RC7_POSN 0x7 #define _PORTC_RC7_POSITION 0x7 #define _PORTC_RC7_SIZE 0x1 #define _PORTC_RC7_LENGTH 0x1 #define _PORTC_RC7_MASK 0x80 #define _PORTC_CCP2_POSN 0x1 #define _PORTC_CCP2_POSITION 0x1 #define _PORTC_CCP2_SIZE 0x1 #define _PORTC_CCP2_LENGTH 0x1 #define _PORTC_CCP2_MASK 0x2 #define _PORTC_PA1_POSN 0x2 #define _PORTC_PA1_POSITION 0x2 #define _PORTC_PA1_SIZE 0x1 #define _PORTC_PA1_LENGTH 0x1 #define _PORTC_PA1_MASK 0x4 #define _PORTC_PA2_POSN 0x1 #define _PORTC_PA2_POSITION 0x1 #define _PORTC_PA2_SIZE 0x1 #define _PORTC_PA2_LENGTH 0x1 #define _PORTC_PA2_MASK 0x2 // Register: PORTE #define PORTE PORTE extern volatile unsigned char PORTE @ 0xF84; #ifndef _LIB_BUILD asm("PORTE equ 0F84h"); #endif // bitfield definitions typedef union { struct { unsigned :3; unsigned RE3 :1; }; struct { unsigned :3; unsigned CCP9E :1; }; struct { unsigned :3; unsigned PC3E :1; }; } PORTEbits_t; extern volatile PORTEbits_t PORTEbits @ 0xF84; // bitfield macros #define _PORTE_RE3_POSN 0x3 #define _PORTE_RE3_POSITION 0x3 #define _PORTE_RE3_SIZE 0x1 #define _PORTE_RE3_LENGTH 0x1 #define _PORTE_RE3_MASK 0x8 #define _PORTE_CCP9E_POSN 0x3 #define _PORTE_CCP9E_POSITION 0x3 #define _PORTE_CCP9E_SIZE 0x1 #define _PORTE_CCP9E_LENGTH 0x1 #define _PORTE_CCP9E_MASK 0x8 #define _PORTE_PC3E_POSN 0x3 #define _PORTE_PC3E_POSITION 0x3 #define _PORTE_PC3E_SIZE 0x1 #define _PORTE_PC3E_LENGTH 0x1 #define _PORTE_PC3E_MASK 0x8 // Register: TMR4 #define TMR4 TMR4 extern volatile unsigned char TMR4 @ 0xF87; #ifndef _LIB_BUILD asm("TMR4 equ 0F87h"); #endif // bitfield definitions typedef union { struct { unsigned TMR4 :8; }; } TMR4bits_t; extern volatile TMR4bits_t TMR4bits @ 0xF87; // bitfield macros #define _TMR4_TMR4_POSN 0x0 #define _TMR4_TMR4_POSITION 0x0 #define _TMR4_TMR4_SIZE 0x8 #define _TMR4_TMR4_LENGTH 0x8 #define _TMR4_TMR4_MASK 0xFF // Register: T4CON #define T4CON T4CON extern volatile unsigned char T4CON @ 0xF88; #ifndef _LIB_BUILD asm("T4CON equ 0F88h"); #endif // bitfield definitions typedef union { struct { unsigned T4CKPS :2; unsigned TMR4ON :1; unsigned T4OUTPS :4; }; struct { unsigned T4CKPS0 :1; unsigned T4CKPS1 :1; unsigned :1; unsigned T4OUTPS0 :1; unsigned T4OUTPS1 :1; unsigned T4OUTPS2 :1; unsigned T4OUTPS3 :1; }; } T4CONbits_t; extern volatile T4CONbits_t T4CONbits @ 0xF88; // bitfield macros #define _T4CON_T4CKPS_POSN 0x0 #define _T4CON_T4CKPS_POSITION 0x0 #define _T4CON_T4CKPS_SIZE 0x2 #define _T4CON_T4CKPS_LENGTH 0x2 #define _T4CON_T4CKPS_MASK 0x3 #define _T4CON_TMR4ON_POSN 0x2 #define _T4CON_TMR4ON_POSITION 0x2 #define _T4CON_TMR4ON_SIZE 0x1 #define _T4CON_TMR4ON_LENGTH 0x1 #define _T4CON_TMR4ON_MASK 0x4 #define _T4CON_T4OUTPS_POSN 0x3 #define _T4CON_T4OUTPS_POSITION 0x3 #define _T4CON_T4OUTPS_SIZE 0x4 #define _T4CON_T4OUTPS_LENGTH 0x4 #define _T4CON_T4OUTPS_MASK 0x78 #define _T4CON_T4CKPS0_POSN 0x0 #define _T4CON_T4CKPS0_POSITION 0x0 #define _T4CON_T4CKPS0_SIZE 0x1 #define _T4CON_T4CKPS0_LENGTH 0x1 #define _T4CON_T4CKPS0_MASK 0x1 #define _T4CON_T4CKPS1_POSN 0x1 #define _T4CON_T4CKPS1_POSITION 0x1 #define _T4CON_T4CKPS1_SIZE 0x1 #define _T4CON_T4CKPS1_LENGTH 0x1 #define _T4CON_T4CKPS1_MASK 0x2 #define _T4CON_T4OUTPS0_POSN 0x3 #define _T4CON_T4OUTPS0_POSITION 0x3 #define _T4CON_T4OUTPS0_SIZE 0x1 #define _T4CON_T4OUTPS0_LENGTH 0x1 #define _T4CON_T4OUTPS0_MASK 0x8 #define _T4CON_T4OUTPS1_POSN 0x4 #define _T4CON_T4OUTPS1_POSITION 0x4 #define _T4CON_T4OUTPS1_SIZE 0x1 #define _T4CON_T4OUTPS1_LENGTH 0x1 #define _T4CON_T4OUTPS1_MASK 0x10 #define _T4CON_T4OUTPS2_POSN 0x5 #define _T4CON_T4OUTPS2_POSITION 0x5 #define _T4CON_T4OUTPS2_SIZE 0x1 #define _T4CON_T4OUTPS2_LENGTH 0x1 #define _T4CON_T4OUTPS2_MASK 0x20 #define _T4CON_T4OUTPS3_POSN 0x6 #define _T4CON_T4OUTPS3_POSITION 0x6 #define _T4CON_T4OUTPS3_SIZE 0x1 #define _T4CON_T4OUTPS3_LENGTH 0x1 #define _T4CON_T4OUTPS3_MASK 0x40 // Register: LATA #define LATA LATA extern volatile unsigned char LATA @ 0xF89; #ifndef _LIB_BUILD asm("LATA equ 0F89h"); #endif // bitfield definitions typedef union { struct { unsigned LATA0 :1; unsigned LATA1 :1; unsigned LATA2 :1; unsigned LATA3 :1; unsigned :1; unsigned LATA5 :1; unsigned LATA6 :1; unsigned LATA7 :1; }; struct { unsigned LA0 :1; unsigned LA1 :1; unsigned LA2 :1; unsigned LA3 :1; unsigned :1; unsigned LA5 :1; unsigned LA6 :1; unsigned LA7 :1; }; } LATAbits_t; extern volatile LATAbits_t LATAbits @ 0xF89; // bitfield macros #define _LATA_LATA0_POSN 0x0 #define _LATA_LATA0_POSITION 0x0 #define _LATA_LATA0_SIZE 0x1 #define _LATA_LATA0_LENGTH 0x1 #define _LATA_LATA0_MASK 0x1 #define _LATA_LATA1_POSN 0x1 #define _LATA_LATA1_POSITION 0x1 #define _LATA_LATA1_SIZE 0x1 #define _LATA_LATA1_LENGTH 0x1 #define _LATA_LATA1_MASK 0x2 #define _LATA_LATA2_POSN 0x2 #define _LATA_LATA2_POSITION 0x2 #define _LATA_LATA2_SIZE 0x1 #define _LATA_LATA2_LENGTH 0x1 #define _LATA_LATA2_MASK 0x4 #define _LATA_LATA3_POSN 0x3 #define _LATA_LATA3_POSITION 0x3 #define _LATA_LATA3_SIZE 0x1 #define _LATA_LATA3_LENGTH 0x1 #define _LATA_LATA3_MASK 0x8 #define _LATA_LATA5_POSN 0x5 #define _LATA_LATA5_POSITION 0x5 #define _LATA_LATA5_SIZE 0x1 #define _LATA_LATA5_LENGTH 0x1 #define _LATA_LATA5_MASK 0x20 #define _LATA_LATA6_POSN 0x6 #define _LATA_LATA6_POSITION 0x6 #define _LATA_LATA6_SIZE 0x1 #define _LATA_LATA6_LENGTH 0x1 #define _LATA_LATA6_MASK 0x40 #define _LATA_LATA7_POSN 0x7 #define _LATA_LATA7_POSITION 0x7 #define _LATA_LATA7_SIZE 0x1 #define _LATA_LATA7_LENGTH 0x1 #define _LATA_LATA7_MASK 0x80 #define _LATA_LA0_POSN 0x0 #define _LATA_LA0_POSITION 0x0 #define _LATA_LA0_SIZE 0x1 #define _LATA_LA0_LENGTH 0x1 #define _LATA_LA0_MASK 0x1 #define _LATA_LA1_POSN 0x1 #define _LATA_LA1_POSITION 0x1 #define _LATA_LA1_SIZE 0x1 #define _LATA_LA1_LENGTH 0x1 #define _LATA_LA1_MASK 0x2 #define _LATA_LA2_POSN 0x2 #define _LATA_LA2_POSITION 0x2 #define _LATA_LA2_SIZE 0x1 #define _LATA_LA2_LENGTH 0x1 #define _LATA_LA2_MASK 0x4 #define _LATA_LA3_POSN 0x3 #define _LATA_LA3_POSITION 0x3 #define _LATA_LA3_SIZE 0x1 #define _LATA_LA3_LENGTH 0x1 #define _LATA_LA3_MASK 0x8 #define _LATA_LA5_POSN 0x5 #define _LATA_LA5_POSITION 0x5 #define _LATA_LA5_SIZE 0x1 #define _LATA_LA5_LENGTH 0x1 #define _LATA_LA5_MASK 0x20 #define _LATA_LA6_POSN 0x6 #define _LATA_LA6_POSITION 0x6 #define _LATA_LA6_SIZE 0x1 #define _LATA_LA6_LENGTH 0x1 #define _LATA_LA6_MASK 0x40 #define _LATA_LA7_POSN 0x7 #define _LATA_LA7_POSITION 0x7 #define _LATA_LA7_SIZE 0x1 #define _LATA_LA7_LENGTH 0x1 #define _LATA_LA7_MASK 0x80 // Register: LATB #define LATB LATB extern volatile unsigned char LATB @ 0xF8A; #ifndef _LIB_BUILD asm("LATB equ 0F8Ah"); #endif // bitfield definitions typedef union { struct { unsigned LATB0 :1; unsigned LATB1 :1; unsigned LATB2 :1; unsigned LATB3 :1; unsigned LATB4 :1; unsigned LATB5 :1; unsigned LATB6 :1; unsigned LATB7 :1; }; struct { unsigned LB0 :1; unsigned LB1 :1; unsigned LB2 :1; unsigned LB3 :1; unsigned LB4 :1; unsigned LB5 :1; unsigned LB6 :1; unsigned LB7 :1; }; } LATBbits_t; extern volatile LATBbits_t LATBbits @ 0xF8A; // bitfield macros #define _LATB_LATB0_POSN 0x0 #define _LATB_LATB0_POSITION 0x0 #define _LATB_LATB0_SIZE 0x1 #define _LATB_LATB0_LENGTH 0x1 #define _LATB_LATB0_MASK 0x1 #define _LATB_LATB1_POSN 0x1 #define _LATB_LATB1_POSITION 0x1 #define _LATB_LATB1_SIZE 0x1 #define _LATB_LATB1_LENGTH 0x1 #define _LATB_LATB1_MASK 0x2 #define _LATB_LATB2_POSN 0x2 #define _LATB_LATB2_POSITION 0x2 #define _LATB_LATB2_SIZE 0x1 #define _LATB_LATB2_LENGTH 0x1 #define _LATB_LATB2_MASK 0x4 #define _LATB_LATB3_POSN 0x3 #define _LATB_LATB3_POSITION 0x3 #define _LATB_LATB3_SIZE 0x1 #define _LATB_LATB3_LENGTH 0x1 #define _LATB_LATB3_MASK 0x8 #define _LATB_LATB4_POSN 0x4 #define _LATB_LATB4_POSITION 0x4 #define _LATB_LATB4_SIZE 0x1 #define _LATB_LATB4_LENGTH 0x1 #define _LATB_LATB4_MASK 0x10 #define _LATB_LATB5_POSN 0x5 #define _LATB_LATB5_POSITION 0x5 #define _LATB_LATB5_SIZE 0x1 #define _LATB_LATB5_LENGTH 0x1 #define _LATB_LATB5_MASK 0x20 #define _LATB_LATB6_POSN 0x6 #define _LATB_LATB6_POSITION 0x6 #define _LATB_LATB6_SIZE 0x1 #define _LATB_LATB6_LENGTH 0x1 #define _LATB_LATB6_MASK 0x40 #define _LATB_LATB7_POSN 0x7 #define _LATB_LATB7_POSITION 0x7 #define _LATB_LATB7_SIZE 0x1 #define _LATB_LATB7_LENGTH 0x1 #define _LATB_LATB7_MASK 0x80 #define _LATB_LB0_POSN 0x0 #define _LATB_LB0_POSITION 0x0 #define _LATB_LB0_SIZE 0x1 #define _LATB_LB0_LENGTH 0x1 #define _LATB_LB0_MASK 0x1 #define _LATB_LB1_POSN 0x1 #define _LATB_LB1_POSITION 0x1 #define _LATB_LB1_SIZE 0x1 #define _LATB_LB1_LENGTH 0x1 #define _LATB_LB1_MASK 0x2 #define _LATB_LB2_POSN 0x2 #define _LATB_LB2_POSITION 0x2 #define _LATB_LB2_SIZE 0x1 #define _LATB_LB2_LENGTH 0x1 #define _LATB_LB2_MASK 0x4 #define _LATB_LB3_POSN 0x3 #define _LATB_LB3_POSITION 0x3 #define _LATB_LB3_SIZE 0x1 #define _LATB_LB3_LENGTH 0x1 #define _LATB_LB3_MASK 0x8 #define _LATB_LB4_POSN 0x4 #define _LATB_LB4_POSITION 0x4 #define _LATB_LB4_SIZE 0x1 #define _LATB_LB4_LENGTH 0x1 #define _LATB_LB4_MASK 0x10 #define _LATB_LB5_POSN 0x5 #define _LATB_LB5_POSITION 0x5 #define _LATB_LB5_SIZE 0x1 #define _LATB_LB5_LENGTH 0x1 #define _LATB_LB5_MASK 0x20 #define _LATB_LB6_POSN 0x6 #define _LATB_LB6_POSITION 0x6 #define _LATB_LB6_SIZE 0x1 #define _LATB_LB6_LENGTH 0x1 #define _LATB_LB6_MASK 0x40 #define _LATB_LB7_POSN 0x7 #define _LATB_LB7_POSITION 0x7 #define _LATB_LB7_SIZE 0x1 #define _LATB_LB7_LENGTH 0x1 #define _LATB_LB7_MASK 0x80 // Register: LATC #define LATC LATC extern volatile unsigned char LATC @ 0xF8B; #ifndef _LIB_BUILD asm("LATC equ 0F8Bh"); #endif // bitfield definitions typedef union { struct { unsigned LATC0 :1; unsigned LATC1 :1; unsigned LATC2 :1; unsigned LATC3 :1; unsigned LATC4 :1; unsigned LATC5 :1; unsigned LATC6 :1; unsigned LATC7 :1; }; struct { unsigned LC0 :1; unsigned LC1 :1; unsigned LC2 :1; unsigned LC3 :1; unsigned LC4 :1; unsigned LC5 :1; unsigned LC6 :1; unsigned LC7 :1; }; } LATCbits_t; extern volatile LATCbits_t LATCbits @ 0xF8B; // bitfield macros #define _LATC_LATC0_POSN 0x0 #define _LATC_LATC0_POSITION 0x0 #define _LATC_LATC0_SIZE 0x1 #define _LATC_LATC0_LENGTH 0x1 #define _LATC_LATC0_MASK 0x1 #define _LATC_LATC1_POSN 0x1 #define _LATC_LATC1_POSITION 0x1 #define _LATC_LATC1_SIZE 0x1 #define _LATC_LATC1_LENGTH 0x1 #define _LATC_LATC1_MASK 0x2 #define _LATC_LATC2_POSN 0x2 #define _LATC_LATC2_POSITION 0x2 #define _LATC_LATC2_SIZE 0x1 #define _LATC_LATC2_LENGTH 0x1 #define _LATC_LATC2_MASK 0x4 #define _LATC_LATC3_POSN 0x3 #define _LATC_LATC3_POSITION 0x3 #define _LATC_LATC3_SIZE 0x1 #define _LATC_LATC3_LENGTH 0x1 #define _LATC_LATC3_MASK 0x8 #define _LATC_LATC4_POSN 0x4 #define _LATC_LATC4_POSITION 0x4 #define _LATC_LATC4_SIZE 0x1 #define _LATC_LATC4_LENGTH 0x1 #define _LATC_LATC4_MASK 0x10 #define _LATC_LATC5_POSN 0x5 #define _LATC_LATC5_POSITION 0x5 #define _LATC_LATC5_SIZE 0x1 #define _LATC_LATC5_LENGTH 0x1 #define _LATC_LATC5_MASK 0x20 #define _LATC_LATC6_POSN 0x6 #define _LATC_LATC6_POSITION 0x6 #define _LATC_LATC6_SIZE 0x1 #define _LATC_LATC6_LENGTH 0x1 #define _LATC_LATC6_MASK 0x40 #define _LATC_LATC7_POSN 0x7 #define _LATC_LATC7_POSITION 0x7 #define _LATC_LATC7_SIZE 0x1 #define _LATC_LATC7_LENGTH 0x1 #define _LATC_LATC7_MASK 0x80 #define _LATC_LC0_POSN 0x0 #define _LATC_LC0_POSITION 0x0 #define _LATC_LC0_SIZE 0x1 #define _LATC_LC0_LENGTH 0x1 #define _LATC_LC0_MASK 0x1 #define _LATC_LC1_POSN 0x1 #define _LATC_LC1_POSITION 0x1 #define _LATC_LC1_SIZE 0x1 #define _LATC_LC1_LENGTH 0x1 #define _LATC_LC1_MASK 0x2 #define _LATC_LC2_POSN 0x2 #define _LATC_LC2_POSITION 0x2 #define _LATC_LC2_SIZE 0x1 #define _LATC_LC2_LENGTH 0x1 #define _LATC_LC2_MASK 0x4 #define _LATC_LC3_POSN 0x3 #define _LATC_LC3_POSITION 0x3 #define _LATC_LC3_SIZE 0x1 #define _LATC_LC3_LENGTH 0x1 #define _LATC_LC3_MASK 0x8 #define _LATC_LC4_POSN 0x4 #define _LATC_LC4_POSITION 0x4 #define _LATC_LC4_SIZE 0x1 #define _LATC_LC4_LENGTH 0x1 #define _LATC_LC4_MASK 0x10 #define _LATC_LC5_POSN 0x5 #define _LATC_LC5_POSITION 0x5 #define _LATC_LC5_SIZE 0x1 #define _LATC_LC5_LENGTH 0x1 #define _LATC_LC5_MASK 0x20 #define _LATC_LC6_POSN 0x6 #define _LATC_LC6_POSITION 0x6 #define _LATC_LC6_SIZE 0x1 #define _LATC_LC6_LENGTH 0x1 #define _LATC_LC6_MASK 0x40 #define _LATC_LC7_POSN 0x7 #define _LATC_LC7_POSITION 0x7 #define _LATC_LC7_SIZE 0x1 #define _LATC_LC7_LENGTH 0x1 #define _LATC_LC7_MASK 0x80 // Register: SLRCON #define SLRCON SLRCON extern volatile unsigned char SLRCON @ 0xF90; #ifndef _LIB_BUILD asm("SLRCON equ 0F90h"); #endif // bitfield definitions typedef union { struct { unsigned SLRA :1; unsigned SLRB :1; unsigned SLRC :1; }; } SLRCONbits_t; extern volatile SLRCONbits_t SLRCONbits @ 0xF90; // bitfield macros #define _SLRCON_SLRA_POSN 0x0 #define _SLRCON_SLRA_POSITION 0x0 #define _SLRCON_SLRA_SIZE 0x1 #define _SLRCON_SLRA_LENGTH 0x1 #define _SLRCON_SLRA_MASK 0x1 #define _SLRCON_SLRB_POSN 0x1 #define _SLRCON_SLRB_POSITION 0x1 #define _SLRCON_SLRB_SIZE 0x1 #define _SLRCON_SLRB_LENGTH 0x1 #define _SLRCON_SLRB_MASK 0x2 #define _SLRCON_SLRC_POSN 0x2 #define _SLRCON_SLRC_POSITION 0x2 #define _SLRCON_SLRC_SIZE 0x1 #define _SLRCON_SLRC_LENGTH 0x1 #define _SLRCON_SLRC_MASK 0x4 // Register: ODCON #define ODCON ODCON extern volatile unsigned char ODCON @ 0xF91; #ifndef _LIB_BUILD asm("ODCON equ 0F91h"); #endif // bitfield definitions typedef union { struct { unsigned U1OD :1; unsigned U2OD :1; unsigned CCP1OD :1; unsigned CCP2OD :1; unsigned CCP3OD :1; unsigned CCP4OD :1; unsigned CCP5OD :1; unsigned SSPOD :1; }; } ODCONbits_t; extern volatile ODCONbits_t ODCONbits @ 0xF91; // bitfield macros #define _ODCON_U1OD_POSN 0x0 #define _ODCON_U1OD_POSITION 0x0 #define _ODCON_U1OD_SIZE 0x1 #define _ODCON_U1OD_LENGTH 0x1 #define _ODCON_U1OD_MASK 0x1 #define _ODCON_U2OD_POSN 0x1 #define _ODCON_U2OD_POSITION 0x1 #define _ODCON_U2OD_SIZE 0x1 #define _ODCON_U2OD_LENGTH 0x1 #define _ODCON_U2OD_MASK 0x2 #define _ODCON_CCP1OD_POSN 0x2 #define _ODCON_CCP1OD_POSITION 0x2 #define _ODCON_CCP1OD_SIZE 0x1 #define _ODCON_CCP1OD_LENGTH 0x1 #define _ODCON_CCP1OD_MASK 0x4 #define _ODCON_CCP2OD_POSN 0x3 #define _ODCON_CCP2OD_POSITION 0x3 #define _ODCON_CCP2OD_SIZE 0x1 #define _ODCON_CCP2OD_LENGTH 0x1 #define _ODCON_CCP2OD_MASK 0x8 #define _ODCON_CCP3OD_POSN 0x4 #define _ODCON_CCP3OD_POSITION 0x4 #define _ODCON_CCP3OD_SIZE 0x1 #define _ODCON_CCP3OD_LENGTH 0x1 #define _ODCON_CCP3OD_MASK 0x10 #define _ODCON_CCP4OD_POSN 0x5 #define _ODCON_CCP4OD_POSITION 0x5 #define _ODCON_CCP4OD_SIZE 0x1 #define _ODCON_CCP4OD_LENGTH 0x1 #define _ODCON_CCP4OD_MASK 0x20 #define _ODCON_CCP5OD_POSN 0x6 #define _ODCON_CCP5OD_POSITION 0x6 #define _ODCON_CCP5OD_SIZE 0x1 #define _ODCON_CCP5OD_LENGTH 0x1 #define _ODCON_CCP5OD_MASK 0x40 #define _ODCON_SSPOD_POSN 0x7 #define _ODCON_SSPOD_POSITION 0x7 #define _ODCON_SSPOD_SIZE 0x1 #define _ODCON_SSPOD_LENGTH 0x1 #define _ODCON_SSPOD_MASK 0x80 // Register: TRISA #define TRISA TRISA extern volatile unsigned char TRISA @ 0xF92; #ifndef _LIB_BUILD asm("TRISA equ 0F92h"); #endif // bitfield definitions typedef union { struct { unsigned TRISA0 :1; unsigned TRISA1 :1; unsigned TRISA2 :1; unsigned TRISA3 :1; unsigned :1; unsigned TRISA5 :1; unsigned TRISA6 :1; unsigned TRISA7 :1; }; } TRISAbits_t; extern volatile TRISAbits_t TRISAbits @ 0xF92; // bitfield macros #define _TRISA_TRISA0_POSN 0x0 #define _TRISA_TRISA0_POSITION 0x0 #define _TRISA_TRISA0_SIZE 0x1 #define _TRISA_TRISA0_LENGTH 0x1 #define _TRISA_TRISA0_MASK 0x1 #define _TRISA_TRISA1_POSN 0x1 #define _TRISA_TRISA1_POSITION 0x1 #define _TRISA_TRISA1_SIZE 0x1 #define _TRISA_TRISA1_LENGTH 0x1 #define _TRISA_TRISA1_MASK 0x2 #define _TRISA_TRISA2_POSN 0x2 #define _TRISA_TRISA2_POSITION 0x2 #define _TRISA_TRISA2_SIZE 0x1 #define _TRISA_TRISA2_LENGTH 0x1 #define _TRISA_TRISA2_MASK 0x4 #define _TRISA_TRISA3_POSN 0x3 #define _TRISA_TRISA3_POSITION 0x3 #define _TRISA_TRISA3_SIZE 0x1 #define _TRISA_TRISA3_LENGTH 0x1 #define _TRISA_TRISA3_MASK 0x8 #define _TRISA_TRISA5_POSN 0x5 #define _TRISA_TRISA5_POSITION 0x5 #define _TRISA_TRISA5_SIZE 0x1 #define _TRISA_TRISA5_LENGTH 0x1 #define _TRISA_TRISA5_MASK 0x20 #define _TRISA_TRISA6_POSN 0x6 #define _TRISA_TRISA6_POSITION 0x6 #define _TRISA_TRISA6_SIZE 0x1 #define _TRISA_TRISA6_LENGTH 0x1 #define _TRISA_TRISA6_MASK 0x40 #define _TRISA_TRISA7_POSN 0x7 #define _TRISA_TRISA7_POSITION 0x7 #define _TRISA_TRISA7_SIZE 0x1 #define _TRISA_TRISA7_LENGTH 0x1 #define _TRISA_TRISA7_MASK 0x80 // Register: TRISB #define TRISB TRISB extern volatile unsigned char TRISB @ 0xF93; #ifndef _LIB_BUILD asm("TRISB equ 0F93h"); #endif // bitfield definitions typedef union { struct { unsigned TRISB0 :1; unsigned TRISB1 :1; unsigned TRISB2 :1; unsigned TRISB3 :1; unsigned TRISB4 :1; unsigned TRISB5 :1; unsigned TRISB6 :1; unsigned TRISB7 :1; }; } TRISBbits_t; extern volatile TRISBbits_t TRISBbits @ 0xF93; // bitfield macros #define _TRISB_TRISB0_POSN 0x0 #define _TRISB_TRISB0_POSITION 0x0 #define _TRISB_TRISB0_SIZE 0x1 #define _TRISB_TRISB0_LENGTH 0x1 #define _TRISB_TRISB0_MASK 0x1 #define _TRISB_TRISB1_POSN 0x1 #define _TRISB_TRISB1_POSITION 0x1 #define _TRISB_TRISB1_SIZE 0x1 #define _TRISB_TRISB1_LENGTH 0x1 #define _TRISB_TRISB1_MASK 0x2 #define _TRISB_TRISB2_POSN 0x2 #define _TRISB_TRISB2_POSITION 0x2 #define _TRISB_TRISB2_SIZE 0x1 #define _TRISB_TRISB2_LENGTH 0x1 #define _TRISB_TRISB2_MASK 0x4 #define _TRISB_TRISB3_POSN 0x3 #define _TRISB_TRISB3_POSITION 0x3 #define _TRISB_TRISB3_SIZE 0x1 #define _TRISB_TRISB3_LENGTH 0x1 #define _TRISB_TRISB3_MASK 0x8 #define _TRISB_TRISB4_POSN 0x4 #define _TRISB_TRISB4_POSITION 0x4 #define _TRISB_TRISB4_SIZE 0x1 #define _TRISB_TRISB4_LENGTH 0x1 #define _TRISB_TRISB4_MASK 0x10 #define _TRISB_TRISB5_POSN 0x5 #define _TRISB_TRISB5_POSITION 0x5 #define _TRISB_TRISB5_SIZE 0x1 #define _TRISB_TRISB5_LENGTH 0x1 #define _TRISB_TRISB5_MASK 0x20 #define _TRISB_TRISB6_POSN 0x6 #define _TRISB_TRISB6_POSITION 0x6 #define _TRISB_TRISB6_SIZE 0x1 #define _TRISB_TRISB6_LENGTH 0x1 #define _TRISB_TRISB6_MASK 0x40 #define _TRISB_TRISB7_POSN 0x7 #define _TRISB_TRISB7_POSITION 0x7 #define _TRISB_TRISB7_SIZE 0x1 #define _TRISB_TRISB7_LENGTH 0x1 #define _TRISB_TRISB7_MASK 0x80 // Register: TRISC #define TRISC TRISC extern volatile unsigned char TRISC @ 0xF94; #ifndef _LIB_BUILD asm("TRISC equ 0F94h"); #endif // bitfield definitions typedef union { struct { unsigned TRISC0 :1; unsigned TRISC1 :1; unsigned TRISC2 :1; unsigned TRISC3 :1; unsigned TRISC4 :1; unsigned TRISC5 :1; unsigned TRISC6 :1; unsigned TRISC7 :1; }; } TRISCbits_t; extern volatile TRISCbits_t TRISCbits @ 0xF94; // bitfield macros #define _TRISC_TRISC0_POSN 0x0 #define _TRISC_TRISC0_POSITION 0x0 #define _TRISC_TRISC0_SIZE 0x1 #define _TRISC_TRISC0_LENGTH 0x1 #define _TRISC_TRISC0_MASK 0x1 #define _TRISC_TRISC1_POSN 0x1 #define _TRISC_TRISC1_POSITION 0x1 #define _TRISC_TRISC1_SIZE 0x1 #define _TRISC_TRISC1_LENGTH 0x1 #define _TRISC_TRISC1_MASK 0x2 #define _TRISC_TRISC2_POSN 0x2 #define _TRISC_TRISC2_POSITION 0x2 #define _TRISC_TRISC2_SIZE 0x1 #define _TRISC_TRISC2_LENGTH 0x1 #define _TRISC_TRISC2_MASK 0x4 #define _TRISC_TRISC3_POSN 0x3 #define _TRISC_TRISC3_POSITION 0x3 #define _TRISC_TRISC3_SIZE 0x1 #define _TRISC_TRISC3_LENGTH 0x1 #define _TRISC_TRISC3_MASK 0x8 #define _TRISC_TRISC4_POSN 0x4 #define _TRISC_TRISC4_POSITION 0x4 #define _TRISC_TRISC4_SIZE 0x1 #define _TRISC_TRISC4_LENGTH 0x1 #define _TRISC_TRISC4_MASK 0x10 #define _TRISC_TRISC5_POSN 0x5 #define _TRISC_TRISC5_POSITION 0x5 #define _TRISC_TRISC5_SIZE 0x1 #define _TRISC_TRISC5_LENGTH 0x1 #define _TRISC_TRISC5_MASK 0x20 #define _TRISC_TRISC6_POSN 0x6 #define _TRISC_TRISC6_POSITION 0x6 #define _TRISC_TRISC6_SIZE 0x1 #define _TRISC_TRISC6_LENGTH 0x1 #define _TRISC_TRISC6_MASK 0x40 #define _TRISC_TRISC7_POSN 0x7 #define _TRISC_TRISC7_POSITION 0x7 #define _TRISC_TRISC7_SIZE 0x1 #define _TRISC_TRISC7_LENGTH 0x1 #define _TRISC_TRISC7_MASK 0x80 // Register: CCPTMRS #define CCPTMRS CCPTMRS extern volatile unsigned char CCPTMRS @ 0xF99; #ifndef _LIB_BUILD asm("CCPTMRS equ 0F99h"); #endif // bitfield definitions typedef union { struct { unsigned C1TSEL :1; unsigned C2TSEL :1; unsigned C3TSEL :1; unsigned C4TSEL :1; unsigned C5TSEL :1; }; } CCPTMRSbits_t; extern volatile CCPTMRSbits_t CCPTMRSbits @ 0xF99; // bitfield macros #define _CCPTMRS_C1TSEL_POSN 0x0 #define _CCPTMRS_C1TSEL_POSITION 0x0 #define _CCPTMRS_C1TSEL_SIZE 0x1 #define _CCPTMRS_C1TSEL_LENGTH 0x1 #define _CCPTMRS_C1TSEL_MASK 0x1 #define _CCPTMRS_C2TSEL_POSN 0x1 #define _CCPTMRS_C2TSEL_POSITION 0x1 #define _CCPTMRS_C2TSEL_SIZE 0x1 #define _CCPTMRS_C2TSEL_LENGTH 0x1 #define _CCPTMRS_C2TSEL_MASK 0x2 #define _CCPTMRS_C3TSEL_POSN 0x2 #define _CCPTMRS_C3TSEL_POSITION 0x2 #define _CCPTMRS_C3TSEL_SIZE 0x1 #define _CCPTMRS_C3TSEL_LENGTH 0x1 #define _CCPTMRS_C3TSEL_MASK 0x4 #define _CCPTMRS_C4TSEL_POSN 0x3 #define _CCPTMRS_C4TSEL_POSITION 0x3 #define _CCPTMRS_C4TSEL_SIZE 0x1 #define _CCPTMRS_C4TSEL_LENGTH 0x1 #define _CCPTMRS_C4TSEL_MASK 0x8 #define _CCPTMRS_C5TSEL_POSN 0x4 #define _CCPTMRS_C5TSEL_POSITION 0x4 #define _CCPTMRS_C5TSEL_SIZE 0x1 #define _CCPTMRS_C5TSEL_LENGTH 0x1 #define _CCPTMRS_C5TSEL_MASK 0x10 // Register: TRISE #define TRISE TRISE extern volatile unsigned char TRISE @ 0x096; #ifndef _LIB_BUILD asm("TRISE equ 096h"); #endif // bitfield definitions typedef union { struct { unsigned :3; unsigned TRISE3 :1; }; } TRISEbits_t; extern volatile TRISEbits_t TRISEbits @ 0x096; // bitfield macros #define _TRISE_TRISE3_POSN 0x3 #define _TRISE_TRISE3_POSITION 0x3 #define _TRISE_TRISE3_SIZE 0x1 #define _TRISE_TRISE3_LENGTH 0x1 #define _TRISE_TRISE3_MASK // Register: REFOCON #define REFOCON REFOCON extern volatile unsigned char REFOCON @ 0xF9A; #ifndef _LIB_BUILD asm("REFOCON equ 0F9Ah"); #endif // bitfield definitions typedef union { struct { unsigned RODIV :4; unsigned ROSEL :1; unsigned ROSSLP :1; unsigned :1; unsigned ROON :1; }; struct { unsigned RODIV0 :1; unsigned RODIV1 :1; unsigned RODIV2 :1; unsigned RODIV3 :1; }; } REFOCONbits_t; extern volatile REFOCONbits_t REFOCONbits @ 0xF9A; // bitfield macros #define _REFOCON_RODIV_POSN 0x0 #define _REFOCON_RODIV_POSITION 0x0 #define _REFOCON_RODIV_SIZE 0x4 #define _REFOCON_RODIV_LENGTH 0x4 #define _REFOCON_RODIV_MASK 0xF #define _REFOCON_ROSEL_POSN 0x4 #define _REFOCON_ROSEL_POSITION 0x4 #define _REFOCON_ROSEL_SIZE 0x1 #define _REFOCON_ROSEL_LENGTH 0x1 #define _REFOCON_ROSEL_MASK 0x10 #define _REFOCON_ROSSLP_POSN 0x5 #define _REFOCON_ROSSLP_POSITION 0x5 #define _REFOCON_ROSSLP_SIZE 0x1 #define _REFOCON_ROSSLP_LENGTH 0x1 #define _REFOCON_ROSSLP_MASK 0x20 #define _REFOCON_ROON_POSN 0x7 #define _REFOCON_ROON_POSITION 0x7 #define _REFOCON_ROON_SIZE 0x1 #define _REFOCON_ROON_LENGTH 0x1 #define _REFOCON_ROON_MASK 0x80 #define _REFOCON_RODIV0_POSN 0x0 #define _REFOCON_RODIV0_POSITION 0x0 #define _REFOCON_RODIV0_SIZE 0x1 #define _REFOCON_RODIV0_LENGTH 0x1 #define _REFOCON_RODIV0_MASK 0x1 #define _REFOCON_RODIV1_POSN 0x1 #define _REFOCON_RODIV1_POSITION 0x1 #define _REFOCON_RODIV1_SIZE 0x1 #define _REFOCON_RODIV1_LENGTH 0x1 #define _REFOCON_RODIV1_MASK 0x2 #define _REFOCON_RODIV2_POSN 0x2 #define _REFOCON_RODIV2_POSITION 0x2 #define _REFOCON_RODIV2_SIZE 0x1 #define _REFOCON_RODIV2_LENGTH 0x1 #define _REFOCON_RODIV2_MASK 0x4 #define _REFOCON_RODIV3_POSN 0x3 #define _REFOCON_RODIV3_POSITION 0x3 #define _REFOCON_RODIV3_SIZE 0x1 #define _REFOCON_RODIV3_LENGTH 0x1 #define _REFOCON_RODIV3_MASK 0x8 // Register: OSCTUNE #define OSCTUNE OSCTUNE extern volatile unsigned char OSCTUNE @ 0xF9B; #ifndef _LIB_BUILD asm("OSCTUNE equ 0F9Bh"); #endif // bitfield definitions typedef union { struct { unsigned TUN :6; unsigned PLLEN :1; unsigned INTSRC :1; }; struct { unsigned TUN0 :1; unsigned TUN1 :1; unsigned TUN2 :1; unsigned TUN3 :1; unsigned TUN4 :1; unsigned TUN5 :1; }; } OSCTUNEbits_t; extern volatile OSCTUNEbits_t OSCTUNEbits @ 0xF9B; // bitfield macros #define _OSCTUNE_TUN_POSN 0x0 #define _OSCTUNE_TUN_POSITION 0x0 #define _OSCTUNE_TUN_SIZE 0x6 #define _OSCTUNE_TUN_LENGTH 0x6 #define _OSCTUNE_TUN_MASK 0x3F #define _OSCTUNE_PLLEN_POSN 0x6 #define _OSCTUNE_PLLEN_POSITION 0x6 #define _OSCTUNE_PLLEN_SIZE 0x1 #define _OSCTUNE_PLLEN_LENGTH 0x1 #define _OSCTUNE_PLLEN_MASK 0x40 #define _OSCTUNE_INTSRC_POSN 0x7 #define _OSCTUNE_INTSRC_POSITION 0x7 #define _OSCTUNE_INTSRC_SIZE 0x1 #define _OSCTUNE_INTSRC_LENGTH 0x1 #define _OSCTUNE_INTSRC_MASK 0x80 #define _OSCTUNE_TUN0_POSN 0x0 #define _OSCTUNE_TUN0_POSITION 0x0 #define _OSCTUNE_TUN0_SIZE 0x1 #define _OSCTUNE_TUN0_LENGTH 0x1 #define _OSCTUNE_TUN0_MASK 0x1 #define _OSCTUNE_TUN1_POSN 0x1 #define _OSCTUNE_TUN1_POSITION 0x1 #define _OSCTUNE_TUN1_SIZE 0x1 #define _OSCTUNE_TUN1_LENGTH 0x1 #define _OSCTUNE_TUN1_MASK 0x2 #define _OSCTUNE_TUN2_POSN 0x2 #define _OSCTUNE_TUN2_POSITION 0x2 #define _OSCTUNE_TUN2_SIZE 0x1 #define _OSCTUNE_TUN2_LENGTH 0x1 #define _OSCTUNE_TUN2_MASK 0x4 #define _OSCTUNE_TUN3_POSN 0x3 #define _OSCTUNE_TUN3_POSITION 0x3 #define _OSCTUNE_TUN3_SIZE 0x1 #define _OSCTUNE_TUN3_LENGTH 0x1 #define _OSCTUNE_TUN3_MASK 0x8 #define _OSCTUNE_TUN4_POSN 0x4 #define _OSCTUNE_TUN4_POSITION 0x4 #define _OSCTUNE_TUN4_SIZE 0x1 #define _OSCTUNE_TUN4_LENGTH 0x1 #define _OSCTUNE_TUN4_MASK 0x10 #define _OSCTUNE_TUN5_POSN 0x5 #define _OSCTUNE_TUN5_POSITION 0x5 #define _OSCTUNE_TUN5_SIZE 0x1 #define _OSCTUNE_TUN5_LENGTH 0x1 #define _OSCTUNE_TUN5_MASK 0x20 // Register: PSTR1CON #define PSTR1CON PSTR1CON extern volatile unsigned char PSTR1CON @ 0xF9C; #ifndef _LIB_BUILD asm("PSTR1CON equ 0F9Ch"); #endif // bitfield definitions typedef union { struct { unsigned STRA :1; unsigned STRB :1; unsigned STRC :1; unsigned STRD :1; unsigned STRSYNC :1; unsigned :1; unsigned CMPL :2; }; struct { unsigned :6; unsigned CMPL0 :1; unsigned CMPL1 :1; }; } PSTR1CONbits_t; extern volatile PSTR1CONbits_t PSTR1CONbits @ 0xF9C; // bitfield macros #define _PSTR1CON_STRA_POSN 0x0 #define _PSTR1CON_STRA_POSITION 0x0 #define _PSTR1CON_STRA_SIZE 0x1 #define _PSTR1CON_STRA_LENGTH 0x1 #define _PSTR1CON_STRA_MASK 0x1 #define _PSTR1CON_STRB_POSN 0x1 #define _PSTR1CON_STRB_POSITION 0x1 #define _PSTR1CON_STRB_SIZE 0x1 #define _PSTR1CON_STRB_LENGTH 0x1 #define _PSTR1CON_STRB_MASK 0x2 #define _PSTR1CON_STRC_POSN 0x2 #define _PSTR1CON_STRC_POSITION 0x2 #define _PSTR1CON_STRC_SIZE 0x1 #define _PSTR1CON_STRC_LENGTH 0x1 #define _PSTR1CON_STRC_MASK 0x4 #define _PSTR1CON_STRD_POSN 0x3 #define _PSTR1CON_STRD_POSITION 0x3 #define _PSTR1CON_STRD_SIZE 0x1 #define _PSTR1CON_STRD_LENGTH 0x1 #define _PSTR1CON_STRD_MASK 0x8 #define _PSTR1CON_STRSYNC_POSN 0x4 #define _PSTR1CON_STRSYNC_POSITION 0x4 #define _PSTR1CON_STRSYNC_SIZE 0x1 #define _PSTR1CON_STRSYNC_LENGTH 0x1 #define _PSTR1CON_STRSYNC_MASK 0x10 #define _PSTR1CON_CMPL_POSN 0x6 #define _PSTR1CON_CMPL_POSITION 0x6 #define _PSTR1CON_CMPL_SIZE 0x2 #define _PSTR1CON_CMPL_LENGTH 0x2 #define _PSTR1CON_CMPL_MASK 0xC0 #define _PSTR1CON_CMPL0_POSN 0x6 #define _PSTR1CON_CMPL0_POSITION 0x6 #define _PSTR1CON_CMPL0_SIZE 0x1 #define _PSTR1CON_CMPL0_LENGTH 0x1 #define _PSTR1CON_CMPL0_MASK 0x40 #define _PSTR1CON_CMPL1_POSN 0x7 #define _PSTR1CON_CMPL1_POSITION 0x7 #define _PSTR1CON_CMPL1_SIZE 0x1 #define _PSTR1CON_CMPL1_LENGTH 0x1 #define _PSTR1CON_CMPL1_MASK 0x80 // Register: PIE1 #define PIE1 PIE1 extern volatile unsigned char PIE1 @ 0xF9D; #ifndef _LIB_BUILD asm("PIE1 equ 0F9Dh"); #endif // bitfield definitions typedef union { struct { unsigned TMR1IE :1; unsigned TMR2IE :1; unsigned TMR1GIE :1; unsigned SSPIE :1; unsigned TX1IE :1; unsigned RC1IE :1; unsigned ADIE :1; }; struct { unsigned :4; unsigned TXIE :1; unsigned RCIE :1; }; } PIE1bits_t; extern volatile PIE1bits_t PIE1bits @ 0xF9D; // bitfield macros #define _PIE1_TMR1IE_POSN 0x0 #define _PIE1_TMR1IE_POSITION 0x0 #define _PIE1_TMR1IE_SIZE 0x1 #define _PIE1_TMR1IE_LENGTH 0x1 #define _PIE1_TMR1IE_MASK 0x1 #define _PIE1_TMR2IE_POSN 0x1 #define _PIE1_TMR2IE_POSITION 0x1 #define _PIE1_TMR2IE_SIZE 0x1 #define _PIE1_TMR2IE_LENGTH 0x1 #define _PIE1_TMR2IE_MASK 0x2 #define _PIE1_TMR1GIE_POSN 0x2 #define _PIE1_TMR1GIE_POSITION 0x2 #define _PIE1_TMR1GIE_SIZE 0x1 #define _PIE1_TMR1GIE_LENGTH 0x1 #define _PIE1_TMR1GIE_MASK 0x4 #define _PIE1_SSPIE_POSN 0x3 #define _PIE1_SSPIE_POSITION 0x3 #define _PIE1_SSPIE_SIZE 0x1 #define _PIE1_SSPIE_LENGTH 0x1 #define _PIE1_SSPIE_MASK 0x8 #define _PIE1_TX1IE_POSN 0x4 #define _PIE1_TX1IE_POSITION 0x4 #define _PIE1_TX1IE_SIZE 0x1 #define _PIE1_TX1IE_LENGTH 0x1 #define _PIE1_TX1IE_MASK 0x10 #define _PIE1_RC1IE_POSN 0x5 #define _PIE1_RC1IE_POSITION 0x5 #define _PIE1_RC1IE_SIZE 0x1 #define _PIE1_RC1IE_LENGTH 0x1 #define _PIE1_RC1IE_MASK 0x20 #define _PIE1_ADIE_POSN 0x6 #define _PIE1_ADIE_POSITION 0x6 #define _PIE1_ADIE_SIZE 0x1 #define _PIE1_ADIE_LENGTH 0x1 #define _PIE1_ADIE_MASK 0x40 #define _PIE1_TXIE_POSN 0x4 #define _PIE1_TXIE_POSITION 0x4 #define _PIE1_TXIE_SIZE 0x1 #define _PIE1_TXIE_LENGTH 0x1 #define _PIE1_TXIE_MASK 0x10 #define _PIE1_RCIE_POSN 0x5 #define _PIE1_RCIE_POSITION 0x5 #define _PIE1_RCIE_SIZE 0x1 #define _PIE1_RCIE_LENGTH 0x1 #define _PIE1_RCIE_MASK 0x20 // Register: PIR1 #define PIR1 PIR1 extern volatile unsigned char PIR1 @ 0xF9E; #ifndef _LIB_BUILD asm("PIR1 equ 0F9Eh"); #endif // bitfield definitions typedef union { struct { unsigned TMR1IF :1; unsigned TMR2IF :1; unsigned TMR1GIF :1; unsigned SSPIF :1; unsigned TX1IF :1; unsigned RC1IF :1; unsigned ADIF :1; }; struct { unsigned :4; unsigned TXIF :1; unsigned RCIF :1; }; } PIR1bits_t; extern volatile PIR1bits_t PIR1bits @ 0xF9E; // bitfield macros #define _PIR1_TMR1IF_POSN 0x0 #define _PIR1_TMR1IF_POSITION 0x0 #define _PIR1_TMR1IF_SIZE 0x1 #define _PIR1_TMR1IF_LENGTH 0x1 #define _PIR1_TMR1IF_MASK 0x1 #define _PIR1_TMR2IF_POSN 0x1 #define _PIR1_TMR2IF_POSITION 0x1 #define _PIR1_TMR2IF_SIZE 0x1 #define _PIR1_TMR2IF_LENGTH 0x1 #define _PIR1_TMR2IF_MASK 0x2 #define _PIR1_TMR1GIF_POSN 0x2 #define _PIR1_TMR1GIF_POSITION 0x2 #define _PIR1_TMR1GIF_SIZE 0x1 #define _PIR1_TMR1GIF_LENGTH 0x1 #define _PIR1_TMR1GIF_MASK 0x4 #define _PIR1_SSPIF_POSN 0x3 #define _PIR1_SSPIF_POSITION 0x3 #define _PIR1_SSPIF_SIZE 0x1 #define _PIR1_SSPIF_LENGTH 0x1 #define _PIR1_SSPIF_MASK 0x8 #define _PIR1_TX1IF_POSN 0x4 #define _PIR1_TX1IF_POSITION 0x4 #define _PIR1_TX1IF_SIZE 0x1 #define _PIR1_TX1IF_LENGTH 0x1 #define _PIR1_TX1IF_MASK 0x10 #define _PIR1_RC1IF_POSN 0x5 #define _PIR1_RC1IF_POSITION 0x5 #define _PIR1_RC1IF_SIZE 0x1 #define _PIR1_RC1IF_LENGTH 0x1 #define _PIR1_RC1IF_MASK 0x20 #define _PIR1_ADIF_POSN 0x6 #define _PIR1_ADIF_POSITION 0x6 #define _PIR1_ADIF_SIZE 0x1 #define _PIR1_ADIF_LENGTH 0x1 #define _PIR1_ADIF_MASK 0x40 #define _PIR1_TXIF_POSN 0x4 #define _PIR1_TXIF_POSITION 0x4 #define _PIR1_TXIF_SIZE 0x1 #define _PIR1_TXIF_LENGTH 0x1 #define _PIR1_TXIF_MASK 0x10 #define _PIR1_RCIF_POSN 0x5 #define _PIR1_RCIF_POSITION 0x5 #define _PIR1_RCIF_SIZE 0x1 #define _PIR1_RCIF_LENGTH 0x1 #define _PIR1_RCIF_MASK 0x20 // Register: IPR1 #define IPR1 IPR1 extern volatile unsigned char IPR1 @ 0xF9F; #ifndef _LIB_BUILD asm("IPR1 equ 0F9Fh"); #endif // bitfield definitions typedef union { struct { unsigned TMR1IP :1; unsigned TMR2IP :1; unsigned TMR1GIP :1; unsigned SSPIP :1; unsigned TX1IP :1; unsigned RC1IP :1; unsigned ADIP :1; }; struct { unsigned :4; unsigned TXIP :1; unsigned RCIP :1; }; } IPR1bits_t; extern volatile IPR1bits_t IPR1bits @ 0xF9F; // bitfield macros #define _IPR1_TMR1IP_POSN 0x0 #define _IPR1_TMR1IP_POSITION 0x0 #define _IPR1_TMR1IP_SIZE 0x1 #define _IPR1_TMR1IP_LENGTH 0x1 #define _IPR1_TMR1IP_MASK 0x1 #define _IPR1_TMR2IP_POSN 0x1 #define _IPR1_TMR2IP_POSITION 0x1 #define _IPR1_TMR2IP_SIZE 0x1 #define _IPR1_TMR2IP_LENGTH 0x1 #define _IPR1_TMR2IP_MASK 0x2 #define _IPR1_TMR1GIP_POSN 0x2 #define _IPR1_TMR1GIP_POSITION 0x2 #define _IPR1_TMR1GIP_SIZE 0x1 #define _IPR1_TMR1GIP_LENGTH 0x1 #define _IPR1_TMR1GIP_MASK 0x4 #define _IPR1_SSPIP_POSN 0x3 #define _IPR1_SSPIP_POSITION 0x3 #define _IPR1_SSPIP_SIZE 0x1 #define _IPR1_SSPIP_LENGTH 0x1 #define _IPR1_SSPIP_MASK 0x8 #define _IPR1_TX1IP_POSN 0x4 #define _IPR1_TX1IP_POSITION 0x4 #define _IPR1_TX1IP_SIZE 0x1 #define _IPR1_TX1IP_LENGTH 0x1 #define _IPR1_TX1IP_MASK 0x10 #define _IPR1_RC1IP_POSN 0x5 #define _IPR1_RC1IP_POSITION 0x5 #define _IPR1_RC1IP_SIZE 0x1 #define _IPR1_RC1IP_LENGTH 0x1 #define _IPR1_RC1IP_MASK 0x20 #define _IPR1_ADIP_POSN 0x6 #define _IPR1_ADIP_POSITION 0x6 #define _IPR1_ADIP_SIZE 0x1 #define _IPR1_ADIP_LENGTH 0x1 #define _IPR1_ADIP_MASK 0x40 #define _IPR1_TXIP_POSN 0x4 #define _IPR1_TXIP_POSITION 0x4 #define _IPR1_TXIP_SIZE 0x1 #define _IPR1_TXIP_LENGTH 0x1 #define _IPR1_TXIP_MASK 0x10 #define _IPR1_RCIP_POSN 0x5 #define _IPR1_RCIP_POSITION 0x5 #define _IPR1_RCIP_SIZE 0x1 #define _IPR1_RCIP_LENGTH 0x1 #define _IPR1_RCIP_MASK 0x20 // Register: PIE2 #define PIE2 PIE2 extern volatile unsigned char PIE2 @ 0xFA0; #ifndef _LIB_BUILD asm("PIE2 equ 0FA0h"); #endif // bitfield definitions typedef union { struct { unsigned TMR3GIE :1; unsigned TMR3IE :1; unsigned HLVDIE :1; unsigned BCLIE :1; unsigned :3; unsigned OSCFIE :1; }; struct { unsigned :2; unsigned LVDIE :1; }; } PIE2bits_t; extern volatile PIE2bits_t PIE2bits @ 0xFA0; // bitfield macros #define _PIE2_TMR3GIE_POSN 0x0 #define _PIE2_TMR3GIE_POSITION 0x0 #define _PIE2_TMR3GIE_SIZE 0x1 #define _PIE2_TMR3GIE_LENGTH 0x1 #define _PIE2_TMR3GIE_MASK 0x1 #define _PIE2_TMR3IE_POSN 0x1 #define _PIE2_TMR3IE_POSITION 0x1 #define _PIE2_TMR3IE_SIZE 0x1 #define _PIE2_TMR3IE_LENGTH 0x1 #define _PIE2_TMR3IE_MASK 0x2 #define _PIE2_HLVDIE_POSN 0x2 #define _PIE2_HLVDIE_POSITION 0x2 #define _PIE2_HLVDIE_SIZE 0x1 #define _PIE2_HLVDIE_LENGTH 0x1 #define _PIE2_HLVDIE_MASK 0x4 #define _PIE2_BCLIE_POSN 0x3 #define _PIE2_BCLIE_POSITION 0x3 #define _PIE2_BCLIE_SIZE 0x1 #define _PIE2_BCLIE_LENGTH 0x1 #define _PIE2_BCLIE_MASK 0x8 #define _PIE2_OSCFIE_POSN 0x7 #define _PIE2_OSCFIE_POSITION 0x7 #define _PIE2_OSCFIE_SIZE 0x1 #define _PIE2_OSCFIE_LENGTH 0x1 #define _PIE2_OSCFIE_MASK 0x80 #define _PIE2_LVDIE_POSN 0x2 #define _PIE2_LVDIE_POSITION 0x2 #define _PIE2_LVDIE_SIZE 0x1 #define _PIE2_LVDIE_LENGTH 0x1 #define _PIE2_LVDIE_MASK 0x4 // Register: PIR2 #define PIR2 PIR2 extern volatile unsigned char PIR2 @ 0xFA1; #ifndef _LIB_BUILD asm("PIR2 equ 0FA1h"); #endif // bitfield definitions typedef union { struct { unsigned TMR3GIF :1; unsigned TMR3IF :1; unsigned HLVDIF :1; unsigned BCLIF :1; unsigned :3; unsigned OSCFIF :1; }; struct { unsigned :2; unsigned LVDIF :1; }; } PIR2bits_t; extern volatile PIR2bits_t PIR2bits @ 0xFA1; // bitfield macros #define _PIR2_TMR3GIF_POSN 0x0 #define _PIR2_TMR3GIF_POSITION 0x0 #define _PIR2_TMR3GIF_SIZE 0x1 #define _PIR2_TMR3GIF_LENGTH 0x1 #define _PIR2_TMR3GIF_MASK 0x1 #define _PIR2_TMR3IF_POSN 0x1 #define _PIR2_TMR3IF_POSITION 0x1 #define _PIR2_TMR3IF_SIZE 0x1 #define _PIR2_TMR3IF_LENGTH 0x1 #define _PIR2_TMR3IF_MASK 0x2 #define _PIR2_HLVDIF_POSN 0x2 #define _PIR2_HLVDIF_POSITION 0x2 #define _PIR2_HLVDIF_SIZE 0x1 #define _PIR2_HLVDIF_LENGTH 0x1 #define _PIR2_HLVDIF_MASK 0x4 #define _PIR2_BCLIF_POSN 0x3 #define _PIR2_BCLIF_POSITION 0x3 #define _PIR2_BCLIF_SIZE 0x1 #define _PIR2_BCLIF_LENGTH 0x1 #define _PIR2_BCLIF_MASK 0x8 #define _PIR2_OSCFIF_POSN 0x7 #define _PIR2_OSCFIF_POSITION 0x7 #define _PIR2_OSCFIF_SIZE 0x1 #define _PIR2_OSCFIF_LENGTH 0x1 #define _PIR2_OSCFIF_MASK 0x80 #define _PIR2_LVDIF_POSN 0x2 #define _PIR2_LVDIF_POSITION 0x2 #define _PIR2_LVDIF_SIZE 0x1 #define _PIR2_LVDIF_LENGTH 0x1 #define _PIR2_LVDIF_MASK 0x4 // Register: IPR2 #define IPR2 IPR2 extern volatile unsigned char IPR2 @ 0xFA2; #ifndef _LIB_BUILD asm("IPR2 equ 0FA2h"); #endif // bitfield definitions typedef union { struct { unsigned TMR3GIP :1; unsigned TMR3IP :1; unsigned HLVDIP :1; unsigned BCLIP :1; unsigned :3; unsigned OSCFIP :1; }; struct { unsigned :2; unsigned LVDIP :1; }; } IPR2bits_t; extern volatile IPR2bits_t IPR2bits @ 0xFA2; // bitfield macros #define _IPR2_TMR3GIP_POSN 0x0 #define _IPR2_TMR3GIP_POSITION 0x0 #define _IPR2_TMR3GIP_SIZE 0x1 #define _IPR2_TMR3GIP_LENGTH 0x1 #define _IPR2_TMR3GIP_MASK 0x1 #define _IPR2_TMR3IP_POSN 0x1 #define _IPR2_TMR3IP_POSITION 0x1 #define _IPR2_TMR3IP_SIZE 0x1 #define _IPR2_TMR3IP_LENGTH 0x1 #define _IPR2_TMR3IP_MASK 0x2 #define _IPR2_HLVDIP_POSN 0x2 #define _IPR2_HLVDIP_POSITION 0x2 #define _IPR2_HLVDIP_SIZE 0x1 #define _IPR2_HLVDIP_LENGTH 0x1 #define _IPR2_HLVDIP_MASK 0x4 #define _IPR2_BCLIP_POSN 0x3 #define _IPR2_BCLIP_POSITION 0x3 #define _IPR2_BCLIP_SIZE 0x1 #define _IPR2_BCLIP_LENGTH 0x1 #define _IPR2_BCLIP_MASK 0x8 #define _IPR2_OSCFIP_POSN 0x7 #define _IPR2_OSCFIP_POSITION 0x7 #define _IPR2_OSCFIP_SIZE 0x1 #define _IPR2_OSCFIP_LENGTH 0x1 #define _IPR2_OSCFIP_MASK 0x80 #define _IPR2_LVDIP_POSN 0x2 #define _IPR2_LVDIP_POSITION 0x2 #define _IPR2_LVDIP_SIZE 0x1 #define _IPR2_LVDIP_LENGTH 0x1 #define _IPR2_LVDIP_MASK 0x4 // Register: PIE3 #define PIE3 PIE3 extern volatile unsigned char PIE3 @ 0xFA3; #ifndef _LIB_BUILD asm("PIE3 equ 0FA3h"); #endif // bitfield definitions typedef union { struct { unsigned :1; unsigned CCP1IE :1; unsigned CCP2IE :1; unsigned CTMUIE :1; unsigned TX2IE :1; unsigned RC2IE :1; }; struct { unsigned :1; unsigned RXB1IE :1; unsigned TXB0IE :1; unsigned TXB1IE :1; unsigned TXB2IE :1; }; struct { unsigned :1; unsigned RXBNIE :1; unsigned :2; unsigned TXBNIE :1; }; } PIE3bits_t; extern volatile PIE3bits_t PIE3bits @ 0xFA3; // bitfield macros #define _PIE3_CCP1IE_POSN 0x1 #define _PIE3_CCP1IE_POSITION 0x1 #define _PIE3_CCP1IE_SIZE 0x1 #define _PIE3_CCP1IE_LENGTH 0x1 #define _PIE3_CCP1IE_MASK 0x2 #define _PIE3_CCP2IE_POSN 0x2 #define _PIE3_CCP2IE_POSITION 0x2 #define _PIE3_CCP2IE_SIZE 0x1 #define _PIE3_CCP2IE_LENGTH 0x1 #define _PIE3_CCP2IE_MASK 0x4 #define _PIE3_CTMUIE_POSN 0x3 #define _PIE3_CTMUIE_POSITION 0x3 #define _PIE3_CTMUIE_SIZE 0x1 #define _PIE3_CTMUIE_LENGTH 0x1 #define _PIE3_CTMUIE_MASK 0x8 #define _PIE3_TX2IE_POSN 0x4 #define _PIE3_TX2IE_POSITION 0x4 #define _PIE3_TX2IE_SIZE 0x1 #define _PIE3_TX2IE_LENGTH 0x1 #define _PIE3_TX2IE_MASK 0x10 #define _PIE3_RC2IE_POSN 0x5 #define _PIE3_RC2IE_POSITION 0x5 #define _PIE3_RC2IE_SIZE 0x1 #define _PIE3_RC2IE_LENGTH 0x1 #define _PIE3_RC2IE_MASK 0x20 #define _PIE3_RXB1IE_POSN 0x1 #define _PIE3_RXB1IE_POSITION 0x1 #define _PIE3_RXB1IE_SIZE 0x1 #define _PIE3_RXB1IE_LENGTH 0x1 #define _PIE3_RXB1IE_MASK 0x2 #define _PIE3_TXB0IE_POSN 0x2 #define _PIE3_TXB0IE_POSITION 0x2 #define _PIE3_TXB0IE_SIZE 0x1 #define _PIE3_TXB0IE_LENGTH 0x1 #define _PIE3_TXB0IE_MASK 0x4 #define _PIE3_TXB1IE_POSN 0x3 #define _PIE3_TXB1IE_POSITION 0x3 #define _PIE3_TXB1IE_SIZE 0x1 #define _PIE3_TXB1IE_LENGTH 0x1 #define _PIE3_TXB1IE_MASK 0x8 #define _PIE3_TXB2IE_POSN 0x4 #define _PIE3_TXB2IE_POSITION 0x4 #define _PIE3_TXB2IE_SIZE 0x1 #define _PIE3_TXB2IE_LENGTH 0x1 #define _PIE3_TXB2IE_MASK 0x10 #define _PIE3_RXBNIE_POSN 0x1 #define _PIE3_RXBNIE_POSITION 0x1 #define _PIE3_RXBNIE_SIZE 0x1 #define _PIE3_RXBNIE_LENGTH 0x1 #define _PIE3_RXBNIE_MASK 0x2 #define _PIE3_TXBNIE_POSN 0x4 #define _PIE3_TXBNIE_POSITION 0x4 #define _PIE3_TXBNIE_SIZE 0x1 #define _PIE3_TXBNIE_LENGTH 0x1 #define _PIE3_TXBNIE_MASK 0x10 // Register: PIR3 #define PIR3 PIR3 extern volatile unsigned char PIR3 @ 0xFA4; #ifndef _LIB_BUILD asm("PIR3 equ 0FA4h"); #endif // bitfield definitions typedef union { struct { unsigned :1; unsigned CCP1IF :1; unsigned CCP2IF :1; unsigned CTMUIF :1; unsigned TX2IF :1; unsigned RC2IF :1; }; struct { unsigned :1; unsigned RXBNIF :1; unsigned :2; unsigned TXBNIF :1; }; } PIR3bits_t; extern volatile PIR3bits_t PIR3bits @ 0xFA4; // bitfield macros #define _PIR3_CCP1IF_POSN 0x1 #define _PIR3_CCP1IF_POSITION 0x1 #define _PIR3_CCP1IF_SIZE 0x1 #define _PIR3_CCP1IF_LENGTH 0x1 #define _PIR3_CCP1IF_MASK 0x2 #define _PIR3_CCP2IF_POSN 0x2 #define _PIR3_CCP2IF_POSITION 0x2 #define _PIR3_CCP2IF_SIZE 0x1 #define _PIR3_CCP2IF_LENGTH 0x1 #define _PIR3_CCP2IF_MASK 0x4 #define _PIR3_CTMUIF_POSN 0x3 #define _PIR3_CTMUIF_POSITION 0x3 #define _PIR3_CTMUIF_SIZE 0x1 #define _PIR3_CTMUIF_LENGTH 0x1 #define _PIR3_CTMUIF_MASK 0x8 #define _PIR3_TX2IF_POSN 0x4 #define _PIR3_TX2IF_POSITION 0x4 #define _PIR3_TX2IF_SIZE 0x1 #define _PIR3_TX2IF_LENGTH 0x1 #define _PIR3_TX2IF_MASK 0x10 #define _PIR3_RC2IF_POSN 0x5 #define _PIR3_RC2IF_POSITION 0x5 #define _PIR3_RC2IF_SIZE 0x1 #define _PIR3_RC2IF_LENGTH 0x1 #define _PIR3_RC2IF_MASK 0x20 #define _PIR3_RXBNIF_POSN 0x1 #define _PIR3_RXBNIF_POSITION 0x1 #define _PIR3_RXBNIF_SIZE 0x1 #define _PIR3_RXBNIF_LENGTH 0x1 #define _PIR3_RXBNIF_MASK 0x2 #define _PIR3_TXBNIF_POSN 0x4 #define _PIR3_TXBNIF_POSITION 0x4 #define _PIR3_TXBNIF_SIZE 0x1 #define _PIR3_TXBNIF_LENGTH 0x1 #define _PIR3_TXBNIF_MASK 0x10 // Register: IPR3 #define IPR3 IPR3 extern volatile unsigned char IPR3 @ 0xFA5; #ifndef _LIB_BUILD asm("IPR3 equ 0FA5h"); #endif // bitfield definitions typedef union { struct { unsigned :1; unsigned CCP1IP :1; unsigned CCP2IP :1; unsigned CTMUIP :1; unsigned TX2IP :1; unsigned RC2IP :1; }; struct { unsigned :1; unsigned RXBNIP :1; unsigned :2; unsigned TXBNIP :1; }; } IPR3bits_t; extern volatile IPR3bits_t IPR3bits @ 0xFA5; // bitfield macros #define _IPR3_CCP1IP_POSN 0x1 #define _IPR3_CCP1IP_POSITION 0x1 #define _IPR3_CCP1IP_SIZE 0x1 #define _IPR3_CCP1IP_LENGTH 0x1 #define _IPR3_CCP1IP_MASK 0x2 #define _IPR3_CCP2IP_POSN 0x2 #define _IPR3_CCP2IP_POSITION 0x2 #define _IPR3_CCP2IP_SIZE 0x1 #define _IPR3_CCP2IP_LENGTH 0x1 #define _IPR3_CCP2IP_MASK 0x4 #define _IPR3_CTMUIP_POSN 0x3 #define _IPR3_CTMUIP_POSITION 0x3 #define _IPR3_CTMUIP_SIZE 0x1 #define _IPR3_CTMUIP_LENGTH 0x1 #define _IPR3_CTMUIP_MASK 0x8 #define _IPR3_TX2IP_POSN 0x4 #define _IPR3_TX2IP_POSITION 0x4 #define _IPR3_TX2IP_SIZE 0x1 #define _IPR3_TX2IP_LENGTH 0x1 #define _IPR3_TX2IP_MASK 0x10 #define _IPR3_RC2IP_POSN 0x5 #define _IPR3_RC2IP_POSITION 0x5 #define _IPR3_RC2IP_SIZE 0x1 #define _IPR3_RC2IP_LENGTH 0x1 #define _IPR3_RC2IP_MASK 0x20 #define _IPR3_RXBNIP_POSN 0x1 #define _IPR3_RXBNIP_POSITION 0x1 #define _IPR3_RXBNIP_SIZE 0x1 #define _IPR3_RXBNIP_LENGTH 0x1 #define _IPR3_RXBNIP_MASK 0x2 #define _IPR3_TXBNIP_POSN 0x4 #define _IPR3_TXBNIP_POSITION 0x4 #define _IPR3_TXBNIP_SIZE 0x1 #define _IPR3_TXBNIP_LENGTH 0x1 #define _IPR3_TXBNIP_MASK 0x10 // Register: RCSTA2 #define RCSTA2 RCSTA2 extern volatile unsigned char RCSTA2 @ 0xFA6; #ifndef _LIB_BUILD asm("RCSTA2 equ 0FA6h"); #endif // bitfield definitions typedef union { struct { unsigned RX9D :1; unsigned OERR :1; unsigned FERR :1; unsigned ADDEN :1; unsigned CREN :1; unsigned SREN :1; unsigned RX9 :1; unsigned SPEN :1; }; struct { unsigned RX9D2 :1; unsigned OERR2 :1; unsigned FERR2 :1; unsigned ADDEN2 :1; unsigned CREN2 :1; unsigned SREN2 :1; unsigned RX92 :1; unsigned SPEN2 :1; }; struct { unsigned RCD82 :1; unsigned :5; unsigned RC8_92 :1; }; struct { unsigned :6; unsigned RC92 :1; }; } RCSTA2bits_t; extern volatile RCSTA2bits_t RCSTA2bits @ 0xFA6; // bitfield macros #define _RCSTA2_RX9D_POSN 0x0 #define _RCSTA2_RX9D_POSITION 0x0 #define _RCSTA2_RX9D_SIZE 0x1 #define _RCSTA2_RX9D_LENGTH 0x1 #define _RCSTA2_RX9D_MASK 0x1 #define _RCSTA2_OERR_POSN 0x1 #define _RCSTA2_OERR_POSITION 0x1 #define _RCSTA2_OERR_SIZE 0x1 #define _RCSTA2_OERR_LENGTH 0x1 #define _RCSTA2_OERR_MASK 0x2 #define _RCSTA2_FERR_POSN 0x2 #define _RCSTA2_FERR_POSITION 0x2 #define _RCSTA2_FERR_SIZE 0x1 #define _RCSTA2_FERR_LENGTH 0x1 #define _RCSTA2_FERR_MASK 0x4 #define _RCSTA2_ADDEN_POSN 0x3 #define _RCSTA2_ADDEN_POSITION 0x3 #define _RCSTA2_ADDEN_SIZE 0x1 #define _RCSTA2_ADDEN_LENGTH 0x1 #define _RCSTA2_ADDEN_MASK 0x8 #define _RCSTA2_CREN_POSN 0x4 #define _RCSTA2_CREN_POSITION 0x4 #define _RCSTA2_CREN_SIZE 0x1 #define _RCSTA2_CREN_LENGTH 0x1 #define _RCSTA2_CREN_MASK 0x10 #define _RCSTA2_SREN_POSN 0x5 #define _RCSTA2_SREN_POSITION 0x5 #define _RCSTA2_SREN_SIZE 0x1 #define _RCSTA2_SREN_LENGTH 0x1 #define _RCSTA2_SREN_MASK 0x20 #define _RCSTA2_RX9_POSN 0x6 #define _RCSTA2_RX9_POSITION 0x6 #define _RCSTA2_RX9_SIZE 0x1 #define _RCSTA2_RX9_LENGTH 0x1 #define _RCSTA2_RX9_MASK 0x40 #define _RCSTA2_SPEN_POSN 0x7 #define _RCSTA2_SPEN_POSITION 0x7 #define _RCSTA2_SPEN_SIZE 0x1 #define _RCSTA2_SPEN_LENGTH 0x1 #define _RCSTA2_SPEN_MASK 0x80 #define _RCSTA2_RX9D2_POSN 0x0 #define _RCSTA2_RX9D2_POSITION 0x0 #define _RCSTA2_RX9D2_SIZE 0x1 #define _RCSTA2_RX9D2_LENGTH 0x1 #define _RCSTA2_RX9D2_MASK 0x1 #define _RCSTA2_OERR2_POSN 0x1 #define _RCSTA2_OERR2_POSITION 0x1 #define _RCSTA2_OERR2_SIZE 0x1 #define _RCSTA2_OERR2_LENGTH 0x1 #define _RCSTA2_OERR2_MASK 0x2 #define _RCSTA2_FERR2_POSN 0x2 #define _RCSTA2_FERR2_POSITION 0x2 #define _RCSTA2_FERR2_SIZE 0x1 #define _RCSTA2_FERR2_LENGTH 0x1 #define _RCSTA2_FERR2_MASK 0x4 #define _RCSTA2_ADDEN2_POSN 0x3 #define _RCSTA2_ADDEN2_POSITION 0x3 #define _RCSTA2_ADDEN2_SIZE 0x1 #define _RCSTA2_ADDEN2_LENGTH 0x1 #define _RCSTA2_ADDEN2_MASK 0x8 #define _RCSTA2_CREN2_POSN 0x4 #define _RCSTA2_CREN2_POSITION 0x4 #define _RCSTA2_CREN2_SIZE 0x1 #define _RCSTA2_CREN2_LENGTH 0x1 #define _RCSTA2_CREN2_MASK 0x10 #define _RCSTA2_SREN2_POSN 0x5 #define _RCSTA2_SREN2_POSITION 0x5 #define _RCSTA2_SREN2_SIZE 0x1 #define _RCSTA2_SREN2_LENGTH 0x1 #define _RCSTA2_SREN2_MASK 0x20 #define _RCSTA2_RX92_POSN 0x6 #define _RCSTA2_RX92_POSITION 0x6 #define _RCSTA2_RX92_SIZE 0x1 #define _RCSTA2_RX92_LENGTH 0x1 #define _RCSTA2_RX92_MASK 0x40 #define _RCSTA2_SPEN2_POSN 0x7 #define _RCSTA2_SPEN2_POSITION 0x7 #define _RCSTA2_SPEN2_SIZE 0x1 #define _RCSTA2_SPEN2_LENGTH 0x1 #define _RCSTA2_SPEN2_MASK 0x80 #define _RCSTA2_RCD82_POSN 0x0 #define _RCSTA2_RCD82_POSITION 0x0 #define _RCSTA2_RCD82_SIZE 0x1 #define _RCSTA2_RCD82_LENGTH 0x1 #define _RCSTA2_RCD82_MASK 0x1 #define _RCSTA2_RC8_92_POSN 0x6 #define _RCSTA2_RC8_92_POSITION 0x6 #define _RCSTA2_RC8_92_SIZE 0x1 #define _RCSTA2_RC8_92_LENGTH 0x1 #define _RCSTA2_RC8_92_MASK 0x40 #define _RCSTA2_RC92_POSN 0x6 #define _RCSTA2_RC92_POSITION 0x6 #define _RCSTA2_RC92_SIZE 0x1 #define _RCSTA2_RC92_LENGTH 0x1 #define _RCSTA2_RC92_MASK 0x40 // Register: BAUDCON1 #define BAUDCON1 BAUDCON1 extern volatile unsigned char BAUDCON1 @ 0xFA7; #ifndef _LIB_BUILD asm("BAUDCON1 equ 0FA7h"); #endif // bitfield definitions typedef union { struct { unsigned ABDEN :1; unsigned WUE :1; unsigned :1; unsigned BRG16 :1; unsigned TXCKP :1; unsigned RXDTP :1; unsigned RCIDL :1; unsigned ABDOVF :1; }; struct { unsigned :6; unsigned RCMT :1; }; struct { unsigned ABDEN1 :1; unsigned WUE1 :1; unsigned :1; unsigned BRG161 :1; unsigned CKTXP :1; unsigned DTRXP :1; unsigned RCIDL1 :1; unsigned ABDOVF1 :1; }; struct { unsigned :4; unsigned SCKP :1; unsigned DTRXP1 :1; unsigned RCMT1 :1; }; struct { unsigned :4; unsigned SCKP1 :1; unsigned RXDTP1 :1; }; struct { unsigned :4; unsigned TXCKP1 :1; }; } BAUDCON1bits_t; extern volatile BAUDCON1bits_t BAUDCON1bits @ 0xFA7; // bitfield macros #define _BAUDCON1_ABDEN_POSN 0x0 #define _BAUDCON1_ABDEN_POSITION 0x0 #define _BAUDCON1_ABDEN_SIZE 0x1 #define _BAUDCON1_ABDEN_LENGTH 0x1 #define _BAUDCON1_ABDEN_MASK 0x1 #define _BAUDCON1_WUE_POSN 0x1 #define _BAUDCON1_WUE_POSITION 0x1 #define _BAUDCON1_WUE_SIZE 0x1 #define _BAUDCON1_WUE_LENGTH 0x1 #define _BAUDCON1_WUE_MASK 0x2 #define _BAUDCON1_BRG16_POSN 0x3 #define _BAUDCON1_BRG16_POSITION 0x3 #define _BAUDCON1_BRG16_SIZE 0x1 #define _BAUDCON1_BRG16_LENGTH 0x1 #define _BAUDCON1_BRG16_MASK 0x8 #define _BAUDCON1_TXCKP_POSN 0x4 #define _BAUDCON1_TXCKP_POSITION 0x4 #define _BAUDCON1_TXCKP_SIZE 0x1 #define _BAUDCON1_TXCKP_LENGTH 0x1 #define _BAUDCON1_TXCKP_MASK 0x10 #define _BAUDCON1_RXDTP_POSN 0x5 #define _BAUDCON1_RXDTP_POSITION 0x5 #define _BAUDCON1_RXDTP_SIZE 0x1 #define _BAUDCON1_RXDTP_LENGTH 0x1 #define _BAUDCON1_RXDTP_MASK 0x20 #define _BAUDCON1_RCIDL_POSN 0x6 #define _BAUDCON1_RCIDL_POSITION 0x6 #define _BAUDCON1_RCIDL_SIZE 0x1 #define _BAUDCON1_RCIDL_LENGTH 0x1 #define _BAUDCON1_RCIDL_MASK 0x40 #define _BAUDCON1_ABDOVF_POSN 0x7 #define _BAUDCON1_ABDOVF_POSITION 0x7 #define _BAUDCON1_ABDOVF_SIZE 0x1 #define _BAUDCON1_ABDOVF_LENGTH 0x1 #define _BAUDCON1_ABDOVF_MASK 0x80 #define _BAUDCON1_RCMT_POSN 0x6 #define _BAUDCON1_RCMT_POSITION 0x6 #define _BAUDCON1_RCMT_SIZE 0x1 #define _BAUDCON1_RCMT_LENGTH 0x1 #define _BAUDCON1_RCMT_MASK 0x40 #define _BAUDCON1_ABDEN1_POSN 0x0 #define _BAUDCON1_ABDEN1_POSITION 0x0 #define _BAUDCON1_ABDEN1_SIZE 0x1 #define _BAUDCON1_ABDEN1_LENGTH 0x1 #define _BAUDCON1_ABDEN1_MASK 0x1 #define _BAUDCON1_WUE1_POSN 0x1 #define _BAUDCON1_WUE1_POSITION 0x1 #define _BAUDCON1_WUE1_SIZE 0x1 #define _BAUDCON1_WUE1_LENGTH 0x1 #define _BAUDCON1_WUE1_MASK 0x2 #define _BAUDCON1_BRG161_POSN 0x3 #define _BAUDCON1_BRG161_POSITION 0x3 #define _BAUDCON1_BRG161_SIZE 0x1 #define _BAUDCON1_BRG161_LENGTH 0x1 #define _BAUDCON1_BRG161_MASK 0x8 #define _BAUDCON1_CKTXP_POSN 0x4 #define _BAUDCON1_CKTXP_POSITION 0x4 #define _BAUDCON1_CKTXP_SIZE 0x1 #define _BAUDCON1_CKTXP_LENGTH 0x1 #define _BAUDCON1_CKTXP_MASK 0x10 #define _BAUDCON1_DTRXP_POSN 0x5 #define _BAUDCON1_DTRXP_POSITION 0x5 #define _BAUDCON1_DTRXP_SIZE 0x1 #define _BAUDCON1_DTRXP_LENGTH 0x1 #define _BAUDCON1_DTRXP_MASK 0x20 #define _BAUDCON1_RCIDL1_POSN 0x6 #define _BAUDCON1_RCIDL1_POSITION 0x6 #define _BAUDCON1_RCIDL1_SIZE 0x1 #define _BAUDCON1_RCIDL1_LENGTH 0x1 #define _BAUDCON1_RCIDL1_MASK 0x40 #define _BAUDCON1_ABDOVF1_POSN 0x7 #define _BAUDCON1_ABDOVF1_POSITION 0x7 #define _BAUDCON1_ABDOVF1_SIZE 0x1 #define _BAUDCON1_ABDOVF1_LENGTH 0x1 #define _BAUDCON1_ABDOVF1_MASK 0x80 #define _BAUDCON1_SCKP_POSN 0x4 #define _BAUDCON1_SCKP_POSITION 0x4 #define _BAUDCON1_SCKP_SIZE 0x1 #define _BAUDCON1_SCKP_LENGTH 0x1 #define _BAUDCON1_SCKP_MASK 0x10 #define _BAUDCON1_DTRXP1_POSN 0x5 #define _BAUDCON1_DTRXP1_POSITION 0x5 #define _BAUDCON1_DTRXP1_SIZE 0x1 #define _BAUDCON1_DTRXP1_LENGTH 0x1 #define _BAUDCON1_DTRXP1_MASK 0x20 #define _BAUDCON1_RCMT1_POSN 0x6 #define _BAUDCON1_RCMT1_POSITION 0x6 #define _BAUDCON1_RCMT1_SIZE 0x1 #define _BAUDCON1_RCMT1_LENGTH 0x1 #define _BAUDCON1_RCMT1_MASK 0x40 #define _BAUDCON1_SCKP1_POSN 0x4 #define _BAUDCON1_SCKP1_POSITION 0x4 #define _BAUDCON1_SCKP1_SIZE 0x1 #define _BAUDCON1_SCKP1_LENGTH 0x1 #define _BAUDCON1_SCKP1_MASK 0x10 #define _BAUDCON1_RXDTP1_POSN 0x5 #define _BAUDCON1_RXDTP1_POSITION 0x5 #define _BAUDCON1_RXDTP1_SIZE 0x1 #define _BAUDCON1_RXDTP1_LENGTH 0x1 #define _BAUDCON1_RXDTP1_MASK 0x20 #define _BAUDCON1_TXCKP1_POSN 0x4 #define _BAUDCON1_TXCKP1_POSITION 0x4 #define _BAUDCON1_TXCKP1_SIZE 0x1 #define _BAUDCON1_TXCKP1_LENGTH 0x1 #define _BAUDCON1_TXCKP1_MASK 0x10 // Register: HLVDCON #define HLVDCON HLVDCON extern volatile unsigned char HLVDCON @ 0xFA8; #ifndef _LIB_BUILD asm("HLVDCON equ 0FA8h"); #endif // bitfield definitions typedef union { struct { unsigned HLVDL :4; unsigned HLVDEN :1; unsigned IRVST :1; unsigned BGVST :1; unsigned VDIRMAG :1; }; struct { unsigned HLVDL0 :1; unsigned HLVDL1 :1; unsigned HLVDL2 :1; unsigned HLVDL3 :1; }; } HLVDCONbits_t; extern volatile HLVDCONbits_t HLVDCONbits @ 0xFA8; // bitfield macros #define _HLVDCON_HLVDL_POSN 0x0 #define _HLVDCON_HLVDL_POSITION 0x0 #define _HLVDCON_HLVDL_SIZE 0x4 #define _HLVDCON_HLVDL_LENGTH 0x4 #define _HLVDCON_HLVDL_MASK 0xF #define _HLVDCON_HLVDEN_POSN 0x4 #define _HLVDCON_HLVDEN_POSITION 0x4 #define _HLVDCON_HLVDEN_SIZE 0x1 #define _HLVDCON_HLVDEN_LENGTH 0x1 #define _HLVDCON_HLVDEN_MASK 0x10 #define _HLVDCON_IRVST_POSN 0x5 #define _HLVDCON_IRVST_POSITION 0x5 #define _HLVDCON_IRVST_SIZE 0x1 #define _HLVDCON_IRVST_LENGTH 0x1 #define _HLVDCON_IRVST_MASK 0x20 #define _HLVDCON_BGVST_POSN 0x6 #define _HLVDCON_BGVST_POSITION 0x6 #define _HLVDCON_BGVST_SIZE 0x1 #define _HLVDCON_BGVST_LENGTH 0x1 #define _HLVDCON_BGVST_MASK 0x40 #define _HLVDCON_VDIRMAG_POSN 0x7 #define _HLVDCON_VDIRMAG_POSITION 0x7 #define _HLVDCON_VDIRMAG_SIZE 0x1 #define _HLVDCON_VDIRMAG_LENGTH 0x1 #define _HLVDCON_VDIRMAG_MASK 0x80 #define _HLVDCON_HLVDL0_POSN 0x0 #define _HLVDCON_HLVDL0_POSITION 0x0 #define _HLVDCON_HLVDL0_SIZE 0x1 #define _HLVDCON_HLVDL0_LENGTH 0x1 #define _HLVDCON_HLVDL0_MASK 0x1 #define _HLVDCON_HLVDL1_POSN 0x1 #define _HLVDCON_HLVDL1_POSITION 0x1 #define _HLVDCON_HLVDL1_SIZE 0x1 #define _HLVDCON_HLVDL1_LENGTH 0x1 #define _HLVDCON_HLVDL1_MASK 0x2 #define _HLVDCON_HLVDL2_POSN 0x2 #define _HLVDCON_HLVDL2_POSITION 0x2 #define _HLVDCON_HLVDL2_SIZE 0x1 #define _HLVDCON_HLVDL2_LENGTH 0x1 #define _HLVDCON_HLVDL2_MASK 0x4 #define _HLVDCON_HLVDL3_POSN 0x3 #define _HLVDCON_HLVDL3_POSITION 0x3 #define _HLVDCON_HLVDL3_SIZE 0x1 #define _HLVDCON_HLVDL3_LENGTH 0x1 #define _HLVDCON_HLVDL3_MASK 0x8 // Register: PR4 #define PR4 PR4 extern volatile unsigned char PR4 @ 0xFA9; #ifndef _LIB_BUILD asm("PR4 equ 0FA9h"); #endif // bitfield definitions typedef union { struct { unsigned PR4 :8; }; } PR4bits_t; extern volatile PR4bits_t PR4bits @ 0xFA9; // bitfield macros #define _PR4_PR4_POSN 0x0 #define _PR4_PR4_POSITION 0x0 #define _PR4_PR4_SIZE 0x8 #define _PR4_PR4_LENGTH 0x8 #define _PR4_PR4_MASK 0xFF // Register: T1GCON #define T1GCON T1GCON extern volatile unsigned char T1GCON @ 0xFAA; #ifndef _LIB_BUILD asm("T1GCON equ 0FAAh"); #endif // bitfield definitions typedef union { struct { unsigned :3; unsigned T1GGO_NOT_T1DONE :1; }; struct { unsigned T1GSS :2; unsigned T1GVAL :1; unsigned T1GGO_nT1DONE :1; unsigned T1GSPM :1; unsigned T1GTM :1; unsigned T1GPOL :1; unsigned TMR1GE :1; }; struct { unsigned T1GSS0 :1; unsigned T1GSS1 :1; unsigned :1; unsigned T1GGO :1; }; struct { unsigned :3; unsigned NOT_T1DONE :1; }; struct { unsigned :3; unsigned nT1DONE :1; }; } T1GCONbits_t; extern volatile T1GCONbits_t T1GCONbits @ 0xFAA; // bitfield macros #define _T1GCON_T1GGO_NOT_T1DONE_POSN 0x3 #define _T1GCON_T1GGO_NOT_T1DONE_POSITION 0x3 #define _T1GCON_T1GGO_NOT_T1DONE_SIZE 0x1 #define _T1GCON_T1GGO_NOT_T1DONE_LENGTH 0x1 #define _T1GCON_T1GGO_NOT_T1DONE_MASK 0x8 #define _T1GCON_T1GSS_POSN 0x0 #define _T1GCON_T1GSS_POSITION 0x0 #define _T1GCON_T1GSS_SIZE 0x2 #define _T1GCON_T1GSS_LENGTH 0x2 #define _T1GCON_T1GSS_MASK 0x3 #define _T1GCON_T1GVAL_POSN 0x2 #define _T1GCON_T1GVAL_POSITION 0x2 #define _T1GCON_T1GVAL_SIZE 0x1 #define _T1GCON_T1GVAL_LENGTH 0x1 #define _T1GCON_T1GVAL_MASK 0x4 #define _T1GCON_T1GGO_nT1DONE_POSN 0x3 #define _T1GCON_T1GGO_nT1DONE_POSITION 0x3 #define _T1GCON_T1GGO_nT1DONE_SIZE 0x1 #define _T1GCON_T1GGO_nT1DONE_LENGTH 0x1 #define _T1GCON_T1GGO_nT1DONE_MASK 0x8 #define _T1GCON_T1GSPM_POSN 0x4 #define _T1GCON_T1GSPM_POSITION 0x4 #define _T1GCON_T1GSPM_SIZE 0x1 #define _T1GCON_T1GSPM_LENGTH 0x1 #define _T1GCON_T1GSPM_MASK 0x10 #define _T1GCON_T1GTM_POSN 0x5 #define _T1GCON_T1GTM_POSITION 0x5 #define _T1GCON_T1GTM_SIZE 0x1 #define _T1GCON_T1GTM_LENGTH 0x1 #define _T1GCON_T1GTM_MASK 0x20 #define _T1GCON_T1GPOL_POSN 0x6 #define _T1GCON_T1GPOL_POSITION 0x6 #define _T1GCON_T1GPOL_SIZE 0x1 #define _T1GCON_T1GPOL_LENGTH 0x1 #define _T1GCON_T1GPOL_MASK 0x40 #define _T1GCON_TMR1GE_POSN 0x7 #define _T1GCON_TMR1GE_POSITION 0x7 #define _T1GCON_TMR1GE_SIZE 0x1 #define _T1GCON_TMR1GE_LENGTH 0x1 #define _T1GCON_TMR1GE_MASK 0x80 #define _T1GCON_T1GSS0_POSN 0x0 #define _T1GCON_T1GSS0_POSITION 0x0 #define _T1GCON_T1GSS0_SIZE 0x1 #define _T1GCON_T1GSS0_LENGTH 0x1 #define _T1GCON_T1GSS0_MASK 0x1 #define _T1GCON_T1GSS1_POSN 0x1 #define _T1GCON_T1GSS1_POSITION 0x1 #define _T1GCON_T1GSS1_SIZE 0x1 #define _T1GCON_T1GSS1_LENGTH 0x1 #define _T1GCON_T1GSS1_MASK 0x2 #define _T1GCON_T1GGO_POSN 0x3 #define _T1GCON_T1GGO_POSITION 0x3 #define _T1GCON_T1GGO_SIZE 0x1 #define _T1GCON_T1GGO_LENGTH 0x1 #define _T1GCON_T1GGO_MASK 0x8 #define _T1GCON_NOT_T1DONE_POSN 0x3 #define _T1GCON_NOT_T1DONE_POSITION 0x3 #define _T1GCON_NOT_T1DONE_SIZE 0x1 #define _T1GCON_NOT_T1DONE_LENGTH 0x1 #define _T1GCON_NOT_T1DONE_MASK 0x8 #define _T1GCON_nT1DONE_POSN 0x3 #define _T1GCON_nT1DONE_POSITION 0x3 #define _T1GCON_nT1DONE_SIZE 0x1 #define _T1GCON_nT1DONE_LENGTH 0x1 #define _T1GCON_nT1DONE_MASK 0x8 // Register: RCSTA1 #define RCSTA1 RCSTA1 extern volatile unsigned char RCSTA1 @ 0xFAB; #ifndef _LIB_BUILD asm("RCSTA1 equ 0FABh"); #endif // aliases extern volatile unsigned char RCSTA @ 0xFAB; #ifndef _LIB_BUILD asm("RCSTA equ 0FABh"); #endif // bitfield definitions typedef union { struct { unsigned RX9D :1; unsigned OERR :1; unsigned FERR :1; unsigned ADDEN :1; unsigned CREN :1; unsigned SREN :1; unsigned RX9 :1; unsigned SPEN :1; }; struct { unsigned RCD8 :1; unsigned :2; unsigned ADEN :1; unsigned :2; unsigned RC9 :1; }; struct { unsigned :6; unsigned NOT_RC8 :1; }; struct { unsigned :6; unsigned nRC8 :1; }; struct { unsigned :6; unsigned RC8_9 :1; }; struct { unsigned RX9D1 :1; unsigned OERR1 :1; unsigned FERR1 :1; unsigned ADDEN1 :1; unsigned CREN1 :1; unsigned SREN1 :1; unsigned RX91 :1; unsigned SPEN1 :1; }; struct { unsigned :5; unsigned SRENA :1; }; } RCSTA1bits_t; extern volatile RCSTA1bits_t RCSTA1bits @ 0xFAB; // bitfield macros #define _RCSTA1_RX9D_POSN 0x0 #define _RCSTA1_RX9D_POSITION 0x0 #define _RCSTA1_RX9D_SIZE 0x1 #define _RCSTA1_RX9D_LENGTH 0x1 #define _RCSTA1_RX9D_MASK 0x1 #define _RCSTA1_OERR_POSN 0x1 #define _RCSTA1_OERR_POSITION 0x1 #define _RCSTA1_OERR_SIZE 0x1 #define _RCSTA1_OERR_LENGTH 0x1 #define _RCSTA1_OERR_MASK 0x2 #define _RCSTA1_FERR_POSN 0x2 #define _RCSTA1_FERR_POSITION 0x2 #define _RCSTA1_FERR_SIZE 0x1 #define _RCSTA1_FERR_LENGTH 0x1 #define _RCSTA1_FERR_MASK 0x4 #define _RCSTA1_ADDEN_POSN 0x3 #define _RCSTA1_ADDEN_POSITION 0x3 #define _RCSTA1_ADDEN_SIZE 0x1 #define _RCSTA1_ADDEN_LENGTH 0x1 #define _RCSTA1_ADDEN_MASK 0x8 #define _RCSTA1_CREN_POSN 0x4 #define _RCSTA1_CREN_POSITION 0x4 #define _RCSTA1_CREN_SIZE 0x1 #define _RCSTA1_CREN_LENGTH 0x1 #define _RCSTA1_CREN_MASK 0x10 #define _RCSTA1_SREN_POSN 0x5 #define _RCSTA1_SREN_POSITION 0x5 #define _RCSTA1_SREN_SIZE 0x1 #define _RCSTA1_SREN_LENGTH 0x1 #define _RCSTA1_SREN_MASK 0x20 #define _RCSTA1_RX9_POSN 0x6 #define _RCSTA1_RX9_POSITION 0x6 #define _RCSTA1_RX9_SIZE 0x1 #define _RCSTA1_RX9_LENGTH 0x1 #define _RCSTA1_RX9_MASK 0x40 #define _RCSTA1_SPEN_POSN 0x7 #define _RCSTA1_SPEN_POSITION 0x7 #define _RCSTA1_SPEN_SIZE 0x1 #define _RCSTA1_SPEN_LENGTH 0x1 #define _RCSTA1_SPEN_MASK 0x80 #define _RCSTA1_RCD8_POSN 0x0 #define _RCSTA1_RCD8_POSITION 0x0 #define _RCSTA1_RCD8_SIZE 0x1 #define _RCSTA1_RCD8_LENGTH 0x1 #define _RCSTA1_RCD8_MASK 0x1 #define _RCSTA1_ADEN_POSN 0x3 #define _RCSTA1_ADEN_POSITION 0x3 #define _RCSTA1_ADEN_SIZE 0x1 #define _RCSTA1_ADEN_LENGTH 0x1 #define _RCSTA1_ADEN_MASK 0x8 #define _RCSTA1_RC9_POSN 0x6 #define _RCSTA1_RC9_POSITION 0x6 #define _RCSTA1_RC9_SIZE 0x1 #define _RCSTA1_RC9_LENGTH 0x1 #define _RCSTA1_RC9_MASK 0x40 #define _RCSTA1_NOT_RC8_POSN 0x6 #define _RCSTA1_NOT_RC8_POSITION 0x6 #define _RCSTA1_NOT_RC8_SIZE 0x1 #define _RCSTA1_NOT_RC8_LENGTH 0x1 #define _RCSTA1_NOT_RC8_MASK 0x40 #define _RCSTA1_nRC8_POSN 0x6 #define _RCSTA1_nRC8_POSITION 0x6 #define _RCSTA1_nRC8_SIZE 0x1 #define _RCSTA1_nRC8_LENGTH 0x1 #define _RCSTA1_nRC8_MASK 0x40 #define _RCSTA1_RC8_9_POSN 0x6 #define _RCSTA1_RC8_9_POSITION 0x6 #define _RCSTA1_RC8_9_SIZE 0x1 #define _RCSTA1_RC8_9_LENGTH 0x1 #define _RCSTA1_RC8_9_MASK 0x40 #define _RCSTA1_RX9D1_POSN 0x0 #define _RCSTA1_RX9D1_POSITION 0x0 #define _RCSTA1_RX9D1_SIZE 0x1 #define _RCSTA1_RX9D1_LENGTH 0x1 #define _RCSTA1_RX9D1_MASK 0x1 #define _RCSTA1_OERR1_POSN 0x1 #define _RCSTA1_OERR1_POSITION 0x1 #define _RCSTA1_OERR1_SIZE 0x1 #define _RCSTA1_OERR1_LENGTH 0x1 #define _RCSTA1_OERR1_MASK 0x2 #define _RCSTA1_FERR1_POSN 0x2 #define _RCSTA1_FERR1_POSITION 0x2 #define _RCSTA1_FERR1_SIZE 0x1 #define _RCSTA1_FERR1_LENGTH 0x1 #define _RCSTA1_FERR1_MASK 0x4 #define _RCSTA1_ADDEN1_POSN 0x3 #define _RCSTA1_ADDEN1_POSITION 0x3 #define _RCSTA1_ADDEN1_SIZE 0x1 #define _RCSTA1_ADDEN1_LENGTH 0x1 #define _RCSTA1_ADDEN1_MASK 0x8 #define _RCSTA1_CREN1_POSN 0x4 #define _RCSTA1_CREN1_POSITION 0x4 #define _RCSTA1_CREN1_SIZE 0x1 #define _RCSTA1_CREN1_LENGTH 0x1 #define _RCSTA1_CREN1_MASK 0x10 #define _RCSTA1_SREN1_POSN 0x5 #define _RCSTA1_SREN1_POSITION 0x5 #define _RCSTA1_SREN1_SIZE 0x1 #define _RCSTA1_SREN1_LENGTH 0x1 #define _RCSTA1_SREN1_MASK 0x20 #define _RCSTA1_RX91_POSN 0x6 #define _RCSTA1_RX91_POSITION 0x6 #define _RCSTA1_RX91_SIZE 0x1 #define _RCSTA1_RX91_LENGTH 0x1 #define _RCSTA1_RX91_MASK 0x40 #define _RCSTA1_SPEN1_POSN 0x7 #define _RCSTA1_SPEN1_POSITION 0x7 #define _RCSTA1_SPEN1_SIZE 0x1 #define _RCSTA1_SPEN1_LENGTH 0x1 #define _RCSTA1_SPEN1_MASK 0x80 #define _RCSTA1_SRENA_POSN 0x5 #define _RCSTA1_SRENA_POSITION 0x5 #define _RCSTA1_SRENA_SIZE 0x1 #define _RCSTA1_SRENA_LENGTH 0x1 #define _RCSTA1_SRENA_MASK 0x20 // alias bitfield definitions typedef union { struct { unsigned RX9D :1; unsigned OERR :1; unsigned FERR :1; unsigned ADDEN :1; unsigned CREN :1; unsigned SREN :1; unsigned RX9 :1; unsigned SPEN :1; }; struct { unsigned RCD8 :1; unsigned :2; unsigned ADEN :1; unsigned :2; unsigned RC9 :1; }; struct { unsigned :6; unsigned NOT_RC8 :1; }; struct { unsigned :6; unsigned nRC8 :1; }; struct { unsigned :6; unsigned RC8_9 :1; }; struct { unsigned RX9D1 :1; unsigned OERR1 :1; unsigned FERR1 :1; unsigned ADDEN1 :1; unsigned CREN1 :1; unsigned SREN1 :1; unsigned RX91 :1; unsigned SPEN1 :1; }; struct { unsigned :5; unsigned SRENA :1; }; } RCSTAbits_t; extern volatile RCSTAbits_t RCSTAbits @ 0xFAB; // bitfield macros #define _RCSTA_RX9D_POSN 0x0 #define _RCSTA_RX9D_POSITION 0x0 #define _RCSTA_RX9D_SIZE 0x1 #define _RCSTA_RX9D_LENGTH 0x1 #define _RCSTA_RX9D_MASK 0x1 #define _RCSTA_OERR_POSN 0x1 #define _RCSTA_OERR_POSITION 0x1 #define _RCSTA_OERR_SIZE 0x1 #define _RCSTA_OERR_LENGTH 0x1 #define _RCSTA_OERR_MASK 0x2 #define _RCSTA_FERR_POSN 0x2 #define _RCSTA_FERR_POSITION 0x2 #define _RCSTA_FERR_SIZE 0x1 #define _RCSTA_FERR_LENGTH 0x1 #define _RCSTA_FERR_MASK 0x4 #define _RCSTA_ADDEN_POSN 0x3 #define _RCSTA_ADDEN_POSITION 0x3 #define _RCSTA_ADDEN_SIZE 0x1 #define _RCSTA_ADDEN_LENGTH 0x1 #define _RCSTA_ADDEN_MASK 0x8 #define _RCSTA_CREN_POSN 0x4 #define _RCSTA_CREN_POSITION 0x4 #define _RCSTA_CREN_SIZE 0x1 #define _RCSTA_CREN_LENGTH 0x1 #define _RCSTA_CREN_MASK 0x10 #define _RCSTA_SREN_POSN 0x5 #define _RCSTA_SREN_POSITION 0x5 #define _RCSTA_SREN_SIZE 0x1 #define _RCSTA_SREN_LENGTH 0x1 #define _RCSTA_SREN_MASK 0x20 #define _RCSTA_RX9_POSN 0x6 #define _RCSTA_RX9_POSITION 0x6 #define _RCSTA_RX9_SIZE 0x1 #define _RCSTA_RX9_LENGTH 0x1 #define _RCSTA_RX9_MASK 0x40 #define _RCSTA_SPEN_POSN 0x7 #define _RCSTA_SPEN_POSITION 0x7 #define _RCSTA_SPEN_SIZE 0x1 #define _RCSTA_SPEN_LENGTH 0x1 #define _RCSTA_SPEN_MASK 0x80 #define _RCSTA_RCD8_POSN 0x0 #define _RCSTA_RCD8_POSITION 0x0 #define _RCSTA_RCD8_SIZE 0x1 #define _RCSTA_RCD8_LENGTH 0x1 #define _RCSTA_RCD8_MASK 0x1 #define _RCSTA_ADEN_POSN 0x3 #define _RCSTA_ADEN_POSITION 0x3 #define _RCSTA_ADEN_SIZE 0x1 #define _RCSTA_ADEN_LENGTH 0x1 #define _RCSTA_ADEN_MASK 0x8 #define _RCSTA_RC9_POSN 0x6 #define _RCSTA_RC9_POSITION 0x6 #define _RCSTA_RC9_SIZE 0x1 #define _RCSTA_RC9_LENGTH 0x1 #define _RCSTA_RC9_MASK 0x40 #define _RCSTA_NOT_RC8_POSN 0x6 #define _RCSTA_NOT_RC8_POSITION 0x6 #define _RCSTA_NOT_RC8_SIZE 0x1 #define _RCSTA_NOT_RC8_LENGTH 0x1 #define _RCSTA_NOT_RC8_MASK 0x40 #define _RCSTA_nRC8_POSN 0x6 #define _RCSTA_nRC8_POSITION 0x6 #define _RCSTA_nRC8_SIZE 0x1 #define _RCSTA_nRC8_LENGTH 0x1 #define _RCSTA_nRC8_MASK 0x40 #define _RCSTA_RC8_9_POSN 0x6 #define _RCSTA_RC8_9_POSITION 0x6 #define _RCSTA_RC8_9_SIZE 0x1 #define _RCSTA_RC8_9_LENGTH 0x1 #define _RCSTA_RC8_9_MASK 0x40 #define _RCSTA_RX9D1_POSN 0x0 #define _RCSTA_RX9D1_POSITION 0x0 #define _RCSTA_RX9D1_SIZE 0x1 #define _RCSTA_RX9D1_LENGTH 0x1 #define _RCSTA_RX9D1_MASK 0x1 #define _RCSTA_OERR1_POSN 0x1 #define _RCSTA_OERR1_POSITION 0x1 #define _RCSTA_OERR1_SIZE 0x1 #define _RCSTA_OERR1_LENGTH 0x1 #define _RCSTA_OERR1_MASK 0x2 #define _RCSTA_FERR1_POSN 0x2 #define _RCSTA_FERR1_POSITION 0x2 #define _RCSTA_FERR1_SIZE 0x1 #define _RCSTA_FERR1_LENGTH 0x1 #define _RCSTA_FERR1_MASK 0x4 #define _RCSTA_ADDEN1_POSN 0x3 #define _RCSTA_ADDEN1_POSITION 0x3 #define _RCSTA_ADDEN1_SIZE 0x1 #define _RCSTA_ADDEN1_LENGTH 0x1 #define _RCSTA_ADDEN1_MASK 0x8 #define _RCSTA_CREN1_POSN 0x4 #define _RCSTA_CREN1_POSITION 0x4 #define _RCSTA_CREN1_SIZE 0x1 #define _RCSTA_CREN1_LENGTH 0x1 #define _RCSTA_CREN1_MASK 0x10 #define _RCSTA_SREN1_POSN 0x5 #define _RCSTA_SREN1_POSITION 0x5 #define _RCSTA_SREN1_SIZE 0x1 #define _RCSTA_SREN1_LENGTH 0x1 #define _RCSTA_SREN1_MASK 0x20 #define _RCSTA_RX91_POSN 0x6 #define _RCSTA_RX91_POSITION 0x6 #define _RCSTA_RX91_SIZE 0x1 #define _RCSTA_RX91_LENGTH 0x1 #define _RCSTA_RX91_MASK 0x40 #define _RCSTA_SPEN1_POSN 0x7 #define _RCSTA_SPEN1_POSITION 0x7 #define _RCSTA_SPEN1_SIZE 0x1 #define _RCSTA_SPEN1_LENGTH 0x1 #define _RCSTA_SPEN1_MASK 0x80 #define _RCSTA_SRENA_POSN 0x5 #define _RCSTA_SRENA_POSITION 0x5 #define _RCSTA_SRENA_SIZE 0x1 #define _RCSTA_SRENA_LENGTH 0x1 #define _RCSTA_SRENA_MASK 0x20 // Register: TXSTA1 #define TXSTA1 TXSTA1 extern volatile unsigned char TXSTA1 @ 0xFAC; #ifndef _LIB_BUILD asm("TXSTA1 equ 0FACh"); #endif // aliases extern volatile unsigned char TXSTA @ 0xFAC; #ifndef _LIB_BUILD asm("TXSTA equ 0FACh"); #endif // bitfield definitions typedef union { struct { unsigned TX9D :1; unsigned TRMT :1; unsigned BRGH :1; unsigned SENDB :1; unsigned SYNC :1; unsigned TXEN :1; unsigned TX9 :1; unsigned CSRC :1; }; struct { unsigned TXD8 :1; unsigned :5; unsigned TX8_9 :1; }; struct { unsigned :6; unsigned NOT_TX8 :1; }; struct { unsigned :6; unsigned nTX8 :1; }; struct { unsigned TX9D1 :1; unsigned TRMT1 :1; unsigned BRGH1 :1; unsigned SENDB1 :1; unsigned SYNC1 :1; unsigned TXEN1 :1; unsigned TX91 :1; unsigned CSRC1 :1; }; } TXSTA1bits_t; extern volatile TXSTA1bits_t TXSTA1bits @ 0xFAC; // bitfield macros #define _TXSTA1_TX9D_POSN 0x0 #define _TXSTA1_TX9D_POSITION 0x0 #define _TXSTA1_TX9D_SIZE 0x1 #define _TXSTA1_TX9D_LENGTH 0x1 #define _TXSTA1_TX9D_MASK 0x1 #define _TXSTA1_TRMT_POSN 0x1 #define _TXSTA1_TRMT_POSITION 0x1 #define _TXSTA1_TRMT_SIZE 0x1 #define _TXSTA1_TRMT_LENGTH 0x1 #define _TXSTA1_TRMT_MASK 0x2 #define _TXSTA1_BRGH_POSN 0x2 #define _TXSTA1_BRGH_POSITION 0x2 #define _TXSTA1_BRGH_SIZE 0x1 #define _TXSTA1_BRGH_LENGTH 0x1 #define _TXSTA1_BRGH_MASK 0x4 #define _TXSTA1_SENDB_POSN 0x3 #define _TXSTA1_SENDB_POSITION 0x3 #define _TXSTA1_SENDB_SIZE 0x1 #define _TXSTA1_SENDB_LENGTH 0x1 #define _TXSTA1_SENDB_MASK 0x8 #define _TXSTA1_SYNC_POSN 0x4 #define _TXSTA1_SYNC_POSITION 0x4 #define _TXSTA1_SYNC_SIZE 0x1 #define _TXSTA1_SYNC_LENGTH 0x1 #define _TXSTA1_SYNC_MASK 0x10 #define _TXSTA1_TXEN_POSN 0x5 #define _TXSTA1_TXEN_POSITION 0x5 #define _TXSTA1_TXEN_SIZE 0x1 #define _TXSTA1_TXEN_LENGTH 0x1 #define _TXSTA1_TXEN_MASK 0x20 #define _TXSTA1_TX9_POSN 0x6 #define _TXSTA1_TX9_POSITION 0x6 #define _TXSTA1_TX9_SIZE 0x1 #define _TXSTA1_TX9_LENGTH 0x1 #define _TXSTA1_TX9_MASK 0x40 #define _TXSTA1_CSRC_POSN 0x7 #define _TXSTA1_CSRC_POSITION 0x7 #define _TXSTA1_CSRC_SIZE 0x1 #define _TXSTA1_CSRC_LENGTH 0x1 #define _TXSTA1_CSRC_MASK 0x80 #define _TXSTA1_TXD8_POSN 0x0 #define _TXSTA1_TXD8_POSITION 0x0 #define _TXSTA1_TXD8_SIZE 0x1 #define _TXSTA1_TXD8_LENGTH 0x1 #define _TXSTA1_TXD8_MASK 0x1 #define _TXSTA1_TX8_9_POSN 0x6 #define _TXSTA1_TX8_9_POSITION 0x6 #define _TXSTA1_TX8_9_SIZE 0x1 #define _TXSTA1_TX8_9_LENGTH 0x1 #define _TXSTA1_TX8_9_MASK 0x40 #define _TXSTA1_NOT_TX8_POSN 0x6 #define _TXSTA1_NOT_TX8_POSITION 0x6 #define _TXSTA1_NOT_TX8_SIZE 0x1 #define _TXSTA1_NOT_TX8_LENGTH 0x1 #define _TXSTA1_NOT_TX8_MASK 0x40 #define _TXSTA1_nTX8_POSN 0x6 #define _TXSTA1_nTX8_POSITION 0x6 #define _TXSTA1_nTX8_SIZE 0x1 #define _TXSTA1_nTX8_LENGTH 0x1 #define _TXSTA1_nTX8_MASK 0x40 #define _TXSTA1_TX9D1_POSN 0x0 #define _TXSTA1_TX9D1_POSITION 0x0 #define _TXSTA1_TX9D1_SIZE 0x1 #define _TXSTA1_TX9D1_LENGTH 0x1 #define _TXSTA1_TX9D1_MASK 0x1 #define _TXSTA1_TRMT1_POSN 0x1 #define _TXSTA1_TRMT1_POSITION 0x1 #define _TXSTA1_TRMT1_SIZE 0x1 #define _TXSTA1_TRMT1_LENGTH 0x1 #define _TXSTA1_TRMT1_MASK 0x2 #define _TXSTA1_BRGH1_POSN 0x2 #define _TXSTA1_BRGH1_POSITION 0x2 #define _TXSTA1_BRGH1_SIZE 0x1 #define _TXSTA1_BRGH1_LENGTH 0x1 #define _TXSTA1_BRGH1_MASK 0x4 #define _TXSTA1_SENDB1_POSN 0x3 #define _TXSTA1_SENDB1_POSITION 0x3 #define _TXSTA1_SENDB1_SIZE 0x1 #define _TXSTA1_SENDB1_LENGTH 0x1 #define _TXSTA1_SENDB1_MASK 0x8 #define _TXSTA1_SYNC1_POSN 0x4 #define _TXSTA1_SYNC1_POSITION 0x4 #define _TXSTA1_SYNC1_SIZE 0x1 #define _TXSTA1_SYNC1_LENGTH 0x1 #define _TXSTA1_SYNC1_MASK 0x10 #define _TXSTA1_TXEN1_POSN 0x5 #define _TXSTA1_TXEN1_POSITION 0x5 #define _TXSTA1_TXEN1_SIZE 0x1 #define _TXSTA1_TXEN1_LENGTH 0x1 #define _TXSTA1_TXEN1_MASK 0x20 #define _TXSTA1_TX91_POSN 0x6 #define _TXSTA1_TX91_POSITION 0x6 #define _TXSTA1_TX91_SIZE 0x1 #define _TXSTA1_TX91_LENGTH 0x1 #define _TXSTA1_TX91_MASK 0x40 #define _TXSTA1_CSRC1_POSN 0x7 #define _TXSTA1_CSRC1_POSITION 0x7 #define _TXSTA1_CSRC1_SIZE 0x1 #define _TXSTA1_CSRC1_LENGTH 0x1 #define _TXSTA1_CSRC1_MASK 0x80 // alias bitfield definitions typedef union { struct { unsigned TX9D :1; unsigned TRMT :1; unsigned BRGH :1; unsigned SENDB :1; unsigned SYNC :1; unsigned TXEN :1; unsigned TX9 :1; unsigned CSRC :1; }; struct { unsigned TXD8 :1; unsigned :5; unsigned TX8_9 :1; }; struct { unsigned :6; unsigned NOT_TX8 :1; }; struct { unsigned :6; unsigned nTX8 :1; }; struct { unsigned TX9D1 :1; unsigned TRMT1 :1; unsigned BRGH1 :1; unsigned SENDB1 :1; unsigned SYNC1 :1; unsigned TXEN1 :1; unsigned TX91 :1; unsigned CSRC1 :1; }; } TXSTAbits_t; extern volatile TXSTAbits_t TXSTAbits @ 0xFAC; // bitfield macros #define _TXSTA_TX9D_POSN 0x0 #define _TXSTA_TX9D_POSITION 0x0 #define _TXSTA_TX9D_SIZE 0x1 #define _TXSTA_TX9D_LENGTH 0x1 #define _TXSTA_TX9D_MASK 0x1 #define _TXSTA_TRMT_POSN 0x1 #define _TXSTA_TRMT_POSITION 0x1 #define _TXSTA_TRMT_SIZE 0x1 #define _TXSTA_TRMT_LENGTH 0x1 #define _TXSTA_TRMT_MASK 0x2 #define _TXSTA_BRGH_POSN 0x2 #define _TXSTA_BRGH_POSITION 0x2 #define _TXSTA_BRGH_SIZE 0x1 #define _TXSTA_BRGH_LENGTH 0x1 #define _TXSTA_BRGH_MASK 0x4 #define _TXSTA_SENDB_POSN 0x3 #define _TXSTA_SENDB_POSITION 0x3 #define _TXSTA_SENDB_SIZE 0x1 #define _TXSTA_SENDB_LENGTH 0x1 #define _TXSTA_SENDB_MASK 0x8 #define _TXSTA_SYNC_POSN 0x4 #define _TXSTA_SYNC_POSITION 0x4 #define _TXSTA_SYNC_SIZE 0x1 #define _TXSTA_SYNC_LENGTH 0x1 #define _TXSTA_SYNC_MASK 0x10 #define _TXSTA_TXEN_POSN 0x5 #define _TXSTA_TXEN_POSITION 0x5 #define _TXSTA_TXEN_SIZE 0x1 #define _TXSTA_TXEN_LENGTH 0x1 #define _TXSTA_TXEN_MASK 0x20 #define _TXSTA_TX9_POSN 0x6 #define _TXSTA_TX9_POSITION 0x6 #define _TXSTA_TX9_SIZE 0x1 #define _TXSTA_TX9_LENGTH 0x1 #define _TXSTA_TX9_MASK 0x40 #define _TXSTA_CSRC_POSN 0x7 #define _TXSTA_CSRC_POSITION 0x7 #define _TXSTA_CSRC_SIZE 0x1 #define _TXSTA_CSRC_LENGTH 0x1 #define _TXSTA_CSRC_MASK 0x80 #define _TXSTA_TXD8_POSN 0x0 #define _TXSTA_TXD8_POSITION 0x0 #define _TXSTA_TXD8_SIZE 0x1 #define _TXSTA_TXD8_LENGTH 0x1 #define _TXSTA_TXD8_MASK 0x1 #define _TXSTA_TX8_9_POSN 0x6 #define _TXSTA_TX8_9_POSITION 0x6 #define _TXSTA_TX8_9_SIZE 0x1 #define _TXSTA_TX8_9_LENGTH 0x1 #define _TXSTA_TX8_9_MASK 0x40 #define _TXSTA_NOT_TX8_POSN 0x6 #define _TXSTA_NOT_TX8_POSITION 0x6 #define _TXSTA_NOT_TX8_SIZE 0x1 #define _TXSTA_NOT_TX8_LENGTH 0x1 #define _TXSTA_NOT_TX8_MASK 0x40 #define _TXSTA_nTX8_POSN 0x6 #define _TXSTA_nTX8_POSITION 0x6 #define _TXSTA_nTX8_SIZE 0x1 #define _TXSTA_nTX8_LENGTH 0x1 #define _TXSTA_nTX8_MASK 0x40 #define _TXSTA_TX9D1_POSN 0x0 #define _TXSTA_TX9D1_POSITION 0x0 #define _TXSTA_TX9D1_SIZE 0x1 #define _TXSTA_TX9D1_LENGTH 0x1 #define _TXSTA_TX9D1_MASK 0x1 #define _TXSTA_TRMT1_POSN 0x1 #define _TXSTA_TRMT1_POSITION 0x1 #define _TXSTA_TRMT1_SIZE 0x1 #define _TXSTA_TRMT1_LENGTH 0x1 #define _TXSTA_TRMT1_MASK 0x2 #define _TXSTA_BRGH1_POSN 0x2 #define _TXSTA_BRGH1_POSITION 0x2 #define _TXSTA_BRGH1_SIZE 0x1 #define _TXSTA_BRGH1_LENGTH 0x1 #define _TXSTA_BRGH1_MASK 0x4 #define _TXSTA_SENDB1_POSN 0x3 #define _TXSTA_SENDB1_POSITION 0x3 #define _TXSTA_SENDB1_SIZE 0x1 #define _TXSTA_SENDB1_LENGTH 0x1 #define _TXSTA_SENDB1_MASK 0x8 #define _TXSTA_SYNC1_POSN 0x4 #define _TXSTA_SYNC1_POSITION 0x4 #define _TXSTA_SYNC1_SIZE 0x1 #define _TXSTA_SYNC1_LENGTH 0x1 #define _TXSTA_SYNC1_MASK 0x10 #define _TXSTA_TXEN1_POSN 0x5 #define _TXSTA_TXEN1_POSITION 0x5 #define _TXSTA_TXEN1_SIZE 0x1 #define _TXSTA_TXEN1_LENGTH 0x1 #define _TXSTA_TXEN1_MASK 0x20 #define _TXSTA_TX91_POSN 0x6 #define _TXSTA_TX91_POSITION 0x6 #define _TXSTA_TX91_SIZE 0x1 #define _TXSTA_TX91_LENGTH 0x1 #define _TXSTA_TX91_MASK 0x40 #define _TXSTA_CSRC1_POSN 0x7 #define _TXSTA_CSRC1_POSITION 0x7 #define _TXSTA_CSRC1_SIZE 0x1 #define _TXSTA_CSRC1_LENGTH 0x1 #define _TXSTA_CSRC1_MASK 0x80 // Register: TXREG1 #define TXREG1 TXREG1 extern volatile unsigned char TXREG1 @ 0xFAD; #ifndef _LIB_BUILD asm("TXREG1 equ 0FADh"); #endif // aliases extern volatile unsigned char TXREG @ 0xFAD; #ifndef _LIB_BUILD asm("TXREG equ 0FADh"); #endif // bitfield definitions typedef union { struct { unsigned TXREG1 :8; }; } TXREG1bits_t; extern volatile TXREG1bits_t TXREG1bits @ 0xFAD; // bitfield macros #define _TXREG1_TXREG1_POSN 0x0 #define _TXREG1_TXREG1_POSITION 0x0 #define _TXREG1_TXREG1_SIZE 0x8 #define _TXREG1_TXREG1_LENGTH 0x8 #define _TXREG1_TXREG1_MASK 0xFF // alias bitfield definitions typedef union { struct { unsigned TXREG1 :8; }; } TXREGbits_t; extern volatile TXREGbits_t TXREGbits @ 0xFAD; // bitfield macros #define _TXREG_TXREG1_POSN 0x0 #define _TXREG_TXREG1_POSITION 0x0 #define _TXREG_TXREG1_SIZE 0x8 #define _TXREG_TXREG1_LENGTH 0x8 #define _TXREG_TXREG1_MASK 0xFF // Register: RCREG1 #define RCREG1 RCREG1 extern volatile unsigned char RCREG1 @ 0xFAE; #ifndef _LIB_BUILD asm("RCREG1 equ 0FAEh"); #endif // aliases extern volatile unsigned char RCREG @ 0xFAE; #ifndef _LIB_BUILD asm("RCREG equ 0FAEh"); #endif // bitfield definitions typedef union { struct { unsigned RCREG1 :8; }; } RCREG1bits_t; extern volatile RCREG1bits_t RCREG1bits @ 0xFAE; // bitfield macros #define _RCREG1_RCREG1_POSN 0x0 #define _RCREG1_RCREG1_POSITION 0x0 #define _RCREG1_RCREG1_SIZE 0x8 #define _RCREG1_RCREG1_LENGTH 0x8 #define _RCREG1_RCREG1_MASK 0xFF // alias bitfield definitions typedef union { struct { unsigned RCREG1 :8; }; } RCREGbits_t; extern volatile RCREGbits_t RCREGbits @ 0xFAE; // bitfield macros #define _RCREG_RCREG1_POSN 0x0 #define _RCREG_RCREG1_POSITION 0x0 #define _RCREG_RCREG1_SIZE 0x8 #define _RCREG_RCREG1_LENGTH 0x8 #define _RCREG_RCREG1_MASK 0xFF // Register: SPBRG1 #define SPBRG1 SPBRG1 extern volatile unsigned char SPBRG1 @ 0xFAF; #ifndef _LIB_BUILD asm("SPBRG1 equ 0FAFh"); #endif // aliases extern volatile unsigned char SPBRG @ 0xFAF; #ifndef _LIB_BUILD asm("SPBRG equ 0FAFh"); #endif // bitfield definitions typedef union { struct { unsigned SPBRG1 :8; }; } SPBRG1bits_t; extern volatile SPBRG1bits_t SPBRG1bits @ 0xFAF; // bitfield macros #define _SPBRG1_SPBRG1_POSN 0x0 #define _SPBRG1_SPBRG1_POSITION 0x0 #define _SPBRG1_SPBRG1_SIZE 0x8 #define _SPBRG1_SPBRG1_LENGTH 0x8 #define _SPBRG1_SPBRG1_MASK 0xFF // alias bitfield definitions typedef union { struct { unsigned SPBRG1 :8; }; } SPBRGbits_t; extern volatile SPBRGbits_t SPBRGbits @ 0xFAF; // bitfield macros #define _SPBRG_SPBRG1_POSN 0x0 #define _SPBRG_SPBRG1_POSITION 0x0 #define _SPBRG_SPBRG1_SIZE 0x8 #define _SPBRG_SPBRG1_LENGTH 0x8 #define _SPBRG_SPBRG1_MASK 0xFF // Register: T3GCON #define T3GCON T3GCON extern volatile unsigned char T3GCON @ 0xFB0; #ifndef _LIB_BUILD asm("T3GCON equ 0FB0h"); #endif // bitfield definitions typedef union { struct { unsigned :3; unsigned T3GGO_NOT_T3DONE :1; }; struct { unsigned T3GSS :2; unsigned T3GVAL :1; unsigned T3GGO_nT3DONE :1; unsigned T3GSPM :1; unsigned T3GTM :1; unsigned T3GPOL :1; unsigned TMR3GE :1; }; struct { unsigned T3GSS0 :1; unsigned T3GSS1 :1; unsigned :1; unsigned T3GGO :1; }; struct { unsigned :3; unsigned NOT_T3DONE :1; }; struct { unsigned :3; unsigned nT3DONE :1; }; } T3GCONbits_t; extern volatile T3GCONbits_t T3GCONbits @ 0xFB0; // bitfield macros #define _T3GCON_T3GGO_NOT_T3DONE_POSN 0x3 #define _T3GCON_T3GGO_NOT_T3DONE_POSITION 0x3 #define _T3GCON_T3GGO_NOT_T3DONE_SIZE 0x1 #define _T3GCON_T3GGO_NOT_T3DONE_LENGTH 0x1 #define _T3GCON_T3GGO_NOT_T3DONE_MASK 0x8 #define _T3GCON_T3GSS_POSN 0x0 #define _T3GCON_T3GSS_POSITION 0x0 #define _T3GCON_T3GSS_SIZE 0x2 #define _T3GCON_T3GSS_LENGTH 0x2 #define _T3GCON_T3GSS_MASK 0x3 #define _T3GCON_T3GVAL_POSN 0x2 #define _T3GCON_T3GVAL_POSITION 0x2 #define _T3GCON_T3GVAL_SIZE 0x1 #define _T3GCON_T3GVAL_LENGTH 0x1 #define _T3GCON_T3GVAL_MASK 0x4 #define _T3GCON_T3GGO_nT3DONE_POSN 0x3 #define _T3GCON_T3GGO_nT3DONE_POSITION 0x3 #define _T3GCON_T3GGO_nT3DONE_SIZE 0x1 #define _T3GCON_T3GGO_nT3DONE_LENGTH 0x1 #define _T3GCON_T3GGO_nT3DONE_MASK 0x8 #define _T3GCON_T3GSPM_POSN 0x4 #define _T3GCON_T3GSPM_POSITION 0x4 #define _T3GCON_T3GSPM_SIZE 0x1 #define _T3GCON_T3GSPM_LENGTH 0x1 #define _T3GCON_T3GSPM_MASK 0x10 #define _T3GCON_T3GTM_POSN 0x5 #define _T3GCON_T3GTM_POSITION 0x5 #define _T3GCON_T3GTM_SIZE 0x1 #define _T3GCON_T3GTM_LENGTH 0x1 #define _T3GCON_T3GTM_MASK 0x20 #define _T3GCON_T3GPOL_POSN 0x6 #define _T3GCON_T3GPOL_POSITION 0x6 #define _T3GCON_T3GPOL_SIZE 0x1 #define _T3GCON_T3GPOL_LENGTH 0x1 #define _T3GCON_T3GPOL_MASK 0x40 #define _T3GCON_TMR3GE_POSN 0x7 #define _T3GCON_TMR3GE_POSITION 0x7 #define _T3GCON_TMR3GE_SIZE 0x1 #define _T3GCON_TMR3GE_LENGTH 0x1 #define _T3GCON_TMR3GE_MASK 0x80 #define _T3GCON_T3GSS0_POSN 0x0 #define _T3GCON_T3GSS0_POSITION 0x0 #define _T3GCON_T3GSS0_SIZE 0x1 #define _T3GCON_T3GSS0_LENGTH 0x1 #define _T3GCON_T3GSS0_MASK 0x1 #define _T3GCON_T3GSS1_POSN 0x1 #define _T3GCON_T3GSS1_POSITION 0x1 #define _T3GCON_T3GSS1_SIZE 0x1 #define _T3GCON_T3GSS1_LENGTH 0x1 #define _T3GCON_T3GSS1_MASK 0x2 #define _T3GCON_T3GGO_POSN 0x3 #define _T3GCON_T3GGO_POSITION 0x3 #define _T3GCON_T3GGO_SIZE 0x1 #define _T3GCON_T3GGO_LENGTH 0x1 #define _T3GCON_T3GGO_MASK 0x8 #define _T3GCON_NOT_T3DONE_POSN 0x3 #define _T3GCON_NOT_T3DONE_POSITION 0x3 #define _T3GCON_NOT_T3DONE_SIZE 0x1 #define _T3GCON_NOT_T3DONE_LENGTH 0x1 #define _T3GCON_NOT_T3DONE_MASK 0x8 #define _T3GCON_nT3DONE_POSN 0x3 #define _T3GCON_nT3DONE_POSITION 0x3 #define _T3GCON_nT3DONE_SIZE 0x1 #define _T3GCON_nT3DONE_LENGTH 0x1 #define _T3GCON_nT3DONE_MASK 0x8 // Register: T3CON #define T3CON T3CON extern volatile unsigned char T3CON @ 0xFB1; #ifndef _LIB_BUILD asm("T3CON equ 0FB1h"); #endif // bitfield definitions typedef union { struct { unsigned :2; unsigned NOT_T3SYNC :1; }; struct { unsigned TMR3ON :1; unsigned RD16 :1; unsigned nT3SYNC :1; unsigned SOSCEN :1; unsigned T3CKPS :2; unsigned TMR3CS :2; }; struct { unsigned :4; unsigned T3CKPS0 :1; unsigned T3CKPS1 :1; unsigned TMR3CS0 :1; unsigned TMR3CS1 :1; }; struct { unsigned :3; unsigned SOSCEN3 :1; unsigned :3; unsigned RD163 :1; }; struct { unsigned :7; unsigned T3RD16 :1; }; } T3CONbits_t; extern volatile T3CONbits_t T3CONbits @ 0xFB1; // bitfield macros #define _T3CON_NOT_T3SYNC_POSN 0x2 #define _T3CON_NOT_T3SYNC_POSITION 0x2 #define _T3CON_NOT_T3SYNC_SIZE 0x1 #define _T3CON_NOT_T3SYNC_LENGTH 0x1 #define _T3CON_NOT_T3SYNC_MASK 0x4 #define _T3CON_TMR3ON_POSN 0x0 #define _T3CON_TMR3ON_POSITION 0x0 #define _T3CON_TMR3ON_SIZE 0x1 #define _T3CON_TMR3ON_LENGTH 0x1 #define _T3CON_TMR3ON_MASK 0x1 #define _T3CON_RD16_POSN 0x1 #define _T3CON_RD16_POSITION 0x1 #define _T3CON_RD16_SIZE 0x1 #define _T3CON_RD16_LENGTH 0x1 #define _T3CON_RD16_MASK 0x2 #define _T3CON_nT3SYNC_POSN 0x2 #define _T3CON_nT3SYNC_POSITION 0x2 #define _T3CON_nT3SYNC_SIZE 0x1 #define _T3CON_nT3SYNC_LENGTH 0x1 #define _T3CON_nT3SYNC_MASK 0x4 #define _T3CON_SOSCEN_POSN 0x3 #define _T3CON_SOSCEN_POSITION 0x3 #define _T3CON_SOSCEN_SIZE 0x1 #define _T3CON_SOSCEN_LENGTH 0x1 #define _T3CON_SOSCEN_MASK 0x8 #define _T3CON_T3CKPS_POSN 0x4 #define _T3CON_T3CKPS_POSITION 0x4 #define _T3CON_T3CKPS_SIZE 0x2 #define _T3CON_T3CKPS_LENGTH 0x2 #define _T3CON_T3CKPS_MASK 0x30 #define _T3CON_TMR3CS_POSN 0x6 #define _T3CON_TMR3CS_POSITION 0x6 #define _T3CON_TMR3CS_SIZE 0x2 #define _T3CON_TMR3CS_LENGTH 0x2 #define _T3CON_TMR3CS_MASK 0xC0 #define _T3CON_T3CKPS0_POSN 0x4 #define _T3CON_T3CKPS0_POSITION 0x4 #define _T3CON_T3CKPS0_SIZE 0x1 #define _T3CON_T3CKPS0_LENGTH 0x1 #define _T3CON_T3CKPS0_MASK 0x10 #define _T3CON_T3CKPS1_POSN 0x5 #define _T3CON_T3CKPS1_POSITION 0x5 #define _T3CON_T3CKPS1_SIZE 0x1 #define _T3CON_T3CKPS1_LENGTH 0x1 #define _T3CON_T3CKPS1_MASK 0x20 #define _T3CON_TMR3CS0_POSN 0x6 #define _T3CON_TMR3CS0_POSITION 0x6 #define _T3CON_TMR3CS0_SIZE 0x1 #define _T3CON_TMR3CS0_LENGTH 0x1 #define _T3CON_TMR3CS0_MASK 0x40 #define _T3CON_TMR3CS1_POSN 0x7 #define _T3CON_TMR3CS1_POSITION 0x7 #define _T3CON_TMR3CS1_SIZE 0x1 #define _T3CON_TMR3CS1_LENGTH 0x1 #define _T3CON_TMR3CS1_MASK 0x80 #define _T3CON_SOSCEN3_POSN 0x3 #define _T3CON_SOSCEN3_POSITION 0x3 #define _T3CON_SOSCEN3_SIZE 0x1 #define _T3CON_SOSCEN3_LENGTH 0x1 #define _T3CON_SOSCEN3_MASK 0x8 #define _T3CON_RD163_POSN 0x7 #define _T3CON_RD163_POSITION 0x7 #define _T3CON_RD163_SIZE 0x1 #define _T3CON_RD163_LENGTH 0x1 #define _T3CON_RD163_MASK 0x80 #define _T3CON_T3RD16_POSN 0x7 #define _T3CON_T3RD16_POSITION 0x7 #define _T3CON_T3RD16_SIZE 0x1 #define _T3CON_T3RD16_LENGTH 0x1 #define _T3CON_T3RD16_MASK 0x80 // Register: TMR3 #define TMR3 TMR3 extern volatile unsigned short TMR3 @ 0xFB2; #ifndef _LIB_BUILD asm("TMR3 equ 0FB2h"); #endif // Register: TMR3L #define TMR3L TMR3L extern volatile unsigned char TMR3L @ 0xFB2; #ifndef _LIB_BUILD asm("TMR3L equ 0FB2h"); #endif // bitfield definitions typedef union { struct { unsigned TMR3L :8; }; } TMR3Lbits_t; extern volatile TMR3Lbits_t TMR3Lbits @ 0xFB2; // bitfield macros #define _TMR3L_TMR3L_POSN 0x0 #define _TMR3L_TMR3L_POSITION 0x0 #define _TMR3L_TMR3L_SIZE 0x8 #define _TMR3L_TMR3L_LENGTH 0x8 #define _TMR3L_TMR3L_MASK 0xFF // Register: TMR3H #define TMR3H TMR3H extern volatile unsigned char TMR3H @ 0xFB3; #ifndef _LIB_BUILD asm("TMR3H equ 0FB3h"); #endif // bitfield definitions typedef union { struct { unsigned TMR3H :8; }; } TMR3Hbits_t; extern volatile TMR3Hbits_t TMR3Hbits @ 0xFB3; // bitfield macros #define _TMR3H_TMR3H_POSN 0x0 #define _TMR3H_TMR3H_POSITION 0x0 #define _TMR3H_TMR3H_SIZE 0x8 #define _TMR3H_TMR3H_LENGTH 0x8 #define _TMR3H_TMR3H_MASK 0xFF // Register: CMSTAT #define CMSTAT CMSTAT extern volatile unsigned char CMSTAT @ 0xFB4; #ifndef _LIB_BUILD asm("CMSTAT equ 0FB4h"); #endif // aliases extern volatile unsigned char CMSTATUS @ 0xFB4; #ifndef _LIB_BUILD asm("CMSTATUS equ 0FB4h"); #endif // bitfield definitions typedef union { struct { unsigned :6; unsigned CMP1OUT :1; unsigned CMP2OUT :1; }; struct { unsigned :6; unsigned C2OUT :1; unsigned C3OUT :1; }; } CMSTATbits_t; extern volatile CMSTATbits_t CMSTATbits @ 0xFB4; // bitfield macros #define _CMSTAT_CMP1OUT_POSN 0x6 #define _CMSTAT_CMP1OUT_POSITION 0x6 #define _CMSTAT_CMP1OUT_SIZE 0x1 #define _CMSTAT_CMP1OUT_LENGTH 0x1 #define _CMSTAT_CMP1OUT_MASK 0x40 #define _CMSTAT_CMP2OUT_POSN 0x7 #define _CMSTAT_CMP2OUT_POSITION 0x7 #define _CMSTAT_CMP2OUT_SIZE 0x1 #define _CMSTAT_CMP2OUT_LENGTH 0x1 #define _CMSTAT_CMP2OUT_MASK 0x80 #define _CMSTAT_C2OUT_POSN 0x6 #define _CMSTAT_C2OUT_POSITION 0x6 #define _CMSTAT_C2OUT_SIZE 0x1 #define _CMSTAT_C2OUT_LENGTH 0x1 #define _CMSTAT_C2OUT_MASK 0x40 #define _CMSTAT_C3OUT_POSN 0x7 #define _CMSTAT_C3OUT_POSITION 0x7 #define _CMSTAT_C3OUT_SIZE 0x1 #define _CMSTAT_C3OUT_LENGTH 0x1 #define _CMSTAT_C3OUT_MASK 0x80 // alias bitfield definitions typedef union { struct { unsigned :6; unsigned CMP1OUT :1; unsigned CMP2OUT :1; }; struct { unsigned :6; unsigned C2OUT :1; unsigned C3OUT :1; }; } CMSTATUSbits_t; extern volatile CMSTATUSbits_t CMSTATUSbits @ 0xFB4; // bitfield macros #define _CMSTATUS_CMP1OUT_POSN 0x6 #define _CMSTATUS_CMP1OUT_POSITION 0x6 #define _CMSTATUS_CMP1OUT_SIZE 0x1 #define _CMSTATUS_CMP1OUT_LENGTH 0x1 #define _CMSTATUS_CMP1OUT_MASK 0x40 #define _CMSTATUS_CMP2OUT_POSN 0x7 #define _CMSTATUS_CMP2OUT_POSITION 0x7 #define _CMSTATUS_CMP2OUT_SIZE 0x1 #define _CMSTATUS_CMP2OUT_LENGTH 0x1 #define _CMSTATUS_CMP2OUT_MASK 0x80 #define _CMSTATUS_C2OUT_POSN 0x6 #define _CMSTATUS_C2OUT_POSITION 0x6 #define _CMSTATUS_C2OUT_SIZE 0x1 #define _CMSTATUS_C2OUT_LENGTH 0x1 #define _CMSTATUS_C2OUT_MASK 0x40 #define _CMSTATUS_C3OUT_POSN 0x7 #define _CMSTATUS_C3OUT_POSITION 0x7 #define _CMSTATUS_C3OUT_SIZE 0x1 #define _CMSTATUS_C3OUT_LENGTH 0x1 #define _CMSTATUS_C3OUT_MASK 0x80 // Register: CVRCON #define CVRCON CVRCON extern volatile unsigned char CVRCON @ 0xFB5; #ifndef _LIB_BUILD asm("CVRCON equ 0FB5h"); #endif // bitfield definitions typedef union { struct { unsigned CVR :5; unsigned CVRSS :1; unsigned CVROE :1; unsigned CVREN :1; }; struct { unsigned CVR0 :1; unsigned CVR1 :1; unsigned CVR2 :1; unsigned CVR3 :1; unsigned CVR4 :1; }; struct { unsigned :5; unsigned CVRR :1; unsigned CVROEN :1; }; } CVRCONbits_t; extern volatile CVRCONbits_t CVRCONbits @ 0xFB5; // bitfield macros #define _CVRCON_CVR_POSN 0x0 #define _CVRCON_CVR_POSITION 0x0 #define _CVRCON_CVR_SIZE 0x5 #define _CVRCON_CVR_LENGTH 0x5 #define _CVRCON_CVR_MASK 0x1F #define _CVRCON_CVRSS_POSN 0x5 #define _CVRCON_CVRSS_POSITION 0x5 #define _CVRCON_CVRSS_SIZE 0x1 #define _CVRCON_CVRSS_LENGTH 0x1 #define _CVRCON_CVRSS_MASK 0x20 #define _CVRCON_CVROE_POSN 0x6 #define _CVRCON_CVROE_POSITION 0x6 #define _CVRCON_CVROE_SIZE 0x1 #define _CVRCON_CVROE_LENGTH 0x1 #define _CVRCON_CVROE_MASK 0x40 #define _CVRCON_CVREN_POSN 0x7 #define _CVRCON_CVREN_POSITION 0x7 #define _CVRCON_CVREN_SIZE 0x1 #define _CVRCON_CVREN_LENGTH 0x1 #define _CVRCON_CVREN_MASK 0x80 #define _CVRCON_CVR0_POSN 0x0 #define _CVRCON_CVR0_POSITION 0x0 #define _CVRCON_CVR0_SIZE 0x1 #define _CVRCON_CVR0_LENGTH 0x1 #define _CVRCON_CVR0_MASK 0x1 #define _CVRCON_CVR1_POSN 0x1 #define _CVRCON_CVR1_POSITION 0x1 #define _CVRCON_CVR1_SIZE 0x1 #define _CVRCON_CVR1_LENGTH 0x1 #define _CVRCON_CVR1_MASK 0x2 #define _CVRCON_CVR2_POSN 0x2 #define _CVRCON_CVR2_POSITION 0x2 #define _CVRCON_CVR2_SIZE 0x1 #define _CVRCON_CVR2_LENGTH 0x1 #define _CVRCON_CVR2_MASK 0x4 #define _CVRCON_CVR3_POSN 0x3 #define _CVRCON_CVR3_POSITION 0x3 #define _CVRCON_CVR3_SIZE 0x1 #define _CVRCON_CVR3_LENGTH 0x1 #define _CVRCON_CVR3_MASK 0x8 #define _CVRCON_CVR4_POSN 0x4 #define _CVRCON_CVR4_POSITION 0x4 #define _CVRCON_CVR4_SIZE 0x1 #define _CVRCON_CVR4_LENGTH 0x1 #define _CVRCON_CVR4_MASK 0x10 #define _CVRCON_CVRR_POSN 0x5 #define _CVRCON_CVRR_POSITION 0x5 #define _CVRCON_CVRR_SIZE 0x1 #define _CVRCON_CVRR_LENGTH 0x1 #define _CVRCON_CVRR_MASK 0x20 #define _CVRCON_CVROEN_POSN 0x6 #define _CVRCON_CVROEN_POSITION 0x6 #define _CVRCON_CVROEN_SIZE 0x1 #define _CVRCON_CVROEN_LENGTH 0x1 #define _CVRCON_CVROEN_MASK 0x40 // Register: PIE4 #define PIE4 PIE4 extern volatile unsigned char PIE4 @ 0xFB6; #ifndef _LIB_BUILD asm("PIE4 equ 0FB6h"); #endif // bitfield definitions typedef union { struct { unsigned CCP3IE :1; unsigned CCP4IE :1; unsigned CCP5IE :1; unsigned :1; unsigned CMP1IE :1; unsigned CMP2IE :1; unsigned EEIE :1; unsigned TMR4IE :1; }; } PIE4bits_t; extern volatile PIE4bits_t PIE4bits @ 0xFB6; // bitfield macros #define _PIE4_CCP3IE_POSN 0x0 #define _PIE4_CCP3IE_POSITION 0x0 #define _PIE4_CCP3IE_SIZE 0x1 #define _PIE4_CCP3IE_LENGTH 0x1 #define _PIE4_CCP3IE_MASK 0x1 #define _PIE4_CCP4IE_POSN 0x1 #define _PIE4_CCP4IE_POSITION 0x1 #define _PIE4_CCP4IE_SIZE 0x1 #define _PIE4_CCP4IE_LENGTH 0x1 #define _PIE4_CCP4IE_MASK 0x2 #define _PIE4_CCP5IE_POSN 0x2 #define _PIE4_CCP5IE_POSITION 0x2 #define _PIE4_CCP5IE_SIZE 0x1 #define _PIE4_CCP5IE_LENGTH 0x1 #define _PIE4_CCP5IE_MASK 0x4 #define _PIE4_CMP1IE_POSN 0x4 #define _PIE4_CMP1IE_POSITION 0x4 #define _PIE4_CMP1IE_SIZE 0x1 #define _PIE4_CMP1IE_LENGTH 0x1 #define _PIE4_CMP1IE_MASK 0x10 #define _PIE4_CMP2IE_POSN 0x5 #define _PIE4_CMP2IE_POSITION 0x5 #define _PIE4_CMP2IE_SIZE 0x1 #define _PIE4_CMP2IE_LENGTH 0x1 #define _PIE4_CMP2IE_MASK 0x20 #define _PIE4_EEIE_POSN 0x6 #define _PIE4_EEIE_POSITION 0x6 #define _PIE4_EEIE_SIZE 0x1 #define _PIE4_EEIE_LENGTH 0x1 #define _PIE4_EEIE_MASK 0x40 #define _PIE4_TMR4IE_POSN 0x7 #define _PIE4_TMR4IE_POSITION 0x7 #define _PIE4_TMR4IE_SIZE 0x1 #define _PIE4_TMR4IE_LENGTH 0x1 #define _PIE4_TMR4IE_MASK 0x80 // Register: PIR4 #define PIR4 PIR4 extern volatile unsigned char PIR4 @ 0xFB7; #ifndef _LIB_BUILD asm("PIR4 equ 0FB7h"); #endif // bitfield definitions typedef union { struct { unsigned CCP3IF :1; unsigned CCP4IF :1; unsigned CCP5IF :1; unsigned :1; unsigned CMP1IF :1; unsigned CMP2IF :1; unsigned EEIF :1; unsigned TMR4IF :1; }; } PIR4bits_t; extern volatile PIR4bits_t PIR4bits @ 0xFB7; // bitfield macros #define _PIR4_CCP3IF_POSN 0x0 #define _PIR4_CCP3IF_POSITION 0x0 #define _PIR4_CCP3IF_SIZE 0x1 #define _PIR4_CCP3IF_LENGTH 0x1 #define _PIR4_CCP3IF_MASK 0x1 #define _PIR4_CCP4IF_POSN 0x1 #define _PIR4_CCP4IF_POSITION 0x1 #define _PIR4_CCP4IF_SIZE 0x1 #define _PIR4_CCP4IF_LENGTH 0x1 #define _PIR4_CCP4IF_MASK 0x2 #define _PIR4_CCP5IF_POSN 0x2 #define _PIR4_CCP5IF_POSITION 0x2 #define _PIR4_CCP5IF_SIZE 0x1 #define _PIR4_CCP5IF_LENGTH 0x1 #define _PIR4_CCP5IF_MASK 0x4 #define _PIR4_CMP1IF_POSN 0x4 #define _PIR4_CMP1IF_POSITION 0x4 #define _PIR4_CMP1IF_SIZE 0x1 #define _PIR4_CMP1IF_LENGTH 0x1 #define _PIR4_CMP1IF_MASK 0x10 #define _PIR4_CMP2IF_POSN 0x5 #define _PIR4_CMP2IF_POSITION 0x5 #define _PIR4_CMP2IF_SIZE 0x1 #define _PIR4_CMP2IF_LENGTH 0x1 #define _PIR4_CMP2IF_MASK 0x20 #define _PIR4_EEIF_POSN 0x6 #define _PIR4_EEIF_POSITION 0x6 #define _PIR4_EEIF_SIZE 0x1 #define _PIR4_EEIF_LENGTH 0x1 #define _PIR4_EEIF_MASK 0x40 #define _PIR4_TMR4IF_POSN 0x7 #define _PIR4_TMR4IF_POSITION 0x7 #define _PIR4_TMR4IF_SIZE 0x1 #define _PIR4_TMR4IF_LENGTH 0x1 #define _PIR4_TMR4IF_MASK 0x80 // Register: IPR4 #define IPR4 IPR4 extern volatile unsigned char IPR4 @ 0xFB8; #ifndef _LIB_BUILD asm("IPR4 equ 0FB8h"); #endif // bitfield definitions typedef union { struct { unsigned CCP3IP :1; unsigned CCP4IP :1; unsigned CCP5IP :1; unsigned :1; unsigned CMP1IP :1; unsigned CMP2IP :1; unsigned EEIP :1; unsigned TMR4IP :1; }; struct { unsigned CCIP3IP :1; }; } IPR4bits_t; extern volatile IPR4bits_t IPR4bits @ 0xFB8; // bitfield macros #define _IPR4_CCP3IP_POSN 0x0 #define _IPR4_CCP3IP_POSITION 0x0 #define _IPR4_CCP3IP_SIZE 0x1 #define _IPR4_CCP3IP_LENGTH 0x1 #define _IPR4_CCP3IP_MASK 0x1 #define _IPR4_CCP4IP_POSN 0x1 #define _IPR4_CCP4IP_POSITION 0x1 #define _IPR4_CCP4IP_SIZE 0x1 #define _IPR4_CCP4IP_LENGTH 0x1 #define _IPR4_CCP4IP_MASK 0x2 #define _IPR4_CCP5IP_POSN 0x2 #define _IPR4_CCP5IP_POSITION 0x2 #define _IPR4_CCP5IP_SIZE 0x1 #define _IPR4_CCP5IP_LENGTH 0x1 #define _IPR4_CCP5IP_MASK 0x4 #define _IPR4_CMP1IP_POSN 0x4 #define _IPR4_CMP1IP_POSITION 0x4 #define _IPR4_CMP1IP_SIZE 0x1 #define _IPR4_CMP1IP_LENGTH 0x1 #define _IPR4_CMP1IP_MASK 0x10 #define _IPR4_CMP2IP_POSN 0x5 #define _IPR4_CMP2IP_POSITION 0x5 #define _IPR4_CMP2IP_SIZE 0x1 #define _IPR4_CMP2IP_LENGTH 0x1 #define _IPR4_CMP2IP_MASK 0x20 #define _IPR4_EEIP_POSN 0x6 #define _IPR4_EEIP_POSITION 0x6 #define _IPR4_EEIP_SIZE 0x1 #define _IPR4_EEIP_LENGTH 0x1 #define _IPR4_EEIP_MASK 0x40 #define _IPR4_TMR4IP_POSN 0x7 #define _IPR4_TMR4IP_POSITION 0x7 #define _IPR4_TMR4IP_SIZE 0x1 #define _IPR4_TMR4IP_LENGTH 0x1 #define _IPR4_TMR4IP_MASK 0x80 #define _IPR4_CCIP3IP_POSN 0x0 #define _IPR4_CCIP3IP_POSITION 0x0 #define _IPR4_CCIP3IP_SIZE 0x1 #define _IPR4_CCIP3IP_LENGTH 0x1 #define _IPR4_CCIP3IP_MASK 0x1 // Register: BAUDCON2 #define BAUDCON2 BAUDCON2 extern volatile unsigned char BAUDCON2 @ 0xFB9; #ifndef _LIB_BUILD asm("BAUDCON2 equ 0FB9h"); #endif // bitfield definitions typedef union { struct { unsigned ABDEN :1; unsigned WUE :1; unsigned :1; unsigned BRG16 :1; unsigned TXCKP :1; unsigned RXDTP :1; unsigned RCIDL :1; unsigned ABDOVF :1; }; struct { unsigned :6; unsigned RCMT :1; }; struct { unsigned ABDEN2 :1; unsigned WUE2 :1; unsigned :1; unsigned BRG162 :1; unsigned SCKP2 :1; unsigned DTRXP2 :1; unsigned RCIDL2 :1; unsigned ABDOVF2 :1; }; struct { unsigned :4; unsigned TXCKP2 :1; unsigned RXDTP2 :1; unsigned RCMT2 :1; }; } BAUDCON2bits_t; extern volatile BAUDCON2bits_t BAUDCON2bits @ 0xFB9; // bitfield macros #define _BAUDCON2_ABDEN_POSN 0x0 #define _BAUDCON2_ABDEN_POSITION 0x0 #define _BAUDCON2_ABDEN_SIZE 0x1 #define _BAUDCON2_ABDEN_LENGTH 0x1 #define _BAUDCON2_ABDEN_MASK 0x1 #define _BAUDCON2_WUE_POSN 0x1 #define _BAUDCON2_WUE_POSITION 0x1 #define _BAUDCON2_WUE_SIZE 0x1 #define _BAUDCON2_WUE_LENGTH 0x1 #define _BAUDCON2_WUE_MASK 0x2 #define _BAUDCON2_BRG16_POSN 0x3 #define _BAUDCON2_BRG16_POSITION 0x3 #define _BAUDCON2_BRG16_SIZE 0x1 #define _BAUDCON2_BRG16_LENGTH 0x1 #define _BAUDCON2_BRG16_MASK 0x8 #define _BAUDCON2_TXCKP_POSN 0x4 #define _BAUDCON2_TXCKP_POSITION 0x4 #define _BAUDCON2_TXCKP_SIZE 0x1 #define _BAUDCON2_TXCKP_LENGTH 0x1 #define _BAUDCON2_TXCKP_MASK 0x10 #define _BAUDCON2_RXDTP_POSN 0x5 #define _BAUDCON2_RXDTP_POSITION 0x5 #define _BAUDCON2_RXDTP_SIZE 0x1 #define _BAUDCON2_RXDTP_LENGTH 0x1 #define _BAUDCON2_RXDTP_MASK 0x20 #define _BAUDCON2_RCIDL_POSN 0x6 #define _BAUDCON2_RCIDL_POSITION 0x6 #define _BAUDCON2_RCIDL_SIZE 0x1 #define _BAUDCON2_RCIDL_LENGTH 0x1 #define _BAUDCON2_RCIDL_MASK 0x40 #define _BAUDCON2_ABDOVF_POSN 0x7 #define _BAUDCON2_ABDOVF_POSITION 0x7 #define _BAUDCON2_ABDOVF_SIZE 0x1 #define _BAUDCON2_ABDOVF_LENGTH 0x1 #define _BAUDCON2_ABDOVF_MASK 0x80 #define _BAUDCON2_RCMT_POSN 0x6 #define _BAUDCON2_RCMT_POSITION 0x6 #define _BAUDCON2_RCMT_SIZE 0x1 #define _BAUDCON2_RCMT_LENGTH 0x1 #define _BAUDCON2_RCMT_MASK 0x40 #define _BAUDCON2_ABDEN2_POSN 0x0 #define _BAUDCON2_ABDEN2_POSITION 0x0 #define _BAUDCON2_ABDEN2_SIZE 0x1 #define _BAUDCON2_ABDEN2_LENGTH 0x1 #define _BAUDCON2_ABDEN2_MASK 0x1 #define _BAUDCON2_WUE2_POSN 0x1 #define _BAUDCON2_WUE2_POSITION 0x1 #define _BAUDCON2_WUE2_SIZE 0x1 #define _BAUDCON2_WUE2_LENGTH 0x1 #define _BAUDCON2_WUE2_MASK 0x2 #define _BAUDCON2_BRG162_POSN 0x3 #define _BAUDCON2_BRG162_POSITION 0x3 #define _BAUDCON2_BRG162_SIZE 0x1 #define _BAUDCON2_BRG162_LENGTH 0x1 #define _BAUDCON2_BRG162_MASK 0x8 #define _BAUDCON2_SCKP2_POSN 0x4 #define _BAUDCON2_SCKP2_POSITION 0x4 #define _BAUDCON2_SCKP2_SIZE 0x1 #define _BAUDCON2_SCKP2_LENGTH 0x1 #define _BAUDCON2_SCKP2_MASK 0x10 #define _BAUDCON2_DTRXP2_POSN 0x5 #define _BAUDCON2_DTRXP2_POSITION 0x5 #define _BAUDCON2_DTRXP2_SIZE 0x1 #define _BAUDCON2_DTRXP2_LENGTH 0x1 #define _BAUDCON2_DTRXP2_MASK 0x20 #define _BAUDCON2_RCIDL2_POSN 0x6 #define _BAUDCON2_RCIDL2_POSITION 0x6 #define _BAUDCON2_RCIDL2_SIZE 0x1 #define _BAUDCON2_RCIDL2_LENGTH 0x1 #define _BAUDCON2_RCIDL2_MASK 0x40 #define _BAUDCON2_ABDOVF2_POSN 0x7 #define _BAUDCON2_ABDOVF2_POSITION 0x7 #define _BAUDCON2_ABDOVF2_SIZE 0x1 #define _BAUDCON2_ABDOVF2_LENGTH 0x1 #define _BAUDCON2_ABDOVF2_MASK 0x80 #define _BAUDCON2_TXCKP2_POSN 0x4 #define _BAUDCON2_TXCKP2_POSITION 0x4 #define _BAUDCON2_TXCKP2_SIZE 0x1 #define _BAUDCON2_TXCKP2_LENGTH 0x1 #define _BAUDCON2_TXCKP2_MASK 0x10 #define _BAUDCON2_RXDTP2_POSN 0x5 #define _BAUDCON2_RXDTP2_POSITION 0x5 #define _BAUDCON2_RXDTP2_SIZE 0x1 #define _BAUDCON2_RXDTP2_LENGTH 0x1 #define _BAUDCON2_RXDTP2_MASK 0x20 #define _BAUDCON2_RCMT2_POSN 0x6 #define _BAUDCON2_RCMT2_POSITION 0x6 #define _BAUDCON2_RCMT2_SIZE 0x1 #define _BAUDCON2_RCMT2_LENGTH 0x1 #define _BAUDCON2_RCMT2_MASK 0x40 // Register: TXSTA2 #define TXSTA2 TXSTA2 extern volatile unsigned char TXSTA2 @ 0xFBA; #ifndef _LIB_BUILD asm("TXSTA2 equ 0FBAh"); #endif // bitfield definitions typedef union { struct { unsigned TX9D :1; unsigned TRMT :1; unsigned BRGH :1; unsigned SENDB :1; unsigned SYNC :1; unsigned TXEN :1; unsigned TX9 :1; unsigned CSRC :1; }; struct { unsigned TX9D2 :1; unsigned TRMT2 :1; unsigned BRGH2 :1; unsigned SENDB2 :1; unsigned SYNC2 :1; unsigned TXEN2 :1; unsigned TX92 :1; unsigned CSRC2 :1; }; struct { unsigned TXD82 :1; unsigned :5; unsigned TX8_92 :1; }; } TXSTA2bits_t; extern volatile TXSTA2bits_t TXSTA2bits @ 0xFBA; // bitfield macros #define _TXSTA2_TX9D_POSN 0x0 #define _TXSTA2_TX9D_POSITION 0x0 #define _TXSTA2_TX9D_SIZE 0x1 #define _TXSTA2_TX9D_LENGTH 0x1 #define _TXSTA2_TX9D_MASK 0x1 #define _TXSTA2_TRMT_POSN 0x1 #define _TXSTA2_TRMT_POSITION 0x1 #define _TXSTA2_TRMT_SIZE 0x1 #define _TXSTA2_TRMT_LENGTH 0x1 #define _TXSTA2_TRMT_MASK 0x2 #define _TXSTA2_BRGH_POSN 0x2 #define _TXSTA2_BRGH_POSITION 0x2 #define _TXSTA2_BRGH_SIZE 0x1 #define _TXSTA2_BRGH_LENGTH 0x1 #define _TXSTA2_BRGH_MASK 0x4 #define _TXSTA2_SENDB_POSN 0x3 #define _TXSTA2_SENDB_POSITION 0x3 #define _TXSTA2_SENDB_SIZE 0x1 #define _TXSTA2_SENDB_LENGTH 0x1 #define _TXSTA2_SENDB_MASK 0x8 #define _TXSTA2_SYNC_POSN 0x4 #define _TXSTA2_SYNC_POSITION 0x4 #define _TXSTA2_SYNC_SIZE 0x1 #define _TXSTA2_SYNC_LENGTH 0x1 #define _TXSTA2_SYNC_MASK 0x10 #define _TXSTA2_TXEN_POSN 0x5 #define _TXSTA2_TXEN_POSITION 0x5 #define _TXSTA2_TXEN_SIZE 0x1 #define _TXSTA2_TXEN_LENGTH 0x1 #define _TXSTA2_TXEN_MASK 0x20 #define _TXSTA2_TX9_POSN 0x6 #define _TXSTA2_TX9_POSITION 0x6 #define _TXSTA2_TX9_SIZE 0x1 #define _TXSTA2_TX9_LENGTH 0x1 #define _TXSTA2_TX9_MASK 0x40 #define _TXSTA2_CSRC_POSN 0x7 #define _TXSTA2_CSRC_POSITION 0x7 #define _TXSTA2_CSRC_SIZE 0x1 #define _TXSTA2_CSRC_LENGTH 0x1 #define _TXSTA2_CSRC_MASK 0x80 #define _TXSTA2_TX9D2_POSN 0x0 #define _TXSTA2_TX9D2_POSITION 0x0 #define _TXSTA2_TX9D2_SIZE 0x1 #define _TXSTA2_TX9D2_LENGTH 0x1 #define _TXSTA2_TX9D2_MASK 0x1 #define _TXSTA2_TRMT2_POSN 0x1 #define _TXSTA2_TRMT2_POSITION 0x1 #define _TXSTA2_TRMT2_SIZE 0x1 #define _TXSTA2_TRMT2_LENGTH 0x1 #define _TXSTA2_TRMT2_MASK 0x2 #define _TXSTA2_BRGH2_POSN 0x2 #define _TXSTA2_BRGH2_POSITION 0x2 #define _TXSTA2_BRGH2_SIZE 0x1 #define _TXSTA2_BRGH2_LENGTH 0x1 #define _TXSTA2_BRGH2_MASK 0x4 #define _TXSTA2_SENDB2_POSN 0x3 #define _TXSTA2_SENDB2_POSITION 0x3 #define _TXSTA2_SENDB2_SIZE 0x1 #define _TXSTA2_SENDB2_LENGTH 0x1 #define _TXSTA2_SENDB2_MASK 0x8 #define _TXSTA2_SYNC2_POSN 0x4 #define _TXSTA2_SYNC2_POSITION 0x4 #define _TXSTA2_SYNC2_SIZE 0x1 #define _TXSTA2_SYNC2_LENGTH 0x1 #define _TXSTA2_SYNC2_MASK 0x10 #define _TXSTA2_TXEN2_POSN 0x5 #define _TXSTA2_TXEN2_POSITION 0x5 #define _TXSTA2_TXEN2_SIZE 0x1 #define _TXSTA2_TXEN2_LENGTH 0x1 #define _TXSTA2_TXEN2_MASK 0x20 #define _TXSTA2_TX92_POSN 0x6 #define _TXSTA2_TX92_POSITION 0x6 #define _TXSTA2_TX92_SIZE 0x1 #define _TXSTA2_TX92_LENGTH 0x1 #define _TXSTA2_TX92_MASK 0x40 #define _TXSTA2_CSRC2_POSN 0x7 #define _TXSTA2_CSRC2_POSITION 0x7 #define _TXSTA2_CSRC2_SIZE 0x1 #define _TXSTA2_CSRC2_LENGTH 0x1 #define _TXSTA2_CSRC2_MASK 0x80 #define _TXSTA2_TXD82_POSN 0x0 #define _TXSTA2_TXD82_POSITION 0x0 #define _TXSTA2_TXD82_SIZE 0x1 #define _TXSTA2_TXD82_LENGTH 0x1 #define _TXSTA2_TXD82_MASK 0x1 #define _TXSTA2_TX8_92_POSN 0x6 #define _TXSTA2_TX8_92_POSITION 0x6 #define _TXSTA2_TX8_92_SIZE 0x1 #define _TXSTA2_TX8_92_LENGTH 0x1 #define _TXSTA2_TX8_92_MASK 0x40 // Register: CCP1CON #define CCP1CON CCP1CON extern volatile unsigned char CCP1CON @ 0xFBB; #ifndef _LIB_BUILD asm("CCP1CON equ 0FBBh"); #endif // aliases extern volatile unsigned char ECCP1CON @ 0xFBB; #ifndef _LIB_BUILD asm("ECCP1CON equ 0FBBh"); #endif // bitfield definitions typedef union { struct { unsigned CCP1M :4; unsigned DC1B :2; unsigned P1M :2; }; struct { unsigned CCP1M0 :1; unsigned CCP1M1 :1; unsigned CCP1M2 :1; unsigned CCP1M3 :1; unsigned DC1B0 :1; unsigned DC1B1 :1; unsigned P1M0 :1; unsigned P1M1 :1; }; struct { unsigned :4; unsigned CCP1Y :1; unsigned CCP1X :1; }; } CCP1CONbits_t; extern volatile CCP1CONbits_t CCP1CONbits @ 0xFBB; // bitfield macros #define _CCP1CON_CCP1M_POSN 0x0 #define _CCP1CON_CCP1M_POSITION 0x0 #define _CCP1CON_CCP1M_SIZE 0x4 #define _CCP1CON_CCP1M_LENGTH 0x4 #define _CCP1CON_CCP1M_MASK 0xF #define _CCP1CON_DC1B_POSN 0x4 #define _CCP1CON_DC1B_POSITION 0x4 #define _CCP1CON_DC1B_SIZE 0x2 #define _CCP1CON_DC1B_LENGTH 0x2 #define _CCP1CON_DC1B_MASK 0x30 #define _CCP1CON_P1M_POSN 0x6 #define _CCP1CON_P1M_POSITION 0x6 #define _CCP1CON_P1M_SIZE 0x2 #define _CCP1CON_P1M_LENGTH 0x2 #define _CCP1CON_P1M_MASK 0xC0 #define _CCP1CON_CCP1M0_POSN 0x0 #define _CCP1CON_CCP1M0_POSITION 0x0 #define _CCP1CON_CCP1M0_SIZE 0x1 #define _CCP1CON_CCP1M0_LENGTH 0x1 #define _CCP1CON_CCP1M0_MASK 0x1 #define _CCP1CON_CCP1M1_POSN 0x1 #define _CCP1CON_CCP1M1_POSITION 0x1 #define _CCP1CON_CCP1M1_SIZE 0x1 #define _CCP1CON_CCP1M1_LENGTH 0x1 #define _CCP1CON_CCP1M1_MASK 0x2 #define _CCP1CON_CCP1M2_POSN 0x2 #define _CCP1CON_CCP1M2_POSITION 0x2 #define _CCP1CON_CCP1M2_SIZE 0x1 #define _CCP1CON_CCP1M2_LENGTH 0x1 #define _CCP1CON_CCP1M2_MASK 0x4 #define _CCP1CON_CCP1M3_POSN 0x3 #define _CCP1CON_CCP1M3_POSITION 0x3 #define _CCP1CON_CCP1M3_SIZE 0x1 #define _CCP1CON_CCP1M3_LENGTH 0x1 #define _CCP1CON_CCP1M3_MASK 0x8 #define _CCP1CON_DC1B0_POSN 0x4 #define _CCP1CON_DC1B0_POSITION 0x4 #define _CCP1CON_DC1B0_SIZE 0x1 #define _CCP1CON_DC1B0_LENGTH 0x1 #define _CCP1CON_DC1B0_MASK 0x10 #define _CCP1CON_DC1B1_POSN 0x5 #define _CCP1CON_DC1B1_POSITION 0x5 #define _CCP1CON_DC1B1_SIZE 0x1 #define _CCP1CON_DC1B1_LENGTH 0x1 #define _CCP1CON_DC1B1_MASK 0x20 #define _CCP1CON_P1M0_POSN 0x6 #define _CCP1CON_P1M0_POSITION 0x6 #define _CCP1CON_P1M0_SIZE 0x1 #define _CCP1CON_P1M0_LENGTH 0x1 #define _CCP1CON_P1M0_MASK 0x40 #define _CCP1CON_P1M1_POSN 0x7 #define _CCP1CON_P1M1_POSITION 0x7 #define _CCP1CON_P1M1_SIZE 0x1 #define _CCP1CON_P1M1_LENGTH 0x1 #define _CCP1CON_P1M1_MASK 0x80 #define _CCP1CON_CCP1Y_POSN 0x4 #define _CCP1CON_CCP1Y_POSITION 0x4 #define _CCP1CON_CCP1Y_SIZE 0x1 #define _CCP1CON_CCP1Y_LENGTH 0x1 #define _CCP1CON_CCP1Y_MASK 0x10 #define _CCP1CON_CCP1X_POSN 0x5 #define _CCP1CON_CCP1X_POSITION 0x5 #define _CCP1CON_CCP1X_SIZE 0x1 #define _CCP1CON_CCP1X_LENGTH 0x1 #define _CCP1CON_CCP1X_MASK 0x20 // alias bitfield definitions typedef union { struct { unsigned CCP1M :4; unsigned DC1B :2; unsigned P1M :2; }; struct { unsigned CCP1M0 :1; unsigned CCP1M1 :1; unsigned CCP1M2 :1; unsigned CCP1M3 :1; unsigned DC1B0 :1; unsigned DC1B1 :1; unsigned P1M0 :1; unsigned P1M1 :1; }; struct { unsigned :4; unsigned CCP1Y :1; unsigned CCP1X :1; }; } ECCP1CONbits_t; extern volatile ECCP1CONbits_t ECCP1CONbits @ 0xFBB; // bitfield macros #define _ECCP1CON_CCP1M_POSN 0x0 #define _ECCP1CON_CCP1M_POSITION 0x0 #define _ECCP1CON_CCP1M_SIZE 0x4 #define _ECCP1CON_CCP1M_LENGTH 0x4 #define _ECCP1CON_CCP1M_MASK 0xF #define _ECCP1CON_DC1B_POSN 0x4 #define _ECCP1CON_DC1B_POSITION 0x4 #define _ECCP1CON_DC1B_SIZE 0x2 #define _ECCP1CON_DC1B_LENGTH 0x2 #define _ECCP1CON_DC1B_MASK 0x30 #define _ECCP1CON_P1M_POSN 0x6 #define _ECCP1CON_P1M_POSITION 0x6 #define _ECCP1CON_P1M_SIZE 0x2 #define _ECCP1CON_P1M_LENGTH 0x2 #define _ECCP1CON_P1M_MASK 0xC0 #define _ECCP1CON_CCP1M0_POSN 0x0 #define _ECCP1CON_CCP1M0_POSITION 0x0 #define _ECCP1CON_CCP1M0_SIZE 0x1 #define _ECCP1CON_CCP1M0_LENGTH 0x1 #define _ECCP1CON_CCP1M0_MASK 0x1 #define _ECCP1CON_CCP1M1_POSN 0x1 #define _ECCP1CON_CCP1M1_POSITION 0x1 #define _ECCP1CON_CCP1M1_SIZE 0x1 #define _ECCP1CON_CCP1M1_LENGTH 0x1 #define _ECCP1CON_CCP1M1_MASK 0x2 #define _ECCP1CON_CCP1M2_POSN 0x2 #define _ECCP1CON_CCP1M2_POSITION 0x2 #define _ECCP1CON_CCP1M2_SIZE 0x1 #define _ECCP1CON_CCP1M2_LENGTH 0x1 #define _ECCP1CON_CCP1M2_MASK 0x4 #define _ECCP1CON_CCP1M3_POSN 0x3 #define _ECCP1CON_CCP1M3_POSITION 0x3 #define _ECCP1CON_CCP1M3_SIZE 0x1 #define _ECCP1CON_CCP1M3_LENGTH 0x1 #define _ECCP1CON_CCP1M3_MASK 0x8 #define _ECCP1CON_DC1B0_POSN 0x4 #define _ECCP1CON_DC1B0_POSITION 0x4 #define _ECCP1CON_DC1B0_SIZE 0x1 #define _ECCP1CON_DC1B0_LENGTH 0x1 #define _ECCP1CON_DC1B0_MASK 0x10 #define _ECCP1CON_DC1B1_POSN 0x5 #define _ECCP1CON_DC1B1_POSITION 0x5 #define _ECCP1CON_DC1B1_SIZE 0x1 #define _ECCP1CON_DC1B1_LENGTH 0x1 #define _ECCP1CON_DC1B1_MASK 0x20 #define _ECCP1CON_P1M0_POSN 0x6 #define _ECCP1CON_P1M0_POSITION 0x6 #define _ECCP1CON_P1M0_SIZE 0x1 #define _ECCP1CON_P1M0_LENGTH 0x1 #define _ECCP1CON_P1M0_MASK 0x40 #define _ECCP1CON_P1M1_POSN 0x7 #define _ECCP1CON_P1M1_POSITION 0x7 #define _ECCP1CON_P1M1_SIZE 0x1 #define _ECCP1CON_P1M1_LENGTH 0x1 #define _ECCP1CON_P1M1_MASK 0x80 #define _ECCP1CON_CCP1Y_POSN 0x4 #define _ECCP1CON_CCP1Y_POSITION 0x4 #define _ECCP1CON_CCP1Y_SIZE 0x1 #define _ECCP1CON_CCP1Y_LENGTH 0x1 #define _ECCP1CON_CCP1Y_MASK 0x10 #define _ECCP1CON_CCP1X_POSN 0x5 #define _ECCP1CON_CCP1X_POSITION 0x5 #define _ECCP1CON_CCP1X_SIZE 0x1 #define _ECCP1CON_CCP1X_LENGTH 0x1 #define _ECCP1CON_CCP1X_MASK 0x20 // Register: CCPR1 #define CCPR1 CCPR1 extern volatile unsigned short CCPR1 @ 0xFBC; #ifndef _LIB_BUILD asm("CCPR1 equ 0FBCh"); #endif // Register: CCPR1L #define CCPR1L CCPR1L extern volatile unsigned char CCPR1L @ 0xFBC; #ifndef _LIB_BUILD asm("CCPR1L equ 0FBCh"); #endif // bitfield definitions typedef union { struct { unsigned CCPR1L :8; }; } CCPR1Lbits_t; extern volatile CCPR1Lbits_t CCPR1Lbits @ 0xFBC; // bitfield macros #define _CCPR1L_CCPR1L_POSN 0x0 #define _CCPR1L_CCPR1L_POSITION 0x0 #define _CCPR1L_CCPR1L_SIZE 0x8 #define _CCPR1L_CCPR1L_LENGTH 0x8 #define _CCPR1L_CCPR1L_MASK 0xFF // Register: CCPR1H #define CCPR1H CCPR1H extern volatile unsigned char CCPR1H @ 0xFBD; #ifndef _LIB_BUILD asm("CCPR1H equ 0FBDh"); #endif // bitfield definitions typedef union { struct { unsigned CCPR1H :8; }; } CCPR1Hbits_t; extern volatile CCPR1Hbits_t CCPR1Hbits @ 0xFBD; // bitfield macros #define _CCPR1H_CCPR1H_POSN 0x0 #define _CCPR1H_CCPR1H_POSITION 0x0 #define _CCPR1H_CCPR1H_SIZE 0x8 #define _CCPR1H_CCPR1H_LENGTH 0x8 #define _CCPR1H_CCPR1H_MASK 0xFF // Register: ECCP1DEL #define ECCP1DEL ECCP1DEL extern volatile unsigned char ECCP1DEL @ 0xFBE; #ifndef _LIB_BUILD asm("ECCP1DEL equ 0FBEh"); #endif // aliases extern volatile unsigned char PWM1CON @ 0xFBE; #ifndef _LIB_BUILD asm("PWM1CON equ 0FBEh"); #endif // bitfield definitions typedef union { struct { unsigned P1DC :7; unsigned P1RSEN :1; }; struct { unsigned P1DC0 :1; unsigned P1DC1 :1; unsigned P1DC2 :1; unsigned P1DC3 :1; unsigned P1DC4 :1; unsigned P1DC5 :1; unsigned P1DC6 :1; }; } ECCP1DELbits_t; extern volatile ECCP1DELbits_t ECCP1DELbits @ 0xFBE; // bitfield macros #define _ECCP1DEL_P1DC_POSN 0x0 #define _ECCP1DEL_P1DC_POSITION 0x0 #define _ECCP1DEL_P1DC_SIZE 0x7 #define _ECCP1DEL_P1DC_LENGTH 0x7 #define _ECCP1DEL_P1DC_MASK 0x7F #define _ECCP1DEL_P1RSEN_POSN 0x7 #define _ECCP1DEL_P1RSEN_POSITION 0x7 #define _ECCP1DEL_P1RSEN_SIZE 0x1 #define _ECCP1DEL_P1RSEN_LENGTH 0x1 #define _ECCP1DEL_P1RSEN_MASK 0x80 #define _ECCP1DEL_P1DC0_POSN 0x0 #define _ECCP1DEL_P1DC0_POSITION 0x0 #define _ECCP1DEL_P1DC0_SIZE 0x1 #define _ECCP1DEL_P1DC0_LENGTH 0x1 #define _ECCP1DEL_P1DC0_MASK 0x1 #define _ECCP1DEL_P1DC1_POSN 0x1 #define _ECCP1DEL_P1DC1_POSITION 0x1 #define _ECCP1DEL_P1DC1_SIZE 0x1 #define _ECCP1DEL_P1DC1_LENGTH 0x1 #define _ECCP1DEL_P1DC1_MASK 0x2 #define _ECCP1DEL_P1DC2_POSN 0x2 #define _ECCP1DEL_P1DC2_POSITION 0x2 #define _ECCP1DEL_P1DC2_SIZE 0x1 #define _ECCP1DEL_P1DC2_LENGTH 0x1 #define _ECCP1DEL_P1DC2_MASK 0x4 #define _ECCP1DEL_P1DC3_POSN 0x3 #define _ECCP1DEL_P1DC3_POSITION 0x3 #define _ECCP1DEL_P1DC3_SIZE 0x1 #define _ECCP1DEL_P1DC3_LENGTH 0x1 #define _ECCP1DEL_P1DC3_MASK 0x8 #define _ECCP1DEL_P1DC4_POSN 0x4 #define _ECCP1DEL_P1DC4_POSITION 0x4 #define _ECCP1DEL_P1DC4_SIZE 0x1 #define _ECCP1DEL_P1DC4_LENGTH 0x1 #define _ECCP1DEL_P1DC4_MASK 0x10 #define _ECCP1DEL_P1DC5_POSN 0x5 #define _ECCP1DEL_P1DC5_POSITION 0x5 #define _ECCP1DEL_P1DC5_SIZE 0x1 #define _ECCP1DEL_P1DC5_LENGTH 0x1 #define _ECCP1DEL_P1DC5_MASK 0x20 #define _ECCP1DEL_P1DC6_POSN 0x6 #define _ECCP1DEL_P1DC6_POSITION 0x6 #define _ECCP1DEL_P1DC6_SIZE 0x1 #define _ECCP1DEL_P1DC6_LENGTH 0x1 #define _ECCP1DEL_P1DC6_MASK 0x40 // alias bitfield definitions typedef union { struct { unsigned P1DC :7; unsigned P1RSEN :1; }; struct { unsigned P1DC0 :1; unsigned P1DC1 :1; unsigned P1DC2 :1; unsigned P1DC3 :1; unsigned P1DC4 :1; unsigned P1DC5 :1; unsigned P1DC6 :1; }; } PWM1CONbits_t; extern volatile PWM1CONbits_t PWM1CONbits @ 0xFBE; // bitfield macros #define _PWM1CON_P1DC_POSN 0x0 #define _PWM1CON_P1DC_POSITION 0x0 #define _PWM1CON_P1DC_SIZE 0x7 #define _PWM1CON_P1DC_LENGTH 0x7 #define _PWM1CON_P1DC_MASK 0x7F #define _PWM1CON_P1RSEN_POSN 0x7 #define _PWM1CON_P1RSEN_POSITION 0x7 #define _PWM1CON_P1RSEN_SIZE 0x1 #define _PWM1CON_P1RSEN_LENGTH 0x1 #define _PWM1CON_P1RSEN_MASK 0x80 #define _PWM1CON_P1DC0_POSN 0x0 #define _PWM1CON_P1DC0_POSITION 0x0 #define _PWM1CON_P1DC0_SIZE 0x1 #define _PWM1CON_P1DC0_LENGTH 0x1 #define _PWM1CON_P1DC0_MASK 0x1 #define _PWM1CON_P1DC1_POSN 0x1 #define _PWM1CON_P1DC1_POSITION 0x1 #define _PWM1CON_P1DC1_SIZE 0x1 #define _PWM1CON_P1DC1_LENGTH 0x1 #define _PWM1CON_P1DC1_MASK 0x2 #define _PWM1CON_P1DC2_POSN 0x2 #define _PWM1CON_P1DC2_POSITION 0x2 #define _PWM1CON_P1DC2_SIZE 0x1 #define _PWM1CON_P1DC2_LENGTH 0x1 #define _PWM1CON_P1DC2_MASK 0x4 #define _PWM1CON_P1DC3_POSN 0x3 #define _PWM1CON_P1DC3_POSITION 0x3 #define _PWM1CON_P1DC3_SIZE 0x1 #define _PWM1CON_P1DC3_LENGTH 0x1 #define _PWM1CON_P1DC3_MASK 0x8 #define _PWM1CON_P1DC4_POSN 0x4 #define _PWM1CON_P1DC4_POSITION 0x4 #define _PWM1CON_P1DC4_SIZE 0x1 #define _PWM1CON_P1DC4_LENGTH 0x1 #define _PWM1CON_P1DC4_MASK 0x10 #define _PWM1CON_P1DC5_POSN 0x5 #define _PWM1CON_P1DC5_POSITION 0x5 #define _PWM1CON_P1DC5_SIZE 0x1 #define _PWM1CON_P1DC5_LENGTH 0x1 #define _PWM1CON_P1DC5_MASK 0x20 #define _PWM1CON_P1DC6_POSN 0x6 #define _PWM1CON_P1DC6_POSITION 0x6 #define _PWM1CON_P1DC6_SIZE 0x1 #define _PWM1CON_P1DC6_LENGTH 0x1 #define _PWM1CON_P1DC6_MASK 0x40 // Register: ECCP1AS #define ECCP1AS ECCP1AS extern volatile unsigned char ECCP1AS @ 0xFBF; #ifndef _LIB_BUILD asm("ECCP1AS equ 0FBFh"); #endif // bitfield definitions typedef union { struct { unsigned PSS1BD :2; unsigned PSS1AC :2; unsigned ECCP1AS :3; unsigned ECCP1ASE :1; }; struct { unsigned PSS1BD0 :1; unsigned PSS1BD1 :1; unsigned PSS1AC0 :1; unsigned PSS1AC1 :1; unsigned ECCP1AS0 :1; unsigned ECCP1AS1 :1; unsigned ECCP1AS2 :1; }; } ECCP1ASbits_t; extern volatile ECCP1ASbits_t ECCP1ASbits @ 0xFBF; // bitfield macros #define _ECCP1AS_PSS1BD_POSN 0x0 #define _ECCP1AS_PSS1BD_POSITION 0x0 #define _ECCP1AS_PSS1BD_SIZE 0x2 #define _ECCP1AS_PSS1BD_LENGTH 0x2 #define _ECCP1AS_PSS1BD_MASK 0x3 #define _ECCP1AS_PSS1AC_POSN 0x2 #define _ECCP1AS_PSS1AC_POSITION 0x2 #define _ECCP1AS_PSS1AC_SIZE 0x2 #define _ECCP1AS_PSS1AC_LENGTH 0x2 #define _ECCP1AS_PSS1AC_MASK 0xC #define _ECCP1AS_ECCP1AS_POSN 0x4 #define _ECCP1AS_ECCP1AS_POSITION 0x4 #define _ECCP1AS_ECCP1AS_SIZE 0x3 #define _ECCP1AS_ECCP1AS_LENGTH 0x3 #define _ECCP1AS_ECCP1AS_MASK 0x70 #define _ECCP1AS_ECCP1ASE_POSN 0x7 #define _ECCP1AS_ECCP1ASE_POSITION 0x7 #define _ECCP1AS_ECCP1ASE_SIZE 0x1 #define _ECCP1AS_ECCP1ASE_LENGTH 0x1 #define _ECCP1AS_ECCP1ASE_MASK 0x80 #define _ECCP1AS_PSS1BD0_POSN 0x0 #define _ECCP1AS_PSS1BD0_POSITION 0x0 #define _ECCP1AS_PSS1BD0_SIZE 0x1 #define _ECCP1AS_PSS1BD0_LENGTH 0x1 #define _ECCP1AS_PSS1BD0_MASK 0x1 #define _ECCP1AS_PSS1BD1_POSN 0x1 #define _ECCP1AS_PSS1BD1_POSITION 0x1 #define _ECCP1AS_PSS1BD1_SIZE 0x1 #define _ECCP1AS_PSS1BD1_LENGTH 0x1 #define _ECCP1AS_PSS1BD1_MASK 0x2 #define _ECCP1AS_PSS1AC0_POSN 0x2 #define _ECCP1AS_PSS1AC0_POSITION 0x2 #define _ECCP1AS_PSS1AC0_SIZE 0x1 #define _ECCP1AS_PSS1AC0_LENGTH 0x1 #define _ECCP1AS_PSS1AC0_MASK 0x4 #define _ECCP1AS_PSS1AC1_POSN 0x3 #define _ECCP1AS_PSS1AC1_POSITION 0x3 #define _ECCP1AS_PSS1AC1_SIZE 0x1 #define _ECCP1AS_PSS1AC1_LENGTH 0x1 #define _ECCP1AS_PSS1AC1_MASK 0x8 #define _ECCP1AS_ECCP1AS0_POSN 0x4 #define _ECCP1AS_ECCP1AS0_POSITION 0x4 #define _ECCP1AS_ECCP1AS0_SIZE 0x1 #define _ECCP1AS_ECCP1AS0_LENGTH 0x1 #define _ECCP1AS_ECCP1AS0_MASK 0x10 #define _ECCP1AS_ECCP1AS1_POSN 0x5 #define _ECCP1AS_ECCP1AS1_POSITION 0x5 #define _ECCP1AS_ECCP1AS1_SIZE 0x1 #define _ECCP1AS_ECCP1AS1_LENGTH 0x1 #define _ECCP1AS_ECCP1AS1_MASK 0x20 #define _ECCP1AS_ECCP1AS2_POSN 0x6 #define _ECCP1AS_ECCP1AS2_POSITION 0x6 #define _ECCP1AS_ECCP1AS2_SIZE 0x1 #define _ECCP1AS_ECCP1AS2_LENGTH 0x1 #define _ECCP1AS_ECCP1AS2_MASK 0x40 // Register: ADCON2 #define ADCON2 ADCON2 extern volatile unsigned char ADCON2 @ 0xFC0; #ifndef _LIB_BUILD asm("ADCON2 equ 0FC0h"); #endif // bitfield definitions typedef union { struct { unsigned ADCS :3; unsigned ACQT :3; unsigned :1; unsigned ADFM :1; }; struct { unsigned ADCS0 :1; unsigned ADCS1 :1; unsigned ADCS2 :1; unsigned ACQT0 :1; unsigned ACQT1 :1; unsigned ACQT2 :1; }; } ADCON2bits_t; extern volatile ADCON2bits_t ADCON2bits @ 0xFC0; // bitfield macros #define _ADCON2_ADCS_POSN 0x0 #define _ADCON2_ADCS_POSITION 0x0 #define _ADCON2_ADCS_SIZE 0x3 #define _ADCON2_ADCS_LENGTH 0x3 #define _ADCON2_ADCS_MASK 0x7 #define _ADCON2_ACQT_POSN 0x3 #define _ADCON2_ACQT_POSITION 0x3 #define _ADCON2_ACQT_SIZE 0x3 #define _ADCON2_ACQT_LENGTH 0x3 #define _ADCON2_ACQT_MASK 0x38 #define _ADCON2_ADFM_POSN 0x7 #define _ADCON2_ADFM_POSITION 0x7 #define _ADCON2_ADFM_SIZE 0x1 #define _ADCON2_ADFM_LENGTH 0x1 #define _ADCON2_ADFM_MASK 0x80 #define _ADCON2_ADCS0_POSN 0x0 #define _ADCON2_ADCS0_POSITION 0x0 #define _ADCON2_ADCS0_SIZE 0x1 #define _ADCON2_ADCS0_LENGTH 0x1 #define _ADCON2_ADCS0_MASK 0x1 #define _ADCON2_ADCS1_POSN 0x1 #define _ADCON2_ADCS1_POSITION 0x1 #define _ADCON2_ADCS1_SIZE 0x1 #define _ADCON2_ADCS1_LENGTH 0x1 #define _ADCON2_ADCS1_MASK 0x2 #define _ADCON2_ADCS2_POSN 0x2 #define _ADCON2_ADCS2_POSITION 0x2 #define _ADCON2_ADCS2_SIZE 0x1 #define _ADCON2_ADCS2_LENGTH 0x1 #define _ADCON2_ADCS2_MASK 0x4 #define _ADCON2_ACQT0_POSN 0x3 #define _ADCON2_ACQT0_POSITION 0x3 #define _ADCON2_ACQT0_SIZE 0x1 #define _ADCON2_ACQT0_LENGTH 0x1 #define _ADCON2_ACQT0_MASK 0x8 #define _ADCON2_ACQT1_POSN 0x4 #define _ADCON2_ACQT1_POSITION 0x4 #define _ADCON2_ACQT1_SIZE 0x1 #define _ADCON2_ACQT1_LENGTH 0x1 #define _ADCON2_ACQT1_MASK 0x10 #define _ADCON2_ACQT2_POSN 0x5 #define _ADCON2_ACQT2_POSITION 0x5 #define _ADCON2_ACQT2_SIZE 0x1 #define _ADCON2_ACQT2_LENGTH 0x1 #define _ADCON2_ACQT2_MASK 0x20 // Register: ADCON1 #define ADCON1 ADCON1 extern volatile unsigned char ADCON1 @ 0xFC1; #ifndef _LIB_BUILD asm("ADCON1 equ 0FC1h"); #endif // bitfield definitions typedef union { struct { unsigned CHSN :3; unsigned VNCFG :1; unsigned VCFG :2; unsigned TRIGSEL :2; }; struct { unsigned CHSN0 :1; unsigned CHSN1 :1; unsigned CHSN2 :1; unsigned :1; unsigned VCFG0 :1; unsigned VCFG1 :1; unsigned TRIGSEL0 :1; unsigned TRIGSEL1 :1; }; struct { unsigned :3; unsigned CHSN3 :1; unsigned VCFG01 :1; unsigned VCFG11 :1; }; } ADCON1bits_t; extern volatile ADCON1bits_t ADCON1bits @ 0xFC1; // bitfield macros #define _ADCON1_CHSN_POSN 0x0 #define _ADCON1_CHSN_POSITION 0x0 #define _ADCON1_CHSN_SIZE 0x3 #define _ADCON1_CHSN_LENGTH 0x3 #define _ADCON1_CHSN_MASK 0x7 #define _ADCON1_VNCFG_POSN 0x3 #define _ADCON1_VNCFG_POSITION 0x3 #define _ADCON1_VNCFG_SIZE 0x1 #define _ADCON1_VNCFG_LENGTH 0x1 #define _ADCON1_VNCFG_MASK 0x8 #define _ADCON1_VCFG_POSN 0x4 #define _ADCON1_VCFG_POSITION 0x4 #define _ADCON1_VCFG_SIZE 0x2 #define _ADCON1_VCFG_LENGTH 0x2 #define _ADCON1_VCFG_MASK 0x30 #define _ADCON1_TRIGSEL_POSN 0x6 #define _ADCON1_TRIGSEL_POSITION 0x6 #define _ADCON1_TRIGSEL_SIZE 0x2 #define _ADCON1_TRIGSEL_LENGTH 0x2 #define _ADCON1_TRIGSEL_MASK 0xC0 #define _ADCON1_CHSN0_POSN 0x0 #define _ADCON1_CHSN0_POSITION 0x0 #define _ADCON1_CHSN0_SIZE 0x1 #define _ADCON1_CHSN0_LENGTH 0x1 #define _ADCON1_CHSN0_MASK 0x1 #define _ADCON1_CHSN1_POSN 0x1 #define _ADCON1_CHSN1_POSITION 0x1 #define _ADCON1_CHSN1_SIZE 0x1 #define _ADCON1_CHSN1_LENGTH 0x1 #define _ADCON1_CHSN1_MASK 0x2 #define _ADCON1_CHSN2_POSN 0x2 #define _ADCON1_CHSN2_POSITION 0x2 #define _ADCON1_CHSN2_SIZE 0x1 #define _ADCON1_CHSN2_LENGTH 0x1 #define _ADCON1_CHSN2_MASK 0x4 #define _ADCON1_VCFG0_POSN 0x4 #define _ADCON1_VCFG0_POSITION 0x4 #define _ADCON1_VCFG0_SIZE 0x1 #define _ADCON1_VCFG0_LENGTH 0x1 #define _ADCON1_VCFG0_MASK 0x10 #define _ADCON1_VCFG1_POSN 0x5 #define _ADCON1_VCFG1_POSITION 0x5 #define _ADCON1_VCFG1_SIZE 0x1 #define _ADCON1_VCFG1_LENGTH 0x1 #define _ADCON1_VCFG1_MASK 0x20 #define _ADCON1_TRIGSEL0_POSN 0x6 #define _ADCON1_TRIGSEL0_POSITION 0x6 #define _ADCON1_TRIGSEL0_SIZE 0x1 #define _ADCON1_TRIGSEL0_LENGTH 0x1 #define _ADCON1_TRIGSEL0_MASK 0x40 #define _ADCON1_TRIGSEL1_POSN 0x7 #define _ADCON1_TRIGSEL1_POSITION 0x7 #define _ADCON1_TRIGSEL1_SIZE 0x1 #define _ADCON1_TRIGSEL1_LENGTH 0x1 #define _ADCON1_TRIGSEL1_MASK 0x80 #define _ADCON1_CHSN3_POSN 0x3 #define _ADCON1_CHSN3_POSITION 0x3 #define _ADCON1_CHSN3_SIZE 0x1 #define _ADCON1_CHSN3_LENGTH 0x1 #define _ADCON1_CHSN3_MASK 0x8 #define _ADCON1_VCFG01_POSN 0x4 #define _ADCON1_VCFG01_POSITION 0x4 #define _ADCON1_VCFG01_SIZE 0x1 #define _ADCON1_VCFG01_LENGTH 0x1 #define _ADCON1_VCFG01_MASK 0x10 #define _ADCON1_VCFG11_POSN 0x5 #define _ADCON1_VCFG11_POSITION 0x5 #define _ADCON1_VCFG11_SIZE 0x1 #define _ADCON1_VCFG11_LENGTH 0x1 #define _ADCON1_VCFG11_MASK 0x20 // Register: ADCON0 #define ADCON0 ADCON0 extern volatile unsigned char ADCON0 @ 0xFC2; #ifndef _LIB_BUILD asm("ADCON0 equ 0FC2h"); #endif // bitfield definitions typedef union { struct { unsigned :1; unsigned GO_NOT_DONE :1; }; struct { unsigned ADON :1; unsigned GO_nDONE :1; unsigned CHS :5; }; struct { unsigned :1; unsigned DONE :1; unsigned CHS0 :1; unsigned CHS1 :1; unsigned CHS2 :1; unsigned CHS3 :1; unsigned CHS4 :1; }; struct { unsigned :1; unsigned GO :1; }; struct { unsigned :1; unsigned NOT_DONE :1; }; struct { unsigned :1; unsigned nDONE :1; }; struct { unsigned :1; unsigned GODONE :1; }; struct { unsigned :1; unsigned GO_DONE :1; }; } ADCON0bits_t; extern volatile ADCON0bits_t ADCON0bits @ 0xFC2; // bitfield macros #define _ADCON0_GO_NOT_DONE_POSN 0x1 #define _ADCON0_GO_NOT_DONE_POSITION 0x1 #define _ADCON0_GO_NOT_DONE_SIZE 0x1 #define _ADCON0_GO_NOT_DONE_LENGTH 0x1 #define _ADCON0_GO_NOT_DONE_MASK 0x2 #define _ADCON0_ADON_POSN 0x0 #define _ADCON0_ADON_POSITION 0x0 #define _ADCON0_ADON_SIZE 0x1 #define _ADCON0_ADON_LENGTH 0x1 #define _ADCON0_ADON_MASK 0x1 #define _ADCON0_GO_nDONE_POSN 0x1 #define _ADCON0_GO_nDONE_POSITION 0x1 #define _ADCON0_GO_nDONE_SIZE 0x1 #define _ADCON0_GO_nDONE_LENGTH 0x1 #define _ADCON0_GO_nDONE_MASK 0x2 #define _ADCON0_CHS_POSN 0x2 #define _ADCON0_CHS_POSITION 0x2 #define _ADCON0_CHS_SIZE 0x5 #define _ADCON0_CHS_LENGTH 0x5 #define _ADCON0_CHS_MASK 0x7C #define _ADCON0_DONE_POSN 0x1 #define _ADCON0_DONE_POSITION 0x1 #define _ADCON0_DONE_SIZE 0x1 #define _ADCON0_DONE_LENGTH 0x1 #define _ADCON0_DONE_MASK 0x2 #define _ADCON0_CHS0_POSN 0x2 #define _ADCON0_CHS0_POSITION 0x2 #define _ADCON0_CHS0_SIZE 0x1 #define _ADCON0_CHS0_LENGTH 0x1 #define _ADCON0_CHS0_MASK 0x4 #define _ADCON0_CHS1_POSN 0x3 #define _ADCON0_CHS1_POSITION 0x3 #define _ADCON0_CHS1_SIZE 0x1 #define _ADCON0_CHS1_LENGTH 0x1 #define _ADCON0_CHS1_MASK 0x8 #define _ADCON0_CHS2_POSN 0x4 #define _ADCON0_CHS2_POSITION 0x4 #define _ADCON0_CHS2_SIZE 0x1 #define _ADCON0_CHS2_LENGTH 0x1 #define _ADCON0_CHS2_MASK 0x10 #define _ADCON0_CHS3_POSN 0x5 #define _ADCON0_CHS3_POSITION 0x5 #define _ADCON0_CHS3_SIZE 0x1 #define _ADCON0_CHS3_LENGTH 0x1 #define _ADCON0_CHS3_MASK 0x20 #define _ADCON0_CHS4_POSN 0x6 #define _ADCON0_CHS4_POSITION 0x6 #define _ADCON0_CHS4_SIZE 0x1 #define _ADCON0_CHS4_LENGTH 0x1 #define _ADCON0_CHS4_MASK 0x40 #define _ADCON0_GO_POSN 0x1 #define _ADCON0_GO_POSITION 0x1 #define _ADCON0_GO_SIZE 0x1 #define _ADCON0_GO_LENGTH 0x1 #define _ADCON0_GO_MASK 0x2 #define _ADCON0_NOT_DONE_POSN 0x1 #define _ADCON0_NOT_DONE_POSITION 0x1 #define _ADCON0_NOT_DONE_SIZE 0x1 #define _ADCON0_NOT_DONE_LENGTH 0x1 #define _ADCON0_NOT_DONE_MASK 0x2 #define _ADCON0_nDONE_POSN 0x1 #define _ADCON0_nDONE_POSITION 0x1 #define _ADCON0_nDONE_SIZE 0x1 #define _ADCON0_nDONE_LENGTH 0x1 #define _ADCON0_nDONE_MASK 0x2 #define _ADCON0_GODONE_POSN 0x1 #define _ADCON0_GODONE_POSITION 0x1 #define _ADCON0_GODONE_SIZE 0x1 #define _ADCON0_GODONE_LENGTH 0x1 #define _ADCON0_GODONE_MASK 0x2 #define _ADCON0_GO_DONE_POSN 0x1 #define _ADCON0_GO_DONE_POSITION 0x1 #define _ADCON0_GO_DONE_SIZE 0x1 #define _ADCON0_GO_DONE_LENGTH 0x1 #define _ADCON0_GO_DONE_MASK 0x2 // Register: ADRES #define ADRES ADRES extern volatile unsigned short ADRES @ 0xFC3; #ifndef _LIB_BUILD asm("ADRES equ 0FC3h"); #endif // Register: ADRESL #define ADRESL ADRESL extern volatile unsigned char ADRESL @ 0xFC3; #ifndef _LIB_BUILD asm("ADRESL equ 0FC3h"); #endif // bitfield definitions typedef union { struct { unsigned ADRESL :8; }; } ADRESLbits_t; extern volatile ADRESLbits_t ADRESLbits @ 0xFC3; // bitfield macros #define _ADRESL_ADRESL_POSN 0x0 #define _ADRESL_ADRESL_POSITION 0x0 #define _ADRESL_ADRESL_SIZE 0x8 #define _ADRESL_ADRESL_LENGTH 0x8 #define _ADRESL_ADRESL_MASK 0xFF // Register: ADRESH #define ADRESH ADRESH extern volatile unsigned char ADRESH @ 0xFC4; #ifndef _LIB_BUILD asm("ADRESH equ 0FC4h"); #endif // bitfield definitions typedef union { struct { unsigned ADRESH :8; }; } ADRESHbits_t; extern volatile ADRESHbits_t ADRESHbits @ 0xFC4; // bitfield macros #define _ADRESH_ADRESH_POSN 0x0 #define _ADRESH_ADRESH_POSITION 0x0 #define _ADRESH_ADRESH_SIZE 0x8 #define _ADRESH_ADRESH_LENGTH 0x8 #define _ADRESH_ADRESH_MASK 0xFF // Register: SSPCON2 #define SSPCON2 SSPCON2 extern volatile unsigned char SSPCON2 @ 0xFC5; #ifndef _LIB_BUILD asm("SSPCON2 equ 0FC5h"); #endif // bitfield definitions typedef union { struct { unsigned SEN :1; unsigned RSEN :1; unsigned PEN :1; unsigned RCEN :1; unsigned ACKEN :1; unsigned ACKDT :1; unsigned ACKSTAT :1; unsigned GCEN :1; }; struct { unsigned :1; unsigned ADMSK1 :1; unsigned ADMSK2 :1; unsigned ADMSK3 :1; unsigned ADMSK4 :1; unsigned ADMSK5 :1; }; } SSPCON2bits_t; extern volatile SSPCON2bits_t SSPCON2bits @ 0xFC5; // bitfield macros #define _SSPCON2_SEN_POSN 0x0 #define _SSPCON2_SEN_POSITION 0x0 #define _SSPCON2_SEN_SIZE 0x1 #define _SSPCON2_SEN_LENGTH 0x1 #define _SSPCON2_SEN_MASK 0x1 #define _SSPCON2_RSEN_POSN 0x1 #define _SSPCON2_RSEN_POSITION 0x1 #define _SSPCON2_RSEN_SIZE 0x1 #define _SSPCON2_RSEN_LENGTH 0x1 #define _SSPCON2_RSEN_MASK 0x2 #define _SSPCON2_PEN_POSN 0x2 #define _SSPCON2_PEN_POSITION 0x2 #define _SSPCON2_PEN_SIZE 0x1 #define _SSPCON2_PEN_LENGTH 0x1 #define _SSPCON2_PEN_MASK 0x4 #define _SSPCON2_RCEN_POSN 0x3 #define _SSPCON2_RCEN_POSITION 0x3 #define _SSPCON2_RCEN_SIZE 0x1 #define _SSPCON2_RCEN_LENGTH 0x1 #define _SSPCON2_RCEN_MASK 0x8 #define _SSPCON2_ACKEN_POSN 0x4 #define _SSPCON2_ACKEN_POSITION 0x4 #define _SSPCON2_ACKEN_SIZE 0x1 #define _SSPCON2_ACKEN_LENGTH 0x1 #define _SSPCON2_ACKEN_MASK 0x10 #define _SSPCON2_ACKDT_POSN 0x5 #define _SSPCON2_ACKDT_POSITION 0x5 #define _SSPCON2_ACKDT_SIZE 0x1 #define _SSPCON2_ACKDT_LENGTH 0x1 #define _SSPCON2_ACKDT_MASK 0x20 #define _SSPCON2_ACKSTAT_POSN 0x6 #define _SSPCON2_ACKSTAT_POSITION 0x6 #define _SSPCON2_ACKSTAT_SIZE 0x1 #define _SSPCON2_ACKSTAT_LENGTH 0x1 #define _SSPCON2_ACKSTAT_MASK 0x40 #define _SSPCON2_GCEN_POSN 0x7 #define _SSPCON2_GCEN_POSITION 0x7 #define _SSPCON2_GCEN_SIZE 0x1 #define _SSPCON2_GCEN_LENGTH 0x1 #define _SSPCON2_GCEN_MASK 0x80 #define _SSPCON2_ADMSK1_POSN 0x1 #define _SSPCON2_ADMSK1_POSITION 0x1 #define _SSPCON2_ADMSK1_SIZE 0x1 #define _SSPCON2_ADMSK1_LENGTH 0x1 #define _SSPCON2_ADMSK1_MASK 0x2 #define _SSPCON2_ADMSK2_POSN 0x2 #define _SSPCON2_ADMSK2_POSITION 0x2 #define _SSPCON2_ADMSK2_SIZE 0x1 #define _SSPCON2_ADMSK2_LENGTH 0x1 #define _SSPCON2_ADMSK2_MASK 0x4 #define _SSPCON2_ADMSK3_POSN 0x3 #define _SSPCON2_ADMSK3_POSITION 0x3 #define _SSPCON2_ADMSK3_SIZE 0x1 #define _SSPCON2_ADMSK3_LENGTH 0x1 #define _SSPCON2_ADMSK3_MASK 0x8 #define _SSPCON2_ADMSK4_POSN 0x4 #define _SSPCON2_ADMSK4_POSITION 0x4 #define _SSPCON2_ADMSK4_SIZE 0x1 #define _SSPCON2_ADMSK4_LENGTH 0x1 #define _SSPCON2_ADMSK4_MASK 0x10 #define _SSPCON2_ADMSK5_POSN 0x5 #define _SSPCON2_ADMSK5_POSITION 0x5 #define _SSPCON2_ADMSK5_SIZE 0x1 #define _SSPCON2_ADMSK5_LENGTH 0x1 #define _SSPCON2_ADMSK5_MASK 0x20 // Register: SSPCON1 #define SSPCON1 SSPCON1 extern volatile unsigned char SSPCON1 @ 0xFC6; #ifndef _LIB_BUILD asm("SSPCON1 equ 0FC6h"); #endif // bitfield definitions typedef union { struct { unsigned SSPM :4; unsigned CKP :1; unsigned SSPEN :1; unsigned SSPOV :1; unsigned WCOL :1; }; struct { unsigned SSPM0 :1; unsigned SSPM1 :1; unsigned SSPM2 :1; unsigned SSPM3 :1; }; } SSPCON1bits_t; extern volatile SSPCON1bits_t SSPCON1bits @ 0xFC6; // bitfield macros #define _SSPCON1_SSPM_POSN 0x0 #define _SSPCON1_SSPM_POSITION 0x0 #define _SSPCON1_SSPM_SIZE 0x4 #define _SSPCON1_SSPM_LENGTH 0x4 #define _SSPCON1_SSPM_MASK 0xF #define _SSPCON1_CKP_POSN 0x4 #define _SSPCON1_CKP_POSITION 0x4 #define _SSPCON1_CKP_SIZE 0x1 #define _SSPCON1_CKP_LENGTH 0x1 #define _SSPCON1_CKP_MASK 0x10 #define _SSPCON1_SSPEN_POSN 0x5 #define _SSPCON1_SSPEN_POSITION 0x5 #define _SSPCON1_SSPEN_SIZE 0x1 #define _SSPCON1_SSPEN_LENGTH 0x1 #define _SSPCON1_SSPEN_MASK 0x20 #define _SSPCON1_SSPOV_POSN 0x6 #define _SSPCON1_SSPOV_POSITION 0x6 #define _SSPCON1_SSPOV_SIZE 0x1 #define _SSPCON1_SSPOV_LENGTH 0x1 #define _SSPCON1_SSPOV_MASK 0x40 #define _SSPCON1_WCOL_POSN 0x7 #define _SSPCON1_WCOL_POSITION 0x7 #define _SSPCON1_WCOL_SIZE 0x1 #define _SSPCON1_WCOL_LENGTH 0x1 #define _SSPCON1_WCOL_MASK 0x80 #define _SSPCON1_SSPM0_POSN 0x0 #define _SSPCON1_SSPM0_POSITION 0x0 #define _SSPCON1_SSPM0_SIZE 0x1 #define _SSPCON1_SSPM0_LENGTH 0x1 #define _SSPCON1_SSPM0_MASK 0x1 #define _SSPCON1_SSPM1_POSN 0x1 #define _SSPCON1_SSPM1_POSITION 0x1 #define _SSPCON1_SSPM1_SIZE 0x1 #define _SSPCON1_SSPM1_LENGTH 0x1 #define _SSPCON1_SSPM1_MASK 0x2 #define _SSPCON1_SSPM2_POSN 0x2 #define _SSPCON1_SSPM2_POSITION 0x2 #define _SSPCON1_SSPM2_SIZE 0x1 #define _SSPCON1_SSPM2_LENGTH 0x1 #define _SSPCON1_SSPM2_MASK 0x4 #define _SSPCON1_SSPM3_POSN 0x3 #define _SSPCON1_SSPM3_POSITION 0x3 #define _SSPCON1_SSPM3_SIZE 0x1 #define _SSPCON1_SSPM3_LENGTH 0x1 #define _SSPCON1_SSPM3_MASK 0x8 // Register: SSPSTAT #define SSPSTAT SSPSTAT extern volatile unsigned char SSPSTAT @ 0xFC7; #ifndef _LIB_BUILD asm("SSPSTAT equ 0FC7h"); #endif // bitfield definitions typedef union { struct { unsigned :2; unsigned R_NOT_W :1; }; struct { unsigned :5; unsigned D_NOT_A :1; }; struct { unsigned BF :1; unsigned UA :1; unsigned R_nW :1; unsigned S :1; unsigned P :1; unsigned D_nA :1; unsigned CKE :1; unsigned SMP :1; }; struct { unsigned :2; unsigned R_W :1; unsigned :2; unsigned D_A :1; }; struct { unsigned :2; unsigned nW :1; unsigned :2; unsigned nA :1; }; struct { unsigned :2; unsigned NOT_WRITE :1; }; struct { unsigned :5; unsigned NOT_ADDRESS :1; }; struct { unsigned :2; unsigned nWRITE :1; unsigned :2; unsigned nADDRESS :1; }; struct { unsigned :2; unsigned READ_WRITE :1; unsigned :2; unsigned DATA_ADDRESS :1; }; struct { unsigned :2; unsigned I2C_READ :1; unsigned I2C_START :1; unsigned I2C_STOP :1; unsigned I2C_DAT :1; }; struct { unsigned :2; unsigned RW :1; unsigned START :1; unsigned STOP :1; unsigned DA :1; }; struct { unsigned :2; unsigned NOT_W :1; unsigned :2; unsigned NOT_A :1; }; } SSPSTATbits_t; extern volatile SSPSTATbits_t SSPSTATbits @ 0xFC7; // bitfield macros #define _SSPSTAT_R_NOT_W_POSN 0x2 #define _SSPSTAT_R_NOT_W_POSITION 0x2 #define _SSPSTAT_R_NOT_W_SIZE 0x1 #define _SSPSTAT_R_NOT_W_LENGTH 0x1 #define _SSPSTAT_R_NOT_W_MASK 0x4 #define _SSPSTAT_D_NOT_A_POSN 0x5 #define _SSPSTAT_D_NOT_A_POSITION 0x5 #define _SSPSTAT_D_NOT_A_SIZE 0x1 #define _SSPSTAT_D_NOT_A_LENGTH 0x1 #define _SSPSTAT_D_NOT_A_MASK 0x20 #define _SSPSTAT_BF_POSN 0x0 #define _SSPSTAT_BF_POSITION 0x0 #define _SSPSTAT_BF_SIZE 0x1 #define _SSPSTAT_BF_LENGTH 0x1 #define _SSPSTAT_BF_MASK 0x1 #define _SSPSTAT_UA_POSN 0x1 #define _SSPSTAT_UA_POSITION 0x1 #define _SSPSTAT_UA_SIZE 0x1 #define _SSPSTAT_UA_LENGTH 0x1 #define _SSPSTAT_UA_MASK 0x2 #define _SSPSTAT_R_nW_POSN 0x2 #define _SSPSTAT_R_nW_POSITION 0x2 #define _SSPSTAT_R_nW_SIZE 0x1 #define _SSPSTAT_R_nW_LENGTH 0x1 #define _SSPSTAT_R_nW_MASK 0x4 #define _SSPSTAT_S_POSN 0x3 #define _SSPSTAT_S_POSITION 0x3 #define _SSPSTAT_S_SIZE 0x1 #define _SSPSTAT_S_LENGTH 0x1 #define _SSPSTAT_S_MASK 0x8 #define _SSPSTAT_P_POSN 0x4 #define _SSPSTAT_P_POSITION 0x4 #define _SSPSTAT_P_SIZE 0x1 #define _SSPSTAT_P_LENGTH 0x1 #define _SSPSTAT_P_MASK 0x10 #define _SSPSTAT_D_nA_POSN 0x5 #define _SSPSTAT_D_nA_POSITION 0x5 #define _SSPSTAT_D_nA_SIZE 0x1 #define _SSPSTAT_D_nA_LENGTH 0x1 #define _SSPSTAT_D_nA_MASK 0x20 #define _SSPSTAT_CKE_POSN 0x6 #define _SSPSTAT_CKE_POSITION 0x6 #define _SSPSTAT_CKE_SIZE 0x1 #define _SSPSTAT_CKE_LENGTH 0x1 #define _SSPSTAT_CKE_MASK 0x40 #define _SSPSTAT_SMP_POSN 0x7 #define _SSPSTAT_SMP_POSITION 0x7 #define _SSPSTAT_SMP_SIZE 0x1 #define _SSPSTAT_SMP_LENGTH 0x1 #define _SSPSTAT_SMP_MASK 0x80 #define _SSPSTAT_R_W_POSN 0x2 #define _SSPSTAT_R_W_POSITION 0x2 #define _SSPSTAT_R_W_SIZE 0x1 #define _SSPSTAT_R_W_LENGTH 0x1 #define _SSPSTAT_R_W_MASK 0x4 #define _SSPSTAT_D_A_POSN 0x5 #define _SSPSTAT_D_A_POSITION 0x5 #define _SSPSTAT_D_A_SIZE 0x1 #define _SSPSTAT_D_A_LENGTH 0x1 #define _SSPSTAT_D_A_MASK 0x20 #define _SSPSTAT_nW_POSN 0x2 #define _SSPSTAT_nW_POSITION 0x2 #define _SSPSTAT_nW_SIZE 0x1 #define _SSPSTAT_nW_LENGTH 0x1 #define _SSPSTAT_nW_MASK 0x4 #define _SSPSTAT_nA_POSN 0x5 #define _SSPSTAT_nA_POSITION 0x5 #define _SSPSTAT_nA_SIZE 0x1 #define _SSPSTAT_nA_LENGTH 0x1 #define _SSPSTAT_nA_MASK 0x20 #define _SSPSTAT_NOT_WRITE_POSN 0x2 #define _SSPSTAT_NOT_WRITE_POSITION 0x2 #define _SSPSTAT_NOT_WRITE_SIZE 0x1 #define _SSPSTAT_NOT_WRITE_LENGTH 0x1 #define _SSPSTAT_NOT_WRITE_MASK 0x4 #define _SSPSTAT_NOT_ADDRESS_POSN 0x5 #define _SSPSTAT_NOT_ADDRESS_POSITION 0x5 #define _SSPSTAT_NOT_ADDRESS_SIZE 0x1 #define _SSPSTAT_NOT_ADDRESS_LENGTH 0x1 #define _SSPSTAT_NOT_ADDRESS_MASK 0x20 #define _SSPSTAT_nWRITE_POSN 0x2 #define _SSPSTAT_nWRITE_POSITION 0x2 #define _SSPSTAT_nWRITE_SIZE 0x1 #define _SSPSTAT_nWRITE_LENGTH 0x1 #define _SSPSTAT_nWRITE_MASK 0x4 #define _SSPSTAT_nADDRESS_POSN 0x5 #define _SSPSTAT_nADDRESS_POSITION 0x5 #define _SSPSTAT_nADDRESS_SIZE 0x1 #define _SSPSTAT_nADDRESS_LENGTH 0x1 #define _SSPSTAT_nADDRESS_MASK 0x20 #define _SSPSTAT_READ_WRITE_POSN 0x2 #define _SSPSTAT_READ_WRITE_POSITION 0x2 #define _SSPSTAT_READ_WRITE_SIZE 0x1 #define _SSPSTAT_READ_WRITE_LENGTH 0x1 #define _SSPSTAT_READ_WRITE_MASK 0x4 #define _SSPSTAT_DATA_ADDRESS_POSN 0x5 #define _SSPSTAT_DATA_ADDRESS_POSITION 0x5 #define _SSPSTAT_DATA_ADDRESS_SIZE 0x1 #define _SSPSTAT_DATA_ADDRESS_LENGTH 0x1 #define _SSPSTAT_DATA_ADDRESS_MASK 0x20 #define _SSPSTAT_I2C_READ_POSN 0x2 #define _SSPSTAT_I2C_READ_POSITION 0x2 #define _SSPSTAT_I2C_READ_SIZE 0x1 #define _SSPSTAT_I2C_READ_LENGTH 0x1 #define _SSPSTAT_I2C_READ_MASK 0x4 #define _SSPSTAT_I2C_START_POSN 0x3 #define _SSPSTAT_I2C_START_POSITION 0x3 #define _SSPSTAT_I2C_START_SIZE 0x1 #define _SSPSTAT_I2C_START_LENGTH 0x1 #define _SSPSTAT_I2C_START_MASK 0x8 #define _SSPSTAT_I2C_STOP_POSN 0x4 #define _SSPSTAT_I2C_STOP_POSITION 0x4 #define _SSPSTAT_I2C_STOP_SIZE 0x1 #define _SSPSTAT_I2C_STOP_LENGTH 0x1 #define _SSPSTAT_I2C_STOP_MASK 0x10 #define _SSPSTAT_I2C_DAT_POSN 0x5 #define _SSPSTAT_I2C_DAT_POSITION 0x5 #define _SSPSTAT_I2C_DAT_SIZE 0x1 #define _SSPSTAT_I2C_DAT_LENGTH 0x1 #define _SSPSTAT_I2C_DAT_MASK 0x20 #define _SSPSTAT_RW_POSN 0x2 #define _SSPSTAT_RW_POSITION 0x2 #define _SSPSTAT_RW_SIZE 0x1 #define _SSPSTAT_RW_LENGTH 0x1 #define _SSPSTAT_RW_MASK 0x4 #define _SSPSTAT_START_POSN 0x3 #define _SSPSTAT_START_POSITION 0x3 #define _SSPSTAT_START_SIZE 0x1 #define _SSPSTAT_START_LENGTH 0x1 #define _SSPSTAT_START_MASK 0x8 #define _SSPSTAT_STOP_POSN 0x4 #define _SSPSTAT_STOP_POSITION 0x4 #define _SSPSTAT_STOP_SIZE 0x1 #define _SSPSTAT_STOP_LENGTH 0x1 #define _SSPSTAT_STOP_MASK 0x10 #define _SSPSTAT_DA_POSN 0x5 #define _SSPSTAT_DA_POSITION 0x5 #define _SSPSTAT_DA_SIZE 0x1 #define _SSPSTAT_DA_LENGTH 0x1 #define _SSPSTAT_DA_MASK 0x20 #define _SSPSTAT_NOT_W_POSN 0x2 #define _SSPSTAT_NOT_W_POSITION 0x2 #define _SSPSTAT_NOT_W_SIZE 0x1 #define _SSPSTAT_NOT_W_LENGTH 0x1 #define _SSPSTAT_NOT_W_MASK 0x4 #define _SSPSTAT_NOT_A_POSN 0x5 #define _SSPSTAT_NOT_A_POSITION 0x5 #define _SSPSTAT_NOT_A_SIZE 0x1 #define _SSPSTAT_NOT_A_LENGTH 0x1 #define _SSPSTAT_NOT_A_MASK 0x20 // Register: SSPADD #define SSPADD SSPADD extern volatile unsigned char SSPADD @ 0xFC8; #ifndef _LIB_BUILD asm("SSPADD equ 0FC8h"); #endif // bitfield definitions typedef union { struct { unsigned SSPADD :8; }; struct { unsigned MSK0 :1; unsigned MSK1 :1; unsigned MSK2 :1; unsigned MSK3 :1; unsigned MSK4 :1; unsigned MSK5 :1; unsigned MSK6 :1; unsigned MSK7 :1; }; } SSPADDbits_t; extern volatile SSPADDbits_t SSPADDbits @ 0xFC8; // bitfield macros #define _SSPADD_SSPADD_POSN 0x0 #define _SSPADD_SSPADD_POSITION 0x0 #define _SSPADD_SSPADD_SIZE 0x8 #define _SSPADD_SSPADD_LENGTH 0x8 #define _SSPADD_SSPADD_MASK 0xFF #define _SSPADD_MSK0_POSN 0x0 #define _SSPADD_MSK0_POSITION 0x0 #define _SSPADD_MSK0_SIZE 0x1 #define _SSPADD_MSK0_LENGTH 0x1 #define _SSPADD_MSK0_MASK 0x1 #define _SSPADD_MSK1_POSN 0x1 #define _SSPADD_MSK1_POSITION 0x1 #define _SSPADD_MSK1_SIZE 0x1 #define _SSPADD_MSK1_LENGTH 0x1 #define _SSPADD_MSK1_MASK 0x2 #define _SSPADD_MSK2_POSN 0x2 #define _SSPADD_MSK2_POSITION 0x2 #define _SSPADD_MSK2_SIZE 0x1 #define _SSPADD_MSK2_LENGTH 0x1 #define _SSPADD_MSK2_MASK 0x4 #define _SSPADD_MSK3_POSN 0x3 #define _SSPADD_MSK3_POSITION 0x3 #define _SSPADD_MSK3_SIZE 0x1 #define _SSPADD_MSK3_LENGTH 0x1 #define _SSPADD_MSK3_MASK 0x8 #define _SSPADD_MSK4_POSN 0x4 #define _SSPADD_MSK4_POSITION 0x4 #define _SSPADD_MSK4_SIZE 0x1 #define _SSPADD_MSK4_LENGTH 0x1 #define _SSPADD_MSK4_MASK 0x10 #define _SSPADD_MSK5_POSN 0x5 #define _SSPADD_MSK5_POSITION 0x5 #define _SSPADD_MSK5_SIZE 0x1 #define _SSPADD_MSK5_LENGTH 0x1 #define _SSPADD_MSK5_MASK 0x20 #define _SSPADD_MSK6_POSN 0x6 #define _SSPADD_MSK6_POSITION 0x6 #define _SSPADD_MSK6_SIZE 0x1 #define _SSPADD_MSK6_LENGTH 0x1 #define _SSPADD_MSK6_MASK 0x40 #define _SSPADD_MSK7_POSN 0x7 #define _SSPADD_MSK7_POSITION 0x7 #define _SSPADD_MSK7_SIZE 0x1 #define _SSPADD_MSK7_LENGTH 0x1 #define _SSPADD_MSK7_MASK 0x80 // Register: SSPBUF #define SSPBUF SSPBUF extern volatile unsigned char SSPBUF @ 0xFC9; #ifndef _LIB_BUILD asm("SSPBUF equ 0FC9h"); #endif // bitfield definitions typedef union { struct { unsigned SSPBUF :8; }; } SSPBUFbits_t; extern volatile SSPBUFbits_t SSPBUFbits @ 0xFC9; // bitfield macros #define _SSPBUF_SSPBUF_POSN 0x0 #define _SSPBUF_SSPBUF_POSITION 0x0 #define _SSPBUF_SSPBUF_SIZE 0x8 #define _SSPBUF_SSPBUF_LENGTH 0x8 #define _SSPBUF_SSPBUF_MASK 0xFF // Register: T2CON #define T2CON T2CON extern volatile unsigned char T2CON @ 0xFCA; #ifndef _LIB_BUILD asm("T2CON equ 0FCAh"); #endif // bitfield definitions typedef union { struct { unsigned T2CKPS :2; unsigned TMR2ON :1; unsigned T2OUTPS :4; }; struct { unsigned T2CKPS0 :1; unsigned T2CKPS1 :1; unsigned :1; unsigned T2OUTPS0 :1; unsigned T2OUTPS1 :1; unsigned T2OUTPS2 :1; unsigned T2OUTPS3 :1; }; } T2CONbits_t; extern volatile T2CONbits_t T2CONbits @ 0xFCA; // bitfield macros #define _T2CON_T2CKPS_POSN 0x0 #define _T2CON_T2CKPS_POSITION 0x0 #define _T2CON_T2CKPS_SIZE 0x2 #define _T2CON_T2CKPS_LENGTH 0x2 #define _T2CON_T2CKPS_MASK 0x3 #define _T2CON_TMR2ON_POSN 0x2 #define _T2CON_TMR2ON_POSITION 0x2 #define _T2CON_TMR2ON_SIZE 0x1 #define _T2CON_TMR2ON_LENGTH 0x1 #define _T2CON_TMR2ON_MASK 0x4 #define _T2CON_T2OUTPS_POSN 0x3 #define _T2CON_T2OUTPS_POSITION 0x3 #define _T2CON_T2OUTPS_SIZE 0x4 #define _T2CON_T2OUTPS_LENGTH 0x4 #define _T2CON_T2OUTPS_MASK 0x78 #define _T2CON_T2CKPS0_POSN 0x0 #define _T2CON_T2CKPS0_POSITION 0x0 #define _T2CON_T2CKPS0_SIZE 0x1 #define _T2CON_T2CKPS0_LENGTH 0x1 #define _T2CON_T2CKPS0_MASK 0x1 #define _T2CON_T2CKPS1_POSN 0x1 #define _T2CON_T2CKPS1_POSITION 0x1 #define _T2CON_T2CKPS1_SIZE 0x1 #define _T2CON_T2CKPS1_LENGTH 0x1 #define _T2CON_T2CKPS1_MASK 0x2 #define _T2CON_T2OUTPS0_POSN 0x3 #define _T2CON_T2OUTPS0_POSITION 0x3 #define _T2CON_T2OUTPS0_SIZE 0x1 #define _T2CON_T2OUTPS0_LENGTH 0x1 #define _T2CON_T2OUTPS0_MASK 0x8 #define _T2CON_T2OUTPS1_POSN 0x4 #define _T2CON_T2OUTPS1_POSITION 0x4 #define _T2CON_T2OUTPS1_SIZE 0x1 #define _T2CON_T2OUTPS1_LENGTH 0x1 #define _T2CON_T2OUTPS1_MASK 0x10 #define _T2CON_T2OUTPS2_POSN 0x5 #define _T2CON_T2OUTPS2_POSITION 0x5 #define _T2CON_T2OUTPS2_SIZE 0x1 #define _T2CON_T2OUTPS2_LENGTH 0x1 #define _T2CON_T2OUTPS2_MASK 0x20 #define _T2CON_T2OUTPS3_POSN 0x6 #define _T2CON_T2OUTPS3_POSITION 0x6 #define _T2CON_T2OUTPS3_SIZE 0x1 #define _T2CON_T2OUTPS3_LENGTH 0x1 #define _T2CON_T2OUTPS3_MASK 0x40 // Register: PR2 #define PR2 PR2 extern volatile unsigned char PR2 @ 0xFCB; #ifndef _LIB_BUILD asm("PR2 equ 0FCBh"); #endif // aliases extern volatile unsigned char MEMCON @ 0xFCB; #ifndef _LIB_BUILD asm("MEMCON equ 0FCBh"); #endif // bitfield definitions typedef union { struct { unsigned PR2 :8; }; struct { unsigned :7; unsigned EBDIS :1; }; struct { unsigned :4; unsigned WAIT0 :1; }; struct { unsigned :5; unsigned WAIT1 :1; }; struct { unsigned WM0 :1; }; struct { unsigned :1; unsigned WM1 :1; }; } PR2bits_t; extern volatile PR2bits_t PR2bits @ 0xFCB; // bitfield macros #define _PR2_PR2_POSN 0x0 #define _PR2_PR2_POSITION 0x0 #define _PR2_PR2_SIZE 0x8 #define _PR2_PR2_LENGTH 0x8 #define _PR2_PR2_MASK 0xFF #define _PR2_EBDIS_POSN 0x7 #define _PR2_EBDIS_POSITION 0x7 #define _PR2_EBDIS_SIZE 0x1 #define _PR2_EBDIS_LENGTH 0x1 #define _PR2_EBDIS_MASK 0x80 #define _PR2_WAIT0_POSN 0x4 #define _PR2_WAIT0_POSITION 0x4 #define _PR2_WAIT0_SIZE 0x1 #define _PR2_WAIT0_LENGTH 0x1 #define _PR2_WAIT0_MASK 0x10 #define _PR2_WAIT1_POSN 0x5 #define _PR2_WAIT1_POSITION 0x5 #define _PR2_WAIT1_SIZE 0x1 #define _PR2_WAIT1_LENGTH 0x1 #define _PR2_WAIT1_MASK 0x20 #define _PR2_WM0_POSN 0x0 #define _PR2_WM0_POSITION 0x0 #define _PR2_WM0_SIZE 0x1 #define _PR2_WM0_LENGTH 0x1 #define _PR2_WM0_MASK 0x1 #define _PR2_WM1_POSN 0x1 #define _PR2_WM1_POSITION 0x1 #define _PR2_WM1_SIZE 0x1 #define _PR2_WM1_LENGTH 0x1 #define _PR2_WM1_MASK 0x2 // alias bitfield definitions typedef union { struct { unsigned PR2 :8; }; struct { unsigned :7; unsigned EBDIS :1; }; struct { unsigned :4; unsigned WAIT0 :1; }; struct { unsigned :5; unsigned WAIT1 :1; }; struct { unsigned WM0 :1; }; struct { unsigned :1; unsigned WM1 :1; }; } MEMCONbits_t; extern volatile MEMCONbits_t MEMCONbits @ 0xFCB; // bitfield macros #define _MEMCON_PR2_POSN 0x0 #define _MEMCON_PR2_POSITION 0x0 #define _MEMCON_PR2_SIZE 0x8 #define _MEMCON_PR2_LENGTH 0x8 #define _MEMCON_PR2_MASK 0xFF #define _MEMCON_EBDIS_POSN 0x7 #define _MEMCON_EBDIS_POSITION 0x7 #define _MEMCON_EBDIS_SIZE 0x1 #define _MEMCON_EBDIS_LENGTH 0x1 #define _MEMCON_EBDIS_MASK 0x80 #define _MEMCON_WAIT0_POSN 0x4 #define _MEMCON_WAIT0_POSITION 0x4 #define _MEMCON_WAIT0_SIZE 0x1 #define _MEMCON_WAIT0_LENGTH 0x1 #define _MEMCON_WAIT0_MASK 0x10 #define _MEMCON_WAIT1_POSN 0x5 #define _MEMCON_WAIT1_POSITION 0x5 #define _MEMCON_WAIT1_SIZE 0x1 #define _MEMCON_WAIT1_LENGTH 0x1 #define _MEMCON_WAIT1_MASK 0x20 #define _MEMCON_WM0_POSN 0x0 #define _MEMCON_WM0_POSITION 0x0 #define _MEMCON_WM0_SIZE 0x1 #define _MEMCON_WM0_LENGTH 0x1 #define _MEMCON_WM0_MASK 0x1 #define _MEMCON_WM1_POSN 0x1 #define _MEMCON_WM1_POSITION 0x1 #define _MEMCON_WM1_SIZE 0x1 #define _MEMCON_WM1_LENGTH 0x1 #define _MEMCON_WM1_MASK 0x2 // Register: TMR2 #define TMR2 TMR2 extern volatile unsigned char TMR2 @ 0xFCC; #ifndef _LIB_BUILD asm("TMR2 equ 0FCCh"); #endif // bitfield definitions typedef union { struct { unsigned TMR2 :8; }; } TMR2bits_t; extern volatile TMR2bits_t TMR2bits @ 0xFCC; // bitfield macros #define _TMR2_TMR2_POSN 0x0 #define _TMR2_TMR2_POSITION 0x0 #define _TMR2_TMR2_SIZE 0x8 #define _TMR2_TMR2_LENGTH 0x8 #define _TMR2_TMR2_MASK 0xFF // Register: T1CON #define T1CON T1CON extern volatile unsigned char T1CON @ 0xFCD; #ifndef _LIB_BUILD asm("T1CON equ 0FCDh"); #endif // bitfield definitions typedef union { struct { unsigned :2; unsigned NOT_T1SYNC :1; }; struct { unsigned TMR1ON :1; unsigned RD16 :1; unsigned nT1SYNC :1; unsigned SOSCEN :1; unsigned T1CKPS :2; unsigned TMR1CS :2; }; struct { unsigned :4; unsigned T1CKPS0 :1; unsigned T1CKPS1 :1; unsigned TMR1CS0 :1; unsigned TMR1CS1 :1; }; struct { unsigned :3; unsigned T1OSCEN :1; unsigned :3; unsigned T1RD16 :1; }; } T1CONbits_t; extern volatile T1CONbits_t T1CONbits @ 0xFCD; // bitfield macros #define _T1CON_NOT_T1SYNC_POSN 0x2 #define _T1CON_NOT_T1SYNC_POSITION 0x2 #define _T1CON_NOT_T1SYNC_SIZE 0x1 #define _T1CON_NOT_T1SYNC_LENGTH 0x1 #define _T1CON_NOT_T1SYNC_MASK 0x4 #define _T1CON_TMR1ON_POSN 0x0 #define _T1CON_TMR1ON_POSITION 0x0 #define _T1CON_TMR1ON_SIZE 0x1 #define _T1CON_TMR1ON_LENGTH 0x1 #define _T1CON_TMR1ON_MASK 0x1 #define _T1CON_RD16_POSN 0x1 #define _T1CON_RD16_POSITION 0x1 #define _T1CON_RD16_SIZE 0x1 #define _T1CON_RD16_LENGTH 0x1 #define _T1CON_RD16_MASK 0x2 #define _T1CON_nT1SYNC_POSN 0x2 #define _T1CON_nT1SYNC_POSITION 0x2 #define _T1CON_nT1SYNC_SIZE 0x1 #define _T1CON_nT1SYNC_LENGTH 0x1 #define _T1CON_nT1SYNC_MASK 0x4 #define _T1CON_SOSCEN_POSN 0x3 #define _T1CON_SOSCEN_POSITION 0x3 #define _T1CON_SOSCEN_SIZE 0x1 #define _T1CON_SOSCEN_LENGTH 0x1 #define _T1CON_SOSCEN_MASK 0x8 #define _T1CON_T1CKPS_POSN 0x4 #define _T1CON_T1CKPS_POSITION 0x4 #define _T1CON_T1CKPS_SIZE 0x2 #define _T1CON_T1CKPS_LENGTH 0x2 #define _T1CON_T1CKPS_MASK 0x30 #define _T1CON_TMR1CS_POSN 0x6 #define _T1CON_TMR1CS_POSITION 0x6 #define _T1CON_TMR1CS_SIZE 0x2 #define _T1CON_TMR1CS_LENGTH 0x2 #define _T1CON_TMR1CS_MASK 0xC0 #define _T1CON_T1CKPS0_POSN 0x4 #define _T1CON_T1CKPS0_POSITION 0x4 #define _T1CON_T1CKPS0_SIZE 0x1 #define _T1CON_T1CKPS0_LENGTH 0x1 #define _T1CON_T1CKPS0_MASK 0x10 #define _T1CON_T1CKPS1_POSN 0x5 #define _T1CON_T1CKPS1_POSITION 0x5 #define _T1CON_T1CKPS1_SIZE 0x1 #define _T1CON_T1CKPS1_LENGTH 0x1 #define _T1CON_T1CKPS1_MASK 0x20 #define _T1CON_TMR1CS0_POSN 0x6 #define _T1CON_TMR1CS0_POSITION 0x6 #define _T1CON_TMR1CS0_SIZE 0x1 #define _T1CON_TMR1CS0_LENGTH 0x1 #define _T1CON_TMR1CS0_MASK 0x40 #define _T1CON_TMR1CS1_POSN 0x7 #define _T1CON_TMR1CS1_POSITION 0x7 #define _T1CON_TMR1CS1_SIZE 0x1 #define _T1CON_TMR1CS1_LENGTH 0x1 #define _T1CON_TMR1CS1_MASK 0x80 #define _T1CON_T1OSCEN_POSN 0x3 #define _T1CON_T1OSCEN_POSITION 0x3 #define _T1CON_T1OSCEN_SIZE 0x1 #define _T1CON_T1OSCEN_LENGTH 0x1 #define _T1CON_T1OSCEN_MASK 0x8 #define _T1CON_T1RD16_POSN 0x7 #define _T1CON_T1RD16_POSITION 0x7 #define _T1CON_T1RD16_SIZE 0x1 #define _T1CON_T1RD16_LENGTH 0x1 #define _T1CON_T1RD16_MASK 0x80 // Register: TMR1 #define TMR1 TMR1 extern volatile unsigned short TMR1 @ 0xFCE; #ifndef _LIB_BUILD asm("TMR1 equ 0FCEh"); #endif // Register: TMR1L #define TMR1L TMR1L extern volatile unsigned char TMR1L @ 0xFCE; #ifndef _LIB_BUILD asm("TMR1L equ 0FCEh"); #endif // bitfield definitions typedef union { struct { unsigned TMR1L :8; }; } TMR1Lbits_t; extern volatile TMR1Lbits_t TMR1Lbits @ 0xFCE; // bitfield macros #define _TMR1L_TMR1L_POSN 0x0 #define _TMR1L_TMR1L_POSITION 0x0 #define _TMR1L_TMR1L_SIZE 0x8 #define _TMR1L_TMR1L_LENGTH 0x8 #define _TMR1L_TMR1L_MASK 0xFF // Register: TMR1H #define TMR1H TMR1H extern volatile unsigned char TMR1H @ 0xFCF; #ifndef _LIB_BUILD asm("TMR1H equ 0FCFh"); #endif // bitfield definitions typedef union { struct { unsigned TMR1H :8; }; } TMR1Hbits_t; extern volatile TMR1Hbits_t TMR1Hbits @ 0xFCF; // bitfield macros #define _TMR1H_TMR1H_POSN 0x0 #define _TMR1H_TMR1H_POSITION 0x0 #define _TMR1H_TMR1H_SIZE 0x8 #define _TMR1H_TMR1H_LENGTH 0x8 #define _TMR1H_TMR1H_MASK 0xFF // Register: RCON #define RCON RCON extern volatile unsigned char RCON @ 0xFD0; #ifndef _LIB_BUILD asm("RCON equ 0FD0h"); #endif // bitfield definitions typedef union { struct { unsigned NOT_BOR :1; }; struct { unsigned :1; unsigned NOT_POR :1; }; struct { unsigned :2; unsigned NOT_PD :1; }; struct { unsigned :3; unsigned NOT_TO :1; }; struct { unsigned :4; unsigned NOT_RI :1; }; struct { unsigned :5; unsigned NOT_CM :1; }; struct { unsigned nBOR :1; unsigned nPOR :1; unsigned nPD :1; unsigned nTO :1; unsigned nRI :1; unsigned nCM :1; unsigned SBOREN :1; unsigned IPEN :1; }; struct { unsigned BOR :1; unsigned POR :1; unsigned PD :1; unsigned TO :1; unsigned RI :1; unsigned CM :1; }; } RCONbits_t; extern volatile RCONbits_t RCONbits @ 0xFD0; // bitfield macros #define _RCON_NOT_BOR_POSN 0x0 #define _RCON_NOT_BOR_POSITION 0x0 #define _RCON_NOT_BOR_SIZE 0x1 #define _RCON_NOT_BOR_LENGTH 0x1 #define _RCON_NOT_BOR_MASK 0x1 #define _RCON_NOT_POR_POSN 0x1 #define _RCON_NOT_POR_POSITION 0x1 #define _RCON_NOT_POR_SIZE 0x1 #define _RCON_NOT_POR_LENGTH 0x1 #define _RCON_NOT_POR_MASK 0x2 #define _RCON_NOT_PD_POSN 0x2 #define _RCON_NOT_PD_POSITION 0x2 #define _RCON_NOT_PD_SIZE 0x1 #define _RCON_NOT_PD_LENGTH 0x1 #define _RCON_NOT_PD_MASK 0x4 #define _RCON_NOT_TO_POSN 0x3 #define _RCON_NOT_TO_POSITION 0x3 #define _RCON_NOT_TO_SIZE 0x1 #define _RCON_NOT_TO_LENGTH 0x1 #define _RCON_NOT_TO_MASK 0x8 #define _RCON_NOT_RI_POSN 0x4 #define _RCON_NOT_RI_POSITION 0x4 #define _RCON_NOT_RI_SIZE 0x1 #define _RCON_NOT_RI_LENGTH 0x1 #define _RCON_NOT_RI_MASK 0x10 #define _RCON_NOT_CM_POSN 0x5 #define _RCON_NOT_CM_POSITION 0x5 #define _RCON_NOT_CM_SIZE 0x1 #define _RCON_NOT_CM_LENGTH 0x1 #define _RCON_NOT_CM_MASK 0x20 #define _RCON_nBOR_POSN 0x0 #define _RCON_nBOR_POSITION 0x0 #define _RCON_nBOR_SIZE 0x1 #define _RCON_nBOR_LENGTH 0x1 #define _RCON_nBOR_MASK 0x1 #define _RCON_nPOR_POSN 0x1 #define _RCON_nPOR_POSITION 0x1 #define _RCON_nPOR_SIZE 0x1 #define _RCON_nPOR_LENGTH 0x1 #define _RCON_nPOR_MASK 0x2 #define _RCON_nPD_POSN 0x2 #define _RCON_nPD_POSITION 0x2 #define _RCON_nPD_SIZE 0x1 #define _RCON_nPD_LENGTH 0x1 #define _RCON_nPD_MASK 0x4 #define _RCON_nTO_POSN 0x3 #define _RCON_nTO_POSITION 0x3 #define _RCON_nTO_SIZE 0x1 #define _RCON_nTO_LENGTH 0x1 #define _RCON_nTO_MASK 0x8 #define _RCON_nRI_POSN 0x4 #define _RCON_nRI_POSITION 0x4 #define _RCON_nRI_SIZE 0x1 #define _RCON_nRI_LENGTH 0x1 #define _RCON_nRI_MASK 0x10 #define _RCON_nCM_POSN 0x5 #define _RCON_nCM_POSITION 0x5 #define _RCON_nCM_SIZE 0x1 #define _RCON_nCM_LENGTH 0x1 #define _RCON_nCM_MASK 0x20 #define _RCON_SBOREN_POSN 0x6 #define _RCON_SBOREN_POSITION 0x6 #define _RCON_SBOREN_SIZE 0x1 #define _RCON_SBOREN_LENGTH 0x1 #define _RCON_SBOREN_MASK 0x40 #define _RCON_IPEN_POSN 0x7 #define _RCON_IPEN_POSITION 0x7 #define _RCON_IPEN_SIZE 0x1 #define _RCON_IPEN_LENGTH 0x1 #define _RCON_IPEN_MASK 0x80 #define _RCON_BOR_POSN 0x0 #define _RCON_BOR_POSITION 0x0 #define _RCON_BOR_SIZE 0x1 #define _RCON_BOR_LENGTH 0x1 #define _RCON_BOR_MASK 0x1 #define _RCON_POR_POSN 0x1 #define _RCON_POR_POSITION 0x1 #define _RCON_POR_SIZE 0x1 #define _RCON_POR_LENGTH 0x1 #define _RCON_POR_MASK 0x2 #define _RCON_PD_POSN 0x2 #define _RCON_PD_POSITION 0x2 #define _RCON_PD_SIZE 0x1 #define _RCON_PD_LENGTH 0x1 #define _RCON_PD_MASK 0x4 #define _RCON_TO_POSN 0x3 #define _RCON_TO_POSITION 0x3 #define _RCON_TO_SIZE 0x1 #define _RCON_TO_LENGTH 0x1 #define _RCON_TO_MASK 0x8 #define _RCON_RI_POSN 0x4 #define _RCON_RI_POSITION 0x4 #define _RCON_RI_SIZE 0x1 #define _RCON_RI_LENGTH 0x1 #define _RCON_RI_MASK 0x10 #define _RCON_CM_POSN 0x5 #define _RCON_CM_POSITION 0x5 #define _RCON_CM_SIZE 0x1 #define _RCON_CM_LENGTH 0x1 #define _RCON_CM_MASK 0x20 // Register: WDTCON #define WDTCON WDTCON extern volatile unsigned char WDTCON @ 0xFD1; #ifndef _LIB_BUILD asm("WDTCON equ 0FD1h"); #endif // bitfield definitions typedef union { struct { unsigned SWDTEN :1; unsigned ULPSINK :1; unsigned ULPEN :1; unsigned :1; unsigned SRETEN :1; unsigned ULPLVL :1; unsigned :1; unsigned REGSLP :1; }; struct { unsigned SWDTE :1; }; } WDTCONbits_t; extern volatile WDTCONbits_t WDTCONbits @ 0xFD1; // bitfield macros #define _WDTCON_SWDTEN_POSN 0x0 #define _WDTCON_SWDTEN_POSITION 0x0 #define _WDTCON_SWDTEN_SIZE 0x1 #define _WDTCON_SWDTEN_LENGTH 0x1 #define _WDTCON_SWDTEN_MASK 0x1 #define _WDTCON_ULPSINK_POSN 0x1 #define _WDTCON_ULPSINK_POSITION 0x1 #define _WDTCON_ULPSINK_SIZE 0x1 #define _WDTCON_ULPSINK_LENGTH 0x1 #define _WDTCON_ULPSINK_MASK 0x2 #define _WDTCON_ULPEN_POSN 0x2 #define _WDTCON_ULPEN_POSITION 0x2 #define _WDTCON_ULPEN_SIZE 0x1 #define _WDTCON_ULPEN_LENGTH 0x1 #define _WDTCON_ULPEN_MASK 0x4 #define _WDTCON_SRETEN_POSN 0x4 #define _WDTCON_SRETEN_POSITION 0x4 #define _WDTCON_SRETEN_SIZE 0x1 #define _WDTCON_SRETEN_LENGTH 0x1 #define _WDTCON_SRETEN_MASK 0x10 #define _WDTCON_ULPLVL_POSN 0x5 #define _WDTCON_ULPLVL_POSITION 0x5 #define _WDTCON_ULPLVL_SIZE 0x1 #define _WDTCON_ULPLVL_LENGTH 0x1 #define _WDTCON_ULPLVL_MASK 0x20 #define _WDTCON_REGSLP_POSN 0x7 #define _WDTCON_REGSLP_POSITION 0x7 #define _WDTCON_REGSLP_SIZE 0x1 #define _WDTCON_REGSLP_LENGTH 0x1 #define _WDTCON_REGSLP_MASK 0x80 #define _WDTCON_SWDTE_POSN 0x0 #define _WDTCON_SWDTE_POSITION 0x0 #define _WDTCON_SWDTE_SIZE 0x1 #define _WDTCON_SWDTE_LENGTH 0x1 #define _WDTCON_SWDTE_MASK 0x1 // Register: OSCCON2 #define OSCCON2 OSCCON2 extern volatile unsigned char OSCCON2 @ 0xFD2; #ifndef _LIB_BUILD asm("OSCCON2 equ 0FD2h"); #endif // bitfield definitions typedef union { struct { unsigned MFIOSEL :1; unsigned MFIOFS :1; unsigned :1; unsigned SOSCGO :1; unsigned SOSCDRV :1; unsigned :1; unsigned SOSCRUN :1; }; struct { unsigned LVDL0 :1; unsigned LVDL1 :1; unsigned LVDL2 :1; unsigned LVDL3 :1; }; } OSCCON2bits_t; extern volatile OSCCON2bits_t OSCCON2bits @ 0xFD2; // bitfield macros #define _OSCCON2_MFIOSEL_POSN 0x0 #define _OSCCON2_MFIOSEL_POSITION 0x0 #define _OSCCON2_MFIOSEL_SIZE 0x1 #define _OSCCON2_MFIOSEL_LENGTH 0x1 #define _OSCCON2_MFIOSEL_MASK 0x1 #define _OSCCON2_MFIOFS_POSN 0x1 #define _OSCCON2_MFIOFS_POSITION 0x1 #define _OSCCON2_MFIOFS_SIZE 0x1 #define _OSCCON2_MFIOFS_LENGTH 0x1 #define _OSCCON2_MFIOFS_MASK 0x2 #define _OSCCON2_SOSCGO_POSN 0x3 #define _OSCCON2_SOSCGO_POSITION 0x3 #define _OSCCON2_SOSCGO_SIZE 0x1 #define _OSCCON2_SOSCGO_LENGTH 0x1 #define _OSCCON2_SOSCGO_MASK 0x8 #define _OSCCON2_SOSCDRV_POSN 0x4 #define _OSCCON2_SOSCDRV_POSITION 0x4 #define _OSCCON2_SOSCDRV_SIZE 0x1 #define _OSCCON2_SOSCDRV_LENGTH 0x1 #define _OSCCON2_SOSCDRV_MASK 0x10 #define _OSCCON2_SOSCRUN_POSN 0x6 #define _OSCCON2_SOSCRUN_POSITION 0x6 #define _OSCCON2_SOSCRUN_SIZE 0x1 #define _OSCCON2_SOSCRUN_LENGTH 0x1 #define _OSCCON2_SOSCRUN_MASK 0x40 #define _OSCCON2_LVDL0_POSN 0x0 #define _OSCCON2_LVDL0_POSITION 0x0 #define _OSCCON2_LVDL0_SIZE 0x1 #define _OSCCON2_LVDL0_LENGTH 0x1 #define _OSCCON2_LVDL0_MASK 0x1 #define _OSCCON2_LVDL1_POSN 0x1 #define _OSCCON2_LVDL1_POSITION 0x1 #define _OSCCON2_LVDL1_SIZE 0x1 #define _OSCCON2_LVDL1_LENGTH 0x1 #define _OSCCON2_LVDL1_MASK 0x2 #define _OSCCON2_LVDL2_POSN 0x2 #define _OSCCON2_LVDL2_POSITION 0x2 #define _OSCCON2_LVDL2_SIZE 0x1 #define _OSCCON2_LVDL2_LENGTH 0x1 #define _OSCCON2_LVDL2_MASK 0x4 #define _OSCCON2_LVDL3_POSN 0x3 #define _OSCCON2_LVDL3_POSITION 0x3 #define _OSCCON2_LVDL3_SIZE 0x1 #define _OSCCON2_LVDL3_LENGTH 0x1 #define _OSCCON2_LVDL3_MASK 0x8 // Register: OSCCON #define OSCCON OSCCON extern volatile unsigned char OSCCON @ 0xFD3; #ifndef _LIB_BUILD asm("OSCCON equ 0FD3h"); #endif // bitfield definitions typedef union { struct { unsigned SCS :2; unsigned HFIOFS :1; unsigned OSTS :1; unsigned IRCF :3; unsigned IDLEN :1; }; struct { unsigned SCS0 :1; unsigned SCS1 :1; unsigned :2; unsigned IRCF0 :1; unsigned IRCF1 :1; unsigned IRCF2 :1; }; } OSCCONbits_t; extern volatile OSCCONbits_t OSCCONbits @ 0xFD3; // bitfield macros #define _OSCCON_SCS_POSN 0x0 #define _OSCCON_SCS_POSITION 0x0 #define _OSCCON_SCS_SIZE 0x2 #define _OSCCON_SCS_LENGTH 0x2 #define _OSCCON_SCS_MASK 0x3 #define _OSCCON_HFIOFS_POSN 0x2 #define _OSCCON_HFIOFS_POSITION 0x2 #define _OSCCON_HFIOFS_SIZE 0x1 #define _OSCCON_HFIOFS_LENGTH 0x1 #define _OSCCON_HFIOFS_MASK 0x4 #define _OSCCON_OSTS_POSN 0x3 #define _OSCCON_OSTS_POSITION 0x3 #define _OSCCON_OSTS_SIZE 0x1 #define _OSCCON_OSTS_LENGTH 0x1 #define _OSCCON_OSTS_MASK 0x8 #define _OSCCON_IRCF_POSN 0x4 #define _OSCCON_IRCF_POSITION 0x4 #define _OSCCON_IRCF_SIZE 0x3 #define _OSCCON_IRCF_LENGTH 0x3 #define _OSCCON_IRCF_MASK 0x70 #define _OSCCON_IDLEN_POSN 0x7 #define _OSCCON_IDLEN_POSITION 0x7 #define _OSCCON_IDLEN_SIZE 0x1 #define _OSCCON_IDLEN_LENGTH 0x1 #define _OSCCON_IDLEN_MASK 0x80 #define _OSCCON_SCS0_POSN 0x0 #define _OSCCON_SCS0_POSITION 0x0 #define _OSCCON_SCS0_SIZE 0x1 #define _OSCCON_SCS0_LENGTH 0x1 #define _OSCCON_SCS0_MASK 0x1 #define _OSCCON_SCS1_POSN 0x1 #define _OSCCON_SCS1_POSITION 0x1 #define _OSCCON_SCS1_SIZE 0x1 #define _OSCCON_SCS1_LENGTH 0x1 #define _OSCCON_SCS1_MASK 0x2 #define _OSCCON_IRCF0_POSN 0x4 #define _OSCCON_IRCF0_POSITION 0x4 #define _OSCCON_IRCF0_SIZE 0x1 #define _OSCCON_IRCF0_LENGTH 0x1 #define _OSCCON_IRCF0_MASK 0x10 #define _OSCCON_IRCF1_POSN 0x5 #define _OSCCON_IRCF1_POSITION 0x5 #define _OSCCON_IRCF1_SIZE 0x1 #define _OSCCON_IRCF1_LENGTH 0x1 #define _OSCCON_IRCF1_MASK 0x20 #define _OSCCON_IRCF2_POSN 0x6 #define _OSCCON_IRCF2_POSITION 0x6 #define _OSCCON_IRCF2_SIZE 0x1 #define _OSCCON_IRCF2_LENGTH 0x1 #define _OSCCON_IRCF2_MASK 0x40 // Register: T0CON #define T0CON T0CON extern volatile unsigned char T0CON @ 0xFD5; #ifndef _LIB_BUILD asm("T0CON equ 0FD5h"); #endif // bitfield definitions typedef union { struct { unsigned T0PS :3; unsigned PSA :1; unsigned T0SE :1; unsigned T0CS :1; unsigned T08BIT :1; unsigned TMR0ON :1; }; struct { unsigned T0PS0 :1; unsigned T0PS1 :1; unsigned T0PS2 :1; }; } T0CONbits_t; extern volatile T0CONbits_t T0CONbits @ 0xFD5; // bitfield macros #define _T0CON_T0PS_POSN 0x0 #define _T0CON_T0PS_POSITION 0x0 #define _T0CON_T0PS_SIZE 0x3 #define _T0CON_T0PS_LENGTH 0x3 #define _T0CON_T0PS_MASK 0x7 #define _T0CON_PSA_POSN 0x3 #define _T0CON_PSA_POSITION 0x3 #define _T0CON_PSA_SIZE 0x1 #define _T0CON_PSA_LENGTH 0x1 #define _T0CON_PSA_MASK 0x8 #define _T0CON_T0SE_POSN 0x4 #define _T0CON_T0SE_POSITION 0x4 #define _T0CON_T0SE_SIZE 0x1 #define _T0CON_T0SE_LENGTH 0x1 #define _T0CON_T0SE_MASK 0x10 #define _T0CON_T0CS_POSN 0x5 #define _T0CON_T0CS_POSITION 0x5 #define _T0CON_T0CS_SIZE 0x1 #define _T0CON_T0CS_LENGTH 0x1 #define _T0CON_T0CS_MASK 0x20 #define _T0CON_T08BIT_POSN 0x6 #define _T0CON_T08BIT_POSITION 0x6 #define _T0CON_T08BIT_SIZE 0x1 #define _T0CON_T08BIT_LENGTH 0x1 #define _T0CON_T08BIT_MASK 0x40 #define _T0CON_TMR0ON_POSN 0x7 #define _T0CON_TMR0ON_POSITION 0x7 #define _T0CON_TMR0ON_SIZE 0x1 #define _T0CON_TMR0ON_LENGTH 0x1 #define _T0CON_TMR0ON_MASK 0x80 #define _T0CON_T0PS0_POSN 0x0 #define _T0CON_T0PS0_POSITION 0x0 #define _T0CON_T0PS0_SIZE 0x1 #define _T0CON_T0PS0_LENGTH 0x1 #define _T0CON_T0PS0_MASK 0x1 #define _T0CON_T0PS1_POSN 0x1 #define _T0CON_T0PS1_POSITION 0x1 #define _T0CON_T0PS1_SIZE 0x1 #define _T0CON_T0PS1_LENGTH 0x1 #define _T0CON_T0PS1_MASK 0x2 #define _T0CON_T0PS2_POSN 0x2 #define _T0CON_T0PS2_POSITION 0x2 #define _T0CON_T0PS2_SIZE 0x1 #define _T0CON_T0PS2_LENGTH 0x1 #define _T0CON_T0PS2_MASK 0x4 // Register: TMR0 #define TMR0 TMR0 extern volatile unsigned short TMR0 @ 0xFD6; #ifndef _LIB_BUILD asm("TMR0 equ 0FD6h"); #endif // Register: TMR0L #define TMR0L TMR0L extern volatile unsigned char TMR0L @ 0xFD6; #ifndef _LIB_BUILD asm("TMR0L equ 0FD6h"); #endif // bitfield definitions typedef union { struct { unsigned TMR0L :8; }; } TMR0Lbits_t; extern volatile TMR0Lbits_t TMR0Lbits @ 0xFD6; // bitfield macros #define _TMR0L_TMR0L_POSN 0x0 #define _TMR0L_TMR0L_POSITION 0x0 #define _TMR0L_TMR0L_SIZE 0x8 #define _TMR0L_TMR0L_LENGTH 0x8 #define _TMR0L_TMR0L_MASK 0xFF // Register: TMR0H #define TMR0H TMR0H extern volatile unsigned char TMR0H @ 0xFD7; #ifndef _LIB_BUILD asm("TMR0H equ 0FD7h"); #endif // bitfield definitions typedef union { struct { unsigned TMR0H :8; }; } TMR0Hbits_t; extern volatile TMR0Hbits_t TMR0Hbits @ 0xFD7; // bitfield macros #define _TMR0H_TMR0H_POSN 0x0 #define _TMR0H_TMR0H_POSITION 0x0 #define _TMR0H_TMR0H_SIZE 0x8 #define _TMR0H_TMR0H_LENGTH 0x8 #define _TMR0H_TMR0H_MASK 0xFF // Register: STATUS #define STATUS STATUS extern volatile unsigned char STATUS @ 0xFD8; #ifndef _LIB_BUILD asm("STATUS equ 0FD8h"); #endif // bitfield definitions typedef union { struct { unsigned C :1; unsigned DC :1; unsigned Z :1; unsigned OV :1; unsigned N :1; }; struct { unsigned CARRY :1; unsigned :1; unsigned ZERO :1; unsigned OVERFLOW :1; unsigned NEGATIVE :1; }; } STATUSbits_t; extern volatile STATUSbits_t STATUSbits @ 0xFD8; // bitfield macros #define _STATUS_C_POSN 0x0 #define _STATUS_C_POSITION 0x0 #define _STATUS_C_SIZE 0x1 #define _STATUS_C_LENGTH 0x1 #define _STATUS_C_MASK 0x1 #define _STATUS_DC_POSN 0x1 #define _STATUS_DC_POSITION 0x1 #define _STATUS_DC_SIZE 0x1 #define _STATUS_DC_LENGTH 0x1 #define _STATUS_DC_MASK 0x2 #define _STATUS_Z_POSN 0x2 #define _STATUS_Z_POSITION 0x2 #define _STATUS_Z_SIZE 0x1 #define _STATUS_Z_LENGTH 0x1 #define _STATUS_Z_MASK 0x4 #define _STATUS_OV_POSN 0x3 #define _STATUS_OV_POSITION 0x3 #define _STATUS_OV_SIZE 0x1 #define _STATUS_OV_LENGTH 0x1 #define _STATUS_OV_MASK 0x8 #define _STATUS_N_POSN 0x4 #define _STATUS_N_POSITION 0x4 #define _STATUS_N_SIZE 0x1 #define _STATUS_N_LENGTH 0x1 #define _STATUS_N_MASK 0x10 #define _STATUS_CARRY_POSN 0x0 #define _STATUS_CARRY_POSITION 0x0 #define _STATUS_CARRY_SIZE 0x1 #define _STATUS_CARRY_LENGTH 0x1 #define _STATUS_CARRY_MASK 0x1 #define _STATUS_ZERO_POSN 0x2 #define _STATUS_ZERO_POSITION 0x2 #define _STATUS_ZERO_SIZE 0x1 #define _STATUS_ZERO_LENGTH 0x1 #define _STATUS_ZERO_MASK 0x4 #define _STATUS_OVERFLOW_POSN 0x3 #define _STATUS_OVERFLOW_POSITION 0x3 #define _STATUS_OVERFLOW_SIZE 0x1 #define _STATUS_OVERFLOW_LENGTH 0x1 #define _STATUS_OVERFLOW_MASK 0x8 #define _STATUS_NEGATIVE_POSN 0x4 #define _STATUS_NEGATIVE_POSITION 0x4 #define _STATUS_NEGATIVE_SIZE 0x1 #define _STATUS_NEGATIVE_LENGTH 0x1 #define _STATUS_NEGATIVE_MASK 0x10 // Register: FSR2 #define FSR2 FSR2 extern volatile unsigned short FSR2 @ 0xFD9; #ifndef _LIB_BUILD asm("FSR2 equ 0FD9h"); #endif // Register: FSR2L #define FSR2L FSR2L extern volatile unsigned char FSR2L @ 0xFD9; #ifndef _LIB_BUILD asm("FSR2L equ 0FD9h"); #endif // bitfield definitions typedef union { struct { unsigned FSR2L :8; }; } FSR2Lbits_t; extern volatile FSR2Lbits_t FSR2Lbits @ 0xFD9; // bitfield macros #define _FSR2L_FSR2L_POSN 0x0 #define _FSR2L_FSR2L_POSITION 0x0 #define _FSR2L_FSR2L_SIZE 0x8 #define _FSR2L_FSR2L_LENGTH 0x8 #define _FSR2L_FSR2L_MASK 0xFF // Register: FSR2H #define FSR2H FSR2H extern volatile unsigned char FSR2H @ 0xFDA; #ifndef _LIB_BUILD asm("FSR2H equ 0FDAh"); #endif // bitfield definitions typedef union { struct { unsigned FSR2H :4; }; } FSR2Hbits_t; extern volatile FSR2Hbits_t FSR2Hbits @ 0xFDA; // bitfield macros #define _FSR2H_FSR2H_POSN 0x0 #define _FSR2H_FSR2H_POSITION 0x0 #define _FSR2H_FSR2H_SIZE 0x4 #define _FSR2H_FSR2H_LENGTH 0x4 #define _FSR2H_FSR2H_MASK 0xF // Register: PLUSW2 #define PLUSW2 PLUSW2 extern volatile unsigned char PLUSW2 @ 0xFDB; #ifndef _LIB_BUILD asm("PLUSW2 equ 0FDBh"); #endif // bitfield definitions typedef union { struct { unsigned PLUSW2 :8; }; } PLUSW2bits_t; extern volatile PLUSW2bits_t PLUSW2bits @ 0xFDB; // bitfield macros #define _PLUSW2_PLUSW2_POSN 0x0 #define _PLUSW2_PLUSW2_POSITION 0x0 #define _PLUSW2_PLUSW2_SIZE 0x8 #define _PLUSW2_PLUSW2_LENGTH 0x8 #define _PLUSW2_PLUSW2_MASK 0xFF // Register: PREINC2 #define PREINC2 PREINC2 extern volatile unsigned char PREINC2 @ 0xFDC; #ifndef _LIB_BUILD asm("PREINC2 equ 0FDCh"); #endif // bitfield definitions typedef union { struct { unsigned PREINC2 :8; }; } PREINC2bits_t; extern volatile PREINC2bits_t PREINC2bits @ 0xFDC; // bitfield macros #define _PREINC2_PREINC2_POSN 0x0 #define _PREINC2_PREINC2_POSITION 0x0 #define _PREINC2_PREINC2_SIZE 0x8 #define _PREINC2_PREINC2_LENGTH 0x8 #define _PREINC2_PREINC2_MASK 0xFF // Register: POSTDEC2 #define POSTDEC2 POSTDEC2 extern volatile unsigned char POSTDEC2 @ 0xFDD; #ifndef _LIB_BUILD asm("POSTDEC2 equ 0FDDh"); #endif // bitfield definitions typedef union { struct { unsigned POSTDEC2 :8; }; } POSTDEC2bits_t; extern volatile POSTDEC2bits_t POSTDEC2bits @ 0xFDD; // bitfield macros #define _POSTDEC2_POSTDEC2_POSN 0x0 #define _POSTDEC2_POSTDEC2_POSITION 0x0 #define _POSTDEC2_POSTDEC2_SIZE 0x8 #define _POSTDEC2_POSTDEC2_LENGTH 0x8 #define _POSTDEC2_POSTDEC2_MASK 0xFF // Register: POSTINC2 #define POSTINC2 POSTINC2 extern volatile unsigned char POSTINC2 @ 0xFDE; #ifndef _LIB_BUILD asm("POSTINC2 equ 0FDEh"); #endif // bitfield definitions typedef union { struct { unsigned POSTINC2 :8; }; } POSTINC2bits_t; extern volatile POSTINC2bits_t POSTINC2bits @ 0xFDE; // bitfield macros #define _POSTINC2_POSTINC2_POSN 0x0 #define _POSTINC2_POSTINC2_POSITION 0x0 #define _POSTINC2_POSTINC2_SIZE 0x8 #define _POSTINC2_POSTINC2_LENGTH 0x8 #define _POSTINC2_POSTINC2_MASK 0xFF // Register: INDF2 #define INDF2 INDF2 extern volatile unsigned char INDF2 @ 0xFDF; #ifndef _LIB_BUILD asm("INDF2 equ 0FDFh"); #endif // bitfield definitions typedef union { struct { unsigned INDF2 :8; }; } INDF2bits_t; extern volatile INDF2bits_t INDF2bits @ 0xFDF; // bitfield macros #define _INDF2_INDF2_POSN 0x0 #define _INDF2_INDF2_POSITION 0x0 #define _INDF2_INDF2_SIZE 0x8 #define _INDF2_INDF2_LENGTH 0x8 #define _INDF2_INDF2_MASK 0xFF // Register: BSR #define BSR BSR extern volatile unsigned char BSR @ 0xFE0; #ifndef _LIB_BUILD asm("BSR equ 0FE0h"); #endif // bitfield definitions typedef union { struct { unsigned BSR :4; }; } BSRbits_t; extern volatile BSRbits_t BSRbits @ 0xFE0; // bitfield macros #define _BSR_BSR_POSN 0x0 #define _BSR_BSR_POSITION 0x0 #define _BSR_BSR_SIZE 0x4 #define _BSR_BSR_LENGTH 0x4 #define _BSR_BSR_MASK 0xF // Register: FSR1 #define FSR1 FSR1 extern volatile unsigned short FSR1 @ 0xFE1; #ifndef _LIB_BUILD asm("FSR1 equ 0FE1h"); #endif // Register: FSR1L #define FSR1L FSR1L extern volatile unsigned char FSR1L @ 0xFE1; #ifndef _LIB_BUILD asm("FSR1L equ 0FE1h"); #endif // bitfield definitions typedef union { struct { unsigned FSR1L :8; }; } FSR1Lbits_t; extern volatile FSR1Lbits_t FSR1Lbits @ 0xFE1; // bitfield macros #define _FSR1L_FSR1L_POSN 0x0 #define _FSR1L_FSR1L_POSITION 0x0 #define _FSR1L_FSR1L_SIZE 0x8 #define _FSR1L_FSR1L_LENGTH 0x8 #define _FSR1L_FSR1L_MASK 0xFF // Register: FSR1H #define FSR1H FSR1H extern volatile unsigned char FSR1H @ 0xFE2; #ifndef _LIB_BUILD asm("FSR1H equ 0FE2h"); #endif // bitfield definitions typedef union { struct { unsigned FSR1H :4; }; } FSR1Hbits_t; extern volatile FSR1Hbits_t FSR1Hbits @ 0xFE2; // bitfield macros #define _FSR1H_FSR1H_POSN 0x0 #define _FSR1H_FSR1H_POSITION 0x0 #define _FSR1H_FSR1H_SIZE 0x4 #define _FSR1H_FSR1H_LENGTH 0x4 #define _FSR1H_FSR1H_MASK 0xF // Register: PLUSW1 #define PLUSW1 PLUSW1 extern volatile unsigned char PLUSW1 @ 0xFE3; #ifndef _LIB_BUILD asm("PLUSW1 equ 0FE3h"); #endif // bitfield definitions typedef union { struct { unsigned PLUSW1 :8; }; } PLUSW1bits_t; extern volatile PLUSW1bits_t PLUSW1bits @ 0xFE3; // bitfield macros #define _PLUSW1_PLUSW1_POSN 0x0 #define _PLUSW1_PLUSW1_POSITION 0x0 #define _PLUSW1_PLUSW1_SIZE 0x8 #define _PLUSW1_PLUSW1_LENGTH 0x8 #define _PLUSW1_PLUSW1_MASK 0xFF // Register: PREINC1 #define PREINC1 PREINC1 extern volatile unsigned char PREINC1 @ 0xFE4; #ifndef _LIB_BUILD asm("PREINC1 equ 0FE4h"); #endif // bitfield definitions typedef union { struct { unsigned PREINC1 :8; }; } PREINC1bits_t; extern volatile PREINC1bits_t PREINC1bits @ 0xFE4; // bitfield macros #define _PREINC1_PREINC1_POSN 0x0 #define _PREINC1_PREINC1_POSITION 0x0 #define _PREINC1_PREINC1_SIZE 0x8 #define _PREINC1_PREINC1_LENGTH 0x8 #define _PREINC1_PREINC1_MASK 0xFF // Register: POSTDEC1 #define POSTDEC1 POSTDEC1 extern volatile unsigned char POSTDEC1 @ 0xFE5; #ifndef _LIB_BUILD asm("POSTDEC1 equ 0FE5h"); #endif // bitfield definitions typedef union { struct { unsigned POSTDEC1 :8; }; } POSTDEC1bits_t; extern volatile POSTDEC1bits_t POSTDEC1bits @ 0xFE5; // bitfield macros #define _POSTDEC1_POSTDEC1_POSN 0x0 #define _POSTDEC1_POSTDEC1_POSITION 0x0 #define _POSTDEC1_POSTDEC1_SIZE 0x8 #define _POSTDEC1_POSTDEC1_LENGTH 0x8 #define _POSTDEC1_POSTDEC1_MASK 0xFF // Register: POSTINC1 #define POSTINC1 POSTINC1 extern volatile unsigned char POSTINC1 @ 0xFE6; #ifndef _LIB_BUILD asm("POSTINC1 equ 0FE6h"); #endif // bitfield definitions typedef union { struct { unsigned POSTINC1 :8; }; } POSTINC1bits_t; extern volatile POSTINC1bits_t POSTINC1bits @ 0xFE6; // bitfield macros #define _POSTINC1_POSTINC1_POSN 0x0 #define _POSTINC1_POSTINC1_POSITION 0x0 #define _POSTINC1_POSTINC1_SIZE 0x8 #define _POSTINC1_POSTINC1_LENGTH 0x8 #define _POSTINC1_POSTINC1_MASK 0xFF // Register: INDF1 #define INDF1 INDF1 extern volatile unsigned char INDF1 @ 0xFE7; #ifndef _LIB_BUILD asm("INDF1 equ 0FE7h"); #endif // bitfield definitions typedef union { struct { unsigned INDF1 :8; }; } INDF1bits_t; extern volatile INDF1bits_t INDF1bits @ 0xFE7; // bitfield macros #define _INDF1_INDF1_POSN 0x0 #define _INDF1_INDF1_POSITION 0x0 #define _INDF1_INDF1_SIZE 0x8 #define _INDF1_INDF1_LENGTH 0x8 #define _INDF1_INDF1_MASK 0xFF // Register: WREG #define WREG WREG extern volatile unsigned char WREG @ 0xFE8; #ifndef _LIB_BUILD asm("WREG equ 0FE8h"); #endif // bitfield definitions typedef union { struct { unsigned WREG :8; }; } WREGbits_t; extern volatile WREGbits_t WREGbits @ 0xFE8; // bitfield macros #define _WREG_WREG_POSN 0x0 #define _WREG_WREG_POSITION 0x0 #define _WREG_WREG_SIZE 0x8 #define _WREG_WREG_LENGTH 0x8 #define _WREG_WREG_MASK 0xFF // Register: FSR0 #define FSR0 FSR0 extern volatile unsigned short FSR0 @ 0xFE9; #ifndef _LIB_BUILD asm("FSR0 equ 0FE9h"); #endif // Register: FSR0L #define FSR0L FSR0L extern volatile unsigned char FSR0L @ 0xFE9; #ifndef _LIB_BUILD asm("FSR0L equ 0FE9h"); #endif // bitfield definitions typedef union { struct { unsigned FSR0L :8; }; } FSR0Lbits_t; extern volatile FSR0Lbits_t FSR0Lbits @ 0xFE9; // bitfield macros #define _FSR0L_FSR0L_POSN 0x0 #define _FSR0L_FSR0L_POSITION 0x0 #define _FSR0L_FSR0L_SIZE 0x8 #define _FSR0L_FSR0L_LENGTH 0x8 #define _FSR0L_FSR0L_MASK 0xFF // Register: FSR0H #define FSR0H FSR0H extern volatile unsigned char FSR0H @ 0xFEA; #ifndef _LIB_BUILD asm("FSR0H equ 0FEAh"); #endif // bitfield definitions typedef union { struct { unsigned FSR0H :4; }; } FSR0Hbits_t; extern volatile FSR0Hbits_t FSR0Hbits @ 0xFEA; // bitfield macros #define _FSR0H_FSR0H_POSN 0x0 #define _FSR0H_FSR0H_POSITION 0x0 #define _FSR0H_FSR0H_SIZE 0x4 #define _FSR0H_FSR0H_LENGTH 0x4 #define _FSR0H_FSR0H_MASK 0xF // Register: PLUSW0 #define PLUSW0 PLUSW0 extern volatile unsigned char PLUSW0 @ 0xFEB; #ifndef _LIB_BUILD asm("PLUSW0 equ 0FEBh"); #endif // bitfield definitions typedef union { struct { unsigned PLUSW0 :8; }; } PLUSW0bits_t; extern volatile PLUSW0bits_t PLUSW0bits @ 0xFEB; // bitfield macros #define _PLUSW0_PLUSW0_POSN 0x0 #define _PLUSW0_PLUSW0_POSITION 0x0 #define _PLUSW0_PLUSW0_SIZE 0x8 #define _PLUSW0_PLUSW0_LENGTH 0x8 #define _PLUSW0_PLUSW0_MASK 0xFF // Register: PREINC0 #define PREINC0 PREINC0 extern volatile unsigned char PREINC0 @ 0xFEC; #ifndef _LIB_BUILD asm("PREINC0 equ 0FECh"); #endif // bitfield definitions typedef union { struct { unsigned PREINC0 :8; }; } PREINC0bits_t; extern volatile PREINC0bits_t PREINC0bits @ 0xFEC; // bitfield macros #define _PREINC0_PREINC0_POSN 0x0 #define _PREINC0_PREINC0_POSITION 0x0 #define _PREINC0_PREINC0_SIZE 0x8 #define _PREINC0_PREINC0_LENGTH 0x8 #define _PREINC0_PREINC0_MASK 0xFF // Register: POSTDEC0 #define POSTDEC0 POSTDEC0 extern volatile unsigned char POSTDEC0 @ 0xFED; #ifndef _LIB_BUILD asm("POSTDEC0 equ 0FEDh"); #endif // bitfield definitions typedef union { struct { unsigned POSTDEC0 :8; }; } POSTDEC0bits_t; extern volatile POSTDEC0bits_t POSTDEC0bits @ 0xFED; // bitfield macros #define _POSTDEC0_POSTDEC0_POSN 0x0 #define _POSTDEC0_POSTDEC0_POSITION 0x0 #define _POSTDEC0_POSTDEC0_SIZE 0x8 #define _POSTDEC0_POSTDEC0_LENGTH 0x8 #define _POSTDEC0_POSTDEC0_MASK 0xFF // Register: POSTINC0 #define POSTINC0 POSTINC0 extern volatile unsigned char POSTINC0 @ 0xFEE; #ifndef _LIB_BUILD asm("POSTINC0 equ 0FEEh"); #endif // bitfield definitions typedef union { struct { unsigned POSTINC0 :8; }; } POSTINC0bits_t; extern volatile POSTINC0bits_t POSTINC0bits @ 0xFEE; // bitfield macros #define _POSTINC0_POSTINC0_POSN 0x0 #define _POSTINC0_POSTINC0_POSITION 0x0 #define _POSTINC0_POSTINC0_SIZE 0x8 #define _POSTINC0_POSTINC0_LENGTH 0x8 #define _POSTINC0_POSTINC0_MASK 0xFF // Register: INDF0 #define INDF0 INDF0 extern volatile unsigned char INDF0 @ 0xFEF; #ifndef _LIB_BUILD asm("INDF0 equ 0FEFh"); #endif // bitfield definitions typedef union { struct { unsigned INDF0 :8; }; } INDF0bits_t; extern volatile INDF0bits_t INDF0bits @ 0xFEF; // bitfield macros #define _INDF0_INDF0_POSN 0x0 #define _INDF0_INDF0_POSITION 0x0 #define _INDF0_INDF0_SIZE 0x8 #define _INDF0_INDF0_LENGTH 0x8 #define _INDF0_INDF0_MASK 0xFF // Register: INTCON3 #define INTCON3 INTCON3 extern volatile unsigned char INTCON3 @ 0xFF0; #ifndef _LIB_BUILD asm("INTCON3 equ 0FF0h"); #endif // bitfield definitions typedef union { struct { unsigned INT1IF :1; unsigned INT2IF :1; unsigned INT3IF :1; unsigned INT1IE :1; unsigned INT2IE :1; unsigned INT3IE :1; unsigned INT1IP :1; unsigned INT2IP :1; }; struct { unsigned INT1F :1; unsigned INT2F :1; unsigned INT3F :1; unsigned INT1E :1; unsigned INT2E :1; unsigned INT3E :1; unsigned INT1P :1; unsigned INT2P :1; }; } INTCON3bits_t; extern volatile INTCON3bits_t INTCON3bits @ 0xFF0; // bitfield macros #define _INTCON3_INT1IF_POSN 0x0 #define _INTCON3_INT1IF_POSITION 0x0 #define _INTCON3_INT1IF_SIZE 0x1 #define _INTCON3_INT1IF_LENGTH 0x1 #define _INTCON3_INT1IF_MASK 0x1 #define _INTCON3_INT2IF_POSN 0x1 #define _INTCON3_INT2IF_POSITION 0x1 #define _INTCON3_INT2IF_SIZE 0x1 #define _INTCON3_INT2IF_LENGTH 0x1 #define _INTCON3_INT2IF_MASK 0x2 #define _INTCON3_INT3IF_POSN 0x2 #define _INTCON3_INT3IF_POSITION 0x2 #define _INTCON3_INT3IF_SIZE 0x1 #define _INTCON3_INT3IF_LENGTH 0x1 #define _INTCON3_INT3IF_MASK 0x4 #define _INTCON3_INT1IE_POSN 0x3 #define _INTCON3_INT1IE_POSITION 0x3 #define _INTCON3_INT1IE_SIZE 0x1 #define _INTCON3_INT1IE_LENGTH 0x1 #define _INTCON3_INT1IE_MASK 0x8 #define _INTCON3_INT2IE_POSN 0x4 #define _INTCON3_INT2IE_POSITION 0x4 #define _INTCON3_INT2IE_SIZE 0x1 #define _INTCON3_INT2IE_LENGTH 0x1 #define _INTCON3_INT2IE_MASK 0x10 #define _INTCON3_INT3IE_POSN 0x5 #define _INTCON3_INT3IE_POSITION 0x5 #define _INTCON3_INT3IE_SIZE 0x1 #define _INTCON3_INT3IE_LENGTH 0x1 #define _INTCON3_INT3IE_MASK 0x20 #define _INTCON3_INT1IP_POSN 0x6 #define _INTCON3_INT1IP_POSITION 0x6 #define _INTCON3_INT1IP_SIZE 0x1 #define _INTCON3_INT1IP_LENGTH 0x1 #define _INTCON3_INT1IP_MASK 0x40 #define _INTCON3_INT2IP_POSN 0x7 #define _INTCON3_INT2IP_POSITION 0x7 #define _INTCON3_INT2IP_SIZE 0x1 #define _INTCON3_INT2IP_LENGTH 0x1 #define _INTCON3_INT2IP_MASK 0x80 #define _INTCON3_INT1F_POSN 0x0 #define _INTCON3_INT1F_POSITION 0x0 #define _INTCON3_INT1F_SIZE 0x1 #define _INTCON3_INT1F_LENGTH 0x1 #define _INTCON3_INT1F_MASK 0x1 #define _INTCON3_INT2F_POSN 0x1 #define _INTCON3_INT2F_POSITION 0x1 #define _INTCON3_INT2F_SIZE 0x1 #define _INTCON3_INT2F_LENGTH 0x1 #define _INTCON3_INT2F_MASK 0x2 #define _INTCON3_INT3F_POSN 0x2 #define _INTCON3_INT3F_POSITION 0x2 #define _INTCON3_INT3F_SIZE 0x1 #define _INTCON3_INT3F_LENGTH 0x1 #define _INTCON3_INT3F_MASK 0x4 #define _INTCON3_INT1E_POSN 0x3 #define _INTCON3_INT1E_POSITION 0x3 #define _INTCON3_INT1E_SIZE 0x1 #define _INTCON3_INT1E_LENGTH 0x1 #define _INTCON3_INT1E_MASK 0x8 #define _INTCON3_INT2E_POSN 0x4 #define _INTCON3_INT2E_POSITION 0x4 #define _INTCON3_INT2E_SIZE 0x1 #define _INTCON3_INT2E_LENGTH 0x1 #define _INTCON3_INT2E_MASK 0x10 #define _INTCON3_INT3E_POSN 0x5 #define _INTCON3_INT3E_POSITION 0x5 #define _INTCON3_INT3E_SIZE 0x1 #define _INTCON3_INT3E_LENGTH 0x1 #define _INTCON3_INT3E_MASK 0x20 #define _INTCON3_INT1P_POSN 0x6 #define _INTCON3_INT1P_POSITION 0x6 #define _INTCON3_INT1P_SIZE 0x1 #define _INTCON3_INT1P_LENGTH 0x1 #define _INTCON3_INT1P_MASK 0x40 #define _INTCON3_INT2P_POSN 0x7 #define _INTCON3_INT2P_POSITION 0x7 #define _INTCON3_INT2P_SIZE 0x1 #define _INTCON3_INT2P_LENGTH 0x1 #define _INTCON3_INT2P_MASK 0x80 // Register: INTCON2 #define INTCON2 INTCON2 extern volatile unsigned char INTCON2 @ 0xFF1; #ifndef _LIB_BUILD asm("INTCON2 equ 0FF1h"); #endif // bitfield definitions typedef union { struct { unsigned :7; unsigned NOT_RBPU :1; }; struct { unsigned RBIP :1; unsigned INT3IP :1; unsigned TMR0IP :1; unsigned INTEDG3 :1; unsigned INTEDG2 :1; unsigned INTEDG1 :1; unsigned INTEDG0 :1; unsigned nRBPU :1; }; struct { unsigned :1; unsigned INT3P :1; unsigned T0IP :1; unsigned :4; unsigned RBPU :1; }; } INTCON2bits_t; extern volatile INTCON2bits_t INTCON2bits @ 0xFF1; // bitfield macros #define _INTCON2_NOT_RBPU_POSN 0x7 #define _INTCON2_NOT_RBPU_POSITION 0x7 #define _INTCON2_NOT_RBPU_SIZE 0x1 #define _INTCON2_NOT_RBPU_LENGTH 0x1 #define _INTCON2_NOT_RBPU_MASK 0x80 #define _INTCON2_RBIP_POSN 0x0 #define _INTCON2_RBIP_POSITION 0x0 #define _INTCON2_RBIP_SIZE 0x1 #define _INTCON2_RBIP_LENGTH 0x1 #define _INTCON2_RBIP_MASK 0x1 #define _INTCON2_INT3IP_POSN 0x1 #define _INTCON2_INT3IP_POSITION 0x1 #define _INTCON2_INT3IP_SIZE 0x1 #define _INTCON2_INT3IP_LENGTH 0x1 #define _INTCON2_INT3IP_MASK 0x2 #define _INTCON2_TMR0IP_POSN 0x2 #define _INTCON2_TMR0IP_POSITION 0x2 #define _INTCON2_TMR0IP_SIZE 0x1 #define _INTCON2_TMR0IP_LENGTH 0x1 #define _INTCON2_TMR0IP_MASK 0x4 #define _INTCON2_INTEDG3_POSN 0x3 #define _INTCON2_INTEDG3_POSITION 0x3 #define _INTCON2_INTEDG3_SIZE 0x1 #define _INTCON2_INTEDG3_LENGTH 0x1 #define _INTCON2_INTEDG3_MASK 0x8 #define _INTCON2_INTEDG2_POSN 0x4 #define _INTCON2_INTEDG2_POSITION 0x4 #define _INTCON2_INTEDG2_SIZE 0x1 #define _INTCON2_INTEDG2_LENGTH 0x1 #define _INTCON2_INTEDG2_MASK 0x10 #define _INTCON2_INTEDG1_POSN 0x5 #define _INTCON2_INTEDG1_POSITION 0x5 #define _INTCON2_INTEDG1_SIZE 0x1 #define _INTCON2_INTEDG1_LENGTH 0x1 #define _INTCON2_INTEDG1_MASK 0x20 #define _INTCON2_INTEDG0_POSN 0x6 #define _INTCON2_INTEDG0_POSITION 0x6 #define _INTCON2_INTEDG0_SIZE 0x1 #define _INTCON2_INTEDG0_LENGTH 0x1 #define _INTCON2_INTEDG0_MASK 0x40 #define _INTCON2_nRBPU_POSN 0x7 #define _INTCON2_nRBPU_POSITION 0x7 #define _INTCON2_nRBPU_SIZE 0x1 #define _INTCON2_nRBPU_LENGTH 0x1 #define _INTCON2_nRBPU_MASK 0x80 #define _INTCON2_INT3P_POSN 0x1 #define _INTCON2_INT3P_POSITION 0x1 #define _INTCON2_INT3P_SIZE 0x1 #define _INTCON2_INT3P_LENGTH 0x1 #define _INTCON2_INT3P_MASK 0x2 #define _INTCON2_T0IP_POSN 0x2 #define _INTCON2_T0IP_POSITION 0x2 #define _INTCON2_T0IP_SIZE 0x1 #define _INTCON2_T0IP_LENGTH 0x1 #define _INTCON2_T0IP_MASK 0x4 #define _INTCON2_RBPU_POSN 0x7 #define _INTCON2_RBPU_POSITION 0x7 #define _INTCON2_RBPU_SIZE 0x1 #define _INTCON2_RBPU_LENGTH 0x1 #define _INTCON2_RBPU_MASK 0x80 // Register: INTCON #define INTCON INTCON extern volatile unsigned char INTCON @ 0xFF2; #ifndef _LIB_BUILD asm("INTCON equ 0FF2h"); #endif // aliases extern volatile unsigned char INTCON1 @ 0xFF2; #ifndef _LIB_BUILD asm("INTCON1 equ 0FF2h"); #endif // bitfield definitions typedef union { struct { unsigned RBIF :1; unsigned INT0IF :1; unsigned TMR0IF :1; unsigned RBIE :1; unsigned INT0IE :1; unsigned TMR0IE :1; unsigned PEIE_GIEL :1; unsigned GIE_GIEH :1; }; struct { unsigned :1; unsigned INT0F :1; unsigned T0IF :1; unsigned :1; unsigned INT0E :1; unsigned T0IE :1; unsigned PEIE :1; unsigned GIE :1; }; struct { unsigned :6; unsigned GIEL :1; unsigned GIEH :1; }; } INTCONbits_t; extern volatile INTCONbits_t INTCONbits @ 0xFF2; // bitfield macros #define _INTCON_RBIF_POSN 0x0 #define _INTCON_RBIF_POSITION 0x0 #define _INTCON_RBIF_SIZE 0x1 #define _INTCON_RBIF_LENGTH 0x1 #define _INTCON_RBIF_MASK 0x1 #define _INTCON_INT0IF_POSN 0x1 #define _INTCON_INT0IF_POSITION 0x1 #define _INTCON_INT0IF_SIZE 0x1 #define _INTCON_INT0IF_LENGTH 0x1 #define _INTCON_INT0IF_MASK 0x2 #define _INTCON_TMR0IF_POSN 0x2 #define _INTCON_TMR0IF_POSITION 0x2 #define _INTCON_TMR0IF_SIZE 0x1 #define _INTCON_TMR0IF_LENGTH 0x1 #define _INTCON_TMR0IF_MASK 0x4 #define _INTCON_RBIE_POSN 0x3 #define _INTCON_RBIE_POSITION 0x3 #define _INTCON_RBIE_SIZE 0x1 #define _INTCON_RBIE_LENGTH 0x1 #define _INTCON_RBIE_MASK 0x8 #define _INTCON_INT0IE_POSN 0x4 #define _INTCON_INT0IE_POSITION 0x4 #define _INTCON_INT0IE_SIZE 0x1 #define _INTCON_INT0IE_LENGTH 0x1 #define _INTCON_INT0IE_MASK 0x10 #define _INTCON_TMR0IE_POSN 0x5 #define _INTCON_TMR0IE_POSITION 0x5 #define _INTCON_TMR0IE_SIZE 0x1 #define _INTCON_TMR0IE_LENGTH 0x1 #define _INTCON_TMR0IE_MASK 0x20 #define _INTCON_PEIE_GIEL_POSN 0x6 #define _INTCON_PEIE_GIEL_POSITION 0x6 #define _INTCON_PEIE_GIEL_SIZE 0x1 #define _INTCON_PEIE_GIEL_LENGTH 0x1 #define _INTCON_PEIE_GIEL_MASK 0x40 #define _INTCON_GIE_GIEH_POSN 0x7 #define _INTCON_GIE_GIEH_POSITION 0x7 #define _INTCON_GIE_GIEH_SIZE 0x1 #define _INTCON_GIE_GIEH_LENGTH 0x1 #define _INTCON_GIE_GIEH_MASK 0x80 #define _INTCON_INT0F_POSN 0x1 #define _INTCON_INT0F_POSITION 0x1 #define _INTCON_INT0F_SIZE 0x1 #define _INTCON_INT0F_LENGTH 0x1 #define _INTCON_INT0F_MASK 0x2 #define _INTCON_T0IF_POSN 0x2 #define _INTCON_T0IF_POSITION 0x2 #define _INTCON_T0IF_SIZE 0x1 #define _INTCON_T0IF_LENGTH 0x1 #define _INTCON_T0IF_MASK 0x4 #define _INTCON_INT0E_POSN 0x4 #define _INTCON_INT0E_POSITION 0x4 #define _INTCON_INT0E_SIZE 0x1 #define _INTCON_INT0E_LENGTH 0x1 #define _INTCON_INT0E_MASK 0x10 #define _INTCON_T0IE_POSN 0x5 #define _INTCON_T0IE_POSITION 0x5 #define _INTCON_T0IE_SIZE 0x1 #define _INTCON_T0IE_LENGTH 0x1 #define _INTCON_T0IE_MASK 0x20 #define _INTCON_PEIE_POSN 0x6 #define _INTCON_PEIE_POSITION 0x6 #define _INTCON_PEIE_SIZE 0x1 #define _INTCON_PEIE_LENGTH 0x1 #define _INTCON_PEIE_MASK 0x40 #define _INTCON_GIE_POSN 0x7 #define _INTCON_GIE_POSITION 0x7 #define _INTCON_GIE_SIZE 0x1 #define _INTCON_GIE_LENGTH 0x1 #define _INTCON_GIE_MASK 0x80 #define _INTCON_GIEL_POSN 0x6 #define _INTCON_GIEL_POSITION 0x6 #define _INTCON_GIEL_SIZE 0x1 #define _INTCON_GIEL_LENGTH 0x1 #define _INTCON_GIEL_MASK 0x40 #define _INTCON_GIEH_POSN 0x7 #define _INTCON_GIEH_POSITION 0x7 #define _INTCON_GIEH_SIZE 0x1 #define _INTCON_GIEH_LENGTH 0x1 #define _INTCON_GIEH_MASK 0x80 // alias bitfield definitions typedef union { struct { unsigned RBIF :1; unsigned INT0IF :1; unsigned TMR0IF :1; unsigned RBIE :1; unsigned INT0IE :1; unsigned TMR0IE :1; unsigned PEIE_GIEL :1; unsigned GIE_GIEH :1; }; struct { unsigned :1; unsigned INT0F :1; unsigned T0IF :1; unsigned :1; unsigned INT0E :1; unsigned T0IE :1; unsigned PEIE :1; unsigned GIE :1; }; struct { unsigned :6; unsigned GIEL :1; unsigned GIEH :1; }; } INTCON1bits_t; extern volatile INTCON1bits_t INTCON1bits @ 0xFF2; // bitfield macros #define _INTCON1_RBIF_POSN 0x0 #define _INTCON1_RBIF_POSITION 0x0 #define _INTCON1_RBIF_SIZE 0x1 #define _INTCON1_RBIF_LENGTH 0x1 #define _INTCON1_RBIF_MASK 0x1 #define _INTCON1_INT0IF_POSN 0x1 #define _INTCON1_INT0IF_POSITION 0x1 #define _INTCON1_INT0IF_SIZE 0x1 #define _INTCON1_INT0IF_LENGTH 0x1 #define _INTCON1_INT0IF_MASK 0x2 #define _INTCON1_TMR0IF_POSN 0x2 #define _INTCON1_TMR0IF_POSITION 0x2 #define _INTCON1_TMR0IF_SIZE 0x1 #define _INTCON1_TMR0IF_LENGTH 0x1 #define _INTCON1_TMR0IF_MASK 0x4 #define _INTCON1_RBIE_POSN 0x3 #define _INTCON1_RBIE_POSITION 0x3 #define _INTCON1_RBIE_SIZE 0x1 #define _INTCON1_RBIE_LENGTH 0x1 #define _INTCON1_RBIE_MASK 0x8 #define _INTCON1_INT0IE_POSN 0x4 #define _INTCON1_INT0IE_POSITION 0x4 #define _INTCON1_INT0IE_SIZE 0x1 #define _INTCON1_INT0IE_LENGTH 0x1 #define _INTCON1_INT0IE_MASK 0x10 #define _INTCON1_TMR0IE_POSN 0x5 #define _INTCON1_TMR0IE_POSITION 0x5 #define _INTCON1_TMR0IE_SIZE 0x1 #define _INTCON1_TMR0IE_LENGTH 0x1 #define _INTCON1_TMR0IE_MASK 0x20 #define _INTCON1_PEIE_GIEL_POSN 0x6 #define _INTCON1_PEIE_GIEL_POSITION 0x6 #define _INTCON1_PEIE_GIEL_SIZE 0x1 #define _INTCON1_PEIE_GIEL_LENGTH 0x1 #define _INTCON1_PEIE_GIEL_MASK 0x40 #define _INTCON1_GIE_GIEH_POSN 0x7 #define _INTCON1_GIE_GIEH_POSITION 0x7 #define _INTCON1_GIE_GIEH_SIZE 0x1 #define _INTCON1_GIE_GIEH_LENGTH 0x1 #define _INTCON1_GIE_GIEH_MASK 0x80 #define _INTCON1_INT0F_POSN 0x1 #define _INTCON1_INT0F_POSITION 0x1 #define _INTCON1_INT0F_SIZE 0x1 #define _INTCON1_INT0F_LENGTH 0x1 #define _INTCON1_INT0F_MASK 0x2 #define _INTCON1_T0IF_POSN 0x2 #define _INTCON1_T0IF_POSITION 0x2 #define _INTCON1_T0IF_SIZE 0x1 #define _INTCON1_T0IF_LENGTH 0x1 #define _INTCON1_T0IF_MASK 0x4 #define _INTCON1_INT0E_POSN 0x4 #define _INTCON1_INT0E_POSITION 0x4 #define _INTCON1_INT0E_SIZE 0x1 #define _INTCON1_INT0E_LENGTH 0x1 #define _INTCON1_INT0E_MASK 0x10 #define _INTCON1_T0IE_POSN 0x5 #define _INTCON1_T0IE_POSITION 0x5 #define _INTCON1_T0IE_SIZE 0x1 #define _INTCON1_T0IE_LENGTH 0x1 #define _INTCON1_T0IE_MASK 0x20 #define _INTCON1_PEIE_POSN 0x6 #define _INTCON1_PEIE_POSITION 0x6 #define _INTCON1_PEIE_SIZE 0x1 #define _INTCON1_PEIE_LENGTH 0x1 #define _INTCON1_PEIE_MASK 0x40 #define _INTCON1_GIE_POSN 0x7 #define _INTCON1_GIE_POSITION 0x7 #define _INTCON1_GIE_SIZE 0x1 #define _INTCON1_GIE_LENGTH 0x1 #define _INTCON1_GIE_MASK 0x80 #define _INTCON1_GIEL_POSN 0x6 #define _INTCON1_GIEL_POSITION 0x6 #define _INTCON1_GIEL_SIZE 0x1 #define _INTCON1_GIEL_LENGTH 0x1 #define _INTCON1_GIEL_MASK 0x40 #define _INTCON1_GIEH_POSN 0x7 #define _INTCON1_GIEH_POSITION 0x7 #define _INTCON1_GIEH_SIZE 0x1 #define _INTCON1_GIEH_LENGTH 0x1 #define _INTCON1_GIEH_MASK 0x80 // Register: PROD #define PROD PROD extern volatile unsigned short PROD @ 0xFF3; #ifndef _LIB_BUILD asm("PROD equ 0FF3h"); #endif // Register: PRODL #define PRODL PRODL extern volatile unsigned char PRODL @ 0xFF3; #ifndef _LIB_BUILD asm("PRODL equ 0FF3h"); #endif // bitfield definitions typedef union { struct { unsigned PRODL :8; }; } PRODLbits_t; extern volatile PRODLbits_t PRODLbits @ 0xFF3; // bitfield macros #define _PRODL_PRODL_POSN 0x0 #define _PRODL_PRODL_POSITION 0x0 #define _PRODL_PRODL_SIZE 0x8 #define _PRODL_PRODL_LENGTH 0x8 #define _PRODL_PRODL_MASK 0xFF // Register: PRODH #define PRODH PRODH extern volatile unsigned char PRODH @ 0xFF4; #ifndef _LIB_BUILD asm("PRODH equ 0FF4h"); #endif // bitfield definitions typedef union { struct { unsigned PRODH :8; }; } PRODHbits_t; extern volatile PRODHbits_t PRODHbits @ 0xFF4; // bitfield macros #define _PRODH_PRODH_POSN 0x0 #define _PRODH_PRODH_POSITION 0x0 #define _PRODH_PRODH_SIZE 0x8 #define _PRODH_PRODH_LENGTH 0x8 #define _PRODH_PRODH_MASK 0xFF // Register: TABLAT #define TABLAT TABLAT extern volatile unsigned char TABLAT @ 0xFF5; #ifndef _LIB_BUILD asm("TABLAT equ 0FF5h"); #endif // bitfield definitions typedef union { struct { unsigned TABLAT :8; }; } TABLATbits_t; extern volatile TABLATbits_t TABLATbits @ 0xFF5; // bitfield macros #define _TABLAT_TABLAT_POSN 0x0 #define _TABLAT_TABLAT_POSITION 0x0 #define _TABLAT_TABLAT_SIZE 0x8 #define _TABLAT_TABLAT_LENGTH 0x8 #define _TABLAT_TABLAT_MASK 0xFF // Register: TBLPTR #define TBLPTR TBLPTR #ifndef __CCI__ extern volatile unsigned short long TBLPTR @ 0xFF6; #endif #ifndef _LIB_BUILD asm("TBLPTR equ 0FF6h"); #endif // Register: TBLPTRL #define TBLPTRL TBLPTRL extern volatile unsigned char TBLPTRL @ 0xFF6; #ifndef _LIB_BUILD asm("TBLPTRL equ 0FF6h"); #endif // bitfield definitions typedef union { struct { unsigned TBLPTRL :8; }; } TBLPTRLbits_t; extern volatile TBLPTRLbits_t TBLPTRLbits @ 0xFF6; // bitfield macros #define _TBLPTRL_TBLPTRL_POSN 0x0 #define _TBLPTRL_TBLPTRL_POSITION 0x0 #define _TBLPTRL_TBLPTRL_SIZE 0x8 #define _TBLPTRL_TBLPTRL_LENGTH 0x8 #define _TBLPTRL_TBLPTRL_MASK 0xFF // Register: TBLPTRH #define TBLPTRH TBLPTRH extern volatile unsigned char TBLPTRH @ 0xFF7; #ifndef _LIB_BUILD asm("TBLPTRH equ 0FF7h"); #endif // bitfield definitions typedef union { struct { unsigned TBLPTRH :8; }; } TBLPTRHbits_t; extern volatile TBLPTRHbits_t TBLPTRHbits @ 0xFF7; // bitfield macros #define _TBLPTRH_TBLPTRH_POSN 0x0 #define _TBLPTRH_TBLPTRH_POSITION 0x0 #define _TBLPTRH_TBLPTRH_SIZE 0x8 #define _TBLPTRH_TBLPTRH_LENGTH 0x8 #define _TBLPTRH_TBLPTRH_MASK 0xFF // Register: TBLPTRU #define TBLPTRU TBLPTRU extern volatile unsigned char TBLPTRU @ 0xFF8; #ifndef _LIB_BUILD asm("TBLPTRU equ 0FF8h"); #endif // bitfield definitions typedef union { struct { unsigned TBLPTRU :5; }; } TBLPTRUbits_t; extern volatile TBLPTRUbits_t TBLPTRUbits @ 0xFF8; // bitfield macros #define _TBLPTRU_TBLPTRU_POSN 0x0 #define _TBLPTRU_TBLPTRU_POSITION 0x0 #define _TBLPTRU_TBLPTRU_SIZE 0x5 #define _TBLPTRU_TBLPTRU_LENGTH 0x5 #define _TBLPTRU_TBLPTRU_MASK 0x1F // Register: PCLAT #define PCLAT PCLAT #ifndef __CCI__ extern volatile unsigned short long PCLAT @ 0xFF9; #endif #ifndef _LIB_BUILD asm("PCLAT equ 0FF9h"); #endif // aliases #ifndef __CCI__ extern volatile unsigned short long PC @ 0xFF9; #endif #ifndef _LIB_BUILD asm("PC equ 0FF9h"); #endif // Register: PCL #define PCL PCL extern volatile unsigned char PCL @ 0xFF9; #ifndef _LIB_BUILD asm("PCL equ 0FF9h"); #endif // bitfield definitions typedef union { struct { unsigned PCL :8; }; } PCLbits_t; extern volatile PCLbits_t PCLbits @ 0xFF9; // bitfield macros #define _PCL_PCL_POSN 0x0 #define _PCL_PCL_POSITION 0x0 #define _PCL_PCL_SIZE 0x8 #define _PCL_PCL_LENGTH 0x8 #define _PCL_PCL_MASK 0xFF // Register: PCLATH #define PCLATH PCLATH extern volatile unsigned char PCLATH @ 0xFFA; #ifndef _LIB_BUILD asm("PCLATH equ 0FFAh"); #endif // bitfield definitions typedef union { struct { unsigned PCH :8; }; } PCLATHbits_t; extern volatile PCLATHbits_t PCLATHbits @ 0xFFA; // bitfield macros #define _PCLATH_PCH_POSN 0x0 #define _PCLATH_PCH_POSITION 0x0 #define _PCLATH_PCH_SIZE 0x8 #define _PCLATH_PCH_LENGTH 0x8 #define _PCLATH_PCH_MASK 0xFF // Register: PCLATU #define PCLATU PCLATU extern volatile unsigned char PCLATU @ 0xFFB; #ifndef _LIB_BUILD asm("PCLATU equ 0FFBh"); #endif // bitfield definitions typedef union { struct { unsigned PCU :5; }; } PCLATUbits_t; extern volatile PCLATUbits_t PCLATUbits @ 0xFFB; // bitfield macros #define _PCLATU_PCU_POSN 0x0 #define _PCLATU_PCU_POSITION 0x0 #define _PCLATU_PCU_SIZE 0x5 #define _PCLATU_PCU_LENGTH 0x5 #define _PCLATU_PCU_MASK 0x1F // Register: STKPTR #define STKPTR STKPTR extern volatile unsigned char STKPTR @ 0xFFC; #ifndef _LIB_BUILD asm("STKPTR equ 0FFCh"); #endif // bitfield definitions typedef union { struct { unsigned STKPTR :5; unsigned :1; unsigned STKUNF :1; unsigned STKFUL :1; }; struct { unsigned SP0 :1; unsigned SP1 :1; unsigned SP2 :1; unsigned SP3 :1; unsigned SP4 :1; unsigned :2; unsigned STKOVF :1; }; } STKPTRbits_t; extern volatile STKPTRbits_t STKPTRbits @ 0xFFC; // bitfield macros #define _STKPTR_STKPTR_POSN 0x0 #define _STKPTR_STKPTR_POSITION 0x0 #define _STKPTR_STKPTR_SIZE 0x5 #define _STKPTR_STKPTR_LENGTH 0x5 #define _STKPTR_STKPTR_MASK 0x1F #define _STKPTR_STKUNF_POSN 0x6 #define _STKPTR_STKUNF_POSITION 0x6 #define _STKPTR_STKUNF_SIZE 0x1 #define _STKPTR_STKUNF_LENGTH 0x1 #define _STKPTR_STKUNF_MASK 0x40 #define _STKPTR_STKFUL_POSN 0x7 #define _STKPTR_STKFUL_POSITION 0x7 #define _STKPTR_STKFUL_SIZE 0x1 #define _STKPTR_STKFUL_LENGTH 0x1 #define _STKPTR_STKFUL_MASK 0x80 #define _STKPTR_SP0_POSN 0x0 #define _STKPTR_SP0_POSITION 0x0 #define _STKPTR_SP0_SIZE 0x1 #define _STKPTR_SP0_LENGTH 0x1 #define _STKPTR_SP0_MASK 0x1 #define _STKPTR_SP1_POSN 0x1 #define _STKPTR_SP1_POSITION 0x1 #define _STKPTR_SP1_SIZE 0x1 #define _STKPTR_SP1_LENGTH 0x1 #define _STKPTR_SP1_MASK 0x2 #define _STKPTR_SP2_POSN 0x2 #define _STKPTR_SP2_POSITION 0x2 #define _STKPTR_SP2_SIZE 0x1 #define _STKPTR_SP2_LENGTH 0x1 #define _STKPTR_SP2_MASK 0x4 #define _STKPTR_SP3_POSN 0x3 #define _STKPTR_SP3_POSITION 0x3 #define _STKPTR_SP3_SIZE 0x1 #define _STKPTR_SP3_LENGTH 0x1 #define _STKPTR_SP3_MASK 0x8 #define _STKPTR_SP4_POSN 0x4 #define _STKPTR_SP4_POSITION 0x4 #define _STKPTR_SP4_SIZE 0x1 #define _STKPTR_SP4_LENGTH 0x1 #define _STKPTR_SP4_MASK 0x10 #define _STKPTR_STKOVF_POSN 0x7 #define _STKPTR_STKOVF_POSITION 0x7 #define _STKPTR_STKOVF_SIZE 0x1 #define _STKPTR_STKOVF_LENGTH 0x1 #define _STKPTR_STKOVF_MASK 0x80 // Register: TOS #define TOS TOS #ifndef __CCI__ extern volatile unsigned short long TOS @ 0xFFD; #endif #ifndef _LIB_BUILD asm("TOS equ 0FFDh"); #endif // Register: TOSL #define TOSL TOSL extern volatile unsigned char TOSL @ 0xFFD; #ifndef _LIB_BUILD asm("TOSL equ 0FFDh"); #endif // bitfield definitions typedef union { struct { unsigned TOSL :8; }; } TOSLbits_t; extern volatile TOSLbits_t TOSLbits @ 0xFFD; // bitfield macros #define _TOSL_TOSL_POSN 0x0 #define _TOSL_TOSL_POSITION 0x0 #define _TOSL_TOSL_SIZE 0x8 #define _TOSL_TOSL_LENGTH 0x8 #define _TOSL_TOSL_MASK 0xFF // Register: TOSH #define TOSH TOSH extern volatile unsigned char TOSH @ 0xFFE; #ifndef _LIB_BUILD asm("TOSH equ 0FFEh"); #endif // bitfield definitions typedef union { struct { unsigned TOSH :8; }; } TOSHbits_t; extern volatile TOSHbits_t TOSHbits @ 0xFFE; // bitfield macros #define _TOSH_TOSH_POSN 0x0 #define _TOSH_TOSH_POSITION 0x0 #define _TOSH_TOSH_SIZE 0x8 #define _TOSH_TOSH_LENGTH 0x8 #define _TOSH_TOSH_MASK 0xFF // Register: TOSU #define TOSU TOSU extern volatile unsigned char TOSU @ 0xFFF; #ifndef _LIB_BUILD asm("TOSU equ 0FFFh"); #endif // bitfield definitions typedef union { struct { unsigned TOSU :5; }; } TOSUbits_t; extern volatile TOSUbits_t TOSUbits @ 0xFFF; // bitfield macros #define _TOSU_TOSU_POSN 0x0 #define _TOSU_TOSU_POSITION 0x0 #define _TOSU_TOSU_SIZE 0x5 #define _TOSU_TOSU_LENGTH 0x5 #define _TOSU_TOSU_MASK 0x1F /* * Bit Definitions */ #define _DEPRECATED __attribute__((__deprecated__)) #ifndef BANKMASK #define BANKMASK(addr) ((addr)&0FFh) #endif extern volatile __bit ABDEN1 @ (((unsigned) &BAUDCON1)*8) + 0; #define ABDEN1_bit BANKMASK(BAUDCON1), 0 extern volatile __bit ABDEN2 @ (((unsigned) &BAUDCON2)*8) + 0; #define ABDEN2_bit BANKMASK(BAUDCON2), 0 extern volatile __bit ABDOVF1 @ (((unsigned) &BAUDCON1)*8) + 7; #define ABDOVF1_bit BANKMASK(BAUDCON1), 7 extern volatile __bit ABDOVF2 @ (((unsigned) &BAUDCON2)*8) + 7; #define ABDOVF2_bit BANKMASK(BAUDCON2), 7 extern volatile __bit ACKDT @ (((unsigned) &SSPCON2)*8) + 5; #define ACKDT_bit BANKMASK(SSPCON2), 5 extern volatile __bit ACKEN @ (((unsigned) &SSPCON2)*8) + 4; #define ACKEN_bit BANKMASK(SSPCON2), 4 extern volatile __bit ACKSTAT @ (((unsigned) &SSPCON2)*8) + 6; #define ACKSTAT_bit BANKMASK(SSPCON2), 6 extern volatile __bit ACQT0 @ (((unsigned) &ADCON2)*8) + 3; #define ACQT0_bit BANKMASK(ADCON2), 3 extern volatile __bit ACQT1 @ (((unsigned) &ADCON2)*8) + 4; #define ACQT1_bit BANKMASK(ADCON2), 4 extern volatile __bit ACQT2 @ (((unsigned) &ADCON2)*8) + 5; #define ACQT2_bit BANKMASK(ADCON2), 5 extern volatile __bit ADCMD @ (((unsigned) &PMD1)*8) + 5; #define ADCMD_bit BANKMASK(PMD1), 5 extern volatile __bit ADCS0 @ (((unsigned) &ADCON2)*8) + 0; #define ADCS0_bit BANKMASK(ADCON2), 0 extern volatile __bit ADCS1 @ (((unsigned) &ADCON2)*8) + 1; #define ADCS1_bit BANKMASK(ADCON2), 1 extern volatile __bit ADCS2 @ (((unsigned) &ADCON2)*8) + 2; #define ADCS2_bit BANKMASK(ADCON2), 2 extern volatile __bit ADDEN1 @ (((unsigned) &RCSTA1)*8) + 3; #define ADDEN1_bit BANKMASK(RCSTA1), 3 extern volatile __bit ADDEN2 @ (((unsigned) &RCSTA2)*8) + 3; #define ADDEN2_bit BANKMASK(RCSTA2), 3 extern volatile __bit ADEN @ (((unsigned) &RCSTA1)*8) + 3; #define ADEN_bit BANKMASK(RCSTA1), 3 extern volatile __bit ADFM @ (((unsigned) &ADCON2)*8) + 7; #define ADFM_bit BANKMASK(ADCON2), 7 extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6; #define ADIE_bit BANKMASK(PIE1), 6 extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6; #define ADIF_bit BANKMASK(PIR1), 6 extern volatile __bit ADIP @ (((unsigned) &IPR1)*8) + 6; #define ADIP_bit BANKMASK(IPR1), 6 extern volatile __bit ADMSK1 @ (((unsigned) &SSPCON2)*8) + 1; #define ADMSK1_bit BANKMASK(SSPCON2), 1 extern volatile __bit ADMSK2 @ (((unsigned) &SSPCON2)*8) + 2; #define ADMSK2_bit BANKMASK(SSPCON2), 2 extern volatile __bit ADMSK3 @ (((unsigned) &SSPCON2)*8) + 3; #define ADMSK3_bit BANKMASK(SSPCON2), 3 extern volatile __bit ADMSK4 @ (((unsigned) &SSPCON2)*8) + 4; #define ADMSK4_bit BANKMASK(SSPCON2), 4 extern volatile __bit ADMSK5 @ (((unsigned) &SSPCON2)*8) + 5; #define ADMSK5_bit BANKMASK(SSPCON2), 5 extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0; #define ADON_bit BANKMASK(ADCON0), 0 extern volatile __bit ANSEL0 @ (((unsigned) &ANCON0)*8) + 0; #define ANSEL0_bit BANKMASK(ANCON0), 0 extern volatile __bit ANSEL1 @ (((unsigned) &ANCON0)*8) + 1; #define ANSEL1_bit BANKMASK(ANCON0), 1 extern volatile __bit ANSEL10 @ (((unsigned) &ANCON1)*8) + 2; #define ANSEL10_bit BANKMASK(ANCON1), 2 extern volatile __bit ANSEL2 @ (((unsigned) &ANCON0)*8) + 2; #define ANSEL2_bit BANKMASK(ANCON0), 2 extern volatile __bit ANSEL3 @ (((unsigned) &ANCON0)*8) + 3; #define ANSEL3_bit BANKMASK(ANCON0), 3 extern volatile __bit ANSEL4 @ (((unsigned) &ANCON0)*8) + 4; #define ANSEL4_bit BANKMASK(ANCON0), 4 extern volatile __bit ANSEL8 @ (((unsigned) &ANCON1)*8) + 0; #define ANSEL8_bit BANKMASK(ANCON1), 0 extern volatile __bit ANSEL9 @ (((unsigned) &ANCON1)*8) + 1; #define ANSEL9_bit BANKMASK(ANCON1), 1 extern volatile __bit B0D00 @ (((unsigned) &B0D0)*8) + 0; #define B0D00_bit BANKMASK(B0D0), 0 extern volatile __bit B0D01 @ (((unsigned) &B0D0)*8) + 1; #define B0D01_bit BANKMASK(B0D0), 1 extern volatile __bit B0D02 @ (((unsigned) &B0D0)*8) + 2; #define B0D02_bit BANKMASK(B0D0), 2 extern volatile __bit B0D03 @ (((unsigned) &B0D0)*8) + 3; #define B0D03_bit BANKMASK(B0D0), 3 extern volatile __bit B0D04 @ (((unsigned) &B0D0)*8) + 4; #define B0D04_bit BANKMASK(B0D0), 4 extern volatile __bit B0D05 @ (((unsigned) &B0D0)*8) + 5; #define B0D05_bit BANKMASK(B0D0), 5 extern volatile __bit B0D06 @ (((unsigned) &B0D0)*8) + 6; #define B0D06_bit BANKMASK(B0D0), 6 extern volatile __bit B0D07 @ (((unsigned) &B0D0)*8) + 7; #define B0D07_bit BANKMASK(B0D0), 7 extern volatile __bit B0D10 @ (((unsigned) &B0D1)*8) + 0; #define B0D10_bit BANKMASK(B0D1), 0 extern volatile __bit B0D11 @ (((unsigned) &B0D1)*8) + 1; #define B0D11_bit BANKMASK(B0D1), 1 extern volatile __bit B0D12 @ (((unsigned) &B0D1)*8) + 2; #define B0D12_bit BANKMASK(B0D1), 2 extern volatile __bit B0D13 @ (((unsigned) &B0D1)*8) + 3; #define B0D13_bit BANKMASK(B0D1), 3 extern volatile __bit B0D14 @ (((unsigned) &B0D1)*8) + 4; #define B0D14_bit BANKMASK(B0D1), 4 extern volatile __bit B0D15 @ (((unsigned) &B0D1)*8) + 5; #define B0D15_bit BANKMASK(B0D1), 5 extern volatile __bit B0D16 @ (((unsigned) &B0D1)*8) + 6; #define B0D16_bit BANKMASK(B0D1), 6 extern volatile __bit B0D17 @ (((unsigned) &B0D1)*8) + 7; #define B0D17_bit BANKMASK(B0D1), 7 extern volatile __bit B0D20 @ (((unsigned) &B0D2)*8) + 0; #define B0D20_bit BANKMASK(B0D2), 0 extern volatile __bit B0D21 @ (((unsigned) &B0D2)*8) + 1; #define B0D21_bit BANKMASK(B0D2), 1 extern volatile __bit B0D22 @ (((unsigned) &B0D2)*8) + 2; #define B0D22_bit BANKMASK(B0D2), 2 extern volatile __bit B0D23 @ (((unsigned) &B0D2)*8) + 3; #define B0D23_bit BANKMASK(B0D2), 3 extern volatile __bit B0D24 @ (((unsigned) &B0D2)*8) + 4; #define B0D24_bit BANKMASK(B0D2), 4 extern volatile __bit B0D25 @ (((unsigned) &B0D2)*8) + 5; #define B0D25_bit BANKMASK(B0D2), 5 extern volatile __bit B0D26 @ (((unsigned) &B0D2)*8) + 6; #define B0D26_bit BANKMASK(B0D2), 6 extern volatile __bit B0D27 @ (((unsigned) &B0D2)*8) + 7; #define B0D27_bit BANKMASK(B0D2), 7 extern volatile __bit B0D30 @ (((unsigned) &B0D3)*8) + 0; #define B0D30_bit BANKMASK(B0D3), 0 extern volatile __bit B0D31 @ (((unsigned) &B0D3)*8) + 1; #define B0D31_bit BANKMASK(B0D3), 1 extern volatile __bit B0D32 @ (((unsigned) &B0D3)*8) + 2; #define B0D32_bit BANKMASK(B0D3), 2 extern volatile __bit B0D33 @ (((unsigned) &B0D3)*8) + 3; #define B0D33_bit BANKMASK(B0D3), 3 extern volatile __bit B0D34 @ (((unsigned) &B0D3)*8) + 4; #define B0D34_bit BANKMASK(B0D3), 4 extern volatile __bit B0D35 @ (((unsigned) &B0D3)*8) + 5; #define B0D35_bit BANKMASK(B0D3), 5 extern volatile __bit B0D36 @ (((unsigned) &B0D3)*8) + 6; #define B0D36_bit BANKMASK(B0D3), 6 extern volatile __bit B0D37 @ (((unsigned) &B0D3)*8) + 7; #define B0D37_bit BANKMASK(B0D3), 7 extern volatile __bit B0D40 @ (((unsigned) &B0D4)*8) + 0; #define B0D40_bit BANKMASK(B0D4), 0 extern volatile __bit B0D41 @ (((unsigned) &B0D4)*8) + 1; #define B0D41_bit BANKMASK(B0D4), 1 extern volatile __bit B0D42 @ (((unsigned) &B0D4)*8) + 2; #define B0D42_bit BANKMASK(B0D4), 2 extern volatile __bit B0D43 @ (((unsigned) &B0D4)*8) + 3; #define B0D43_bit BANKMASK(B0D4), 3 extern volatile __bit B0D44 @ (((unsigned) &B0D4)*8) + 4; #define B0D44_bit BANKMASK(B0D4), 4 extern volatile __bit B0D45 @ (((unsigned) &B0D4)*8) + 5; #define B0D45_bit BANKMASK(B0D4), 5 extern volatile __bit B0D46 @ (((unsigned) &B0D4)*8) + 6; #define B0D46_bit BANKMASK(B0D4), 6 extern volatile __bit B0D47 @ (((unsigned) &B0D4)*8) + 7; #define B0D47_bit BANKMASK(B0D4), 7 extern volatile __bit B0D50 @ (((unsigned) &B0D5)*8) + 0; #define B0D50_bit BANKMASK(B0D5), 0 extern volatile __bit B0D51 @ (((unsigned) &B0D5)*8) + 1; #define B0D51_bit BANKMASK(B0D5), 1 extern volatile __bit B0D52 @ (((unsigned) &B0D5)*8) + 2; #define B0D52_bit BANKMASK(B0D5), 2 extern volatile __bit B0D53 @ (((unsigned) &B0D5)*8) + 3; #define B0D53_bit BANKMASK(B0D5), 3 extern volatile __bit B0D54 @ (((unsigned) &B0D5)*8) + 4; #define B0D54_bit BANKMASK(B0D5), 4 extern volatile __bit B0D55 @ (((unsigned) &B0D5)*8) + 5; #define B0D55_bit BANKMASK(B0D5), 5 extern volatile __bit B0D56 @ (((unsigned) &B0D5)*8) + 6; #define B0D56_bit BANKMASK(B0D5), 6 extern volatile __bit B0D57 @ (((unsigned) &B0D5)*8) + 7; #define B0D57_bit BANKMASK(B0D5), 7 extern volatile __bit B0D60 @ (((unsigned) &B0D6)*8) + 0; #define B0D60_bit BANKMASK(B0D6), 0 extern volatile __bit B0D61 @ (((unsigned) &B0D6)*8) + 1; #define B0D61_bit BANKMASK(B0D6), 1 extern volatile __bit B0D62 @ (((unsigned) &B0D6)*8) + 2; #define B0D62_bit BANKMASK(B0D6), 2 extern volatile __bit B0D63 @ (((unsigned) &B0D6)*8) + 3; #define B0D63_bit BANKMASK(B0D6), 3 extern volatile __bit B0D64 @ (((unsigned) &B0D6)*8) + 4; #define B0D64_bit BANKMASK(B0D6), 4 extern volatile __bit B0D65 @ (((unsigned) &B0D6)*8) + 5; #define B0D65_bit BANKMASK(B0D6), 5 extern volatile __bit B0D66 @ (((unsigned) &B0D6)*8) + 6; #define B0D66_bit BANKMASK(B0D6), 6 extern volatile __bit B0D67 @ (((unsigned) &B0D6)*8) + 7; #define B0D67_bit BANKMASK(B0D6), 7 extern volatile __bit B0D70 @ (((unsigned) &B0D7)*8) + 0; #define B0D70_bit BANKMASK(B0D7), 0 extern volatile __bit B0D71 @ (((unsigned) &B0D7)*8) + 1; #define B0D71_bit BANKMASK(B0D7), 1 extern volatile __bit B0D72 @ (((unsigned) &B0D7)*8) + 2; #define B0D72_bit BANKMASK(B0D7), 2 extern volatile __bit B0D73 @ (((unsigned) &B0D7)*8) + 3; #define B0D73_bit BANKMASK(B0D7), 3 extern volatile __bit B0D74 @ (((unsigned) &B0D7)*8) + 4; #define B0D74_bit BANKMASK(B0D7), 4 extern volatile __bit B0D75 @ (((unsigned) &B0D7)*8) + 5; #define B0D75_bit BANKMASK(B0D7), 5 extern volatile __bit B0D76 @ (((unsigned) &B0D7)*8) + 6; #define B0D76_bit BANKMASK(B0D7), 6 extern volatile __bit B0D77 @ (((unsigned) &B0D7)*8) + 7; #define B0D77_bit BANKMASK(B0D7), 7 extern volatile __bit B0DLC0 @ (((unsigned) &B0DLC)*8) + 0; #define B0DLC0_bit BANKMASK(B0DLC), 0 extern volatile __bit B0DLC1 @ (((unsigned) &B0DLC)*8) + 1; #define B0DLC1_bit BANKMASK(B0DLC), 1 extern volatile __bit B0DLC2 @ (((unsigned) &B0DLC)*8) + 2; #define B0DLC2_bit BANKMASK(B0DLC), 2 extern volatile __bit B0DLC3 @ (((unsigned) &B0DLC)*8) + 3; #define B0DLC3_bit BANKMASK(B0DLC), 3 extern volatile __bit B0EID0 @ (((unsigned) &B0EIDL)*8) + 0; #define B0EID0_bit BANKMASK(B0EIDL), 0 extern volatile __bit B0EID1 @ (((unsigned) &B0EIDL)*8) + 1; #define B0EID1_bit BANKMASK(B0EIDL), 1 extern volatile __bit B0EID10 @ (((unsigned) &B0EIDH)*8) + 2; #define B0EID10_bit BANKMASK(B0EIDH), 2 extern volatile __bit B0EID11 @ (((unsigned) &B0EIDH)*8) + 3; #define B0EID11_bit BANKMASK(B0EIDH), 3 extern volatile __bit B0EID12 @ (((unsigned) &B0EIDH)*8) + 4; #define B0EID12_bit BANKMASK(B0EIDH), 4 extern volatile __bit B0EID13 @ (((unsigned) &B0EIDH)*8) + 5; #define B0EID13_bit BANKMASK(B0EIDH), 5 extern volatile __bit B0EID14 @ (((unsigned) &B0EIDH)*8) + 6; #define B0EID14_bit BANKMASK(B0EIDH), 6 extern volatile __bit B0EID15 @ (((unsigned) &B0EIDH)*8) + 7; #define B0EID15_bit BANKMASK(B0EIDH), 7 extern volatile __bit B0EID16 @ (((unsigned) &B0SIDL)*8) + 0; #define B0EID16_bit BANKMASK(B0SIDL), 0 extern volatile __bit B0EID17 @ (((unsigned) &B0SIDL)*8) + 1; #define B0EID17_bit BANKMASK(B0SIDL), 1 extern volatile __bit B0EID2 @ (((unsigned) &B0EIDL)*8) + 2; #define B0EID2_bit BANKMASK(B0EIDL), 2 extern volatile __bit B0EID3 @ (((unsigned) &B0EIDL)*8) + 3; #define B0EID3_bit BANKMASK(B0EIDL), 3 extern volatile __bit B0EID4 @ (((unsigned) &B0EIDL)*8) + 4; #define B0EID4_bit BANKMASK(B0EIDL), 4 extern volatile __bit B0EID5 @ (((unsigned) &B0EIDL)*8) + 5; #define B0EID5_bit BANKMASK(B0EIDL), 5 extern volatile __bit B0EID6 @ (((unsigned) &B0EIDL)*8) + 6; #define B0EID6_bit BANKMASK(B0EIDL), 6 extern volatile __bit B0EID7 @ (((unsigned) &B0EIDL)*8) + 7; #define B0EID7_bit BANKMASK(B0EIDL), 7 extern volatile __bit B0EID8 @ (((unsigned) &B0EIDH)*8) + 0; #define B0EID8_bit BANKMASK(B0EIDH), 0 extern volatile __bit B0EID9 @ (((unsigned) &B0EIDH)*8) + 1; #define B0EID9_bit BANKMASK(B0EIDH), 1 extern volatile __bit B0EXID @ (((unsigned) &B0SIDL)*8) + 3; #define B0EXID_bit BANKMASK(B0SIDL), 3 extern volatile __bit B0FILHIT0 @ (((unsigned) &B0CON)*8) + 0; #define B0FILHIT0_bit BANKMASK(B0CON), 0 extern volatile __bit B0FILHIT1 @ (((unsigned) &B0CON)*8) + 1; #define B0FILHIT1_bit BANKMASK(B0CON), 1 extern volatile __bit B0FILHIT2 @ (((unsigned) &B0CON)*8) + 2; #define B0FILHIT2_bit BANKMASK(B0CON), 2 extern volatile __bit B0FILHIT3 @ (((unsigned) &B0CON)*8) + 3; #define B0FILHIT3_bit BANKMASK(B0CON), 3 extern volatile __bit B0FILHIT4 @ (((unsigned) &B0CON)*8) + 4; #define B0FILHIT4_bit BANKMASK(B0CON), 4 extern volatile __bit B0IE @ (((unsigned) &BIE0)*8) + 2; #define B0IE_bit BANKMASK(BIE0), 2 extern volatile __bit B0RB0 @ (((unsigned) &B0DLC)*8) + 4; #define B0RB0_bit BANKMASK(B0DLC), 4 extern volatile __bit B0RB1 @ (((unsigned) &B0DLC)*8) + 5; #define B0RB1_bit BANKMASK(B0DLC), 5 extern volatile __bit B0RTREN @ (((unsigned) &B0CON)*8) + 2; #define B0RTREN_bit BANKMASK(B0CON), 2 extern volatile __bit B0RTRRO @ (((unsigned) &B0CON)*8) + 5; #define B0RTRRO_bit BANKMASK(B0CON), 5 extern volatile __bit B0RXFUL @ (((unsigned) &B0CON)*8) + 7; #define B0RXFUL_bit BANKMASK(B0CON), 7 extern volatile __bit B0RXM1 @ (((unsigned) &B0CON)*8) + 6; #define B0RXM1_bit BANKMASK(B0CON), 6 extern volatile __bit B0RXRTR @ (((unsigned) &B0DLC)*8) + 6; #define B0RXRTR_bit BANKMASK(B0DLC), 6 extern volatile __bit B0SID0 @ (((unsigned) &B0SIDL)*8) + 5; #define B0SID0_bit BANKMASK(B0SIDL), 5 extern volatile __bit B0SID1 @ (((unsigned) &B0SIDL)*8) + 6; #define B0SID1_bit BANKMASK(B0SIDL), 6 extern volatile __bit B0SID10 @ (((unsigned) &B0SIDH)*8) + 7; #define B0SID10_bit BANKMASK(B0SIDH), 7 extern volatile __bit B0SID2 @ (((unsigned) &B0SIDL)*8) + 7; #define B0SID2_bit BANKMASK(B0SIDL), 7 extern volatile __bit B0SID3 @ (((unsigned) &B0SIDH)*8) + 0; #define B0SID3_bit BANKMASK(B0SIDH), 0 extern volatile __bit B0SID4 @ (((unsigned) &B0SIDH)*8) + 1; #define B0SID4_bit BANKMASK(B0SIDH), 1 extern volatile __bit B0SID5 @ (((unsigned) &B0SIDH)*8) + 2; #define B0SID5_bit BANKMASK(B0SIDH), 2 extern volatile __bit B0SID6 @ (((unsigned) &B0SIDH)*8) + 3; #define B0SID6_bit BANKMASK(B0SIDH), 3 extern volatile __bit B0SID7 @ (((unsigned) &B0SIDH)*8) + 4; #define B0SID7_bit BANKMASK(B0SIDH), 4 extern volatile __bit B0SID8 @ (((unsigned) &B0SIDH)*8) + 5; #define B0SID8_bit BANKMASK(B0SIDH), 5 extern volatile __bit B0SID9 @ (((unsigned) &B0SIDH)*8) + 6; #define B0SID9_bit BANKMASK(B0SIDH), 6 extern volatile __bit B0SRR @ (((unsigned) &B0SIDL)*8) + 4; #define B0SRR_bit BANKMASK(B0SIDL), 4 extern volatile __bit B0TXABT @ (((unsigned) &B0CON)*8) + 6; #define B0TXABT_bit BANKMASK(B0CON), 6 extern volatile __bit B0TXB3IF @ (((unsigned) &B0CON)*8) + 7; #define B0TXB3IF_bit BANKMASK(B0CON), 7 extern volatile __bit B0TXEN @ (((unsigned) &BSEL0)*8) + 2; #define B0TXEN_bit BANKMASK(BSEL0), 2 extern volatile __bit B0TXERR @ (((unsigned) &B0CON)*8) + 4; #define B0TXERR_bit BANKMASK(B0CON), 4 extern volatile __bit B0TXLARB @ (((unsigned) &B0CON)*8) + 5; #define B0TXLARB_bit BANKMASK(B0CON), 5 extern volatile __bit B0TXPRI0 @ (((unsigned) &B0CON)*8) + 0; #define B0TXPRI0_bit BANKMASK(B0CON), 0 extern volatile __bit B0TXPRI1 @ (((unsigned) &B0CON)*8) + 1; #define B0TXPRI1_bit BANKMASK(B0CON), 1 extern volatile __bit B0TXREQ @ (((unsigned) &B0CON)*8) + 3; #define B0TXREQ_bit BANKMASK(B0CON), 3 extern volatile __bit B1D00 @ (((unsigned) &B1D0)*8) + 0; #define B1D00_bit BANKMASK(B1D0), 0 extern volatile __bit B1D01 @ (((unsigned) &B1D0)*8) + 1; #define B1D01_bit BANKMASK(B1D0), 1 extern volatile __bit B1D02 @ (((unsigned) &B1D0)*8) + 2; #define B1D02_bit BANKMASK(B1D0), 2 extern volatile __bit B1D03 @ (((unsigned) &B1D0)*8) + 3; #define B1D03_bit BANKMASK(B1D0), 3 extern volatile __bit B1D04 @ (((unsigned) &B1D0)*8) + 4; #define B1D04_bit BANKMASK(B1D0), 4 extern volatile __bit B1D05 @ (((unsigned) &B1D0)*8) + 5; #define B1D05_bit BANKMASK(B1D0), 5 extern volatile __bit B1D06 @ (((unsigned) &B1D0)*8) + 6; #define B1D06_bit BANKMASK(B1D0), 6 extern volatile __bit B1D07 @ (((unsigned) &B1D0)*8) + 7; #define B1D07_bit BANKMASK(B1D0), 7 extern volatile __bit B1D10 @ (((unsigned) &B1D1)*8) + 0; #define B1D10_bit BANKMASK(B1D1), 0 extern volatile __bit B1D11 @ (((unsigned) &B1D1)*8) + 1; #define B1D11_bit BANKMASK(B1D1), 1 extern volatile __bit B1D12 @ (((unsigned) &B1D1)*8) + 2; #define B1D12_bit BANKMASK(B1D1), 2 extern volatile __bit B1D13 @ (((unsigned) &B1D1)*8) + 3; #define B1D13_bit BANKMASK(B1D1), 3 extern volatile __bit B1D14 @ (((unsigned) &B1D1)*8) + 4; #define B1D14_bit BANKMASK(B1D1), 4 extern volatile __bit B1D15 @ (((unsigned) &B1D1)*8) + 5; #define B1D15_bit BANKMASK(B1D1), 5 extern volatile __bit B1D16 @ (((unsigned) &B1D1)*8) + 6; #define B1D16_bit BANKMASK(B1D1), 6 extern volatile __bit B1D17 @ (((unsigned) &B1D1)*8) + 7; #define B1D17_bit BANKMASK(B1D1), 7 extern volatile __bit B1D20 @ (((unsigned) &B1D2)*8) + 0; #define B1D20_bit BANKMASK(B1D2), 0 extern volatile __bit B1D21 @ (((unsigned) &B1D2)*8) + 1; #define B1D21_bit BANKMASK(B1D2), 1 extern volatile __bit B1D22 @ (((unsigned) &B1D2)*8) + 2; #define B1D22_bit BANKMASK(B1D2), 2 extern volatile __bit B1D23 @ (((unsigned) &B1D2)*8) + 3; #define B1D23_bit BANKMASK(B1D2), 3 extern volatile __bit B1D24 @ (((unsigned) &B1D2)*8) + 4; #define B1D24_bit BANKMASK(B1D2), 4 extern volatile __bit B1D25 @ (((unsigned) &B1D2)*8) + 5; #define B1D25_bit BANKMASK(B1D2), 5 extern volatile __bit B1D26 @ (((unsigned) &B1D2)*8) + 6; #define B1D26_bit BANKMASK(B1D2), 6 extern volatile __bit B1D27 @ (((unsigned) &B1D2)*8) + 7; #define B1D27_bit BANKMASK(B1D2), 7 extern volatile __bit B1D30 @ (((unsigned) &B1D3)*8) + 0; #define B1D30_bit BANKMASK(B1D3), 0 extern volatile __bit B1D31 @ (((unsigned) &B1D3)*8) + 1; #define B1D31_bit BANKMASK(B1D3), 1 extern volatile __bit B1D32 @ (((unsigned) &B1D3)*8) + 2; #define B1D32_bit BANKMASK(B1D3), 2 extern volatile __bit B1D33 @ (((unsigned) &B1D3)*8) + 3; #define B1D33_bit BANKMASK(B1D3), 3 extern volatile __bit B1D34 @ (((unsigned) &B1D3)*8) + 4; #define B1D34_bit BANKMASK(B1D3), 4 extern volatile __bit B1D35 @ (((unsigned) &B1D3)*8) + 5; #define B1D35_bit BANKMASK(B1D3), 5 extern volatile __bit B1D36 @ (((unsigned) &B1D3)*8) + 6; #define B1D36_bit BANKMASK(B1D3), 6 extern volatile __bit B1D37 @ (((unsigned) &B1D3)*8) + 7; #define B1D37_bit BANKMASK(B1D3), 7 extern volatile __bit B1D40 @ (((unsigned) &B1D4)*8) + 0; #define B1D40_bit BANKMASK(B1D4), 0 extern volatile __bit B1D41 @ (((unsigned) &B1D4)*8) + 1; #define B1D41_bit BANKMASK(B1D4), 1 extern volatile __bit B1D42 @ (((unsigned) &B1D4)*8) + 2; #define B1D42_bit BANKMASK(B1D4), 2 extern volatile __bit B1D43 @ (((unsigned) &B1D4)*8) + 3; #define B1D43_bit BANKMASK(B1D4), 3 extern volatile __bit B1D44 @ (((unsigned) &B1D4)*8) + 4; #define B1D44_bit BANKMASK(B1D4), 4 extern volatile __bit B1D45 @ (((unsigned) &B1D4)*8) + 5; #define B1D45_bit BANKMASK(B1D4), 5 extern volatile __bit B1D46 @ (((unsigned) &B1D4)*8) + 6; #define B1D46_bit BANKMASK(B1D4), 6 extern volatile __bit B1D47 @ (((unsigned) &B1D4)*8) + 7; #define B1D47_bit BANKMASK(B1D4), 7 extern volatile __bit B1D50 @ (((unsigned) &B1D5)*8) + 0; #define B1D50_bit BANKMASK(B1D5), 0 extern volatile __bit B1D51 @ (((unsigned) &B1D5)*8) + 1; #define B1D51_bit BANKMASK(B1D5), 1 extern volatile __bit B1D52 @ (((unsigned) &B1D5)*8) + 2; #define B1D52_bit BANKMASK(B1D5), 2 extern volatile __bit B1D53 @ (((unsigned) &B1D5)*8) + 3; #define B1D53_bit BANKMASK(B1D5), 3 extern volatile __bit B1D54 @ (((unsigned) &B1D5)*8) + 4; #define B1D54_bit BANKMASK(B1D5), 4 extern volatile __bit B1D55 @ (((unsigned) &B1D5)*8) + 5; #define B1D55_bit BANKMASK(B1D5), 5 extern volatile __bit B1D56 @ (((unsigned) &B1D5)*8) + 6; #define B1D56_bit BANKMASK(B1D5), 6 extern volatile __bit B1D57 @ (((unsigned) &B1D5)*8) + 7; #define B1D57_bit BANKMASK(B1D5), 7 extern volatile __bit B1D60 @ (((unsigned) &B1D6)*8) + 0; #define B1D60_bit BANKMASK(B1D6), 0 extern volatile __bit B1D61 @ (((unsigned) &B1D6)*8) + 1; #define B1D61_bit BANKMASK(B1D6), 1 extern volatile __bit B1D62 @ (((unsigned) &B1D6)*8) + 2; #define B1D62_bit BANKMASK(B1D6), 2 extern volatile __bit B1D63 @ (((unsigned) &B1D6)*8) + 3; #define B1D63_bit BANKMASK(B1D6), 3 extern volatile __bit B1D64 @ (((unsigned) &B1D6)*8) + 4; #define B1D64_bit BANKMASK(B1D6), 4 extern volatile __bit B1D65 @ (((unsigned) &B1D6)*8) + 5; #define B1D65_bit BANKMASK(B1D6), 5 extern volatile __bit B1D66 @ (((unsigned) &B1D6)*8) + 6; #define B1D66_bit BANKMASK(B1D6), 6 extern volatile __bit B1D67 @ (((unsigned) &B1D6)*8) + 7; #define B1D67_bit BANKMASK(B1D6), 7 extern volatile __bit B1D70 @ (((unsigned) &B1D7)*8) + 0; #define B1D70_bit BANKMASK(B1D7), 0 extern volatile __bit B1D71 @ (((unsigned) &B1D7)*8) + 1; #define B1D71_bit BANKMASK(B1D7), 1 extern volatile __bit B1D72 @ (((unsigned) &B1D7)*8) + 2; #define B1D72_bit BANKMASK(B1D7), 2 extern volatile __bit B1D73 @ (((unsigned) &B1D7)*8) + 3; #define B1D73_bit BANKMASK(B1D7), 3 extern volatile __bit B1D74 @ (((unsigned) &B1D7)*8) + 4; #define B1D74_bit BANKMASK(B1D7), 4 extern volatile __bit B1D75 @ (((unsigned) &B1D7)*8) + 5; #define B1D75_bit BANKMASK(B1D7), 5 extern volatile __bit B1D76 @ (((unsigned) &B1D7)*8) + 6; #define B1D76_bit BANKMASK(B1D7), 6 extern volatile __bit B1D77 @ (((unsigned) &B1D7)*8) + 7; #define B1D77_bit BANKMASK(B1D7), 7 extern volatile __bit B1DLC0 @ (((unsigned) &B1DLC)*8) + 0; #define B1DLC0_bit BANKMASK(B1DLC), 0 extern volatile __bit B1DLC1 @ (((unsigned) &B1DLC)*8) + 1; #define B1DLC1_bit BANKMASK(B1DLC), 1 extern volatile __bit B1DLC2 @ (((unsigned) &B1DLC)*8) + 2; #define B1DLC2_bit BANKMASK(B1DLC), 2 extern volatile __bit B1DLC3 @ (((unsigned) &B1DLC)*8) + 3; #define B1DLC3_bit BANKMASK(B1DLC), 3 extern volatile __bit B1EID0 @ (((unsigned) &B1EIDL)*8) + 0; #define B1EID0_bit BANKMASK(B1EIDL), 0 extern volatile __bit B1EID1 @ (((unsigned) &B1EIDL)*8) + 1; #define B1EID1_bit BANKMASK(B1EIDL), 1 extern volatile __bit B1EID10 @ (((unsigned) &B1EIDH)*8) + 2; #define B1EID10_bit BANKMASK(B1EIDH), 2 extern volatile __bit B1EID11 @ (((unsigned) &B1EIDH)*8) + 3; #define B1EID11_bit BANKMASK(B1EIDH), 3 extern volatile __bit B1EID12 @ (((unsigned) &B1EIDH)*8) + 4; #define B1EID12_bit BANKMASK(B1EIDH), 4 extern volatile __bit B1EID13 @ (((unsigned) &B1EIDH)*8) + 5; #define B1EID13_bit BANKMASK(B1EIDH), 5 extern volatile __bit B1EID14 @ (((unsigned) &B1EIDH)*8) + 6; #define B1EID14_bit BANKMASK(B1EIDH), 6 extern volatile __bit B1EID15 @ (((unsigned) &B1EIDH)*8) + 7; #define B1EID15_bit BANKMASK(B1EIDH), 7 extern volatile __bit B1EID16 @ (((unsigned) &B1SIDL)*8) + 0; #define B1EID16_bit BANKMASK(B1SIDL), 0 extern volatile __bit B1EID17 @ (((unsigned) &B1SIDL)*8) + 1; #define B1EID17_bit BANKMASK(B1SIDL), 1 extern volatile __bit B1EID2 @ (((unsigned) &B1EIDL)*8) + 2; #define B1EID2_bit BANKMASK(B1EIDL), 2 extern volatile __bit B1EID3 @ (((unsigned) &B1EIDL)*8) + 3; #define B1EID3_bit BANKMASK(B1EIDL), 3 extern volatile __bit B1EID4 @ (((unsigned) &B1EIDL)*8) + 4; #define B1EID4_bit BANKMASK(B1EIDL), 4 extern volatile __bit B1EID5 @ (((unsigned) &B1EIDL)*8) + 5; #define B1EID5_bit BANKMASK(B1EIDL), 5 extern volatile __bit B1EID6 @ (((unsigned) &B1EIDL)*8) + 6; #define B1EID6_bit BANKMASK(B1EIDL), 6 extern volatile __bit B1EID7 @ (((unsigned) &B1EIDL)*8) + 7; #define B1EID7_bit BANKMASK(B1EIDL), 7 extern volatile __bit B1EID8 @ (((unsigned) &B1EIDH)*8) + 0; #define B1EID8_bit BANKMASK(B1EIDH), 0 extern volatile __bit B1EID9 @ (((unsigned) &B1EIDH)*8) + 1; #define B1EID9_bit BANKMASK(B1EIDH), 1 extern volatile __bit B1EXID @ (((unsigned) &B1SIDL)*8) + 3; #define B1EXID_bit BANKMASK(B1SIDL), 3 extern volatile __bit B1FILHIT0 @ (((unsigned) &B1CON)*8) + 0; #define B1FILHIT0_bit BANKMASK(B1CON), 0 extern volatile __bit B1FILHIT1 @ (((unsigned) &B1CON)*8) + 1; #define B1FILHIT1_bit BANKMASK(B1CON), 1 extern volatile __bit B1FILHIT2 @ (((unsigned) &B1CON)*8) + 2; #define B1FILHIT2_bit BANKMASK(B1CON), 2 extern volatile __bit B1FILHIT3 @ (((unsigned) &B1CON)*8) + 3; #define B1FILHIT3_bit BANKMASK(B1CON), 3 extern volatile __bit B1FILHIT4 @ (((unsigned) &B1CON)*8) + 4; #define B1FILHIT4_bit BANKMASK(B1CON), 4 extern volatile __bit B1IE @ (((unsigned) &BIE0)*8) + 3; #define B1IE_bit BANKMASK(BIE0), 3 extern volatile __bit B1RB0 @ (((unsigned) &B1DLC)*8) + 4; #define B1RB0_bit BANKMASK(B1DLC), 4 extern volatile __bit B1RB1 @ (((unsigned) &B1DLC)*8) + 5; #define B1RB1_bit BANKMASK(B1DLC), 5 extern volatile __bit B1RTREN @ (((unsigned) &B1CON)*8) + 2; #define B1RTREN_bit BANKMASK(B1CON), 2 extern volatile __bit B1RTRRO @ (((unsigned) &B1CON)*8) + 5; #define B1RTRRO_bit BANKMASK(B1CON), 5 extern volatile __bit B1RXFUL @ (((unsigned) &B1CON)*8) + 7; #define B1RXFUL_bit BANKMASK(B1CON), 7 extern volatile __bit B1RXM1 @ (((unsigned) &B1CON)*8) + 6; #define B1RXM1_bit BANKMASK(B1CON), 6 extern volatile __bit B1RXRTR @ (((unsigned) &B1DLC)*8) + 6; #define B1RXRTR_bit BANKMASK(B1DLC), 6 extern volatile __bit B1SID0 @ (((unsigned) &B1SIDL)*8) + 5; #define B1SID0_bit BANKMASK(B1SIDL), 5 extern volatile __bit B1SID1 @ (((unsigned) &B1SIDL)*8) + 6; #define B1SID1_bit BANKMASK(B1SIDL), 6 extern volatile __bit B1SID10 @ (((unsigned) &B1SIDH)*8) + 7; #define B1SID10_bit BANKMASK(B1SIDH), 7 extern volatile __bit B1SID2 @ (((unsigned) &B1SIDL)*8) + 7; #define B1SID2_bit BANKMASK(B1SIDL), 7 extern volatile __bit B1SID3 @ (((unsigned) &B1SIDH)*8) + 0; #define B1SID3_bit BANKMASK(B1SIDH), 0 extern volatile __bit B1SID4 @ (((unsigned) &B1SIDH)*8) + 1; #define B1SID4_bit BANKMASK(B1SIDH), 1 extern volatile __bit B1SID5 @ (((unsigned) &B1SIDH)*8) + 2; #define B1SID5_bit BANKMASK(B1SIDH), 2 extern volatile __bit B1SID6 @ (((unsigned) &B1SIDH)*8) + 3; #define B1SID6_bit BANKMASK(B1SIDH), 3 extern volatile __bit B1SID7 @ (((unsigned) &B1SIDH)*8) + 4; #define B1SID7_bit BANKMASK(B1SIDH), 4 extern volatile __bit B1SID8 @ (((unsigned) &B1SIDH)*8) + 5; #define B1SID8_bit BANKMASK(B1SIDH), 5 extern volatile __bit B1SID9 @ (((unsigned) &B1SIDH)*8) + 6; #define B1SID9_bit BANKMASK(B1SIDH), 6 extern volatile __bit B1SRR @ (((unsigned) &B1SIDL)*8) + 4; #define B1SRR_bit BANKMASK(B1SIDL), 4 extern volatile __bit B1TXABT @ (((unsigned) &B1CON)*8) + 6; #define B1TXABT_bit BANKMASK(B1CON), 6 extern volatile __bit B1TXB3IF @ (((unsigned) &B1CON)*8) + 7; #define B1TXB3IF_bit BANKMASK(B1CON), 7 extern volatile __bit B1TXEN @ (((unsigned) &BSEL0)*8) + 3; #define B1TXEN_bit BANKMASK(BSEL0), 3 extern volatile __bit B1TXERR @ (((unsigned) &B1CON)*8) + 4; #define B1TXERR_bit BANKMASK(B1CON), 4 extern volatile __bit B1TXLARB @ (((unsigned) &B1CON)*8) + 5; #define B1TXLARB_bit BANKMASK(B1CON), 5 extern volatile __bit B1TXPRI0 @ (((unsigned) &B1CON)*8) + 0; #define B1TXPRI0_bit BANKMASK(B1CON), 0 extern volatile __bit B1TXPRI1 @ (((unsigned) &B1CON)*8) + 1; #define B1TXPRI1_bit BANKMASK(B1CON), 1 extern volatile __bit B1TXREQ @ (((unsigned) &B1CON)*8) + 3; #define B1TXREQ_bit BANKMASK(B1CON), 3 extern volatile __bit B2D00 @ (((unsigned) &B2D0)*8) + 0; #define B2D00_bit BANKMASK(B2D0), 0 extern volatile __bit B2D01 @ (((unsigned) &B2D0)*8) + 1; #define B2D01_bit BANKMASK(B2D0), 1 extern volatile __bit B2D02 @ (((unsigned) &B2D0)*8) + 2; #define B2D02_bit BANKMASK(B2D0), 2 extern volatile __bit B2D03 @ (((unsigned) &B2D0)*8) + 3; #define B2D03_bit BANKMASK(B2D0), 3 extern volatile __bit B2D04 @ (((unsigned) &B2D0)*8) + 4; #define B2D04_bit BANKMASK(B2D0), 4 extern volatile __bit B2D05 @ (((unsigned) &B2D0)*8) + 5; #define B2D05_bit BANKMASK(B2D0), 5 extern volatile __bit B2D06 @ (((unsigned) &B2D0)*8) + 6; #define B2D06_bit BANKMASK(B2D0), 6 extern volatile __bit B2D07 @ (((unsigned) &B2D0)*8) + 7; #define B2D07_bit BANKMASK(B2D0), 7 extern volatile __bit B2D10 @ (((unsigned) &B2D1)*8) + 0; #define B2D10_bit BANKMASK(B2D1), 0 extern volatile __bit B2D11 @ (((unsigned) &B2D1)*8) + 1; #define B2D11_bit BANKMASK(B2D1), 1 extern volatile __bit B2D12 @ (((unsigned) &B2D1)*8) + 2; #define B2D12_bit BANKMASK(B2D1), 2 extern volatile __bit B2D13 @ (((unsigned) &B2D1)*8) + 3; #define B2D13_bit BANKMASK(B2D1), 3 extern volatile __bit B2D14 @ (((unsigned) &B2D1)*8) + 4; #define B2D14_bit BANKMASK(B2D1), 4 extern volatile __bit B2D15 @ (((unsigned) &B2D1)*8) + 5; #define B2D15_bit BANKMASK(B2D1), 5 extern volatile __bit B2D16 @ (((unsigned) &B2D1)*8) + 6; #define B2D16_bit BANKMASK(B2D1), 6 extern volatile __bit B2D17 @ (((unsigned) &B2D1)*8) + 7; #define B2D17_bit BANKMASK(B2D1), 7 extern volatile __bit B2D20 @ (((unsigned) &B2D2)*8) + 0; #define B2D20_bit BANKMASK(B2D2), 0 extern volatile __bit B2D21 @ (((unsigned) &B2D2)*8) + 1; #define B2D21_bit BANKMASK(B2D2), 1 extern volatile __bit B2D22 @ (((unsigned) &B2D2)*8) + 2; #define B2D22_bit BANKMASK(B2D2), 2 extern volatile __bit B2D23 @ (((unsigned) &B2D2)*8) + 3; #define B2D23_bit BANKMASK(B2D2), 3 extern volatile __bit B2D24 @ (((unsigned) &B2D2)*8) + 4; #define B2D24_bit BANKMASK(B2D2), 4 extern volatile __bit B2D25 @ (((unsigned) &B2D2)*8) + 5; #define B2D25_bit BANKMASK(B2D2), 5 extern volatile __bit B2D26 @ (((unsigned) &B2D2)*8) + 6; #define B2D26_bit BANKMASK(B2D2), 6 extern volatile __bit B2D27 @ (((unsigned) &B2D2)*8) + 7; #define B2D27_bit BANKMASK(B2D2), 7 extern volatile __bit B2D30 @ (((unsigned) &B2D3)*8) + 0; #define B2D30_bit BANKMASK(B2D3), 0 extern volatile __bit B2D31 @ (((unsigned) &B2D3)*8) + 1; #define B2D31_bit BANKMASK(B2D3), 1 extern volatile __bit B2D32 @ (((unsigned) &B2D3)*8) + 2; #define B2D32_bit BANKMASK(B2D3), 2 extern volatile __bit B2D33 @ (((unsigned) &B2D3)*8) + 3; #define B2D33_bit BANKMASK(B2D3), 3 extern volatile __bit B2D34 @ (((unsigned) &B2D3)*8) + 4; #define B2D34_bit BANKMASK(B2D3), 4 extern volatile __bit B2D35 @ (((unsigned) &B2D3)*8) + 5; #define B2D35_bit BANKMASK(B2D3), 5 extern volatile __bit B2D36 @ (((unsigned) &B2D3)*8) + 6; #define B2D36_bit BANKMASK(B2D3), 6 extern volatile __bit B2D37 @ (((unsigned) &B2D3)*8) + 7; #define B2D37_bit BANKMASK(B2D3), 7 extern volatile __bit B2D40 @ (((unsigned) &B2D4)*8) + 0; #define B2D40_bit BANKMASK(B2D4), 0 extern volatile __bit B2D41 @ (((unsigned) &B2D4)*8) + 1; #define B2D41_bit BANKMASK(B2D4), 1 extern volatile __bit B2D42 @ (((unsigned) &B2D4)*8) + 2; #define B2D42_bit BANKMASK(B2D4), 2 extern volatile __bit B2D43 @ (((unsigned) &B2D4)*8) + 3; #define B2D43_bit BANKMASK(B2D4), 3 extern volatile __bit B2D44 @ (((unsigned) &B2D4)*8) + 4; #define B2D44_bit BANKMASK(B2D4), 4 extern volatile __bit B2D45 @ (((unsigned) &B2D4)*8) + 5; #define B2D45_bit BANKMASK(B2D4), 5 extern volatile __bit B2D46 @ (((unsigned) &B2D4)*8) + 6; #define B2D46_bit BANKMASK(B2D4), 6 extern volatile __bit B2D47 @ (((unsigned) &B2D4)*8) + 7; #define B2D47_bit BANKMASK(B2D4), 7 extern volatile __bit B2D50 @ (((unsigned) &B2D5)*8) + 0; #define B2D50_bit BANKMASK(B2D5), 0 extern volatile __bit B2D51 @ (((unsigned) &B2D5)*8) + 1; #define B2D51_bit BANKMASK(B2D5), 1 extern volatile __bit B2D52 @ (((unsigned) &B2D5)*8) + 2; #define B2D52_bit BANKMASK(B2D5), 2 extern volatile __bit B2D53 @ (((unsigned) &B2D5)*8) + 3; #define B2D53_bit BANKMASK(B2D5), 3 extern volatile __bit B2D54 @ (((unsigned) &B2D5)*8) + 4; #define B2D54_bit BANKMASK(B2D5), 4 extern volatile __bit B2D55 @ (((unsigned) &B2D5)*8) + 5; #define B2D55_bit BANKMASK(B2D5), 5 extern volatile __bit B2D56 @ (((unsigned) &B2D5)*8) + 6; #define B2D56_bit BANKMASK(B2D5), 6 extern volatile __bit B2D57 @ (((unsigned) &B2D5)*8) + 7; #define B2D57_bit BANKMASK(B2D5), 7 extern volatile __bit B2D60 @ (((unsigned) &B2D6)*8) + 0; #define B2D60_bit BANKMASK(B2D6), 0 extern volatile __bit B2D61 @ (((unsigned) &B2D6)*8) + 1; #define B2D61_bit BANKMASK(B2D6), 1 extern volatile __bit B2D62 @ (((unsigned) &B2D6)*8) + 2; #define B2D62_bit BANKMASK(B2D6), 2 extern volatile __bit B2D63 @ (((unsigned) &B2D6)*8) + 3; #define B2D63_bit BANKMASK(B2D6), 3 extern volatile __bit B2D64 @ (((unsigned) &B2D6)*8) + 4; #define B2D64_bit BANKMASK(B2D6), 4 extern volatile __bit B2D65 @ (((unsigned) &B2D6)*8) + 5; #define B2D65_bit BANKMASK(B2D6), 5 extern volatile __bit B2D66 @ (((unsigned) &B2D6)*8) + 6; #define B2D66_bit BANKMASK(B2D6), 6 extern volatile __bit B2D67 @ (((unsigned) &B2D6)*8) + 7; #define B2D67_bit BANKMASK(B2D6), 7 extern volatile __bit B2D70 @ (((unsigned) &B2D7)*8) + 0; #define B2D70_bit BANKMASK(B2D7), 0 extern volatile __bit B2D71 @ (((unsigned) &B2D7)*8) + 1; #define B2D71_bit BANKMASK(B2D7), 1 extern volatile __bit B2D72 @ (((unsigned) &B2D7)*8) + 2; #define B2D72_bit BANKMASK(B2D7), 2 extern volatile __bit B2D73 @ (((unsigned) &B2D7)*8) + 3; #define B2D73_bit BANKMASK(B2D7), 3 extern volatile __bit B2D74 @ (((unsigned) &B2D7)*8) + 4; #define B2D74_bit BANKMASK(B2D7), 4 extern volatile __bit B2D75 @ (((unsigned) &B2D7)*8) + 5; #define B2D75_bit BANKMASK(B2D7), 5 extern volatile __bit B2D76 @ (((unsigned) &B2D7)*8) + 6; #define B2D76_bit BANKMASK(B2D7), 6 extern volatile __bit B2D77 @ (((unsigned) &B2D7)*8) + 7; #define B2D77_bit BANKMASK(B2D7), 7 extern volatile __bit B2DLC0 @ (((unsigned) &B2DLC)*8) + 0; #define B2DLC0_bit BANKMASK(B2DLC), 0 extern volatile __bit B2DLC1 @ (((unsigned) &B2DLC)*8) + 1; #define B2DLC1_bit BANKMASK(B2DLC), 1 extern volatile __bit B2DLC2 @ (((unsigned) &B2DLC)*8) + 2; #define B2DLC2_bit BANKMASK(B2DLC), 2 extern volatile __bit B2DLC3 @ (((unsigned) &B2DLC)*8) + 3; #define B2DLC3_bit BANKMASK(B2DLC), 3 extern volatile __bit B2EID0 @ (((unsigned) &B2EIDL)*8) + 0; #define B2EID0_bit BANKMASK(B2EIDL), 0 extern volatile __bit B2EID1 @ (((unsigned) &B2EIDL)*8) + 1; #define B2EID1_bit BANKMASK(B2EIDL), 1 extern volatile __bit B2EID10 @ (((unsigned) &B2EIDH)*8) + 2; #define B2EID10_bit BANKMASK(B2EIDH), 2 extern volatile __bit B2EID11 @ (((unsigned) &B2EIDH)*8) + 3; #define B2EID11_bit BANKMASK(B2EIDH), 3 extern volatile __bit B2EID12 @ (((unsigned) &B2EIDH)*8) + 4; #define B2EID12_bit BANKMASK(B2EIDH), 4 extern volatile __bit B2EID13 @ (((unsigned) &B2EIDH)*8) + 5; #define B2EID13_bit BANKMASK(B2EIDH), 5 extern volatile __bit B2EID14 @ (((unsigned) &B2EIDH)*8) + 6; #define B2EID14_bit BANKMASK(B2EIDH), 6 extern volatile __bit B2EID15 @ (((unsigned) &B2EIDH)*8) + 7; #define B2EID15_bit BANKMASK(B2EIDH), 7 extern volatile __bit B2EID16 @ (((unsigned) &B2SIDL)*8) + 0; #define B2EID16_bit BANKMASK(B2SIDL), 0 extern volatile __bit B2EID17 @ (((unsigned) &B2SIDL)*8) + 1; #define B2EID17_bit BANKMASK(B2SIDL), 1 extern volatile __bit B2EID2 @ (((unsigned) &B2EIDL)*8) + 2; #define B2EID2_bit BANKMASK(B2EIDL), 2 extern volatile __bit B2EID3 @ (((unsigned) &B2EIDL)*8) + 3; #define B2EID3_bit BANKMASK(B2EIDL), 3 extern volatile __bit B2EID4 @ (((unsigned) &B2EIDL)*8) + 4; #define B2EID4_bit BANKMASK(B2EIDL), 4 extern volatile __bit B2EID5 @ (((unsigned) &B2EIDL)*8) + 5; #define B2EID5_bit BANKMASK(B2EIDL), 5 extern volatile __bit B2EID6 @ (((unsigned) &B2EIDL)*8) + 6; #define B2EID6_bit BANKMASK(B2EIDL), 6 extern volatile __bit B2EID7 @ (((unsigned) &B2EIDL)*8) + 7; #define B2EID7_bit BANKMASK(B2EIDL), 7 extern volatile __bit B2EID8 @ (((unsigned) &B2EIDH)*8) + 0; #define B2EID8_bit BANKMASK(B2EIDH), 0 extern volatile __bit B2EID9 @ (((unsigned) &B2EIDH)*8) + 1; #define B2EID9_bit BANKMASK(B2EIDH), 1 extern volatile __bit B2EXID @ (((unsigned) &B2SIDL)*8) + 3; #define B2EXID_bit BANKMASK(B2SIDL), 3 extern volatile __bit B2EXIDE @ (((unsigned) &B2SIDL)*8) + 3; #define B2EXIDE_bit BANKMASK(B2SIDL), 3 extern volatile __bit B2FILHIT0 @ (((unsigned) &B2CON)*8) + 0; #define B2FILHIT0_bit BANKMASK(B2CON), 0 extern volatile __bit B2FILHIT1 @ (((unsigned) &B2CON)*8) + 1; #define B2FILHIT1_bit BANKMASK(B2CON), 1 extern volatile __bit B2FILHIT2 @ (((unsigned) &B2CON)*8) + 2; #define B2FILHIT2_bit BANKMASK(B2CON), 2 extern volatile __bit B2FILHIT3 @ (((unsigned) &B2CON)*8) + 3; #define B2FILHIT3_bit BANKMASK(B2CON), 3 extern volatile __bit B2FILHIT4 @ (((unsigned) &B2CON)*8) + 4; #define B2FILHIT4_bit BANKMASK(B2CON), 4 extern volatile __bit B2IE @ (((unsigned) &BIE0)*8) + 4; #define B2IE_bit BANKMASK(BIE0), 4 extern volatile __bit B2RB0 @ (((unsigned) &B2DLC)*8) + 4; #define B2RB0_bit BANKMASK(B2DLC), 4 extern volatile __bit B2RB1 @ (((unsigned) &B2DLC)*8) + 5; #define B2RB1_bit BANKMASK(B2DLC), 5 extern volatile __bit B2RTREN @ (((unsigned) &B2CON)*8) + 2; #define B2RTREN_bit BANKMASK(B2CON), 2 extern volatile __bit B2RTRRO @ (((unsigned) &B2CON)*8) + 5; #define B2RTRRO_bit BANKMASK(B2CON), 5 extern volatile __bit B2RXFUL @ (((unsigned) &B2CON)*8) + 7; #define B2RXFUL_bit BANKMASK(B2CON), 7 extern volatile __bit B2RXM1 @ (((unsigned) &B2CON)*8) + 6; #define B2RXM1_bit BANKMASK(B2CON), 6 extern volatile __bit B2RXRTR @ (((unsigned) &B2DLC)*8) + 6; #define B2RXRTR_bit BANKMASK(B2DLC), 6 extern volatile __bit B2SID0 @ (((unsigned) &B2SIDL)*8) + 5; #define B2SID0_bit BANKMASK(B2SIDL), 5 extern volatile __bit B2SID1 @ (((unsigned) &B2SIDL)*8) + 6; #define B2SID1_bit BANKMASK(B2SIDL), 6 extern volatile __bit B2SID10 @ (((unsigned) &B2SIDH)*8) + 7; #define B2SID10_bit BANKMASK(B2SIDH), 7 extern volatile __bit B2SID2 @ (((unsigned) &B2SIDL)*8) + 7; #define B2SID2_bit BANKMASK(B2SIDL), 7 extern volatile __bit B2SID3 @ (((unsigned) &B2SIDH)*8) + 0; #define B2SID3_bit BANKMASK(B2SIDH), 0 extern volatile __bit B2SID4 @ (((unsigned) &B2SIDH)*8) + 1; #define B2SID4_bit BANKMASK(B2SIDH), 1 extern volatile __bit B2SID5 @ (((unsigned) &B2SIDH)*8) + 2; #define B2SID5_bit BANKMASK(B2SIDH), 2 extern volatile __bit B2SID6 @ (((unsigned) &B2SIDH)*8) + 3; #define B2SID6_bit BANKMASK(B2SIDH), 3 extern volatile __bit B2SID7 @ (((unsigned) &B2SIDH)*8) + 4; #define B2SID7_bit BANKMASK(B2SIDH), 4 extern volatile __bit B2SID8 @ (((unsigned) &B2SIDH)*8) + 5; #define B2SID8_bit BANKMASK(B2SIDH), 5 extern volatile __bit B2SID9 @ (((unsigned) &B2SIDH)*8) + 6; #define B2SID9_bit BANKMASK(B2SIDH), 6 extern volatile __bit B2SRR @ (((unsigned) &B2SIDL)*8) + 4; #define B2SRR_bit BANKMASK(B2SIDL), 4 extern volatile __bit B2TXABT @ (((unsigned) &B2CON)*8) + 6; #define B2TXABT_bit BANKMASK(B2CON), 6 extern volatile __bit B2TXB3IF @ (((unsigned) &B2CON)*8) + 7; #define B2TXB3IF_bit BANKMASK(B2CON), 7 extern volatile __bit B2TXEN @ (((unsigned) &BSEL0)*8) + 4; #define B2TXEN_bit BANKMASK(BSEL0), 4 extern volatile __bit B2TXERR @ (((unsigned) &B2CON)*8) + 4; #define B2TXERR_bit BANKMASK(B2CON), 4 extern volatile __bit B2TXLARB @ (((unsigned) &B2CON)*8) + 5; #define B2TXLARB_bit BANKMASK(B2CON), 5 extern volatile __bit B2TXPRI0 @ (((unsigned) &B2CON)*8) + 0; #define B2TXPRI0_bit BANKMASK(B2CON), 0 extern volatile __bit B2TXPRI1 @ (((unsigned) &B2CON)*8) + 1; #define B2TXPRI1_bit BANKMASK(B2CON), 1 extern volatile __bit B2TXREQ @ (((unsigned) &B2CON)*8) + 3; #define B2TXREQ_bit BANKMASK(B2CON), 3 extern volatile __bit B3D00 @ (((unsigned) &B3D0)*8) + 0; #define B3D00_bit BANKMASK(B3D0), 0 extern volatile __bit B3D01 @ (((unsigned) &B3D0)*8) + 1; #define B3D01_bit BANKMASK(B3D0), 1 extern volatile __bit B3D02 @ (((unsigned) &B3D0)*8) + 2; #define B3D02_bit BANKMASK(B3D0), 2 extern volatile __bit B3D03 @ (((unsigned) &B3D0)*8) + 3; #define B3D03_bit BANKMASK(B3D0), 3 extern volatile __bit B3D04 @ (((unsigned) &B3D0)*8) + 4; #define B3D04_bit BANKMASK(B3D0), 4 extern volatile __bit B3D05 @ (((unsigned) &B3D0)*8) + 5; #define B3D05_bit BANKMASK(B3D0), 5 extern volatile __bit B3D06 @ (((unsigned) &B3D0)*8) + 6; #define B3D06_bit BANKMASK(B3D0), 6 extern volatile __bit B3D07 @ (((unsigned) &B3D0)*8) + 7; #define B3D07_bit BANKMASK(B3D0), 7 extern volatile __bit B3D10 @ (((unsigned) &B3D1)*8) + 0; #define B3D10_bit BANKMASK(B3D1), 0 extern volatile __bit B3D11 @ (((unsigned) &B3D1)*8) + 1; #define B3D11_bit BANKMASK(B3D1), 1 extern volatile __bit B3D12 @ (((unsigned) &B3D1)*8) + 2; #define B3D12_bit BANKMASK(B3D1), 2 extern volatile __bit B3D13 @ (((unsigned) &B3D1)*8) + 3; #define B3D13_bit BANKMASK(B3D1), 3 extern volatile __bit B3D14 @ (((unsigned) &B3D1)*8) + 4; #define B3D14_bit BANKMASK(B3D1), 4 extern volatile __bit B3D15 @ (((unsigned) &B3D1)*8) + 5; #define B3D15_bit BANKMASK(B3D1), 5 extern volatile __bit B3D16 @ (((unsigned) &B3D1)*8) + 6; #define B3D16_bit BANKMASK(B3D1), 6 extern volatile __bit B3D17 @ (((unsigned) &B3D1)*8) + 7; #define B3D17_bit BANKMASK(B3D1), 7 extern volatile __bit B3D20 @ (((unsigned) &B3D2)*8) + 0; #define B3D20_bit BANKMASK(B3D2), 0 extern volatile __bit B3D21 @ (((unsigned) &B3D2)*8) + 1; #define B3D21_bit BANKMASK(B3D2), 1 extern volatile __bit B3D22 @ (((unsigned) &B3D2)*8) + 2; #define B3D22_bit BANKMASK(B3D2), 2 extern volatile __bit B3D23 @ (((unsigned) &B3D2)*8) + 3; #define B3D23_bit BANKMASK(B3D2), 3 extern volatile __bit B3D24 @ (((unsigned) &B3D2)*8) + 4; #define B3D24_bit BANKMASK(B3D2), 4 extern volatile __bit B3D25 @ (((unsigned) &B3D2)*8) + 5; #define B3D25_bit BANKMASK(B3D2), 5 extern volatile __bit B3D26 @ (((unsigned) &B3D2)*8) + 6; #define B3D26_bit BANKMASK(B3D2), 6 extern volatile __bit B3D27 @ (((unsigned) &B3D2)*8) + 7; #define B3D27_bit BANKMASK(B3D2), 7 extern volatile __bit B3D30 @ (((unsigned) &B3D3)*8) + 0; #define B3D30_bit BANKMASK(B3D3), 0 extern volatile __bit B3D31 @ (((unsigned) &B3D3)*8) + 1; #define B3D31_bit BANKMASK(B3D3), 1 extern volatile __bit B3D32 @ (((unsigned) &B3D3)*8) + 2; #define B3D32_bit BANKMASK(B3D3), 2 extern volatile __bit B3D33 @ (((unsigned) &B3D3)*8) + 3; #define B3D33_bit BANKMASK(B3D3), 3 extern volatile __bit B3D34 @ (((unsigned) &B3D3)*8) + 4; #define B3D34_bit BANKMASK(B3D3), 4 extern volatile __bit B3D35 @ (((unsigned) &B3D3)*8) + 5; #define B3D35_bit BANKMASK(B3D3), 5 extern volatile __bit B3D36 @ (((unsigned) &B3D3)*8) + 6; #define B3D36_bit BANKMASK(B3D3), 6 extern volatile __bit B3D37 @ (((unsigned) &B3D3)*8) + 7; #define B3D37_bit BANKMASK(B3D3), 7 extern volatile __bit B3D40 @ (((unsigned) &B3D4)*8) + 0; #define B3D40_bit BANKMASK(B3D4), 0 extern volatile __bit B3D41 @ (((unsigned) &B3D4)*8) + 1; #define B3D41_bit BANKMASK(B3D4), 1 extern volatile __bit B3D42 @ (((unsigned) &B3D4)*8) + 2; #define B3D42_bit BANKMASK(B3D4), 2 extern volatile __bit B3D43 @ (((unsigned) &B3D4)*8) + 3; #define B3D43_bit BANKMASK(B3D4), 3 extern volatile __bit B3D44 @ (((unsigned) &B3D4)*8) + 4; #define B3D44_bit BANKMASK(B3D4), 4 extern volatile __bit B3D45 @ (((unsigned) &B3D4)*8) + 5; #define B3D45_bit BANKMASK(B3D4), 5 extern volatile __bit B3D46 @ (((unsigned) &B3D4)*8) + 6; #define B3D46_bit BANKMASK(B3D4), 6 extern volatile __bit B3D47 @ (((unsigned) &B3D4)*8) + 7; #define B3D47_bit BANKMASK(B3D4), 7 extern volatile __bit B3D50 @ (((unsigned) &B3D5)*8) + 0; #define B3D50_bit BANKMASK(B3D5), 0 extern volatile __bit B3D51 @ (((unsigned) &B3D5)*8) + 1; #define B3D51_bit BANKMASK(B3D5), 1 extern volatile __bit B3D52 @ (((unsigned) &B3D5)*8) + 2; #define B3D52_bit BANKMASK(B3D5), 2 extern volatile __bit B3D53 @ (((unsigned) &B3D5)*8) + 3; #define B3D53_bit BANKMASK(B3D5), 3 extern volatile __bit B3D54 @ (((unsigned) &B3D5)*8) + 4; #define B3D54_bit BANKMASK(B3D5), 4 extern volatile __bit B3D55 @ (((unsigned) &B3D5)*8) + 5; #define B3D55_bit BANKMASK(B3D5), 5 extern volatile __bit B3D56 @ (((unsigned) &B3D5)*8) + 6; #define B3D56_bit BANKMASK(B3D5), 6 extern volatile __bit B3D57 @ (((unsigned) &B3D5)*8) + 7; #define B3D57_bit BANKMASK(B3D5), 7 extern volatile __bit B3D60 @ (((unsigned) &B3D6)*8) + 0; #define B3D60_bit BANKMASK(B3D6), 0 extern volatile __bit B3D61 @ (((unsigned) &B3D6)*8) + 1; #define B3D61_bit BANKMASK(B3D6), 1 extern volatile __bit B3D62 @ (((unsigned) &B3D6)*8) + 2; #define B3D62_bit BANKMASK(B3D6), 2 extern volatile __bit B3D63 @ (((unsigned) &B3D6)*8) + 3; #define B3D63_bit BANKMASK(B3D6), 3 extern volatile __bit B3D64 @ (((unsigned) &B3D6)*8) + 4; #define B3D64_bit BANKMASK(B3D6), 4 extern volatile __bit B3D65 @ (((unsigned) &B3D6)*8) + 5; #define B3D65_bit BANKMASK(B3D6), 5 extern volatile __bit B3D66 @ (((unsigned) &B3D6)*8) + 6; #define B3D66_bit BANKMASK(B3D6), 6 extern volatile __bit B3D67 @ (((unsigned) &B3D6)*8) + 7; #define B3D67_bit BANKMASK(B3D6), 7 extern volatile __bit B3D70 @ (((unsigned) &B3D7)*8) + 0; #define B3D70_bit BANKMASK(B3D7), 0 extern volatile __bit B3D71 @ (((unsigned) &B3D7)*8) + 1; #define B3D71_bit BANKMASK(B3D7), 1 extern volatile __bit B3D72 @ (((unsigned) &B3D7)*8) + 2; #define B3D72_bit BANKMASK(B3D7), 2 extern volatile __bit B3D73 @ (((unsigned) &B3D7)*8) + 3; #define B3D73_bit BANKMASK(B3D7), 3 extern volatile __bit B3D74 @ (((unsigned) &B3D7)*8) + 4; #define B3D74_bit BANKMASK(B3D7), 4 extern volatile __bit B3D75 @ (((unsigned) &B3D7)*8) + 5; #define B3D75_bit BANKMASK(B3D7), 5 extern volatile __bit B3D76 @ (((unsigned) &B3D7)*8) + 6; #define B3D76_bit BANKMASK(B3D7), 6 extern volatile __bit B3D77 @ (((unsigned) &B3D7)*8) + 7; #define B3D77_bit BANKMASK(B3D7), 7 extern volatile __bit B3DLC0 @ (((unsigned) &B3DLC)*8) + 0; #define B3DLC0_bit BANKMASK(B3DLC), 0 extern volatile __bit B3DLC1 @ (((unsigned) &B3DLC)*8) + 1; #define B3DLC1_bit BANKMASK(B3DLC), 1 extern volatile __bit B3DLC2 @ (((unsigned) &B3DLC)*8) + 2; #define B3DLC2_bit BANKMASK(B3DLC), 2 extern volatile __bit B3DLC3 @ (((unsigned) &B3DLC)*8) + 3; #define B3DLC3_bit BANKMASK(B3DLC), 3 extern volatile __bit B3EID0 @ (((unsigned) &B3EIDL)*8) + 0; #define B3EID0_bit BANKMASK(B3EIDL), 0 extern volatile __bit B3EID1 @ (((unsigned) &B3EIDL)*8) + 1; #define B3EID1_bit BANKMASK(B3EIDL), 1 extern volatile __bit B3EID10 @ (((unsigned) &B3EIDH)*8) + 2; #define B3EID10_bit BANKMASK(B3EIDH), 2 extern volatile __bit B3EID11 @ (((unsigned) &B3EIDH)*8) + 3; #define B3EID11_bit BANKMASK(B3EIDH), 3 extern volatile __bit B3EID12 @ (((unsigned) &B3EIDH)*8) + 4; #define B3EID12_bit BANKMASK(B3EIDH), 4 extern volatile __bit B3EID13 @ (((unsigned) &B3EIDH)*8) + 5; #define B3EID13_bit BANKMASK(B3EIDH), 5 extern volatile __bit B3EID14 @ (((unsigned) &B3EIDH)*8) + 6; #define B3EID14_bit BANKMASK(B3EIDH), 6 extern volatile __bit B3EID15 @ (((unsigned) &B3EIDH)*8) + 7; #define B3EID15_bit BANKMASK(B3EIDH), 7 extern volatile __bit B3EID16 @ (((unsigned) &B3SIDL)*8) + 0; #define B3EID16_bit BANKMASK(B3SIDL), 0 extern volatile __bit B3EID17 @ (((unsigned) &B3SIDL)*8) + 1; #define B3EID17_bit BANKMASK(B3SIDL), 1 extern volatile __bit B3EID2 @ (((unsigned) &B3EIDL)*8) + 2; #define B3EID2_bit BANKMASK(B3EIDL), 2 extern volatile __bit B3EID3 @ (((unsigned) &B3EIDL)*8) + 3; #define B3EID3_bit BANKMASK(B3EIDL), 3 extern volatile __bit B3EID4 @ (((unsigned) &B3EIDL)*8) + 4; #define B3EID4_bit BANKMASK(B3EIDL), 4 extern volatile __bit B3EID5 @ (((unsigned) &B3EIDL)*8) + 5; #define B3EID5_bit BANKMASK(B3EIDL), 5 extern volatile __bit B3EID6 @ (((unsigned) &B3EIDL)*8) + 6; #define B3EID6_bit BANKMASK(B3EIDL), 6 extern volatile __bit B3EID7 @ (((unsigned) &B3EIDL)*8) + 7; #define B3EID7_bit BANKMASK(B3EIDL), 7 extern volatile __bit B3EID8 @ (((unsigned) &B3EIDH)*8) + 0; #define B3EID8_bit BANKMASK(B3EIDH), 0 extern volatile __bit B3EID9 @ (((unsigned) &B3EIDH)*8) + 1; #define B3EID9_bit BANKMASK(B3EIDH), 1 extern volatile __bit B3EXID @ (((unsigned) &B3SIDL)*8) + 3; #define B3EXID_bit BANKMASK(B3SIDL), 3 extern volatile __bit B3EXIDE @ (((unsigned) &B3SIDL)*8) + 3; #define B3EXIDE_bit BANKMASK(B3SIDL), 3 extern volatile __bit B3FILHIT0 @ (((unsigned) &B3CON)*8) + 0; #define B3FILHIT0_bit BANKMASK(B3CON), 0 extern volatile __bit B3FILHIT1 @ (((unsigned) &B3CON)*8) + 1; #define B3FILHIT1_bit BANKMASK(B3CON), 1 extern volatile __bit B3FILHIT2 @ (((unsigned) &B3CON)*8) + 2; #define B3FILHIT2_bit BANKMASK(B3CON), 2 extern volatile __bit B3FILHIT3 @ (((unsigned) &B3CON)*8) + 3; #define B3FILHIT3_bit BANKMASK(B3CON), 3 extern volatile __bit B3FILHIT4 @ (((unsigned) &B3CON)*8) + 4; #define B3FILHIT4_bit BANKMASK(B3CON), 4 extern volatile __bit B3IE @ (((unsigned) &BIE0)*8) + 5; #define B3IE_bit BANKMASK(BIE0), 5 extern volatile __bit B3RB0 @ (((unsigned) &B3DLC)*8) + 4; #define B3RB0_bit BANKMASK(B3DLC), 4 extern volatile __bit B3RB1 @ (((unsigned) &B3DLC)*8) + 5; #define B3RB1_bit BANKMASK(B3DLC), 5 extern volatile __bit B3RTREN @ (((unsigned) &B3CON)*8) + 2; #define B3RTREN_bit BANKMASK(B3CON), 2 extern volatile __bit B3RTRRO @ (((unsigned) &B3CON)*8) + 5; #define B3RTRRO_bit BANKMASK(B3CON), 5 extern volatile __bit B3RXFUL @ (((unsigned) &B3CON)*8) + 7; #define B3RXFUL_bit BANKMASK(B3CON), 7 extern volatile __bit B3RXM1 @ (((unsigned) &B3CON)*8) + 6; #define B3RXM1_bit BANKMASK(B3CON), 6 extern volatile __bit B3RXRTR @ (((unsigned) &B3DLC)*8) + 6; #define B3RXRTR_bit BANKMASK(B3DLC), 6 extern volatile __bit B3SID0 @ (((unsigned) &B3SIDL)*8) + 5; #define B3SID0_bit BANKMASK(B3SIDL), 5 extern volatile __bit B3SID1 @ (((unsigned) &B3SIDL)*8) + 6; #define B3SID1_bit BANKMASK(B3SIDL), 6 extern volatile __bit B3SID10 @ (((unsigned) &B3SIDH)*8) + 7; #define B3SID10_bit BANKMASK(B3SIDH), 7 extern volatile __bit B3SID2 @ (((unsigned) &B3SIDL)*8) + 7; #define B3SID2_bit BANKMASK(B3SIDL), 7 extern volatile __bit B3SID3 @ (((unsigned) &B3SIDH)*8) + 0; #define B3SID3_bit BANKMASK(B3SIDH), 0 extern volatile __bit B3SID4 @ (((unsigned) &B3SIDH)*8) + 1; #define B3SID4_bit BANKMASK(B3SIDH), 1 extern volatile __bit B3SID5 @ (((unsigned) &B3SIDH)*8) + 2; #define B3SID5_bit BANKMASK(B3SIDH), 2 extern volatile __bit B3SID6 @ (((unsigned) &B3SIDH)*8) + 3; #define B3SID6_bit BANKMASK(B3SIDH), 3 extern volatile __bit B3SID7 @ (((unsigned) &B3SIDH)*8) + 4; #define B3SID7_bit BANKMASK(B3SIDH), 4 extern volatile __bit B3SID8 @ (((unsigned) &B3SIDH)*8) + 5; #define B3SID8_bit BANKMASK(B3SIDH), 5 extern volatile __bit B3SID9 @ (((unsigned) &B3SIDH)*8) + 6; #define B3SID9_bit BANKMASK(B3SIDH), 6 extern volatile __bit B3SRR @ (((unsigned) &B3SIDL)*8) + 4; #define B3SRR_bit BANKMASK(B3SIDL), 4 extern volatile __bit B3TXABT @ (((unsigned) &B3CON)*8) + 6; #define B3TXABT_bit BANKMASK(B3CON), 6 extern volatile __bit B3TXB3IF @ (((unsigned) &B3CON)*8) + 7; #define B3TXB3IF_bit BANKMASK(B3CON), 7 extern volatile __bit B3TXEN @ (((unsigned) &BSEL0)*8) + 5; #define B3TXEN_bit BANKMASK(BSEL0), 5 extern volatile __bit B3TXERR @ (((unsigned) &B3CON)*8) + 4; #define B3TXERR_bit BANKMASK(B3CON), 4 extern volatile __bit B3TXLARB @ (((unsigned) &B3CON)*8) + 5; #define B3TXLARB_bit BANKMASK(B3CON), 5 extern volatile __bit B3TXPRI0 @ (((unsigned) &B3CON)*8) + 0; #define B3TXPRI0_bit BANKMASK(B3CON), 0 extern volatile __bit B3TXPRI1 @ (((unsigned) &B3CON)*8) + 1; #define B3TXPRI1_bit BANKMASK(B3CON), 1 extern volatile __bit B3TXREQ @ (((unsigned) &B3CON)*8) + 3; #define B3TXREQ_bit BANKMASK(B3CON), 3 extern volatile __bit B4D00 @ (((unsigned) &B4D0)*8) + 0; #define B4D00_bit BANKMASK(B4D0), 0 extern volatile __bit B4D01 @ (((unsigned) &B4D0)*8) + 1; #define B4D01_bit BANKMASK(B4D0), 1 extern volatile __bit B4D02 @ (((unsigned) &B4D0)*8) + 2; #define B4D02_bit BANKMASK(B4D0), 2 extern volatile __bit B4D03 @ (((unsigned) &B4D0)*8) + 3; #define B4D03_bit BANKMASK(B4D0), 3 extern volatile __bit B4D04 @ (((unsigned) &B4D0)*8) + 4; #define B4D04_bit BANKMASK(B4D0), 4 extern volatile __bit B4D05 @ (((unsigned) &B4D0)*8) + 5; #define B4D05_bit BANKMASK(B4D0), 5 extern volatile __bit B4D06 @ (((unsigned) &B4D0)*8) + 6; #define B4D06_bit BANKMASK(B4D0), 6 extern volatile __bit B4D07 @ (((unsigned) &B4D0)*8) + 7; #define B4D07_bit BANKMASK(B4D0), 7 extern volatile __bit B4D10 @ (((unsigned) &B4D1)*8) + 0; #define B4D10_bit BANKMASK(B4D1), 0 extern volatile __bit B4D11 @ (((unsigned) &B4D1)*8) + 1; #define B4D11_bit BANKMASK(B4D1), 1 extern volatile __bit B4D12 @ (((unsigned) &B4D1)*8) + 2; #define B4D12_bit BANKMASK(B4D1), 2 extern volatile __bit B4D13 @ (((unsigned) &B4D1)*8) + 3; #define B4D13_bit BANKMASK(B4D1), 3 extern volatile __bit B4D14 @ (((unsigned) &B4D1)*8) + 4; #define B4D14_bit BANKMASK(B4D1), 4 extern volatile __bit B4D15 @ (((unsigned) &B4D1)*8) + 5; #define B4D15_bit BANKMASK(B4D1), 5 extern volatile __bit B4D16 @ (((unsigned) &B4D1)*8) + 6; #define B4D16_bit BANKMASK(B4D1), 6 extern volatile __bit B4D17 @ (((unsigned) &B4D1)*8) + 7; #define B4D17_bit BANKMASK(B4D1), 7 extern volatile __bit B4D20 @ (((unsigned) &B4D2)*8) + 0; #define B4D20_bit BANKMASK(B4D2), 0 extern volatile __bit B4D21 @ (((unsigned) &B4D2)*8) + 1; #define B4D21_bit BANKMASK(B4D2), 1 extern volatile __bit B4D22 @ (((unsigned) &B4D2)*8) + 2; #define B4D22_bit BANKMASK(B4D2), 2 extern volatile __bit B4D23 @ (((unsigned) &B4D2)*8) + 3; #define B4D23_bit BANKMASK(B4D2), 3 extern volatile __bit B4D24 @ (((unsigned) &B4D2)*8) + 4; #define B4D24_bit BANKMASK(B4D2), 4 extern volatile __bit B4D25 @ (((unsigned) &B4D2)*8) + 5; #define B4D25_bit BANKMASK(B4D2), 5 extern volatile __bit B4D26 @ (((unsigned) &B4D2)*8) + 6; #define B4D26_bit BANKMASK(B4D2), 6 extern volatile __bit B4D27 @ (((unsigned) &B4D2)*8) + 7; #define B4D27_bit BANKMASK(B4D2), 7 extern volatile __bit B4D30 @ (((unsigned) &B4D3)*8) + 0; #define B4D30_bit BANKMASK(B4D3), 0 extern volatile __bit B4D31 @ (((unsigned) &B4D3)*8) + 1; #define B4D31_bit BANKMASK(B4D3), 1 extern volatile __bit B4D32 @ (((unsigned) &B4D3)*8) + 2; #define B4D32_bit BANKMASK(B4D3), 2 extern volatile __bit B4D33 @ (((unsigned) &B4D3)*8) + 3; #define B4D33_bit BANKMASK(B4D3), 3 extern volatile __bit B4D34 @ (((unsigned) &B4D3)*8) + 4; #define B4D34_bit BANKMASK(B4D3), 4 extern volatile __bit B4D35 @ (((unsigned) &B4D3)*8) + 5; #define B4D35_bit BANKMASK(B4D3), 5 extern volatile __bit B4D36 @ (((unsigned) &B4D3)*8) + 6; #define B4D36_bit BANKMASK(B4D3), 6 extern volatile __bit B4D37 @ (((unsigned) &B4D3)*8) + 7; #define B4D37_bit BANKMASK(B4D3), 7 extern volatile __bit B4D40 @ (((unsigned) &B4D4)*8) + 0; #define B4D40_bit BANKMASK(B4D4), 0 extern volatile __bit B4D41 @ (((unsigned) &B4D4)*8) + 1; #define B4D41_bit BANKMASK(B4D4), 1 extern volatile __bit B4D42 @ (((unsigned) &B4D4)*8) + 2; #define B4D42_bit BANKMASK(B4D4), 2 extern volatile __bit B4D43 @ (((unsigned) &B4D4)*8) + 3; #define B4D43_bit BANKMASK(B4D4), 3 extern volatile __bit B4D44 @ (((unsigned) &B4D4)*8) + 4; #define B4D44_bit BANKMASK(B4D4), 4 extern volatile __bit B4D45 @ (((unsigned) &B4D4)*8) + 5; #define B4D45_bit BANKMASK(B4D4), 5 extern volatile __bit B4D46 @ (((unsigned) &B4D4)*8) + 6; #define B4D46_bit BANKMASK(B4D4), 6 extern volatile __bit B4D47 @ (((unsigned) &B4D4)*8) + 7; #define B4D47_bit BANKMASK(B4D4), 7 extern volatile __bit B4D50 @ (((unsigned) &B4D5)*8) + 0; #define B4D50_bit BANKMASK(B4D5), 0 extern volatile __bit B4D51 @ (((unsigned) &B4D5)*8) + 1; #define B4D51_bit BANKMASK(B4D5), 1 extern volatile __bit B4D52 @ (((unsigned) &B4D5)*8) + 2; #define B4D52_bit BANKMASK(B4D5), 2 extern volatile __bit B4D53 @ (((unsigned) &B4D5)*8) + 3; #define B4D53_bit BANKMASK(B4D5), 3 extern volatile __bit B4D54 @ (((unsigned) &B4D5)*8) + 4; #define B4D54_bit BANKMASK(B4D5), 4 extern volatile __bit B4D55 @ (((unsigned) &B4D5)*8) + 5; #define B4D55_bit BANKMASK(B4D5), 5 extern volatile __bit B4D56 @ (((unsigned) &B4D5)*8) + 6; #define B4D56_bit BANKMASK(B4D5), 6 extern volatile __bit B4D57 @ (((unsigned) &B4D5)*8) + 7; #define B4D57_bit BANKMASK(B4D5), 7 extern volatile __bit B4D60 @ (((unsigned) &B4D6)*8) + 0; #define B4D60_bit BANKMASK(B4D6), 0 extern volatile __bit B4D61 @ (((unsigned) &B4D6)*8) + 1; #define B4D61_bit BANKMASK(B4D6), 1 extern volatile __bit B4D62 @ (((unsigned) &B4D6)*8) + 2; #define B4D62_bit BANKMASK(B4D6), 2 extern volatile __bit B4D63 @ (((unsigned) &B4D6)*8) + 3; #define B4D63_bit BANKMASK(B4D6), 3 extern volatile __bit B4D64 @ (((unsigned) &B4D6)*8) + 4; #define B4D64_bit BANKMASK(B4D6), 4 extern volatile __bit B4D65 @ (((unsigned) &B4D6)*8) + 5; #define B4D65_bit BANKMASK(B4D6), 5 extern volatile __bit B4D66 @ (((unsigned) &B4D6)*8) + 6; #define B4D66_bit BANKMASK(B4D6), 6 extern volatile __bit B4D67 @ (((unsigned) &B4D6)*8) + 7; #define B4D67_bit BANKMASK(B4D6), 7 extern volatile __bit B4D70 @ (((unsigned) &B4D7)*8) + 0; #define B4D70_bit BANKMASK(B4D7), 0 extern volatile __bit B4D71 @ (((unsigned) &B4D7)*8) + 1; #define B4D71_bit BANKMASK(B4D7), 1 extern volatile __bit B4D72 @ (((unsigned) &B4D7)*8) + 2; #define B4D72_bit BANKMASK(B4D7), 2 extern volatile __bit B4D73 @ (((unsigned) &B4D7)*8) + 3; #define B4D73_bit BANKMASK(B4D7), 3 extern volatile __bit B4D74 @ (((unsigned) &B4D7)*8) + 4; #define B4D74_bit BANKMASK(B4D7), 4 extern volatile __bit B4D75 @ (((unsigned) &B4D7)*8) + 5; #define B4D75_bit BANKMASK(B4D7), 5 extern volatile __bit B4D76 @ (((unsigned) &B4D7)*8) + 6; #define B4D76_bit BANKMASK(B4D7), 6 extern volatile __bit B4D77 @ (((unsigned) &B4D7)*8) + 7; #define B4D77_bit BANKMASK(B4D7), 7 extern volatile __bit B4DLC0 @ (((unsigned) &B4DLC)*8) + 0; #define B4DLC0_bit BANKMASK(B4DLC), 0 extern volatile __bit B4DLC1 @ (((unsigned) &B4DLC)*8) + 1; #define B4DLC1_bit BANKMASK(B4DLC), 1 extern volatile __bit B4DLC2 @ (((unsigned) &B4DLC)*8) + 2; #define B4DLC2_bit BANKMASK(B4DLC), 2 extern volatile __bit B4DLC3 @ (((unsigned) &B4DLC)*8) + 3; #define B4DLC3_bit BANKMASK(B4DLC), 3 extern volatile __bit B4EID0 @ (((unsigned) &B4EIDL)*8) + 0; #define B4EID0_bit BANKMASK(B4EIDL), 0 extern volatile __bit B4EID1 @ (((unsigned) &B4EIDL)*8) + 1; #define B4EID1_bit BANKMASK(B4EIDL), 1 extern volatile __bit B4EID10 @ (((unsigned) &B4EIDH)*8) + 2; #define B4EID10_bit BANKMASK(B4EIDH), 2 extern volatile __bit B4EID11 @ (((unsigned) &B4EIDH)*8) + 3; #define B4EID11_bit BANKMASK(B4EIDH), 3 extern volatile __bit B4EID12 @ (((unsigned) &B4EIDH)*8) + 4; #define B4EID12_bit BANKMASK(B4EIDH), 4 extern volatile __bit B4EID13 @ (((unsigned) &B4EIDH)*8) + 5; #define B4EID13_bit BANKMASK(B4EIDH), 5 extern volatile __bit B4EID14 @ (((unsigned) &B4EIDH)*8) + 6; #define B4EID14_bit BANKMASK(B4EIDH), 6 extern volatile __bit B4EID15 @ (((unsigned) &B4EIDH)*8) + 7; #define B4EID15_bit BANKMASK(B4EIDH), 7 extern volatile __bit B4EID16 @ (((unsigned) &B4SIDL)*8) + 0; #define B4EID16_bit BANKMASK(B4SIDL), 0 extern volatile __bit B4EID17 @ (((unsigned) &B4SIDL)*8) + 1; #define B4EID17_bit BANKMASK(B4SIDL), 1 extern volatile __bit B4EID2 @ (((unsigned) &B4EIDL)*8) + 2; #define B4EID2_bit BANKMASK(B4EIDL), 2 extern volatile __bit B4EID3 @ (((unsigned) &B4EIDL)*8) + 3; #define B4EID3_bit BANKMASK(B4EIDL), 3 extern volatile __bit B4EID4 @ (((unsigned) &B4EIDL)*8) + 4; #define B4EID4_bit BANKMASK(B4EIDL), 4 extern volatile __bit B4EID5 @ (((unsigned) &B4EIDL)*8) + 5; #define B4EID5_bit BANKMASK(B4EIDL), 5 extern volatile __bit B4EID6 @ (((unsigned) &B4EIDL)*8) + 6; #define B4EID6_bit BANKMASK(B4EIDL), 6 extern volatile __bit B4EID7 @ (((unsigned) &B4EIDL)*8) + 7; #define B4EID7_bit BANKMASK(B4EIDL), 7 extern volatile __bit B4EID8 @ (((unsigned) &B4EIDH)*8) + 0; #define B4EID8_bit BANKMASK(B4EIDH), 0 extern volatile __bit B4EID9 @ (((unsigned) &B4EIDH)*8) + 1; #define B4EID9_bit BANKMASK(B4EIDH), 1 extern volatile __bit B4EXID @ (((unsigned) &B4SIDL)*8) + 3; #define B4EXID_bit BANKMASK(B4SIDL), 3 extern volatile __bit B4EXIDE @ (((unsigned) &B4SIDL)*8) + 3; #define B4EXIDE_bit BANKMASK(B4SIDL), 3 extern volatile __bit B4FILHIT0 @ (((unsigned) &B4CON)*8) + 0; #define B4FILHIT0_bit BANKMASK(B4CON), 0 extern volatile __bit B4FILHIT1 @ (((unsigned) &B4CON)*8) + 1; #define B4FILHIT1_bit BANKMASK(B4CON), 1 extern volatile __bit B4FILHIT2 @ (((unsigned) &B4CON)*8) + 2; #define B4FILHIT2_bit BANKMASK(B4CON), 2 extern volatile __bit B4FILHIT3 @ (((unsigned) &B4CON)*8) + 3; #define B4FILHIT3_bit BANKMASK(B4CON), 3 extern volatile __bit B4FILHIT4 @ (((unsigned) &B4CON)*8) + 4; #define B4FILHIT4_bit BANKMASK(B4CON), 4 extern volatile __bit B4IE @ (((unsigned) &BIE0)*8) + 6; #define B4IE_bit BANKMASK(BIE0), 6 extern volatile __bit B4RB0 @ (((unsigned) &B4DLC)*8) + 4; #define B4RB0_bit BANKMASK(B4DLC), 4 extern volatile __bit B4RB1 @ (((unsigned) &B4DLC)*8) + 5; #define B4RB1_bit BANKMASK(B4DLC), 5 extern volatile __bit B4RTREN @ (((unsigned) &B4CON)*8) + 2; #define B4RTREN_bit BANKMASK(B4CON), 2 extern volatile __bit B4RTRRO @ (((unsigned) &B4CON)*8) + 5; #define B4RTRRO_bit BANKMASK(B4CON), 5 extern volatile __bit B4RXFUL @ (((unsigned) &B4CON)*8) + 7; #define B4RXFUL_bit BANKMASK(B4CON), 7 extern volatile __bit B4RXM1 @ (((unsigned) &B4CON)*8) + 6; #define B4RXM1_bit BANKMASK(B4CON), 6 extern volatile __bit B4RXRTR @ (((unsigned) &B4DLC)*8) + 6; #define B4RXRTR_bit BANKMASK(B4DLC), 6 extern volatile __bit B4SID0 @ (((unsigned) &B4SIDL)*8) + 5; #define B4SID0_bit BANKMASK(B4SIDL), 5 extern volatile __bit B4SID1 @ (((unsigned) &B4SIDL)*8) + 6; #define B4SID1_bit BANKMASK(B4SIDL), 6 extern volatile __bit B4SID10 @ (((unsigned) &B4SIDH)*8) + 7; #define B4SID10_bit BANKMASK(B4SIDH), 7 extern volatile __bit B4SID2 @ (((unsigned) &B4SIDL)*8) + 7; #define B4SID2_bit BANKMASK(B4SIDL), 7 extern volatile __bit B4SID3 @ (((unsigned) &B4SIDH)*8) + 0; #define B4SID3_bit BANKMASK(B4SIDH), 0 extern volatile __bit B4SID4 @ (((unsigned) &B4SIDH)*8) + 1; #define B4SID4_bit BANKMASK(B4SIDH), 1 extern volatile __bit B4SID5 @ (((unsigned) &B4SIDH)*8) + 2; #define B4SID5_bit BANKMASK(B4SIDH), 2 extern volatile __bit B4SID6 @ (((unsigned) &B4SIDH)*8) + 3; #define B4SID6_bit BANKMASK(B4SIDH), 3 extern volatile __bit B4SID7 @ (((unsigned) &B4SIDH)*8) + 4; #define B4SID7_bit BANKMASK(B4SIDH), 4 extern volatile __bit B4SID8 @ (((unsigned) &B4SIDH)*8) + 5; #define B4SID8_bit BANKMASK(B4SIDH), 5 extern volatile __bit B4SID9 @ (((unsigned) &B4SIDH)*8) + 6; #define B4SID9_bit BANKMASK(B4SIDH), 6 extern volatile __bit B4SRR @ (((unsigned) &B4SIDL)*8) + 4; #define B4SRR_bit BANKMASK(B4SIDL), 4 extern volatile __bit B4TXABT @ (((unsigned) &B4CON)*8) + 6; #define B4TXABT_bit BANKMASK(B4CON), 6 extern volatile __bit B4TXB3IF @ (((unsigned) &B4CON)*8) + 7; #define B4TXB3IF_bit BANKMASK(B4CON), 7 extern volatile __bit B4TXEN @ (((unsigned) &BSEL0)*8) + 6; #define B4TXEN_bit BANKMASK(BSEL0), 6 extern volatile __bit B4TXERR @ (((unsigned) &B4CON)*8) + 4; #define B4TXERR_bit BANKMASK(B4CON), 4 extern volatile __bit B4TXLARB @ (((unsigned) &B4CON)*8) + 5; #define B4TXLARB_bit BANKMASK(B4CON), 5 extern volatile __bit B4TXPRI0 @ (((unsigned) &B4CON)*8) + 0; #define B4TXPRI0_bit BANKMASK(B4CON), 0 extern volatile __bit B4TXPRI1 @ (((unsigned) &B4CON)*8) + 1; #define B4TXPRI1_bit BANKMASK(B4CON), 1 extern volatile __bit B4TXREQ @ (((unsigned) &B4CON)*8) + 3; #define B4TXREQ_bit BANKMASK(B4CON), 3 extern volatile __bit B5D00 @ (((unsigned) &B5D0)*8) + 0; #define B5D00_bit BANKMASK(B5D0), 0 extern volatile __bit B5D01 @ (((unsigned) &B5D0)*8) + 1; #define B5D01_bit BANKMASK(B5D0), 1 extern volatile __bit B5D02 @ (((unsigned) &B5D0)*8) + 2; #define B5D02_bit BANKMASK(B5D0), 2 extern volatile __bit B5D03 @ (((unsigned) &B5D0)*8) + 3; #define B5D03_bit BANKMASK(B5D0), 3 extern volatile __bit B5D04 @ (((unsigned) &B5D0)*8) + 4; #define B5D04_bit BANKMASK(B5D0), 4 extern volatile __bit B5D05 @ (((unsigned) &B5D0)*8) + 5; #define B5D05_bit BANKMASK(B5D0), 5 extern volatile __bit B5D06 @ (((unsigned) &B5D0)*8) + 6; #define B5D06_bit BANKMASK(B5D0), 6 extern volatile __bit B5D07 @ (((unsigned) &B5D0)*8) + 7; #define B5D07_bit BANKMASK(B5D0), 7 extern volatile __bit B5D10 @ (((unsigned) &B5D1)*8) + 0; #define B5D10_bit BANKMASK(B5D1), 0 extern volatile __bit B5D11 @ (((unsigned) &B5D1)*8) + 1; #define B5D11_bit BANKMASK(B5D1), 1 extern volatile __bit B5D12 @ (((unsigned) &B5D1)*8) + 2; #define B5D12_bit BANKMASK(B5D1), 2 extern volatile __bit B5D13 @ (((unsigned) &B5D1)*8) + 3; #define B5D13_bit BANKMASK(B5D1), 3 extern volatile __bit B5D14 @ (((unsigned) &B5D1)*8) + 4; #define B5D14_bit BANKMASK(B5D1), 4 extern volatile __bit B5D15 @ (((unsigned) &B5D1)*8) + 5; #define B5D15_bit BANKMASK(B5D1), 5 extern volatile __bit B5D16 @ (((unsigned) &B5D1)*8) + 6; #define B5D16_bit BANKMASK(B5D1), 6 extern volatile __bit B5D17 @ (((unsigned) &B5D1)*8) + 7; #define B5D17_bit BANKMASK(B5D1), 7 extern volatile __bit B5D20 @ (((unsigned) &B5D2)*8) + 0; #define B5D20_bit BANKMASK(B5D2), 0 extern volatile __bit B5D21 @ (((unsigned) &B5D2)*8) + 1; #define B5D21_bit BANKMASK(B5D2), 1 extern volatile __bit B5D22 @ (((unsigned) &B5D2)*8) + 2; #define B5D22_bit BANKMASK(B5D2), 2 extern volatile __bit B5D23 @ (((unsigned) &B5D2)*8) + 3; #define B5D23_bit BANKMASK(B5D2), 3 extern volatile __bit B5D24 @ (((unsigned) &B5D2)*8) + 4; #define B5D24_bit BANKMASK(B5D2), 4 extern volatile __bit B5D25 @ (((unsigned) &B5D2)*8) + 5; #define B5D25_bit BANKMASK(B5D2), 5 extern volatile __bit B5D26 @ (((unsigned) &B5D2)*8) + 6; #define B5D26_bit BANKMASK(B5D2), 6 extern volatile __bit B5D27 @ (((unsigned) &B5D2)*8) + 7; #define B5D27_bit BANKMASK(B5D2), 7 extern volatile __bit B5D30 @ (((unsigned) &B5D3)*8) + 0; #define B5D30_bit BANKMASK(B5D3), 0 extern volatile __bit B5D31 @ (((unsigned) &B5D3)*8) + 1; #define B5D31_bit BANKMASK(B5D3), 1 extern volatile __bit B5D32 @ (((unsigned) &B5D3)*8) + 2; #define B5D32_bit BANKMASK(B5D3), 2 extern volatile __bit B5D33 @ (((unsigned) &B5D3)*8) + 3; #define B5D33_bit BANKMASK(B5D3), 3 extern volatile __bit B5D34 @ (((unsigned) &B5D3)*8) + 4; #define B5D34_bit BANKMASK(B5D3), 4 extern volatile __bit B5D35 @ (((unsigned) &B5D3)*8) + 5; #define B5D35_bit BANKMASK(B5D3), 5 extern volatile __bit B5D36 @ (((unsigned) &B5D3)*8) + 6; #define B5D36_bit BANKMASK(B5D3), 6 extern volatile __bit B5D37 @ (((unsigned) &B5D3)*8) + 7; #define B5D37_bit BANKMASK(B5D3), 7 extern volatile __bit B5D40 @ (((unsigned) &B5D4)*8) + 0; #define B5D40_bit BANKMASK(B5D4), 0 extern volatile __bit B5D41 @ (((unsigned) &B5D4)*8) + 1; #define B5D41_bit BANKMASK(B5D4), 1 extern volatile __bit B5D42 @ (((unsigned) &B5D4)*8) + 2; #define B5D42_bit BANKMASK(B5D4), 2 extern volatile __bit B5D43 @ (((unsigned) &B5D4)*8) + 3; #define B5D43_bit BANKMASK(B5D4), 3 extern volatile __bit B5D44 @ (((unsigned) &B5D4)*8) + 4; #define B5D44_bit BANKMASK(B5D4), 4 extern volatile __bit B5D45 @ (((unsigned) &B5D4)*8) + 5; #define B5D45_bit BANKMASK(B5D4), 5 extern volatile __bit B5D46 @ (((unsigned) &B5D4)*8) + 6; #define B5D46_bit BANKMASK(B5D4), 6 extern volatile __bit B5D47 @ (((unsigned) &B5D4)*8) + 7; #define B5D47_bit BANKMASK(B5D4), 7 extern volatile __bit B5D50 @ (((unsigned) &B5D5)*8) + 0; #define B5D50_bit BANKMASK(B5D5), 0 extern volatile __bit B5D51 @ (((unsigned) &B5D5)*8) + 1; #define B5D51_bit BANKMASK(B5D5), 1 extern volatile __bit B5D52 @ (((unsigned) &B5D5)*8) + 2; #define B5D52_bit BANKMASK(B5D5), 2 extern volatile __bit B5D53 @ (((unsigned) &B5D5)*8) + 3; #define B5D53_bit BANKMASK(B5D5), 3 extern volatile __bit B5D54 @ (((unsigned) &B5D5)*8) + 4; #define B5D54_bit BANKMASK(B5D5), 4 extern volatile __bit B5D55 @ (((unsigned) &B5D5)*8) + 5; #define B5D55_bit BANKMASK(B5D5), 5 extern volatile __bit B5D56 @ (((unsigned) &B5D5)*8) + 6; #define B5D56_bit BANKMASK(B5D5), 6 extern volatile __bit B5D57 @ (((unsigned) &B5D5)*8) + 7; #define B5D57_bit BANKMASK(B5D5), 7 extern volatile __bit B5D60 @ (((unsigned) &B5D6)*8) + 0; #define B5D60_bit BANKMASK(B5D6), 0 extern volatile __bit B5D61 @ (((unsigned) &B5D6)*8) + 1; #define B5D61_bit BANKMASK(B5D6), 1 extern volatile __bit B5D62 @ (((unsigned) &B5D6)*8) + 2; #define B5D62_bit BANKMASK(B5D6), 2 extern volatile __bit B5D63 @ (((unsigned) &B5D6)*8) + 3; #define B5D63_bit BANKMASK(B5D6), 3 extern volatile __bit B5D64 @ (((unsigned) &B5D6)*8) + 4; #define B5D64_bit BANKMASK(B5D6), 4 extern volatile __bit B5D65 @ (((unsigned) &B5D6)*8) + 5; #define B5D65_bit BANKMASK(B5D6), 5 extern volatile __bit B5D66 @ (((unsigned) &B5D6)*8) + 6; #define B5D66_bit BANKMASK(B5D6), 6 extern volatile __bit B5D67 @ (((unsigned) &B5D6)*8) + 7; #define B5D67_bit BANKMASK(B5D6), 7 extern volatile __bit B5D70 @ (((unsigned) &B5D7)*8) + 0; #define B5D70_bit BANKMASK(B5D7), 0 extern volatile __bit B5D71 @ (((unsigned) &B5D7)*8) + 1; #define B5D71_bit BANKMASK(B5D7), 1 extern volatile __bit B5D72 @ (((unsigned) &B5D7)*8) + 2; #define B5D72_bit BANKMASK(B5D7), 2 extern volatile __bit B5D73 @ (((unsigned) &B5D7)*8) + 3; #define B5D73_bit BANKMASK(B5D7), 3 extern volatile __bit B5D74 @ (((unsigned) &B5D7)*8) + 4; #define B5D74_bit BANKMASK(B5D7), 4 extern volatile __bit B5D75 @ (((unsigned) &B5D7)*8) + 5; #define B5D75_bit BANKMASK(B5D7), 5 extern volatile __bit B5D76 @ (((unsigned) &B5D7)*8) + 6; #define B5D76_bit BANKMASK(B5D7), 6 extern volatile __bit B5D77 @ (((unsigned) &B5D7)*8) + 7; #define B5D77_bit BANKMASK(B5D7), 7 extern volatile __bit B5DLC0 @ (((unsigned) &B5DLC)*8) + 0; #define B5DLC0_bit BANKMASK(B5DLC), 0 extern volatile __bit B5DLC1 @ (((unsigned) &B5DLC)*8) + 1; #define B5DLC1_bit BANKMASK(B5DLC), 1 extern volatile __bit B5DLC2 @ (((unsigned) &B5DLC)*8) + 2; #define B5DLC2_bit BANKMASK(B5DLC), 2 extern volatile __bit B5DLC3 @ (((unsigned) &B5DLC)*8) + 3; #define B5DLC3_bit BANKMASK(B5DLC), 3 extern volatile __bit B5EID0 @ (((unsigned) &B5EIDL)*8) + 0; #define B5EID0_bit BANKMASK(B5EIDL), 0 extern volatile __bit B5EID1 @ (((unsigned) &B5EIDL)*8) + 1; #define B5EID1_bit BANKMASK(B5EIDL), 1 extern volatile __bit B5EID10 @ (((unsigned) &B5EIDH)*8) + 2; #define B5EID10_bit BANKMASK(B5EIDH), 2 extern volatile __bit B5EID11 @ (((unsigned) &B5EIDH)*8) + 3; #define B5EID11_bit BANKMASK(B5EIDH), 3 extern volatile __bit B5EID12 @ (((unsigned) &B5EIDH)*8) + 4; #define B5EID12_bit BANKMASK(B5EIDH), 4 extern volatile __bit B5EID13 @ (((unsigned) &B5EIDH)*8) + 5; #define B5EID13_bit BANKMASK(B5EIDH), 5 extern volatile __bit B5EID14 @ (((unsigned) &B5EIDH)*8) + 6; #define B5EID14_bit BANKMASK(B5EIDH), 6 extern volatile __bit B5EID15 @ (((unsigned) &B5EIDH)*8) + 7; #define B5EID15_bit BANKMASK(B5EIDH), 7 extern volatile __bit B5EID16 @ (((unsigned) &B5SIDL)*8) + 0; #define B5EID16_bit BANKMASK(B5SIDL), 0 extern volatile __bit B5EID17 @ (((unsigned) &B5SIDL)*8) + 1; #define B5EID17_bit BANKMASK(B5SIDL), 1 extern volatile __bit B5EID2 @ (((unsigned) &B5EIDL)*8) + 2; #define B5EID2_bit BANKMASK(B5EIDL), 2 extern volatile __bit B5EID3 @ (((unsigned) &B5EIDL)*8) + 3; #define B5EID3_bit BANKMASK(B5EIDL), 3 extern volatile __bit B5EID4 @ (((unsigned) &B5EIDL)*8) + 4; #define B5EID4_bit BANKMASK(B5EIDL), 4 extern volatile __bit B5EID5 @ (((unsigned) &B5EIDL)*8) + 5; #define B5EID5_bit BANKMASK(B5EIDL), 5 extern volatile __bit B5EID6 @ (((unsigned) &B5EIDL)*8) + 6; #define B5EID6_bit BANKMASK(B5EIDL), 6 extern volatile __bit B5EID7 @ (((unsigned) &B5EIDL)*8) + 7; #define B5EID7_bit BANKMASK(B5EIDL), 7 extern volatile __bit B5EID8 @ (((unsigned) &B5EIDH)*8) + 0; #define B5EID8_bit BANKMASK(B5EIDH), 0 extern volatile __bit B5EID9 @ (((unsigned) &B5EIDH)*8) + 1; #define B5EID9_bit BANKMASK(B5EIDH), 1 extern volatile __bit B5EXID @ (((unsigned) &B5SIDL)*8) + 3; #define B5EXID_bit BANKMASK(B5SIDL), 3 extern volatile __bit B5EXIDE @ (((unsigned) &B5SIDL)*8) + 3; #define B5EXIDE_bit BANKMASK(B5SIDL), 3 extern volatile __bit B5FILHIT0 @ (((unsigned) &B5CON)*8) + 0; #define B5FILHIT0_bit BANKMASK(B5CON), 0 extern volatile __bit B5FILHIT1 @ (((unsigned) &B5CON)*8) + 1; #define B5FILHIT1_bit BANKMASK(B5CON), 1 extern volatile __bit B5FILHIT2 @ (((unsigned) &B5CON)*8) + 2; #define B5FILHIT2_bit BANKMASK(B5CON), 2 extern volatile __bit B5FILHIT3 @ (((unsigned) &B5CON)*8) + 3; #define B5FILHIT3_bit BANKMASK(B5CON), 3 extern volatile __bit B5FILHIT4 @ (((unsigned) &B5CON)*8) + 4; #define B5FILHIT4_bit BANKMASK(B5CON), 4 extern volatile __bit B5IE @ (((unsigned) &BIE0)*8) + 7; #define B5IE_bit BANKMASK(BIE0), 7 extern volatile __bit B5RB0 @ (((unsigned) &B5DLC)*8) + 4; #define B5RB0_bit BANKMASK(B5DLC), 4 extern volatile __bit B5RB1 @ (((unsigned) &B5DLC)*8) + 5; #define B5RB1_bit BANKMASK(B5DLC), 5 extern volatile __bit B5RTREN @ (((unsigned) &B5CON)*8) + 2; #define B5RTREN_bit BANKMASK(B5CON), 2 extern volatile __bit B5RTRRO @ (((unsigned) &B5CON)*8) + 5; #define B5RTRRO_bit BANKMASK(B5CON), 5 extern volatile __bit B5RXFUL @ (((unsigned) &B5CON)*8) + 7; #define B5RXFUL_bit BANKMASK(B5CON), 7 extern volatile __bit B5RXM1 @ (((unsigned) &B5CON)*8) + 6; #define B5RXM1_bit BANKMASK(B5CON), 6 extern volatile __bit B5RXRTR @ (((unsigned) &B5DLC)*8) + 6; #define B5RXRTR_bit BANKMASK(B5DLC), 6 extern volatile __bit B5SID0 @ (((unsigned) &B5SIDL)*8) + 5; #define B5SID0_bit BANKMASK(B5SIDL), 5 extern volatile __bit B5SID1 @ (((unsigned) &B5SIDL)*8) + 6; #define B5SID1_bit BANKMASK(B5SIDL), 6 extern volatile __bit B5SID10 @ (((unsigned) &B5SIDH)*8) + 7; #define B5SID10_bit BANKMASK(B5SIDH), 7 extern volatile __bit B5SID2 @ (((unsigned) &B5SIDL)*8) + 7; #define B5SID2_bit BANKMASK(B5SIDL), 7 extern volatile __bit B5SID3 @ (((unsigned) &B5SIDH)*8) + 0; #define B5SID3_bit BANKMASK(B5SIDH), 0 extern volatile __bit B5SID4 @ (((unsigned) &B5SIDH)*8) + 1; #define B5SID4_bit BANKMASK(B5SIDH), 1 extern volatile __bit B5SID5 @ (((unsigned) &B5SIDH)*8) + 2; #define B5SID5_bit BANKMASK(B5SIDH), 2 extern volatile __bit B5SID6 @ (((unsigned) &B5SIDH)*8) + 3; #define B5SID6_bit BANKMASK(B5SIDH), 3 extern volatile __bit B5SID7 @ (((unsigned) &B5SIDH)*8) + 4; #define B5SID7_bit BANKMASK(B5SIDH), 4 extern volatile __bit B5SID8 @ (((unsigned) &B5SIDH)*8) + 5; #define B5SID8_bit BANKMASK(B5SIDH), 5 extern volatile __bit B5SID9 @ (((unsigned) &B5SIDH)*8) + 6; #define B5SID9_bit BANKMASK(B5SIDH), 6 extern volatile __bit B5SRR @ (((unsigned) &B5SIDL)*8) + 4; #define B5SRR_bit BANKMASK(B5SIDL), 4 extern volatile __bit B5TXABT @ (((unsigned) &B5CON)*8) + 6; #define B5TXABT_bit BANKMASK(B5CON), 6 extern volatile __bit B5TXBIF @ (((unsigned) &B5CON)*8) + 7; #define B5TXBIF_bit BANKMASK(B5CON), 7 extern volatile __bit B5TXEN @ (((unsigned) &BSEL0)*8) + 7; #define B5TXEN_bit BANKMASK(BSEL0), 7 extern volatile __bit B5TXERR @ (((unsigned) &B5CON)*8) + 4; #define B5TXERR_bit BANKMASK(B5CON), 4 extern volatile __bit B5TXLARB @ (((unsigned) &B5CON)*8) + 5; #define B5TXLARB_bit BANKMASK(B5CON), 5 extern volatile __bit B5TXPRI0 @ (((unsigned) &B5CON)*8) + 0; #define B5TXPRI0_bit BANKMASK(B5CON), 0 extern volatile __bit B5TXPRI1 @ (((unsigned) &B5CON)*8) + 1; #define B5TXPRI1_bit BANKMASK(B5CON), 1 extern volatile __bit B5TXREQ @ (((unsigned) &B5CON)*8) + 3; #define B5TXREQ_bit BANKMASK(B5CON), 3 extern volatile __bit BCLIE @ (((unsigned) &PIE2)*8) + 3; #define BCLIE_bit BANKMASK(PIE2), 3 extern volatile __bit BCLIF @ (((unsigned) &PIR2)*8) + 3; #define BCLIF_bit BANKMASK(PIR2), 3 extern volatile __bit BCLIP @ (((unsigned) &IPR2)*8) + 3; #define BCLIP_bit BANKMASK(IPR2), 3 extern volatile __bit BF @ (((unsigned) &SSPSTAT)*8) + 0; #define BF_bit BANKMASK(SSPSTAT), 0 extern volatile __bit BGVST @ (((unsigned) &HLVDCON)*8) + 6; #define BGVST_bit BANKMASK(HLVDCON), 6 extern volatile __bit BOR @ (((unsigned) &RCON)*8) + 0; #define BOR_bit BANKMASK(RCON), 0 extern volatile __bit BRG161 @ (((unsigned) &BAUDCON1)*8) + 3; #define BRG161_bit BANKMASK(BAUDCON1), 3 extern volatile __bit BRG162 @ (((unsigned) &BAUDCON2)*8) + 3; #define BRG162_bit BANKMASK(BAUDCON2), 3 extern volatile __bit BRGH1 @ (((unsigned) &TXSTA1)*8) + 2; #define BRGH1_bit BANKMASK(TXSTA1), 2 extern volatile __bit BRGH2 @ (((unsigned) &TXSTA2)*8) + 2; #define BRGH2_bit BANKMASK(TXSTA2), 2 extern volatile __bit BRP0 @ (((unsigned) &BRGCON1)*8) + 0; #define BRP0_bit BANKMASK(BRGCON1), 0 extern volatile __bit BRP1 @ (((unsigned) &BRGCON1)*8) + 1; #define BRP1_bit BANKMASK(BRGCON1), 1 extern volatile __bit BRP2 @ (((unsigned) &BRGCON1)*8) + 2; #define BRP2_bit BANKMASK(BRGCON1), 2 extern volatile __bit BRP3 @ (((unsigned) &BRGCON1)*8) + 3; #define BRP3_bit BANKMASK(BRGCON1), 3 extern volatile __bit BRP4 @ (((unsigned) &BRGCON1)*8) + 4; #define BRP4_bit BANKMASK(BRGCON1), 4 extern volatile __bit BRP5 @ (((unsigned) &BRGCON1)*8) + 5; #define BRP5_bit BANKMASK(BRGCON1), 5 extern volatile __bit C1CH0 @ (((unsigned) &CM1CON)*8) + 0; #define C1CH0_bit BANKMASK(CM1CON), 0 extern volatile __bit C1CH1 @ (((unsigned) &CM1CON)*8) + 1; #define C1CH1_bit BANKMASK(CM1CON), 1 extern volatile __bit C1TSEL @ (((unsigned) &CCPTMRS)*8) + 0; #define C1TSEL_bit BANKMASK(CCPTMRS), 0 extern volatile __bit C2OUT @ (((unsigned) &CMSTAT)*8) + 6; #define C2OUT_bit BANKMASK(CMSTAT), 6 extern volatile __bit C2TSEL @ (((unsigned) &CCPTMRS)*8) + 1; #define C2TSEL_bit BANKMASK(CCPTMRS), 1 extern volatile __bit C3OUT @ (((unsigned) &CMSTAT)*8) + 7; #define C3OUT_bit BANKMASK(CMSTAT), 7 extern volatile __bit C3TSEL @ (((unsigned) &CCPTMRS)*8) + 2; #define C3TSEL_bit BANKMASK(CCPTMRS), 2 extern volatile __bit C4TSEL @ (((unsigned) &CCPTMRS)*8) + 3; #define C4TSEL_bit BANKMASK(CCPTMRS), 3 extern volatile __bit C5TSEL @ (((unsigned) &CCPTMRS)*8) + 4; #define C5TSEL_bit BANKMASK(CCPTMRS), 4 extern volatile __bit CANCAP @ (((unsigned) &CIOCON)*8) + 4; #define CANCAP_bit BANKMASK(CIOCON), 4 extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0; #define CARRY_bit BANKMASK(STATUS), 0 extern volatile __bit CCH01 @ (((unsigned) &CM1CON)*8) + 0; #define CCH01_bit BANKMASK(CM1CON), 0 extern volatile __bit CCH02 @ (((unsigned) &CM2CON)*8) + 0; #define CCH02_bit BANKMASK(CM2CON), 0 extern volatile __bit CCH05 @ (((unsigned) &IPR5)*8) + 0; #define CCH05_bit BANKMASK(IPR5), 0 extern volatile __bit CCH11 @ (((unsigned) &CM1CON)*8) + 1; #define CCH11_bit BANKMASK(CM1CON), 1 extern volatile __bit CCH12 @ (((unsigned) &CM2CON)*8) + 1; #define CCH12_bit BANKMASK(CM2CON), 1 extern volatile __bit CCH15 @ (((unsigned) &IPR5)*8) + 1; #define CCH15_bit BANKMASK(IPR5), 1 extern volatile __bit CCIP3IP @ (((unsigned) &IPR4)*8) + 0; #define CCIP3IP_bit BANKMASK(IPR4), 0 extern volatile __bit CCP1IE @ (((unsigned) &PIE3)*8) + 1; #define CCP1IE_bit BANKMASK(PIE3), 1 extern volatile __bit CCP1IF @ (((unsigned) &PIR3)*8) + 1; #define CCP1IF_bit BANKMASK(PIR3), 1 extern volatile __bit CCP1IP @ (((unsigned) &IPR3)*8) + 1; #define CCP1IP_bit BANKMASK(IPR3), 1 extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0; #define CCP1M0_bit BANKMASK(CCP1CON), 0 extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1; #define CCP1M1_bit BANKMASK(CCP1CON), 1 extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2; #define CCP1M2_bit BANKMASK(CCP1CON), 2 extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3; #define CCP1M3_bit BANKMASK(CCP1CON), 3 extern volatile __bit CCP1MD @ (((unsigned) &PMD0)*8) + 3; #define CCP1MD_bit BANKMASK(PMD0), 3 extern volatile __bit CCP1OD @ (((unsigned) &ODCON)*8) + 2; #define CCP1OD_bit BANKMASK(ODCON), 2 extern volatile __bit CCP1X @ (((unsigned) &CCP1CON)*8) + 5; #define CCP1X_bit BANKMASK(CCP1CON), 5 extern volatile __bit CCP1Y @ (((unsigned) &CCP1CON)*8) + 4; #define CCP1Y_bit BANKMASK(CCP1CON), 4 extern volatile __bit CCP2 @ (((unsigned) &PORTC)*8) + 1; #define CCP2_bit BANKMASK(PORTC), 1 extern volatile __bit CCP2IE @ (((unsigned) &PIE3)*8) + 2; #define CCP2IE_bit BANKMASK(PIE3), 2 extern volatile __bit CCP2IF @ (((unsigned) &PIR3)*8) + 2; #define CCP2IF_bit BANKMASK(PIR3), 2 extern volatile __bit CCP2IP @ (((unsigned) &IPR3)*8) + 2; #define CCP2IP_bit BANKMASK(IPR3), 2 extern volatile __bit CCP2M0 @ (((unsigned) &CCP2CON)*8) + 0; #define CCP2M0_bit BANKMASK(CCP2CON), 0 extern volatile __bit CCP2M1 @ (((unsigned) &CCP2CON)*8) + 1; #define CCP2M1_bit BANKMASK(CCP2CON), 1 extern volatile __bit CCP2M2 @ (((unsigned) &CCP2CON)*8) + 2; #define CCP2M2_bit BANKMASK(CCP2CON), 2 extern volatile __bit CCP2M3 @ (((unsigned) &CCP2CON)*8) + 3; #define CCP2M3_bit BANKMASK(CCP2CON), 3 extern volatile __bit CCP2MD @ (((unsigned) &PMD0)*8) + 4; #define CCP2MD_bit BANKMASK(PMD0), 4 extern volatile __bit CCP2OD @ (((unsigned) &ODCON)*8) + 3; #define CCP2OD_bit BANKMASK(ODCON), 3 extern volatile __bit CCP2X @ (((unsigned) &CCP2CON)*8) + 5; #define CCP2X_bit BANKMASK(CCP2CON), 5 extern volatile __bit CCP2Y @ (((unsigned) &CCP2CON)*8) + 4; #define CCP2Y_bit BANKMASK(CCP2CON), 4 extern volatile __bit CCP2_PA2 @ (((unsigned) &PORTB)*8) + 3; #define CCP2_PA2_bit BANKMASK(PORTB), 3 extern volatile __bit CCP3IE @ (((unsigned) &PIE4)*8) + 0; #define CCP3IE_bit BANKMASK(PIE4), 0 extern volatile __bit CCP3IF @ (((unsigned) &PIR4)*8) + 0; #define CCP3IF_bit BANKMASK(PIR4), 0 extern volatile __bit CCP3IP @ (((unsigned) &IPR4)*8) + 0; #define CCP3IP_bit BANKMASK(IPR4), 0 extern volatile __bit CCP3M0 @ (((unsigned) &CCP3CON)*8) + 0; #define CCP3M0_bit BANKMASK(CCP3CON), 0 extern volatile __bit CCP3M1 @ (((unsigned) &CCP3CON)*8) + 1; #define CCP3M1_bit BANKMASK(CCP3CON), 1 extern volatile __bit CCP3M2 @ (((unsigned) &CCP3CON)*8) + 2; #define CCP3M2_bit BANKMASK(CCP3CON), 2 extern volatile __bit CCP3M3 @ (((unsigned) &CCP3CON)*8) + 3; #define CCP3M3_bit BANKMASK(CCP3CON), 3 extern volatile __bit CCP3MD @ (((unsigned) &PMD0)*8) + 5; #define CCP3MD_bit BANKMASK(PMD0), 5 extern volatile __bit CCP3OD @ (((unsigned) &ODCON)*8) + 4; #define CCP3OD_bit BANKMASK(ODCON), 4 extern volatile __bit CCP3X @ (((unsigned) &CCP3CON)*8) + 5; #define CCP3X_bit BANKMASK(CCP3CON), 5 extern volatile __bit CCP3Y @ (((unsigned) &CCP3CON)*8) + 4; #define CCP3Y_bit BANKMASK(CCP3CON), 4 extern volatile __bit CCP4IE @ (((unsigned) &PIE4)*8) + 1; #define CCP4IE_bit BANKMASK(PIE4), 1 extern volatile __bit CCP4IF @ (((unsigned) &PIR4)*8) + 1; #define CCP4IF_bit BANKMASK(PIR4), 1 extern volatile __bit CCP4IP @ (((unsigned) &IPR4)*8) + 1; #define CCP4IP_bit BANKMASK(IPR4), 1 extern volatile __bit CCP4M0 @ (((unsigned) &CCP4CON)*8) + 0; #define CCP4M0_bit BANKMASK(CCP4CON), 0 extern volatile __bit CCP4M1 @ (((unsigned) &CCP4CON)*8) + 1; #define CCP4M1_bit BANKMASK(CCP4CON), 1 extern volatile __bit CCP4M2 @ (((unsigned) &CCP4CON)*8) + 2; #define CCP4M2_bit BANKMASK(CCP4CON), 2 extern volatile __bit CCP4M3 @ (((unsigned) &CCP4CON)*8) + 3; #define CCP4M3_bit BANKMASK(CCP4CON), 3 extern volatile __bit CCP4MD @ (((unsigned) &PMD0)*8) + 6; #define CCP4MD_bit BANKMASK(PMD0), 6 extern volatile __bit CCP4OD @ (((unsigned) &ODCON)*8) + 5; #define CCP4OD_bit BANKMASK(ODCON), 5 extern volatile __bit CCP4X @ (((unsigned) &CCP4CON)*8) + 5; #define CCP4X_bit BANKMASK(CCP4CON), 5 extern volatile __bit CCP4Y @ (((unsigned) &CCP4CON)*8) + 4; #define CCP4Y_bit BANKMASK(CCP4CON), 4 extern volatile __bit CCP5IE @ (((unsigned) &PIE4)*8) + 2; #define CCP5IE_bit BANKMASK(PIE4), 2 extern volatile __bit CCP5IF @ (((unsigned) &PIR4)*8) + 2; #define CCP5IF_bit BANKMASK(PIR4), 2 extern volatile __bit CCP5IP @ (((unsigned) &IPR4)*8) + 2; #define CCP5IP_bit BANKMASK(IPR4), 2 extern volatile __bit CCP5M0 @ (((unsigned) &CCP5CON)*8) + 0; #define CCP5M0_bit BANKMASK(CCP5CON), 0 extern volatile __bit CCP5M1 @ (((unsigned) &CCP5CON)*8) + 1; #define CCP5M1_bit BANKMASK(CCP5CON), 1 extern volatile __bit CCP5M2 @ (((unsigned) &CCP5CON)*8) + 2; #define CCP5M2_bit BANKMASK(CCP5CON), 2 extern volatile __bit CCP5M3 @ (((unsigned) &CCP5CON)*8) + 3; #define CCP5M3_bit BANKMASK(CCP5CON), 3 extern volatile __bit CCP5MD @ (((unsigned) &PMD0)*8) + 7; #define CCP5MD_bit BANKMASK(PMD0), 7 extern volatile __bit CCP5OD @ (((unsigned) &ODCON)*8) + 6; #define CCP5OD_bit BANKMASK(ODCON), 6 extern volatile __bit CCP5X @ (((unsigned) &CCP5CON)*8) + 5; #define CCP5X_bit BANKMASK(CCP5CON), 5 extern volatile __bit CCP5Y @ (((unsigned) &CCP5CON)*8) + 4; #define CCP5Y_bit BANKMASK(CCP5CON), 4 extern volatile __bit CCP9E @ (((unsigned) &PORTE)*8) + 3; #define CCP9E_bit BANKMASK(PORTE), 3 extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6; #define CFGS_bit BANKMASK(EECON1), 6 extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2; #define CHS0_bit BANKMASK(ADCON0), 2 extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3; #define CHS1_bit BANKMASK(ADCON0), 3 extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4; #define CHS2_bit BANKMASK(ADCON0), 4 extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5; #define CHS3_bit BANKMASK(ADCON0), 5 extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6; #define CHS4_bit BANKMASK(ADCON0), 6 extern volatile __bit CHSN0 @ (((unsigned) &ADCON1)*8) + 0; #define CHSN0_bit BANKMASK(ADCON1), 0 extern volatile __bit CHSN1 @ (((unsigned) &ADCON1)*8) + 1; #define CHSN1_bit BANKMASK(ADCON1), 1 extern volatile __bit CHSN2 @ (((unsigned) &ADCON1)*8) + 2; #define CHSN2_bit BANKMASK(ADCON1), 2 extern volatile __bit CHSN3 @ (((unsigned) &ADCON1)*8) + 3; #define CHSN3_bit BANKMASK(ADCON1), 3 extern volatile __bit CKE @ (((unsigned) &SSPSTAT)*8) + 6; #define CKE_bit BANKMASK(SSPSTAT), 6 extern volatile __bit CKP @ (((unsigned) &SSPCON1)*8) + 4; #define CKP_bit BANKMASK(SSPCON1), 4 extern volatile __bit CKTXP @ (((unsigned) &BAUDCON1)*8) + 4; #define CKTXP_bit BANKMASK(BAUDCON1), 4 extern volatile __bit CLKSEL @ (((unsigned) &CIOCON)*8) + 0; #define CLKSEL_bit BANKMASK(CIOCON), 0 extern volatile __bit CM @ (((unsigned) &RCON)*8) + 5; #define CM_bit BANKMASK(RCON), 5 extern volatile __bit CMP1IE @ (((unsigned) &PIE4)*8) + 4; #define CMP1IE_bit BANKMASK(PIE4), 4 extern volatile __bit CMP1IF @ (((unsigned) &PIR4)*8) + 4; #define CMP1IF_bit BANKMASK(PIR4), 4 extern volatile __bit CMP1IP @ (((unsigned) &IPR4)*8) + 4; #define CMP1IP_bit BANKMASK(IPR4), 4 extern volatile __bit CMP1MD @ (((unsigned) &PMD2)*8) + 0; #define CMP1MD_bit BANKMASK(PMD2), 0 extern volatile __bit CMP1OUT @ (((unsigned) &CMSTAT)*8) + 6; #define CMP1OUT_bit BANKMASK(CMSTAT), 6 extern volatile __bit CMP2IE @ (((unsigned) &PIE4)*8) + 5; #define CMP2IE_bit BANKMASK(PIE4), 5 extern volatile __bit CMP2IF @ (((unsigned) &PIR4)*8) + 5; #define CMP2IF_bit BANKMASK(PIR4), 5 extern volatile __bit CMP2IP @ (((unsigned) &IPR4)*8) + 5; #define CMP2IP_bit BANKMASK(IPR4), 5 extern volatile __bit CMP2MD @ (((unsigned) &PMD2)*8) + 1; #define CMP2MD_bit BANKMASK(PMD2), 1 extern volatile __bit CMP2OUT @ (((unsigned) &CMSTAT)*8) + 7; #define CMP2OUT_bit BANKMASK(CMSTAT), 7 extern volatile __bit CMPL0 @ (((unsigned) &PSTR1CON)*8) + 6; #define CMPL0_bit BANKMASK(PSTR1CON), 6 extern volatile __bit CMPL1 @ (((unsigned) &PSTR1CON)*8) + 7; #define CMPL1_bit BANKMASK(PSTR1CON), 7 extern volatile __bit COE1 @ (((unsigned) &CM1CON)*8) + 6; #define COE1_bit BANKMASK(CM1CON), 6 extern volatile __bit COE2 @ (((unsigned) &CM2CON)*8) + 6; #define COE2_bit BANKMASK(CM2CON), 6 extern volatile __bit CON1 @ (((unsigned) &CM1CON)*8) + 7; #define CON1_bit BANKMASK(CM1CON), 7 extern volatile __bit CON2 @ (((unsigned) &CM2CON)*8) + 7; #define CON2_bit BANKMASK(CM2CON), 7 extern volatile __bit CPOL1 @ (((unsigned) &CM1CON)*8) + 5; #define CPOL1_bit BANKMASK(CM1CON), 5 extern volatile __bit CPOL2 @ (((unsigned) &CM2CON)*8) + 5; #define CPOL2_bit BANKMASK(CM2CON), 5 extern volatile __bit CREF1 @ (((unsigned) &CM1CON)*8) + 2; #define CREF1_bit BANKMASK(CM1CON), 2 extern volatile __bit CREF2 @ (((unsigned) &CM2CON)*8) + 2; #define CREF2_bit BANKMASK(CM2CON), 2 extern volatile __bit CREN1 @ (((unsigned) &RCSTA1)*8) + 4; #define CREN1_bit BANKMASK(RCSTA1), 4 extern volatile __bit CREN2 @ (((unsigned) &RCSTA2)*8) + 4; #define CREN2_bit BANKMASK(RCSTA2), 4 extern volatile __bit CSRC1 @ (((unsigned) &TXSTA1)*8) + 7; #define CSRC1_bit BANKMASK(TXSTA1), 7 extern volatile __bit CSRC2 @ (((unsigned) &TXSTA2)*8) + 7; #define CSRC2_bit BANKMASK(TXSTA2), 7 extern volatile __bit CTMUDS @ (((unsigned) &PADCFG1)*8) + 0; #define CTMUDS_bit BANKMASK(PADCFG1), 0 extern volatile __bit CTMUEN @ (((unsigned) &CTMUCONH)*8) + 7; #define CTMUEN_bit BANKMASK(CTMUCONH), 7 extern volatile __bit CTMUIE @ (((unsigned) &PIE3)*8) + 3; #define CTMUIE_bit BANKMASK(PIE3), 3 extern volatile __bit CTMUIF @ (((unsigned) &PIR3)*8) + 3; #define CTMUIF_bit BANKMASK(PIR3), 3 extern volatile __bit CTMUIP @ (((unsigned) &IPR3)*8) + 3; #define CTMUIP_bit BANKMASK(IPR3), 3 extern volatile __bit CTMUMD @ (((unsigned) &PMD1)*8) + 6; #define CTMUMD_bit BANKMASK(PMD1), 6 extern volatile __bit CTMUSIDL @ (((unsigned) &CTMUCONH)*8) + 5; #define CTMUSIDL_bit BANKMASK(CTMUCONH), 5 extern volatile __bit CTTRIG @ (((unsigned) &CTMUCONH)*8) + 0; #define CTTRIG_bit BANKMASK(CTMUCONH), 0 extern volatile __bit CVR0 @ (((unsigned) &CVRCON)*8) + 0; #define CVR0_bit BANKMASK(CVRCON), 0 extern volatile __bit CVR1 @ (((unsigned) &CVRCON)*8) + 1; #define CVR1_bit BANKMASK(CVRCON), 1 extern volatile __bit CVR2 @ (((unsigned) &CVRCON)*8) + 2; #define CVR2_bit BANKMASK(CVRCON), 2 extern volatile __bit CVR3 @ (((unsigned) &CVRCON)*8) + 3; #define CVR3_bit BANKMASK(CVRCON), 3 extern volatile __bit CVR4 @ (((unsigned) &CVRCON)*8) + 4; #define CVR4_bit BANKMASK(CVRCON), 4 extern volatile __bit CVREN @ (((unsigned) &CVRCON)*8) + 7; #define CVREN_bit BANKMASK(CVRCON), 7 extern volatile __bit CVROE @ (((unsigned) &CVRCON)*8) + 6; #define CVROE_bit BANKMASK(CVRCON), 6 extern volatile __bit CVROEN @ (((unsigned) &CVRCON)*8) + 6; #define CVROEN_bit BANKMASK(CVRCON), 6 extern volatile __bit CVRR @ (((unsigned) &CVRCON)*8) + 5; #define CVRR_bit BANKMASK(CVRCON), 5 extern volatile __bit CVRSS @ (((unsigned) &CVRCON)*8) + 5; #define CVRSS_bit BANKMASK(CVRCON), 5 extern volatile __bit DA @ (((unsigned) &SSPSTAT)*8) + 5; #define DA_bit BANKMASK(SSPSTAT), 5 extern volatile __bit DATA_ADDRESS @ (((unsigned) &SSPSTAT)*8) + 5; #define DATA_ADDRESS_bit BANKMASK(SSPSTAT), 5 extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1; #define DC_bit BANKMASK(STATUS), 1 extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4; #define DC1B0_bit BANKMASK(CCP1CON), 4 extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5; #define DC1B1_bit BANKMASK(CCP1CON), 5 extern volatile __bit DC2B0 @ (((unsigned) &CCP2CON)*8) + 4; #define DC2B0_bit BANKMASK(CCP2CON), 4 extern volatile __bit DC2B1 @ (((unsigned) &CCP2CON)*8) + 5; #define DC2B1_bit BANKMASK(CCP2CON), 5 extern volatile __bit DC3B0 @ (((unsigned) &CCP3CON)*8) + 4; #define DC3B0_bit BANKMASK(CCP3CON), 4 extern volatile __bit DC3B1 @ (((unsigned) &CCP3CON)*8) + 5; #define DC3B1_bit BANKMASK(CCP3CON), 5 extern volatile __bit DC4B0 @ (((unsigned) &CCP4CON)*8) + 4; #define DC4B0_bit BANKMASK(CCP4CON), 4 extern volatile __bit DC4B1 @ (((unsigned) &CCP4CON)*8) + 5; #define DC4B1_bit BANKMASK(CCP4CON), 5 extern volatile __bit DC5B0 @ (((unsigned) &CCP5CON)*8) + 4; #define DC5B0_bit BANKMASK(CCP5CON), 4 extern volatile __bit DC5B1 @ (((unsigned) &CCP5CON)*8) + 5; #define DC5B1_bit BANKMASK(CCP5CON), 5 extern volatile __bit DONE @ (((unsigned) &ADCON0)*8) + 1; #define DONE_bit BANKMASK(ADCON0), 1 extern volatile __bit DRXB0IE @ (((unsigned) &BIE0)*8) + 0; #define DRXB0IE_bit BANKMASK(BIE0), 0 extern volatile __bit DRXB1IE @ (((unsigned) &BIE0)*8) + 1; #define DRXB1IE_bit BANKMASK(BIE0), 1 extern volatile __bit DTRXP @ (((unsigned) &BAUDCON1)*8) + 5; #define DTRXP_bit BANKMASK(BAUDCON1), 5 extern volatile __bit DTRXP1 @ (((unsigned) &BAUDCON1)*8) + 5; #define DTRXP1_bit BANKMASK(BAUDCON1), 5 extern volatile __bit DTRXP2 @ (((unsigned) &BAUDCON2)*8) + 5; #define DTRXP2_bit BANKMASK(BAUDCON2), 5 extern volatile __bit D_A @ (((unsigned) &SSPSTAT)*8) + 5; #define D_A_bit BANKMASK(SSPSTAT), 5 extern volatile __bit D_NOT_A @ (((unsigned) &SSPSTAT)*8) + 5; #define D_NOT_A_bit BANKMASK(SSPSTAT), 5 extern volatile __bit D_nA @ (((unsigned) &SSPSTAT)*8) + 5; #define D_nA_bit BANKMASK(SSPSTAT), 5 extern volatile __bit EBDIS @ (((unsigned) &PR2)*8) + 7; #define EBDIS_bit BANKMASK(PR2), 7 extern volatile __bit ECANMD @ (((unsigned) &PMD2)*8) + 2; #define ECANMD_bit BANKMASK(PMD2), 2 extern volatile __bit ECCP1AS0 @ (((unsigned) &ECCP1AS)*8) + 4; #define ECCP1AS0_bit BANKMASK(ECCP1AS), 4 extern volatile __bit ECCP1AS1 @ (((unsigned) &ECCP1AS)*8) + 5; #define ECCP1AS1_bit BANKMASK(ECCP1AS), 5 extern volatile __bit ECCP1AS2 @ (((unsigned) &ECCP1AS)*8) + 6; #define ECCP1AS2_bit BANKMASK(ECCP1AS), 6 extern volatile __bit ECCP1ASE @ (((unsigned) &ECCP1AS)*8) + 7; #define ECCP1ASE_bit BANKMASK(ECCP1AS), 7 extern volatile __bit EDG1POL @ (((unsigned) &CTMUCONL)*8) + 4; #define EDG1POL_bit BANKMASK(CTMUCONL), 4 extern volatile __bit EDG1SEL0 @ (((unsigned) &CTMUCONL)*8) + 2; #define EDG1SEL0_bit BANKMASK(CTMUCONL), 2 extern volatile __bit EDG1SEL1 @ (((unsigned) &CTMUCONL)*8) + 3; #define EDG1SEL1_bit BANKMASK(CTMUCONL), 3 extern volatile __bit EDG1STAT @ (((unsigned) &CTMUCONL)*8) + 0; #define EDG1STAT_bit BANKMASK(CTMUCONL), 0 extern volatile __bit EDG2POL @ (((unsigned) &CTMUCONL)*8) + 7; #define EDG2POL_bit BANKMASK(CTMUCONL), 7 extern volatile __bit EDG2SEL0 @ (((unsigned) &CTMUCONL)*8) + 5; #define EDG2SEL0_bit BANKMASK(CTMUCONL), 5 extern volatile __bit EDG2SEL1 @ (((unsigned) &CTMUCONL)*8) + 6; #define EDG2SEL1_bit BANKMASK(CTMUCONL), 6 extern volatile __bit EDG2STAT @ (((unsigned) &CTMUCONL)*8) + 1; #define EDG2STAT_bit BANKMASK(CTMUCONL), 1 extern volatile __bit EDGEN @ (((unsigned) &CTMUCONH)*8) + 3; #define EDGEN_bit BANKMASK(CTMUCONH), 3 extern volatile __bit EDGSEQEN @ (((unsigned) &CTMUCONH)*8) + 2; #define EDGSEQEN_bit BANKMASK(CTMUCONH), 2 extern volatile __bit EDI16 @ (((unsigned) &RXB1SIDL)*8) + 0; #define EDI16_bit BANKMASK(RXB1SIDL), 0 extern volatile __bit EDI17 @ (((unsigned) &RXB1SIDL)*8) + 1; #define EDI17_bit BANKMASK(RXB1SIDL), 1 extern volatile __bit EEFS @ (((unsigned) &EECON1)*8) + 6; #define EEFS_bit BANKMASK(EECON1), 6 extern volatile __bit EEIE @ (((unsigned) &PIE4)*8) + 6; #define EEIE_bit BANKMASK(PIE4), 6 extern volatile __bit EEIF @ (((unsigned) &PIR4)*8) + 6; #define EEIF_bit BANKMASK(PIR4), 6 extern volatile __bit EEIP @ (((unsigned) &IPR4)*8) + 6; #define EEIP_bit BANKMASK(IPR4), 6 extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7; #define EEPGD_bit BANKMASK(EECON1), 7 extern volatile __bit EMBMD @ (((unsigned) &PMD1)*8) + 0; #define EMBMD_bit BANKMASK(PMD1), 0 extern volatile __bit ENDRHI @ (((unsigned) &CIOCON)*8) + 5; #define ENDRHI_bit BANKMASK(CIOCON), 5 extern volatile __bit ERRIE @ (((unsigned) &PIE5)*8) + 5; #define ERRIE_bit BANKMASK(PIE5), 5 extern volatile __bit ERRIF @ (((unsigned) &PIR5)*8) + 5; #define ERRIF_bit BANKMASK(PIR5), 5 extern volatile __bit ERRIP @ (((unsigned) &IPR5)*8) + 5; #define ERRIP_bit BANKMASK(IPR5), 5 extern volatile __bit EVPOL01 @ (((unsigned) &CM1CON)*8) + 3; #define EVPOL01_bit BANKMASK(CM1CON), 3 extern volatile __bit EVPOL02 @ (((unsigned) &CM2CON)*8) + 3; #define EVPOL02_bit BANKMASK(CM2CON), 3 extern volatile __bit EVPOL05 @ (((unsigned) &IPR5)*8) + 3; #define EVPOL05_bit BANKMASK(IPR5), 3 extern volatile __bit EVPOL11 @ (((unsigned) &CM1CON)*8) + 4; #define EVPOL11_bit BANKMASK(CM1CON), 4 extern volatile __bit EVPOL12 @ (((unsigned) &CM2CON)*8) + 4; #define EVPOL12_bit BANKMASK(CM2CON), 4 extern volatile __bit EVPOL15 @ (((unsigned) &IPR5)*8) + 4; #define EVPOL15_bit BANKMASK(IPR5), 4 extern volatile __bit EWARN @ (((unsigned) &COMSTAT)*8) + 0; #define EWARN_bit BANKMASK(COMSTAT), 0 extern volatile __bit EWIN0 @ (((unsigned) &ECANCON)*8) + 0; #define EWIN0_bit BANKMASK(ECANCON), 0 extern volatile __bit EWIN1 @ (((unsigned) &ECANCON)*8) + 1; #define EWIN1_bit BANKMASK(ECANCON), 1 extern volatile __bit EWIN2 @ (((unsigned) &ECANCON)*8) + 2; #define EWIN2_bit BANKMASK(ECANCON), 2 extern volatile __bit EWIN3 @ (((unsigned) &ECANCON)*8) + 3; #define EWIN3_bit BANKMASK(ECANCON), 3 extern volatile __bit EWIN4 @ (((unsigned) &ECANCON)*8) + 4; #define EWIN4_bit BANKMASK(ECANCON), 4 extern volatile __bit F0BP_0 @ (((unsigned) &RXFBCON0)*8) + 0; #define F0BP_0_bit BANKMASK(RXFBCON0), 0 extern volatile __bit F0BP_01 @ (((unsigned) &RXFBCON0)*8) + 0; #define F0BP_01_bit BANKMASK(RXFBCON0), 0 extern volatile __bit F0BP_1 @ (((unsigned) &RXFBCON0)*8) + 1; #define F0BP_1_bit BANKMASK(RXFBCON0), 1 extern volatile __bit F0BP_2 @ (((unsigned) &RXFBCON0)*8) + 2; #define F0BP_2_bit BANKMASK(RXFBCON0), 2 extern volatile __bit F0BP_3 @ (((unsigned) &RXFBCON0)*8) + 3; #define F0BP_3_bit BANKMASK(RXFBCON0), 3 extern volatile __bit F10BP_0 @ (((unsigned) &RXFBCON5)*8) + 0; #define F10BP_0_bit BANKMASK(RXFBCON5), 0 extern volatile __bit F10BP_01 @ (((unsigned) &RXFBCON5)*8) + 0; #define F10BP_01_bit BANKMASK(RXFBCON5), 0 extern volatile __bit F10BP_1 @ (((unsigned) &RXFBCON5)*8) + 1; #define F10BP_1_bit BANKMASK(RXFBCON5), 1 extern volatile __bit F10BP_2 @ (((unsigned) &RXFBCON5)*8) + 2; #define F10BP_2_bit BANKMASK(RXFBCON5), 2 extern volatile __bit F10BP_3 @ (((unsigned) &RXFBCON5)*8) + 3; #define F10BP_3_bit BANKMASK(RXFBCON5), 3 extern volatile __bit F11BP_0 @ (((unsigned) &RXFBCON5)*8) + 4; #define F11BP_0_bit BANKMASK(RXFBCON5), 4 extern volatile __bit F11BP_1 @ (((unsigned) &RXFBCON5)*8) + 5; #define F11BP_1_bit BANKMASK(RXFBCON5), 5 extern volatile __bit F11BP_2 @ (((unsigned) &RXFBCON5)*8) + 6; #define F11BP_2_bit BANKMASK(RXFBCON5), 6 extern volatile __bit F11BP_3 @ (((unsigned) &RXFBCON5)*8) + 7; #define F11BP_3_bit BANKMASK(RXFBCON5), 7 extern volatile __bit F12BP_0 @ (((unsigned) &RXFBCON6)*8) + 0; #define F12BP_0_bit BANKMASK(RXFBCON6), 0 extern volatile __bit F12BP_01 @ (((unsigned) &RXFBCON6)*8) + 0; #define F12BP_01_bit BANKMASK(RXFBCON6), 0 extern volatile __bit F12BP_1 @ (((unsigned) &RXFBCON6)*8) + 1; #define F12BP_1_bit BANKMASK(RXFBCON6), 1 extern volatile __bit F12BP_2 @ (((unsigned) &RXFBCON6)*8) + 2; #define F12BP_2_bit BANKMASK(RXFBCON6), 2 extern volatile __bit F12BP_3 @ (((unsigned) &RXFBCON6)*8) + 3; #define F12BP_3_bit BANKMASK(RXFBCON6), 3 extern volatile __bit F13BP_0 @ (((unsigned) &RXFBCON6)*8) + 4; #define F13BP_0_bit BANKMASK(RXFBCON6), 4 extern volatile __bit F13BP_1 @ (((unsigned) &RXFBCON6)*8) + 5; #define F13BP_1_bit BANKMASK(RXFBCON6), 5 extern volatile __bit F13BP_2 @ (((unsigned) &RXFBCON6)*8) + 6; #define F13BP_2_bit BANKMASK(RXFBCON6), 6 extern volatile __bit F13BP_3 @ (((unsigned) &RXFBCON6)*8) + 7; #define F13BP_3_bit BANKMASK(RXFBCON6), 7 extern volatile __bit F14BP_0 @ (((unsigned) &RXFBCON7)*8) + 0; #define F14BP_0_bit BANKMASK(RXFBCON7), 0 extern volatile __bit F14BP_01 @ (((unsigned) &RXFBCON7)*8) + 0; #define F14BP_01_bit BANKMASK(RXFBCON7), 0 extern volatile __bit F14BP_1 @ (((unsigned) &RXFBCON7)*8) + 1; #define F14BP_1_bit BANKMASK(RXFBCON7), 1 extern volatile __bit F14BP_2 @ (((unsigned) &RXFBCON7)*8) + 2; #define F14BP_2_bit BANKMASK(RXFBCON7), 2 extern volatile __bit F14BP_3 @ (((unsigned) &RXFBCON7)*8) + 3; #define F14BP_3_bit BANKMASK(RXFBCON7), 3 extern volatile __bit F15BP_0 @ (((unsigned) &RXFBCON7)*8) + 4; #define F15BP_0_bit BANKMASK(RXFBCON7), 4 extern volatile __bit F15BP_1 @ (((unsigned) &RXFBCON7)*8) + 5; #define F15BP_1_bit BANKMASK(RXFBCON7), 5 extern volatile __bit F15BP_2 @ (((unsigned) &RXFBCON7)*8) + 6; #define F15BP_2_bit BANKMASK(RXFBCON7), 6 extern volatile __bit F15BP_3 @ (((unsigned) &RXFBCON7)*8) + 7; #define F15BP_3_bit BANKMASK(RXFBCON7), 7 extern volatile __bit F1BP_0 @ (((unsigned) &RXFBCON0)*8) + 4; #define F1BP_0_bit BANKMASK(RXFBCON0), 4 extern volatile __bit F1BP_1 @ (((unsigned) &RXFBCON0)*8) + 5; #define F1BP_1_bit BANKMASK(RXFBCON0), 5 extern volatile __bit F1BP_2 @ (((unsigned) &RXFBCON0)*8) + 6; #define F1BP_2_bit BANKMASK(RXFBCON0), 6 extern volatile __bit F1BP_3 @ (((unsigned) &RXFBCON0)*8) + 7; #define F1BP_3_bit BANKMASK(RXFBCON0), 7 extern volatile __bit F2BP_0 @ (((unsigned) &RXFBCON1)*8) + 0; #define F2BP_0_bit BANKMASK(RXFBCON1), 0 extern volatile __bit F2BP_01 @ (((unsigned) &RXFBCON1)*8) + 0; #define F2BP_01_bit BANKMASK(RXFBCON1), 0 extern volatile __bit F2BP_1 @ (((unsigned) &RXFBCON1)*8) + 1; #define F2BP_1_bit BANKMASK(RXFBCON1), 1 extern volatile __bit F2BP_2 @ (((unsigned) &RXFBCON1)*8) + 2; #define F2BP_2_bit BANKMASK(RXFBCON1), 2 extern volatile __bit F2BP_3 @ (((unsigned) &RXFBCON1)*8) + 3; #define F2BP_3_bit BANKMASK(RXFBCON1), 3 extern volatile __bit F3BP_0 @ (((unsigned) &RXFBCON1)*8) + 4; #define F3BP_0_bit BANKMASK(RXFBCON1), 4 extern volatile __bit F3BP_1 @ (((unsigned) &RXFBCON1)*8) + 5; #define F3BP_1_bit BANKMASK(RXFBCON1), 5 extern volatile __bit F3BP_2 @ (((unsigned) &RXFBCON1)*8) + 6; #define F3BP_2_bit BANKMASK(RXFBCON1), 6 extern volatile __bit F3BP_3 @ (((unsigned) &RXFBCON1)*8) + 7; #define F3BP_3_bit BANKMASK(RXFBCON1), 7 extern volatile __bit F4BP_0 @ (((unsigned) &RXFBCON2)*8) + 0; #define F4BP_0_bit BANKMASK(RXFBCON2), 0 extern volatile __bit F4BP_01 @ (((unsigned) &RXFBCON2)*8) + 0; #define F4BP_01_bit BANKMASK(RXFBCON2), 0 extern volatile __bit F4BP_1 @ (((unsigned) &RXFBCON2)*8) + 1; #define F4BP_1_bit BANKMASK(RXFBCON2), 1 extern volatile __bit F4BP_2 @ (((unsigned) &RXFBCON2)*8) + 2; #define F4BP_2_bit BANKMASK(RXFBCON2), 2 extern volatile __bit F4BP_3 @ (((unsigned) &RXFBCON2)*8) + 3; #define F4BP_3_bit BANKMASK(RXFBCON2), 3 extern volatile __bit F5BP_0 @ (((unsigned) &RXFBCON2)*8) + 4; #define F5BP_0_bit BANKMASK(RXFBCON2), 4 extern volatile __bit F5BP_1 @ (((unsigned) &RXFBCON2)*8) + 5; #define F5BP_1_bit BANKMASK(RXFBCON2), 5 extern volatile __bit F5BP_2 @ (((unsigned) &RXFBCON2)*8) + 6; #define F5BP_2_bit BANKMASK(RXFBCON2), 6 extern volatile __bit F5BP_3 @ (((unsigned) &RXFBCON2)*8) + 7; #define F5BP_3_bit BANKMASK(RXFBCON2), 7 extern volatile __bit F6BP_0 @ (((unsigned) &RXFBCON3)*8) + 0; #define F6BP_0_bit BANKMASK(RXFBCON3), 0 extern volatile __bit F6BP_01 @ (((unsigned) &RXFBCON3)*8) + 0; #define F6BP_01_bit BANKMASK(RXFBCON3), 0 extern volatile __bit F6BP_1 @ (((unsigned) &RXFBCON3)*8) + 1; #define F6BP_1_bit BANKMASK(RXFBCON3), 1 extern volatile __bit F6BP_2 @ (((unsigned) &RXFBCON3)*8) + 2; #define F6BP_2_bit BANKMASK(RXFBCON3), 2 extern volatile __bit F6BP_3 @ (((unsigned) &RXFBCON3)*8) + 3; #define F6BP_3_bit BANKMASK(RXFBCON3), 3 extern volatile __bit F7BP_0 @ (((unsigned) &RXFBCON3)*8) + 4; #define F7BP_0_bit BANKMASK(RXFBCON3), 4 extern volatile __bit F7BP_1 @ (((unsigned) &RXFBCON3)*8) + 5; #define F7BP_1_bit BANKMASK(RXFBCON3), 5 extern volatile __bit F7BP_2 @ (((unsigned) &RXFBCON3)*8) + 6; #define F7BP_2_bit BANKMASK(RXFBCON3), 6 extern volatile __bit F7BP_3 @ (((unsigned) &RXFBCON3)*8) + 7; #define F7BP_3_bit BANKMASK(RXFBCON3), 7 extern volatile __bit F8BP_0 @ (((unsigned) &RXFBCON4)*8) + 0; #define F8BP_0_bit BANKMASK(RXFBCON4), 0 extern volatile __bit F8BP_01 @ (((unsigned) &RXFBCON4)*8) + 0; #define F8BP_01_bit BANKMASK(RXFBCON4), 0 extern volatile __bit F8BP_1 @ (((unsigned) &RXFBCON4)*8) + 1; #define F8BP_1_bit BANKMASK(RXFBCON4), 1 extern volatile __bit F8BP_2 @ (((unsigned) &RXFBCON4)*8) + 2; #define F8BP_2_bit BANKMASK(RXFBCON4), 2 extern volatile __bit F8BP_3 @ (((unsigned) &RXFBCON4)*8) + 3; #define F8BP_3_bit BANKMASK(RXFBCON4), 3 extern volatile __bit F9BP_0 @ (((unsigned) &RXFBCON4)*8) + 4; #define F9BP_0_bit BANKMASK(RXFBCON4), 4 extern volatile __bit F9BP_1 @ (((unsigned) &RXFBCON4)*8) + 5; #define F9BP_1_bit BANKMASK(RXFBCON4), 5 extern volatile __bit F9BP_2 @ (((unsigned) &RXFBCON4)*8) + 6; #define F9BP_2_bit BANKMASK(RXFBCON4), 6 extern volatile __bit F9BP_3 @ (((unsigned) &RXFBCON4)*8) + 7; #define F9BP_3_bit BANKMASK(RXFBCON4), 7 extern volatile __bit FERR1 @ (((unsigned) &RCSTA1)*8) + 2; #define FERR1_bit BANKMASK(RCSTA1), 2 extern volatile __bit FERR2 @ (((unsigned) &RCSTA2)*8) + 2; #define FERR2_bit BANKMASK(RCSTA2), 2 extern volatile __bit FIFOEMPTY @ (((unsigned) &COMSTAT)*8) + 7; #define FIFOEMPTY_bit BANKMASK(COMSTAT), 7 extern volatile __bit FIFOWM @ (((unsigned) &ECANCON)*8) + 5; #define FIFOWM_bit BANKMASK(ECANCON), 5 extern volatile __bit FIFOWMIE @ (((unsigned) &PIE5)*8) + 0; #define FIFOWMIE_bit BANKMASK(PIE5), 0 extern volatile __bit FIFOWMIF @ (((unsigned) &PIR5)*8) + 0; #define FIFOWMIF_bit BANKMASK(PIR5), 0 extern volatile __bit FIFOWMIP @ (((unsigned) &IPR5)*8) + 0; #define FIFOWMIP_bit BANKMASK(IPR5), 0 extern volatile __bit FIL0_0 @ (((unsigned) &MSEL0)*8) + 0; #define FIL0_0_bit BANKMASK(MSEL0), 0 extern volatile __bit FIL0_1 @ (((unsigned) &MSEL0)*8) + 1; #define FIL0_1_bit BANKMASK(MSEL0), 1 extern volatile __bit FIL10_0 @ (((unsigned) &MSEL2)*8) + 4; #define FIL10_0_bit BANKMASK(MSEL2), 4 extern volatile __bit FIL10_1 @ (((unsigned) &MSEL2)*8) + 5; #define FIL10_1_bit BANKMASK(MSEL2), 5 extern volatile __bit FIL11_0 @ (((unsigned) &MSEL2)*8) + 6; #define FIL11_0_bit BANKMASK(MSEL2), 6 extern volatile __bit FIL11_1 @ (((unsigned) &MSEL2)*8) + 7; #define FIL11_1_bit BANKMASK(MSEL2), 7 extern volatile __bit FIL12_0 @ (((unsigned) &MSEL3)*8) + 0; #define FIL12_0_bit BANKMASK(MSEL3), 0 extern volatile __bit FIL12_1 @ (((unsigned) &MSEL3)*8) + 1; #define FIL12_1_bit BANKMASK(MSEL3), 1 extern volatile __bit FIL13_0 @ (((unsigned) &MSEL3)*8) + 2; #define FIL13_0_bit BANKMASK(MSEL3), 2 extern volatile __bit FIL13_1 @ (((unsigned) &MSEL3)*8) + 3; #define FIL13_1_bit BANKMASK(MSEL3), 3 extern volatile __bit FIL14_0 @ (((unsigned) &MSEL3)*8) + 4; #define FIL14_0_bit BANKMASK(MSEL3), 4 extern volatile __bit FIL14_1 @ (((unsigned) &MSEL3)*8) + 5; #define FIL14_1_bit BANKMASK(MSEL3), 5 extern volatile __bit FIL15_0 @ (((unsigned) &MSEL3)*8) + 6; #define FIL15_0_bit BANKMASK(MSEL3), 6 extern volatile __bit FIL15_1 @ (((unsigned) &MSEL3)*8) + 7; #define FIL15_1_bit BANKMASK(MSEL3), 7 extern volatile __bit FIL1_0 @ (((unsigned) &MSEL0)*8) + 2; #define FIL1_0_bit BANKMASK(MSEL0), 2 extern volatile __bit FIL1_1 @ (((unsigned) &MSEL0)*8) + 3; #define FIL1_1_bit BANKMASK(MSEL0), 3 extern volatile __bit FIL2_0 @ (((unsigned) &MSEL0)*8) + 4; #define FIL2_0_bit BANKMASK(MSEL0), 4 extern volatile __bit FIL2_1 @ (((unsigned) &MSEL0)*8) + 5; #define FIL2_1_bit BANKMASK(MSEL0), 5 extern volatile __bit FIL3_0 @ (((unsigned) &MSEL0)*8) + 6; #define FIL3_0_bit BANKMASK(MSEL0), 6 extern volatile __bit FIL3_1 @ (((unsigned) &MSEL0)*8) + 7; #define FIL3_1_bit BANKMASK(MSEL0), 7 extern volatile __bit FIL4_0 @ (((unsigned) &MSEL1)*8) + 0; #define FIL4_0_bit BANKMASK(MSEL1), 0 extern volatile __bit FIL4_1 @ (((unsigned) &MSEL1)*8) + 1; #define FIL4_1_bit BANKMASK(MSEL1), 1 extern volatile __bit FIL5_0 @ (((unsigned) &MSEL1)*8) + 2; #define FIL5_0_bit BANKMASK(MSEL1), 2 extern volatile __bit FIL5_1 @ (((unsigned) &MSEL1)*8) + 3; #define FIL5_1_bit BANKMASK(MSEL1), 3 extern volatile __bit FIL6_0 @ (((unsigned) &MSEL1)*8) + 4; #define FIL6_0_bit BANKMASK(MSEL1), 4 extern volatile __bit FIL6_1 @ (((unsigned) &MSEL1)*8) + 5; #define FIL6_1_bit BANKMASK(MSEL1), 5 extern volatile __bit FIL7_0 @ (((unsigned) &MSEL1)*8) + 6; #define FIL7_0_bit BANKMASK(MSEL1), 6 extern volatile __bit FIL7_1 @ (((unsigned) &MSEL1)*8) + 7; #define FIL7_1_bit BANKMASK(MSEL1), 7 extern volatile __bit FIL8_0 @ (((unsigned) &MSEL2)*8) + 0; #define FIL8_0_bit BANKMASK(MSEL2), 0 extern volatile __bit FIL8_1 @ (((unsigned) &MSEL2)*8) + 1; #define FIL8_1_bit BANKMASK(MSEL2), 1 extern volatile __bit FIL9_0 @ (((unsigned) &MSEL2)*8) + 2; #define FIL9_0_bit BANKMASK(MSEL2), 2 extern volatile __bit FIL9_1 @ (((unsigned) &MSEL2)*8) + 3; #define FIL9_1_bit BANKMASK(MSEL2), 3 extern volatile __bit FLC0 @ (((unsigned) &SDFLC)*8) + 0; #define FLC0_bit BANKMASK(SDFLC), 0 extern volatile __bit FLC1 @ (((unsigned) &SDFLC)*8) + 1; #define FLC1_bit BANKMASK(SDFLC), 1 extern volatile __bit FLC2 @ (((unsigned) &SDFLC)*8) + 2; #define FLC2_bit BANKMASK(SDFLC), 2 extern volatile __bit FLC3 @ (((unsigned) &SDFLC)*8) + 3; #define FLC3_bit BANKMASK(SDFLC), 3 extern volatile __bit FLC4 @ (((unsigned) &SDFLC)*8) + 4; #define FLC4_bit BANKMASK(SDFLC), 4 extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4; #define FREE_bit BANKMASK(EECON1), 4 extern volatile __bit GCEN @ (((unsigned) &SSPCON2)*8) + 7; #define GCEN_bit BANKMASK(SSPCON2), 7 extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7; #define GIE_bit BANKMASK(INTCON), 7 extern volatile __bit GIEH @ (((unsigned) &INTCON)*8) + 7; #define GIEH_bit BANKMASK(INTCON), 7 extern volatile __bit GIEL @ (((unsigned) &INTCON)*8) + 6; #define GIEL_bit BANKMASK(INTCON), 6 extern volatile __bit GIE_GIEH @ (((unsigned) &INTCON)*8) + 7; #define GIE_GIEH_bit BANKMASK(INTCON), 7 extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1; #define GO_bit BANKMASK(ADCON0), 1 extern volatile __bit GODONE @ (((unsigned) &ADCON0)*8) + 1; #define GODONE_bit BANKMASK(ADCON0), 1 extern volatile __bit GO_DONE @ (((unsigned) &ADCON0)*8) + 1; #define GO_DONE_bit BANKMASK(ADCON0), 1 extern volatile __bit GO_NOT_DONE @ (((unsigned) &ADCON0)*8) + 1; #define GO_NOT_DONE_bit BANKMASK(ADCON0), 1 extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1; #define GO_nDONE_bit BANKMASK(ADCON0), 1 extern volatile __bit HFIOFS @ (((unsigned) &OSCCON)*8) + 2; #define HFIOFS_bit BANKMASK(OSCCON), 2 extern volatile __bit HLVDEN @ (((unsigned) &HLVDCON)*8) + 4; #define HLVDEN_bit BANKMASK(HLVDCON), 4 extern volatile __bit HLVDIE @ (((unsigned) &PIE2)*8) + 2; #define HLVDIE_bit BANKMASK(PIE2), 2 extern volatile __bit HLVDIF @ (((unsigned) &PIR2)*8) + 2; #define HLVDIF_bit BANKMASK(PIR2), 2 extern volatile __bit HLVDIP @ (((unsigned) &IPR2)*8) + 2; #define HLVDIP_bit BANKMASK(IPR2), 2 extern volatile __bit HLVDL0 @ (((unsigned) &HLVDCON)*8) + 0; #define HLVDL0_bit BANKMASK(HLVDCON), 0 extern volatile __bit HLVDL1 @ (((unsigned) &HLVDCON)*8) + 1; #define HLVDL1_bit BANKMASK(HLVDCON), 1 extern volatile __bit HLVDL2 @ (((unsigned) &HLVDCON)*8) + 2; #define HLVDL2_bit BANKMASK(HLVDCON), 2 extern volatile __bit HLVDL3 @ (((unsigned) &HLVDCON)*8) + 3; #define HLVDL3_bit BANKMASK(HLVDCON), 3 extern volatile __bit I2C_DAT @ (((unsigned) &SSPSTAT)*8) + 5; #define I2C_DAT_bit BANKMASK(SSPSTAT), 5 extern volatile __bit I2C_READ @ (((unsigned) &SSPSTAT)*8) + 2; #define I2C_READ_bit BANKMASK(SSPSTAT), 2 extern volatile __bit I2C_START @ (((unsigned) &SSPSTAT)*8) + 3; #define I2C_START_bit BANKMASK(SSPSTAT), 3 extern volatile __bit I2C_STOP @ (((unsigned) &SSPSTAT)*8) + 4; #define I2C_STOP_bit BANKMASK(SSPSTAT), 4 extern volatile __bit ICODE20 @ (((unsigned) &CANSTAT_RO2)*8) + 1; #define ICODE20_bit BANKMASK(CANSTAT_RO2), 1 extern volatile __bit ICODE21 @ (((unsigned) &CANSTAT_RO2)*8) + 2; #define ICODE21_bit BANKMASK(CANSTAT_RO2), 2 extern volatile __bit IDISSEN @ (((unsigned) &CTMUCONH)*8) + 1; #define IDISSEN_bit BANKMASK(CTMUCONH), 1 extern volatile __bit IDLEN @ (((unsigned) &OSCCON)*8) + 7; #define IDLEN_bit BANKMASK(OSCCON), 7 extern volatile __bit INT0E @ (((unsigned) &INTCON)*8) + 4; #define INT0E_bit BANKMASK(INTCON), 4 extern volatile __bit INT0F @ (((unsigned) &INTCON)*8) + 1; #define INT0F_bit BANKMASK(INTCON), 1 extern volatile __bit INT0IE @ (((unsigned) &INTCON)*8) + 4; #define INT0IE_bit BANKMASK(INTCON), 4 extern volatile __bit INT0IF @ (((unsigned) &INTCON)*8) + 1; #define INT0IF_bit BANKMASK(INTCON), 1 extern volatile __bit INT1E @ (((unsigned) &INTCON3)*8) + 3; #define INT1E_bit BANKMASK(INTCON3), 3 extern volatile __bit INT1F @ (((unsigned) &INTCON3)*8) + 0; #define INT1F_bit BANKMASK(INTCON3), 0 extern volatile __bit INT1IE @ (((unsigned) &INTCON3)*8) + 3; #define INT1IE_bit BANKMASK(INTCON3), 3 extern volatile __bit INT1IF @ (((unsigned) &INTCON3)*8) + 0; #define INT1IF_bit BANKMASK(INTCON3), 0 extern volatile __bit INT1IP @ (((unsigned) &INTCON3)*8) + 6; #define INT1IP_bit BANKMASK(INTCON3), 6 extern volatile __bit INT1P @ (((unsigned) &INTCON3)*8) + 6; #define INT1P_bit BANKMASK(INTCON3), 6 extern volatile __bit INT2E @ (((unsigned) &INTCON3)*8) + 4; #define INT2E_bit BANKMASK(INTCON3), 4 extern volatile __bit INT2F @ (((unsigned) &INTCON3)*8) + 1; #define INT2F_bit BANKMASK(INTCON3), 1 extern volatile __bit INT2IE @ (((unsigned) &INTCON3)*8) + 4; #define INT2IE_bit BANKMASK(INTCON3), 4 extern volatile __bit INT2IF @ (((unsigned) &INTCON3)*8) + 1; #define INT2IF_bit BANKMASK(INTCON3), 1 extern volatile __bit INT2IP @ (((unsigned) &INTCON3)*8) + 7; #define INT2IP_bit BANKMASK(INTCON3), 7 extern volatile __bit INT2P @ (((unsigned) &INTCON3)*8) + 7; #define INT2P_bit BANKMASK(INTCON3), 7 extern volatile __bit INT3E @ (((unsigned) &INTCON3)*8) + 5; #define INT3E_bit BANKMASK(INTCON3), 5 extern volatile __bit INT3F @ (((unsigned) &INTCON3)*8) + 2; #define INT3F_bit BANKMASK(INTCON3), 2 extern volatile __bit INT3IE @ (((unsigned) &INTCON3)*8) + 5; #define INT3IE_bit BANKMASK(INTCON3), 5 extern volatile __bit INT3IF @ (((unsigned) &INTCON3)*8) + 2; #define INT3IF_bit BANKMASK(INTCON3), 2 extern volatile __bit INT3IP @ (((unsigned) &INTCON2)*8) + 1; #define INT3IP_bit BANKMASK(INTCON2), 1 extern volatile __bit INT3P @ (((unsigned) &INTCON2)*8) + 1; #define INT3P_bit BANKMASK(INTCON2), 1 extern volatile __bit INTEDG0 @ (((unsigned) &INTCON2)*8) + 6; #define INTEDG0_bit BANKMASK(INTCON2), 6 extern volatile __bit INTEDG1 @ (((unsigned) &INTCON2)*8) + 5; #define INTEDG1_bit BANKMASK(INTCON2), 5 extern volatile __bit INTEDG2 @ (((unsigned) &INTCON2)*8) + 4; #define INTEDG2_bit BANKMASK(INTCON2), 4 extern volatile __bit INTEDG3 @ (((unsigned) &INTCON2)*8) + 3; #define INTEDG3_bit BANKMASK(INTCON2), 3 extern volatile __bit INTSRC @ (((unsigned) &OSCTUNE)*8) + 7; #define INTSRC_bit BANKMASK(OSCTUNE), 7 extern volatile __bit IOCB4 @ (((unsigned) &IOCB)*8) + 4; #define IOCB4_bit BANKMASK(IOCB), 4 extern volatile __bit IOCB5 @ (((unsigned) &IOCB)*8) + 5; #define IOCB5_bit BANKMASK(IOCB), 5 extern volatile __bit IOCB6 @ (((unsigned) &IOCB)*8) + 6; #define IOCB6_bit BANKMASK(IOCB), 6 extern volatile __bit IOCB7 @ (((unsigned) &IOCB)*8) + 7; #define IOCB7_bit BANKMASK(IOCB), 7 extern volatile __bit IPEN @ (((unsigned) &RCON)*8) + 7; #define IPEN_bit BANKMASK(RCON), 7 extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 4; #define IRCF0_bit BANKMASK(OSCCON), 4 extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 5; #define IRCF1_bit BANKMASK(OSCCON), 5 extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 6; #define IRCF2_bit BANKMASK(OSCCON), 6 extern volatile __bit IRNG0 @ (((unsigned) &CTMUICON)*8) + 0; #define IRNG0_bit BANKMASK(CTMUICON), 0 extern volatile __bit IRNG1 @ (((unsigned) &CTMUICON)*8) + 1; #define IRNG1_bit BANKMASK(CTMUICON), 1 extern volatile __bit IRVST @ (((unsigned) &HLVDCON)*8) + 5; #define IRVST_bit BANKMASK(HLVDCON), 5 extern volatile __bit IRXIE @ (((unsigned) &PIE5)*8) + 7; #define IRXIE_bit BANKMASK(PIE5), 7 extern volatile __bit IRXIF @ (((unsigned) &PIR5)*8) + 7; #define IRXIF_bit BANKMASK(PIR5), 7 extern volatile __bit IRXIP @ (((unsigned) &IPR5)*8) + 7; #define IRXIP_bit BANKMASK(IPR5), 7 extern volatile __bit ITRIM0 @ (((unsigned) &CTMUICON)*8) + 2; #define ITRIM0_bit BANKMASK(CTMUICON), 2 extern volatile __bit ITRIM1 @ (((unsigned) &CTMUICON)*8) + 3; #define ITRIM1_bit BANKMASK(CTMUICON), 3 extern volatile __bit ITRIM2 @ (((unsigned) &CTMUICON)*8) + 4; #define ITRIM2_bit BANKMASK(CTMUICON), 4 extern volatile __bit ITRIM3 @ (((unsigned) &CTMUICON)*8) + 5; #define ITRIM3_bit BANKMASK(CTMUICON), 5 extern volatile __bit ITRIM4 @ (((unsigned) &CTMUICON)*8) + 6; #define ITRIM4_bit BANKMASK(CTMUICON), 6 extern volatile __bit ITRIM5 @ (((unsigned) &CTMUICON)*8) + 7; #define ITRIM5_bit BANKMASK(CTMUICON), 7 extern volatile __bit JTOFF @ (((unsigned) &RXB0CON)*8) + 1; #define JTOFF_bit BANKMASK(RXB0CON), 1 extern volatile __bit JTOFF_FILHIT1 @ (((unsigned) &RXB0CON)*8) + 1; #define JTOFF_FILHIT1_bit BANKMASK(RXB0CON), 1 extern volatile __bit LA0 @ (((unsigned) &LATA)*8) + 0; #define LA0_bit BANKMASK(LATA), 0 extern volatile __bit LA1 @ (((unsigned) &LATA)*8) + 1; #define LA1_bit BANKMASK(LATA), 1 extern volatile __bit LA2 @ (((unsigned) &LATA)*8) + 2; #define LA2_bit BANKMASK(LATA), 2 extern volatile __bit LA3 @ (((unsigned) &LATA)*8) + 3; #define LA3_bit BANKMASK(LATA), 3 extern volatile __bit LA5 @ (((unsigned) &LATA)*8) + 5; #define LA5_bit BANKMASK(LATA), 5 extern volatile __bit LA6 @ (((unsigned) &LATA)*8) + 6; #define LA6_bit BANKMASK(LATA), 6 extern volatile __bit LA7 @ (((unsigned) &LATA)*8) + 7; #define LA7_bit BANKMASK(LATA), 7 extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0; #define LATA0_bit BANKMASK(LATA), 0 extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1; #define LATA1_bit BANKMASK(LATA), 1 extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2; #define LATA2_bit BANKMASK(LATA), 2 extern volatile __bit LATA3 @ (((unsigned) &LATA)*8) + 3; #define LATA3_bit BANKMASK(LATA), 3 extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5; #define LATA5_bit BANKMASK(LATA), 5 extern volatile __bit LATA6 @ (((unsigned) &LATA)*8) + 6; #define LATA6_bit BANKMASK(LATA), 6 extern volatile __bit LATA7 @ (((unsigned) &LATA)*8) + 7; #define LATA7_bit BANKMASK(LATA), 7 extern volatile __bit LATB0 @ (((unsigned) &LATB)*8) + 0; #define LATB0_bit BANKMASK(LATB), 0 extern volatile __bit LATB1 @ (((unsigned) &LATB)*8) + 1; #define LATB1_bit BANKMASK(LATB), 1 extern volatile __bit LATB2 @ (((unsigned) &LATB)*8) + 2; #define LATB2_bit BANKMASK(LATB), 2 extern volatile __bit LATB3 @ (((unsigned) &LATB)*8) + 3; #define LATB3_bit BANKMASK(LATB), 3 extern volatile __bit LATB4 @ (((unsigned) &LATB)*8) + 4; #define LATB4_bit BANKMASK(LATB), 4 extern volatile __bit LATB5 @ (((unsigned) &LATB)*8) + 5; #define LATB5_bit BANKMASK(LATB), 5 extern volatile __bit LATB6 @ (((unsigned) &LATB)*8) + 6; #define LATB6_bit BANKMASK(LATB), 6 extern volatile __bit LATB7 @ (((unsigned) &LATB)*8) + 7; #define LATB7_bit BANKMASK(LATB), 7 extern volatile __bit LATC0 @ (((unsigned) &LATC)*8) + 0; #define LATC0_bit BANKMASK(LATC), 0 extern volatile __bit LATC1 @ (((unsigned) &LATC)*8) + 1; #define LATC1_bit BANKMASK(LATC), 1 extern volatile __bit LATC2 @ (((unsigned) &LATC)*8) + 2; #define LATC2_bit BANKMASK(LATC), 2 extern volatile __bit LATC3 @ (((unsigned) &LATC)*8) + 3; #define LATC3_bit BANKMASK(LATC), 3 extern volatile __bit LATC4 @ (((unsigned) &LATC)*8) + 4; #define LATC4_bit BANKMASK(LATC), 4 extern volatile __bit LATC5 @ (((unsigned) &LATC)*8) + 5; #define LATC5_bit BANKMASK(LATC), 5 extern volatile __bit LATC6 @ (((unsigned) &LATC)*8) + 6; #define LATC6_bit BANKMASK(LATC), 6 extern volatile __bit LATC7 @ (((unsigned) &LATC)*8) + 7; #define LATC7_bit BANKMASK(LATC), 7 extern volatile __bit LB0 @ (((unsigned) &LATB)*8) + 0; #define LB0_bit BANKMASK(LATB), 0 extern volatile __bit LB1 @ (((unsigned) &LATB)*8) + 1; #define LB1_bit BANKMASK(LATB), 1 extern volatile __bit LB2 @ (((unsigned) &LATB)*8) + 2; #define LB2_bit BANKMASK(LATB), 2 extern volatile __bit LB3 @ (((unsigned) &LATB)*8) + 3; #define LB3_bit BANKMASK(LATB), 3 extern volatile __bit LB4 @ (((unsigned) &LATB)*8) + 4; #define LB4_bit BANKMASK(LATB), 4 extern volatile __bit LB5 @ (((unsigned) &LATB)*8) + 5; #define LB5_bit BANKMASK(LATB), 5 extern volatile __bit LB6 @ (((unsigned) &LATB)*8) + 6; #define LB6_bit BANKMASK(LATB), 6 extern volatile __bit LB7 @ (((unsigned) &LATB)*8) + 7; #define LB7_bit BANKMASK(LATB), 7 extern volatile __bit LC0 @ (((unsigned) &LATC)*8) + 0; #define LC0_bit BANKMASK(LATC), 0 extern volatile __bit LC1 @ (((unsigned) &LATC)*8) + 1; #define LC1_bit BANKMASK(LATC), 1 extern volatile __bit LC2 @ (((unsigned) &LATC)*8) + 2; #define LC2_bit BANKMASK(LATC), 2 extern volatile __bit LC3 @ (((unsigned) &LATC)*8) + 3; #define LC3_bit BANKMASK(LATC), 3 extern volatile __bit LC4 @ (((unsigned) &LATC)*8) + 4; #define LC4_bit BANKMASK(LATC), 4 extern volatile __bit LC5 @ (((unsigned) &LATC)*8) + 5; #define LC5_bit BANKMASK(LATC), 5 extern volatile __bit LC6 @ (((unsigned) &LATC)*8) + 6; #define LC6_bit BANKMASK(LATC), 6 extern volatile __bit LC7 @ (((unsigned) &LATC)*8) + 7; #define LC7_bit BANKMASK(LATC), 7 extern volatile __bit LVDIE @ (((unsigned) &PIE2)*8) + 2; #define LVDIE_bit BANKMASK(PIE2), 2 extern volatile __bit LVDIF @ (((unsigned) &PIR2)*8) + 2; #define LVDIF_bit BANKMASK(PIR2), 2 extern volatile __bit LVDIN @ (((unsigned) &PORTA)*8) + 5; #define LVDIN_bit BANKMASK(PORTA), 5 extern volatile __bit LVDIP @ (((unsigned) &IPR2)*8) + 2; #define LVDIP_bit BANKMASK(IPR2), 2 extern volatile __bit LVDL0 @ (((unsigned) &OSCCON2)*8) + 0; #define LVDL0_bit BANKMASK(OSCCON2), 0 extern volatile __bit LVDL1 @ (((unsigned) &OSCCON2)*8) + 1; #define LVDL1_bit BANKMASK(OSCCON2), 1 extern volatile __bit LVDL2 @ (((unsigned) &OSCCON2)*8) + 2; #define LVDL2_bit BANKMASK(OSCCON2), 2 extern volatile __bit LVDL3 @ (((unsigned) &OSCCON2)*8) + 3; #define LVDL3_bit BANKMASK(OSCCON2), 3 extern volatile __bit MDSEL0 @ (((unsigned) &ECANCON)*8) + 6; #define MDSEL0_bit BANKMASK(ECANCON), 6 extern volatile __bit MDSEL1 @ (((unsigned) &ECANCON)*8) + 7; #define MDSEL1_bit BANKMASK(ECANCON), 7 extern volatile __bit MFIOFS @ (((unsigned) &OSCCON2)*8) + 1; #define MFIOFS_bit BANKMASK(OSCCON2), 1 extern volatile __bit MFIOSEL @ (((unsigned) &OSCCON2)*8) + 0; #define MFIOSEL_bit BANKMASK(OSCCON2), 0 extern volatile __bit MSK0 @ (((unsigned) &SSPADD)*8) + 0; #define MSK0_bit BANKMASK(SSPADD), 0 extern volatile __bit MSK1 @ (((unsigned) &SSPADD)*8) + 1; #define MSK1_bit BANKMASK(SSPADD), 1 extern volatile __bit MSK2 @ (((unsigned) &SSPADD)*8) + 2; #define MSK2_bit BANKMASK(SSPADD), 2 extern volatile __bit MSK3 @ (((unsigned) &SSPADD)*8) + 3; #define MSK3_bit BANKMASK(SSPADD), 3 extern volatile __bit MSK4 @ (((unsigned) &SSPADD)*8) + 4; #define MSK4_bit BANKMASK(SSPADD), 4 extern volatile __bit MSK5 @ (((unsigned) &SSPADD)*8) + 5; #define MSK5_bit BANKMASK(SSPADD), 5 extern volatile __bit MSK6 @ (((unsigned) &SSPADD)*8) + 6; #define MSK6_bit BANKMASK(SSPADD), 6 extern volatile __bit MSK7 @ (((unsigned) &SSPADD)*8) + 7; #define MSK7_bit BANKMASK(SSPADD), 7 extern volatile __bit NEGATIVE @ (((unsigned) &STATUS)*8) + 4; #define NEGATIVE_bit BANKMASK(STATUS), 4 extern volatile __bit NOT_A @ (((unsigned) &SSPSTAT)*8) + 5; #define NOT_A_bit BANKMASK(SSPSTAT), 5 extern volatile __bit NOT_ADDRESS @ (((unsigned) &SSPSTAT)*8) + 5; #define NOT_ADDRESS_bit BANKMASK(SSPSTAT), 5 extern volatile __bit NOT_BOR @ (((unsigned) &RCON)*8) + 0; #define NOT_BOR_bit BANKMASK(RCON), 0 extern volatile __bit NOT_CM @ (((unsigned) &RCON)*8) + 5; #define NOT_CM_bit BANKMASK(RCON), 5 extern volatile __bit NOT_DONE @ (((unsigned) &ADCON0)*8) + 1; #define NOT_DONE_bit BANKMASK(ADCON0), 1 extern volatile __bit NOT_FIFOEMPTY @ (((unsigned) &COMSTAT)*8) + 7; #define NOT_FIFOEMPTY_bit BANKMASK(COMSTAT), 7 extern volatile __bit NOT_PD @ (((unsigned) &RCON)*8) + 2; #define NOT_PD_bit BANKMASK(RCON), 2 extern volatile __bit NOT_POR @ (((unsigned) &RCON)*8) + 1; #define NOT_POR_bit BANKMASK(RCON), 1 extern volatile __bit NOT_RBPU @ (((unsigned) &INTCON2)*8) + 7; #define NOT_RBPU_bit BANKMASK(INTCON2), 7 extern volatile __bit NOT_RC8 @ (((unsigned) &RCSTA1)*8) + 6; #define NOT_RC8_bit BANKMASK(RCSTA1), 6 extern volatile __bit NOT_RI @ (((unsigned) &RCON)*8) + 4; #define NOT_RI_bit BANKMASK(RCON), 4 extern volatile __bit NOT_T1DONE @ (((unsigned) &T1GCON)*8) + 3; #define NOT_T1DONE_bit BANKMASK(T1GCON), 3 extern volatile __bit NOT_T1SYNC @ (((unsigned) &T1CON)*8) + 2; #define NOT_T1SYNC_bit BANKMASK(T1CON), 2 extern volatile __bit NOT_T3DONE @ (((unsigned) &T3GCON)*8) + 3; #define NOT_T3DONE_bit BANKMASK(T3GCON), 3 extern volatile __bit NOT_T3SYNC @ (((unsigned) &T3CON)*8) + 2; #define NOT_T3SYNC_bit BANKMASK(T3CON), 2 extern volatile __bit NOT_TO @ (((unsigned) &RCON)*8) + 3; #define NOT_TO_bit BANKMASK(RCON), 3 extern volatile __bit NOT_TX8 @ (((unsigned) &TXSTA1)*8) + 6; #define NOT_TX8_bit BANKMASK(TXSTA1), 6 extern volatile __bit NOT_W @ (((unsigned) &SSPSTAT)*8) + 2; #define NOT_W_bit BANKMASK(SSPSTAT), 2 extern volatile __bit NOT_WRITE @ (((unsigned) &SSPSTAT)*8) + 2; #define NOT_WRITE_bit BANKMASK(SSPSTAT), 2 extern volatile __bit OERR1 @ (((unsigned) &RCSTA1)*8) + 1; #define OERR1_bit BANKMASK(RCSTA1), 1 extern volatile __bit OERR2 @ (((unsigned) &RCSTA2)*8) + 1; #define OERR2_bit BANKMASK(RCSTA2), 1 extern volatile __bit OSCFIE @ (((unsigned) &PIE2)*8) + 7; #define OSCFIE_bit BANKMASK(PIE2), 7 extern volatile __bit OSCFIF @ (((unsigned) &PIR2)*8) + 7; #define OSCFIF_bit BANKMASK(PIR2), 7 extern volatile __bit OSCFIP @ (((unsigned) &IPR2)*8) + 7; #define OSCFIP_bit BANKMASK(IPR2), 7 extern volatile __bit OSTS @ (((unsigned) &OSCCON)*8) + 3; #define OSTS_bit BANKMASK(OSCCON), 3 extern volatile __bit OV @ (((unsigned) &STATUS)*8) + 3; #define OV_bit BANKMASK(STATUS), 3 extern volatile __bit OVERFLOW @ (((unsigned) &STATUS)*8) + 3; #define OVERFLOW_bit BANKMASK(STATUS), 3 extern volatile __bit P1DC0 @ (((unsigned) &ECCP1DEL)*8) + 0; #define P1DC0_bit BANKMASK(ECCP1DEL), 0 extern volatile __bit P1DC1 @ (((unsigned) &ECCP1DEL)*8) + 1; #define P1DC1_bit BANKMASK(ECCP1DEL), 1 extern volatile __bit P1DC2 @ (((unsigned) &ECCP1DEL)*8) + 2; #define P1DC2_bit BANKMASK(ECCP1DEL), 2 extern volatile __bit P1DC3 @ (((unsigned) &ECCP1DEL)*8) + 3; #define P1DC3_bit BANKMASK(ECCP1DEL), 3 extern volatile __bit P1DC4 @ (((unsigned) &ECCP1DEL)*8) + 4; #define P1DC4_bit BANKMASK(ECCP1DEL), 4 extern volatile __bit P1DC5 @ (((unsigned) &ECCP1DEL)*8) + 5; #define P1DC5_bit BANKMASK(ECCP1DEL), 5 extern volatile __bit P1DC6 @ (((unsigned) &ECCP1DEL)*8) + 6; #define P1DC6_bit BANKMASK(ECCP1DEL), 6 extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6; #define P1M0_bit BANKMASK(CCP1CON), 6 extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7; #define P1M1_bit BANKMASK(CCP1CON), 7 extern volatile __bit P1RSEN @ (((unsigned) &ECCP1DEL)*8) + 7; #define P1RSEN_bit BANKMASK(ECCP1DEL), 7 extern volatile __bit PA1 @ (((unsigned) &PORTC)*8) + 2; #define PA1_bit BANKMASK(PORTC), 2 extern volatile __bit PA2 @ (((unsigned) &PORTC)*8) + 1; #define PA2_bit BANKMASK(PORTC), 1 extern volatile __bit PC3E @ (((unsigned) &PORTE)*8) + 3; #define PC3E_bit BANKMASK(PORTE), 3 extern volatile __bit PCFG0 @ (((unsigned) &ANCON0)*8) + 0; #define PCFG0_bit BANKMASK(ANCON0), 0 extern volatile __bit PCFG1 @ (((unsigned) &ANCON0)*8) + 1; #define PCFG1_bit BANKMASK(ANCON0), 1 extern volatile __bit PCFG10 @ (((unsigned) &ANCON1)*8) + 2; #define PCFG10_bit BANKMASK(ANCON1), 2 extern volatile __bit PCFG2 @ (((unsigned) &ANCON0)*8) + 2; #define PCFG2_bit BANKMASK(ANCON0), 2 extern volatile __bit PCFG3 @ (((unsigned) &ANCON0)*8) + 3; #define PCFG3_bit BANKMASK(ANCON0), 3 extern volatile __bit PCFG4 @ (((unsigned) &ANCON0)*8) + 4; #define PCFG4_bit BANKMASK(ANCON0), 4 extern volatile __bit PCFG8 @ (((unsigned) &ANCON1)*8) + 0; #define PCFG8_bit BANKMASK(ANCON1), 0 extern volatile __bit PCFG9 @ (((unsigned) &ANCON1)*8) + 1; #define PCFG9_bit BANKMASK(ANCON1), 1 extern volatile __bit PD @ (((unsigned) &RCON)*8) + 2; #define PD_bit BANKMASK(RCON), 2 extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6; #define PEIE_bit BANKMASK(INTCON), 6 extern volatile __bit PEIE_GIEL @ (((unsigned) &INTCON)*8) + 6; #define PEIE_GIEL_bit BANKMASK(INTCON), 6 extern volatile __bit PEN @ (((unsigned) &SSPCON2)*8) + 2; #define PEN_bit BANKMASK(SSPCON2), 2 extern volatile __bit PLLEN @ (((unsigned) &OSCTUNE)*8) + 6; #define PLLEN_bit BANKMASK(OSCTUNE), 6 extern volatile __bit PMPTTL @ (((unsigned) &PADCFG1)*8) + 0; #define PMPTTL_bit BANKMASK(PADCFG1), 0 extern volatile __bit POR @ (((unsigned) &RCON)*8) + 1; #define POR_bit BANKMASK(RCON), 1 extern volatile __bit PRSEG0 @ (((unsigned) &BRGCON2)*8) + 0; #define PRSEG0_bit BANKMASK(BRGCON2), 0 extern volatile __bit PRSEG1 @ (((unsigned) &BRGCON2)*8) + 1; #define PRSEG1_bit BANKMASK(BRGCON2), 1 extern volatile __bit PRSEG2 @ (((unsigned) &BRGCON2)*8) + 2; #define PRSEG2_bit BANKMASK(BRGCON2), 2 extern volatile __bit PSA @ (((unsigned) &T0CON)*8) + 3; #define PSA_bit BANKMASK(T0CON), 3 extern volatile __bit PSPMD @ (((unsigned) &PMD1)*8) + 7; #define PSPMD_bit BANKMASK(PMD1), 7 extern volatile __bit PSS1AC0 @ (((unsigned) &ECCP1AS)*8) + 2; #define PSS1AC0_bit BANKMASK(ECCP1AS), 2 extern volatile __bit PSS1AC1 @ (((unsigned) &ECCP1AS)*8) + 3; #define PSS1AC1_bit BANKMASK(ECCP1AS), 3 extern volatile __bit PSS1BD0 @ (((unsigned) &ECCP1AS)*8) + 0; #define PSS1BD0_bit BANKMASK(ECCP1AS), 0 extern volatile __bit PSS1BD1 @ (((unsigned) &ECCP1AS)*8) + 1; #define PSS1BD1_bit BANKMASK(ECCP1AS), 1 extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0; #define RA0_bit BANKMASK(PORTA), 0 extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1; #define RA1_bit BANKMASK(PORTA), 1 extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2; #define RA2_bit BANKMASK(PORTA), 2 extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3; #define RA3_bit BANKMASK(PORTA), 3 extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5; #define RA5_bit BANKMASK(PORTA), 5 extern volatile __bit RA6 @ (((unsigned) &PORTA)*8) + 6; #define RA6_bit BANKMASK(PORTA), 6 extern volatile __bit RA7 @ (((unsigned) &PORTA)*8) + 7; #define RA7_bit BANKMASK(PORTA), 7 extern volatile __bit RB0DBEN @ (((unsigned) &RXB0CON)*8) + 2; #define RB0DBEN_bit BANKMASK(RXB0CON), 2 extern volatile __bit RB0DBEN_FILHIT2 @ (((unsigned) &RXB0CON)*8) + 2; #define RB0DBEN_FILHIT2_bit BANKMASK(RXB0CON), 2 extern volatile __bit RB2 @ (((unsigned) &PORTB)*8) + 2; #define RB2_bit BANKMASK(PORTB), 2 extern volatile __bit RB3 @ (((unsigned) &PORTB)*8) + 3; #define RB3_bit BANKMASK(PORTB), 3 extern volatile __bit RB4 @ (((unsigned) &PORTB)*8) + 4; #define RB4_bit BANKMASK(PORTB), 4 extern volatile __bit RB5 @ (((unsigned) &PORTB)*8) + 5; #define RB5_bit BANKMASK(PORTB), 5 extern volatile __bit RB6 @ (((unsigned) &PORTB)*8) + 6; #define RB6_bit BANKMASK(PORTB), 6 extern volatile __bit RB7 @ (((unsigned) &PORTB)*8) + 7; #define RB7_bit BANKMASK(PORTB), 7 extern volatile __bit RBIE @ (((unsigned) &INTCON)*8) + 3; #define RBIE_bit BANKMASK(INTCON), 3 extern volatile __bit RBIF @ (((unsigned) &INTCON)*8) + 0; #define RBIF_bit BANKMASK(INTCON), 0 extern volatile __bit RBIP @ (((unsigned) &INTCON2)*8) + 0; #define RBIP_bit BANKMASK(INTCON2), 0 extern volatile __bit RBPU @ (((unsigned) &INTCON2)*8) + 7; #define RBPU_bit BANKMASK(INTCON2), 7 extern volatile __bit RC0 @ (((unsigned) &PORTC)*8) + 0; #define RC0_bit BANKMASK(PORTC), 0 extern volatile __bit RC1 @ (((unsigned) &PORTC)*8) + 1; #define RC1_bit BANKMASK(PORTC), 1 extern volatile __bit RC1IE @ (((unsigned) &PIE1)*8) + 5; #define RC1IE_bit BANKMASK(PIE1), 5 extern volatile __bit RC1IF @ (((unsigned) &PIR1)*8) + 5; #define RC1IF_bit BANKMASK(PIR1), 5 extern volatile __bit RC1IP @ (((unsigned) &IPR1)*8) + 5; #define RC1IP_bit BANKMASK(IPR1), 5 extern volatile __bit RC2 @ (((unsigned) &PORTC)*8) + 2; #define RC2_bit BANKMASK(PORTC), 2 extern volatile __bit RC2IE @ (((unsigned) &PIE3)*8) + 5; #define RC2IE_bit BANKMASK(PIE3), 5 extern volatile __bit RC2IF @ (((unsigned) &PIR3)*8) + 5; #define RC2IF_bit BANKMASK(PIR3), 5 extern volatile __bit RC2IP @ (((unsigned) &IPR3)*8) + 5; #define RC2IP_bit BANKMASK(IPR3), 5 extern volatile __bit RC3 @ (((unsigned) &PORTC)*8) + 3; #define RC3_bit BANKMASK(PORTC), 3 extern volatile __bit RC4 @ (((unsigned) &PORTC)*8) + 4; #define RC4_bit BANKMASK(PORTC), 4 extern volatile __bit RC5 @ (((unsigned) &PORTC)*8) + 5; #define RC5_bit BANKMASK(PORTC), 5 extern volatile __bit RC6 @ (((unsigned) &PORTC)*8) + 6; #define RC6_bit BANKMASK(PORTC), 6 extern volatile __bit RC7 @ (((unsigned) &PORTC)*8) + 7; #define RC7_bit BANKMASK(PORTC), 7 extern volatile __bit RC8_9 @ (((unsigned) &RCSTA1)*8) + 6; #define RC8_9_bit BANKMASK(RCSTA1), 6 extern volatile __bit RC8_92 @ (((unsigned) &RCSTA2)*8) + 6; #define RC8_92_bit BANKMASK(RCSTA2), 6 extern volatile __bit RC9 @ (((unsigned) &RCSTA1)*8) + 6; #define RC9_bit BANKMASK(RCSTA1), 6 extern volatile __bit RC92 @ (((unsigned) &RCSTA2)*8) + 6; #define RC92_bit BANKMASK(RCSTA2), 6 extern volatile __bit RCD8 @ (((unsigned) &RCSTA1)*8) + 0; #define RCD8_bit BANKMASK(RCSTA1), 0 extern volatile __bit RCD82 @ (((unsigned) &RCSTA2)*8) + 0; #define RCD82_bit BANKMASK(RCSTA2), 0 extern volatile __bit RCEN @ (((unsigned) &SSPCON2)*8) + 3; #define RCEN_bit BANKMASK(SSPCON2), 3 extern volatile __bit RCIDL1 @ (((unsigned) &BAUDCON1)*8) + 6; #define RCIDL1_bit BANKMASK(BAUDCON1), 6 extern volatile __bit RCIDL2 @ (((unsigned) &BAUDCON2)*8) + 6; #define RCIDL2_bit BANKMASK(BAUDCON2), 6 extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5; #define RCIE_bit BANKMASK(PIE1), 5 extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5; #define RCIF_bit BANKMASK(PIR1), 5 extern volatile __bit RCIP @ (((unsigned) &IPR1)*8) + 5; #define RCIP_bit BANKMASK(IPR1), 5 extern volatile __bit RCMT1 @ (((unsigned) &BAUDCON1)*8) + 6; #define RCMT1_bit BANKMASK(BAUDCON1), 6 extern volatile __bit RCMT2 @ (((unsigned) &BAUDCON2)*8) + 6; #define RCMT2_bit BANKMASK(BAUDCON2), 6 extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0; #define RD_bit BANKMASK(EECON1), 0 extern volatile __bit RD163 @ (((unsigned) &T3CON)*8) + 7; #define RD163_bit BANKMASK(T3CON), 7 extern volatile __bit RE3 @ (((unsigned) &PORTE)*8) + 3; #define RE3_bit BANKMASK(PORTE), 3 extern volatile __bit READ_WRITE @ (((unsigned) &SSPSTAT)*8) + 2; #define READ_WRITE_bit BANKMASK(SSPSTAT), 2 extern volatile __bit REC0 @ (((unsigned) &RXERRCNT)*8) + 0; #define REC0_bit BANKMASK(RXERRCNT), 0 extern volatile __bit REC1 @ (((unsigned) &RXERRCNT)*8) + 1; #define REC1_bit BANKMASK(RXERRCNT), 1 extern volatile __bit REC2 @ (((unsigned) &RXERRCNT)*8) + 2; #define REC2_bit BANKMASK(RXERRCNT), 2 extern volatile __bit REC3 @ (((unsigned) &RXERRCNT)*8) + 3; #define REC3_bit BANKMASK(RXERRCNT), 3 extern volatile __bit REC4 @ (((unsigned) &RXERRCNT)*8) + 4; #define REC4_bit BANKMASK(RXERRCNT), 4 extern volatile __bit REC5 @ (((unsigned) &RXERRCNT)*8) + 5; #define REC5_bit BANKMASK(RXERRCNT), 5 extern volatile __bit REC6 @ (((unsigned) &RXERRCNT)*8) + 6; #define REC6_bit BANKMASK(RXERRCNT), 6 extern volatile __bit REC7 @ (((unsigned) &RXERRCNT)*8) + 7; #define REC7_bit BANKMASK(RXERRCNT), 7 extern volatile __bit REGSLP @ (((unsigned) &WDTCON)*8) + 7; #define REGSLP_bit BANKMASK(WDTCON), 7 extern volatile __bit RI @ (((unsigned) &RCON)*8) + 4; #define RI_bit BANKMASK(RCON), 4 extern volatile __bit RJPU @ (((unsigned) &PORTA)*8) + 7; #define RJPU_bit BANKMASK(PORTA), 7 extern volatile __bit RODIV0 @ (((unsigned) &REFOCON)*8) + 0; #define RODIV0_bit BANKMASK(REFOCON), 0 extern volatile __bit RODIV1 @ (((unsigned) &REFOCON)*8) + 1; #define RODIV1_bit BANKMASK(REFOCON), 1 extern volatile __bit RODIV2 @ (((unsigned) &REFOCON)*8) + 2; #define RODIV2_bit BANKMASK(REFOCON), 2 extern volatile __bit RODIV3 @ (((unsigned) &REFOCON)*8) + 3; #define RODIV3_bit BANKMASK(REFOCON), 3 extern volatile __bit ROON @ (((unsigned) &REFOCON)*8) + 7; #define ROON_bit BANKMASK(REFOCON), 7 extern volatile __bit ROSEL @ (((unsigned) &REFOCON)*8) + 4; #define ROSEL_bit BANKMASK(REFOCON), 4 extern volatile __bit ROSSLP @ (((unsigned) &REFOCON)*8) + 5; #define ROSSLP_bit BANKMASK(REFOCON), 5 extern volatile __bit RSEN @ (((unsigned) &SSPCON2)*8) + 1; #define RSEN_bit BANKMASK(SSPCON2), 1 extern volatile __bit RW @ (((unsigned) &SSPSTAT)*8) + 2; #define RW_bit BANKMASK(SSPSTAT), 2 extern volatile __bit RX91 @ (((unsigned) &RCSTA1)*8) + 6; #define RX91_bit BANKMASK(RCSTA1), 6 extern volatile __bit RX92 @ (((unsigned) &RCSTA2)*8) + 6; #define RX92_bit BANKMASK(RCSTA2), 6 extern volatile __bit RX9D1 @ (((unsigned) &RCSTA1)*8) + 0; #define RX9D1_bit BANKMASK(RCSTA1), 0 extern volatile __bit RX9D2 @ (((unsigned) &RCSTA2)*8) + 0; #define RX9D2_bit BANKMASK(RCSTA2), 0 extern volatile __bit RXB0D00 @ (((unsigned) &RXB0D0)*8) + 0; #define RXB0D00_bit BANKMASK(RXB0D0), 0 extern volatile __bit RXB0D01 @ (((unsigned) &RXB0D0)*8) + 1; #define RXB0D01_bit BANKMASK(RXB0D0), 1 extern volatile __bit RXB0D02 @ (((unsigned) &RXB0D0)*8) + 2; #define RXB0D02_bit BANKMASK(RXB0D0), 2 extern volatile __bit RXB0D03 @ (((unsigned) &RXB0D0)*8) + 3; #define RXB0D03_bit BANKMASK(RXB0D0), 3 extern volatile __bit RXB0D04 @ (((unsigned) &RXB0D0)*8) + 4; #define RXB0D04_bit BANKMASK(RXB0D0), 4 extern volatile __bit RXB0D05 @ (((unsigned) &RXB0D0)*8) + 5; #define RXB0D05_bit BANKMASK(RXB0D0), 5 extern volatile __bit RXB0D06 @ (((unsigned) &RXB0D0)*8) + 6; #define RXB0D06_bit BANKMASK(RXB0D0), 6 extern volatile __bit RXB0D07 @ (((unsigned) &RXB0D0)*8) + 7; #define RXB0D07_bit BANKMASK(RXB0D0), 7 extern volatile __bit RXB0D10 @ (((unsigned) &RXB0D1)*8) + 0; #define RXB0D10_bit BANKMASK(RXB0D1), 0 extern volatile __bit RXB0D11 @ (((unsigned) &RXB0D1)*8) + 1; #define RXB0D11_bit BANKMASK(RXB0D1), 1 extern volatile __bit RXB0D12 @ (((unsigned) &RXB0D1)*8) + 2; #define RXB0D12_bit BANKMASK(RXB0D1), 2 extern volatile __bit RXB0D13 @ (((unsigned) &RXB0D1)*8) + 3; #define RXB0D13_bit BANKMASK(RXB0D1), 3 extern volatile __bit RXB0D14 @ (((unsigned) &RXB0D1)*8) + 4; #define RXB0D14_bit BANKMASK(RXB0D1), 4 extern volatile __bit RXB0D15 @ (((unsigned) &RXB0D1)*8) + 5; #define RXB0D15_bit BANKMASK(RXB0D1), 5 extern volatile __bit RXB0D16 @ (((unsigned) &RXB0D1)*8) + 6; #define RXB0D16_bit BANKMASK(RXB0D1), 6 extern volatile __bit RXB0D17 @ (((unsigned) &RXB0D1)*8) + 7; #define RXB0D17_bit BANKMASK(RXB0D1), 7 extern volatile __bit RXB0D20 @ (((unsigned) &RXB0D2)*8) + 0; #define RXB0D20_bit BANKMASK(RXB0D2), 0 extern volatile __bit RXB0D21 @ (((unsigned) &RXB0D2)*8) + 1; #define RXB0D21_bit BANKMASK(RXB0D2), 1 extern volatile __bit RXB0D22 @ (((unsigned) &RXB0D2)*8) + 2; #define RXB0D22_bit BANKMASK(RXB0D2), 2 extern volatile __bit RXB0D23 @ (((unsigned) &RXB0D2)*8) + 3; #define RXB0D23_bit BANKMASK(RXB0D2), 3 extern volatile __bit RXB0D24 @ (((unsigned) &RXB0D2)*8) + 4; #define RXB0D24_bit BANKMASK(RXB0D2), 4 extern volatile __bit RXB0D25 @ (((unsigned) &RXB0D2)*8) + 5; #define RXB0D25_bit BANKMASK(RXB0D2), 5 extern volatile __bit RXB0D26 @ (((unsigned) &RXB0D2)*8) + 6; #define RXB0D26_bit BANKMASK(RXB0D2), 6 extern volatile __bit RXB0D27 @ (((unsigned) &RXB0D2)*8) + 7; #define RXB0D27_bit BANKMASK(RXB0D2), 7 extern volatile __bit RXB0D30 @ (((unsigned) &RXB0D3)*8) + 0; #define RXB0D30_bit BANKMASK(RXB0D3), 0 extern volatile __bit RXB0D31 @ (((unsigned) &RXB0D3)*8) + 1; #define RXB0D31_bit BANKMASK(RXB0D3), 1 extern volatile __bit RXB0D32 @ (((unsigned) &RXB0D3)*8) + 2; #define RXB0D32_bit BANKMASK(RXB0D3), 2 extern volatile __bit RXB0D33 @ (((unsigned) &RXB0D3)*8) + 3; #define RXB0D33_bit BANKMASK(RXB0D3), 3 extern volatile __bit RXB0D34 @ (((unsigned) &RXB0D3)*8) + 4; #define RXB0D34_bit BANKMASK(RXB0D3), 4 extern volatile __bit RXB0D35 @ (((unsigned) &RXB0D3)*8) + 5; #define RXB0D35_bit BANKMASK(RXB0D3), 5 extern volatile __bit RXB0D36 @ (((unsigned) &RXB0D3)*8) + 6; #define RXB0D36_bit BANKMASK(RXB0D3), 6 extern volatile __bit RXB0D37 @ (((unsigned) &RXB0D3)*8) + 7; #define RXB0D37_bit BANKMASK(RXB0D3), 7 extern volatile __bit RXB0D40 @ (((unsigned) &RXB0D4)*8) + 0; #define RXB0D40_bit BANKMASK(RXB0D4), 0 extern volatile __bit RXB0D41 @ (((unsigned) &RXB0D4)*8) + 1; #define RXB0D41_bit BANKMASK(RXB0D4), 1 extern volatile __bit RXB0D42 @ (((unsigned) &RXB0D4)*8) + 2; #define RXB0D42_bit BANKMASK(RXB0D4), 2 extern volatile __bit RXB0D43 @ (((unsigned) &RXB0D4)*8) + 3; #define RXB0D43_bit BANKMASK(RXB0D4), 3 extern volatile __bit RXB0D44 @ (((unsigned) &RXB0D4)*8) + 4; #define RXB0D44_bit BANKMASK(RXB0D4), 4 extern volatile __bit RXB0D45 @ (((unsigned) &RXB0D4)*8) + 5; #define RXB0D45_bit BANKMASK(RXB0D4), 5 extern volatile __bit RXB0D46 @ (((unsigned) &RXB0D4)*8) + 6; #define RXB0D46_bit BANKMASK(RXB0D4), 6 extern volatile __bit RXB0D47 @ (((unsigned) &RXB0D4)*8) + 7; #define RXB0D47_bit BANKMASK(RXB0D4), 7 extern volatile __bit RXB0D50 @ (((unsigned) &RXB0D5)*8) + 0; #define RXB0D50_bit BANKMASK(RXB0D5), 0 extern volatile __bit RXB0D51 @ (((unsigned) &RXB0D5)*8) + 1; #define RXB0D51_bit BANKMASK(RXB0D5), 1 extern volatile __bit RXB0D52 @ (((unsigned) &RXB0D5)*8) + 2; #define RXB0D52_bit BANKMASK(RXB0D5), 2 extern volatile __bit RXB0D53 @ (((unsigned) &RXB0D5)*8) + 3; #define RXB0D53_bit BANKMASK(RXB0D5), 3 extern volatile __bit RXB0D54 @ (((unsigned) &RXB0D5)*8) + 4; #define RXB0D54_bit BANKMASK(RXB0D5), 4 extern volatile __bit RXB0D55 @ (((unsigned) &RXB0D5)*8) + 5; #define RXB0D55_bit BANKMASK(RXB0D5), 5 extern volatile __bit RXB0D56 @ (((unsigned) &RXB0D5)*8) + 6; #define RXB0D56_bit BANKMASK(RXB0D5), 6 extern volatile __bit RXB0D57 @ (((unsigned) &RXB0D5)*8) + 7; #define RXB0D57_bit BANKMASK(RXB0D5), 7 extern volatile __bit RXB0D60 @ (((unsigned) &RXB0D6)*8) + 0; #define RXB0D60_bit BANKMASK(RXB0D6), 0 extern volatile __bit RXB0D61 @ (((unsigned) &RXB0D6)*8) + 1; #define RXB0D61_bit BANKMASK(RXB0D6), 1 extern volatile __bit RXB0D62 @ (((unsigned) &RXB0D6)*8) + 2; #define RXB0D62_bit BANKMASK(RXB0D6), 2 extern volatile __bit RXB0D63 @ (((unsigned) &RXB0D6)*8) + 3; #define RXB0D63_bit BANKMASK(RXB0D6), 3 extern volatile __bit RXB0D64 @ (((unsigned) &RXB0D6)*8) + 4; #define RXB0D64_bit BANKMASK(RXB0D6), 4 extern volatile __bit RXB0D65 @ (((unsigned) &RXB0D6)*8) + 5; #define RXB0D65_bit BANKMASK(RXB0D6), 5 extern volatile __bit RXB0D66 @ (((unsigned) &RXB0D6)*8) + 6; #define RXB0D66_bit BANKMASK(RXB0D6), 6 extern volatile __bit RXB0D67 @ (((unsigned) &RXB0D6)*8) + 7; #define RXB0D67_bit BANKMASK(RXB0D6), 7 extern volatile __bit RXB0D70 @ (((unsigned) &RXB0D7)*8) + 0; #define RXB0D70_bit BANKMASK(RXB0D7), 0 extern volatile __bit RXB0D71 @ (((unsigned) &RXB0D7)*8) + 1; #define RXB0D71_bit BANKMASK(RXB0D7), 1 extern volatile __bit RXB0D72 @ (((unsigned) &RXB0D7)*8) + 2; #define RXB0D72_bit BANKMASK(RXB0D7), 2 extern volatile __bit RXB0D73 @ (((unsigned) &RXB0D7)*8) + 3; #define RXB0D73_bit BANKMASK(RXB0D7), 3 extern volatile __bit RXB0D74 @ (((unsigned) &RXB0D7)*8) + 4; #define RXB0D74_bit BANKMASK(RXB0D7), 4 extern volatile __bit RXB0D75 @ (((unsigned) &RXB0D7)*8) + 5; #define RXB0D75_bit BANKMASK(RXB0D7), 5 extern volatile __bit RXB0D76 @ (((unsigned) &RXB0D7)*8) + 6; #define RXB0D76_bit BANKMASK(RXB0D7), 6 extern volatile __bit RXB0D77 @ (((unsigned) &RXB0D7)*8) + 7; #define RXB0D77_bit BANKMASK(RXB0D7), 7 extern volatile __bit RXB0DLC0 @ (((unsigned) &RXB0DLC)*8) + 0; #define RXB0DLC0_bit BANKMASK(RXB0DLC), 0 extern volatile __bit RXB0DLC1 @ (((unsigned) &RXB0DLC)*8) + 1; #define RXB0DLC1_bit BANKMASK(RXB0DLC), 1 extern volatile __bit RXB0DLC2 @ (((unsigned) &RXB0DLC)*8) + 2; #define RXB0DLC2_bit BANKMASK(RXB0DLC), 2 extern volatile __bit RXB0DLC3 @ (((unsigned) &RXB0DLC)*8) + 3; #define RXB0DLC3_bit BANKMASK(RXB0DLC), 3 extern volatile __bit RXB0EID0 @ (((unsigned) &RXB0EIDL)*8) + 0; #define RXB0EID0_bit BANKMASK(RXB0EIDL), 0 extern volatile __bit RXB0EID1 @ (((unsigned) &RXB0EIDL)*8) + 1; #define RXB0EID1_bit BANKMASK(RXB0EIDL), 1 extern volatile __bit RXB0EID10 @ (((unsigned) &RXB0EIDH)*8) + 2; #define RXB0EID10_bit BANKMASK(RXB0EIDH), 2 extern volatile __bit RXB0EID11 @ (((unsigned) &RXB0EIDH)*8) + 3; #define RXB0EID11_bit BANKMASK(RXB0EIDH), 3 extern volatile __bit RXB0EID12 @ (((unsigned) &RXB0EIDH)*8) + 4; #define RXB0EID12_bit BANKMASK(RXB0EIDH), 4 extern volatile __bit RXB0EID13 @ (((unsigned) &RXB0EIDH)*8) + 5; #define RXB0EID13_bit BANKMASK(RXB0EIDH), 5 extern volatile __bit RXB0EID14 @ (((unsigned) &RXB0EIDH)*8) + 6; #define RXB0EID14_bit BANKMASK(RXB0EIDH), 6 extern volatile __bit RXB0EID15 @ (((unsigned) &RXB0EIDH)*8) + 7; #define RXB0EID15_bit BANKMASK(RXB0EIDH), 7 extern volatile __bit RXB0EID16 @ (((unsigned) &RXB0SIDL)*8) + 0; #define RXB0EID16_bit BANKMASK(RXB0SIDL), 0 extern volatile __bit RXB0EID17 @ (((unsigned) &RXB0SIDL)*8) + 1; #define RXB0EID17_bit BANKMASK(RXB0SIDL), 1 extern volatile __bit RXB0EID2 @ (((unsigned) &RXB0EIDL)*8) + 2; #define RXB0EID2_bit BANKMASK(RXB0EIDL), 2 extern volatile __bit RXB0EID3 @ (((unsigned) &RXB0EIDL)*8) + 3; #define RXB0EID3_bit BANKMASK(RXB0EIDL), 3 extern volatile __bit RXB0EID4 @ (((unsigned) &RXB0EIDL)*8) + 4; #define RXB0EID4_bit BANKMASK(RXB0EIDL), 4 extern volatile __bit RXB0EID5 @ (((unsigned) &RXB0EIDL)*8) + 5; #define RXB0EID5_bit BANKMASK(RXB0EIDL), 5 extern volatile __bit RXB0EID6 @ (((unsigned) &RXB0EIDL)*8) + 6; #define RXB0EID6_bit BANKMASK(RXB0EIDL), 6 extern volatile __bit RXB0EID7 @ (((unsigned) &RXB0EIDL)*8) + 7; #define RXB0EID7_bit BANKMASK(RXB0EIDL), 7 extern volatile __bit RXB0EID8 @ (((unsigned) &RXB0EIDH)*8) + 0; #define RXB0EID8_bit BANKMASK(RXB0EIDH), 0 extern volatile __bit RXB0EID9 @ (((unsigned) &RXB0EIDH)*8) + 1; #define RXB0EID9_bit BANKMASK(RXB0EIDH), 1 extern volatile __bit RXB0EXID @ (((unsigned) &RXB0SIDL)*8) + 3; #define RXB0EXID_bit BANKMASK(RXB0SIDL), 3 extern volatile __bit RXB0FILHIT0 @ (((unsigned) &RXB0CON)*8) + 0; #define RXB0FILHIT0_bit BANKMASK(RXB0CON), 0 extern volatile __bit RXB0FILHIT1 @ (((unsigned) &RXB0CON)*8) + 1; #define RXB0FILHIT1_bit BANKMASK(RXB0CON), 1 extern volatile __bit RXB0FILHIT2 @ (((unsigned) &RXB0CON)*8) + 2; #define RXB0FILHIT2_bit BANKMASK(RXB0CON), 2 extern volatile __bit RXB0FILHIT3 @ (((unsigned) &RXB0CON)*8) + 3; #define RXB0FILHIT3_bit BANKMASK(RXB0CON), 3 extern volatile __bit RXB0FILHIT4 @ (((unsigned) &RXB0CON)*8) + 4; #define RXB0FILHIT4_bit BANKMASK(RXB0CON), 4 extern volatile __bit RXB0FUL @ (((unsigned) &RXB0CON)*8) + 7; #define RXB0FUL_bit BANKMASK(RXB0CON), 7 extern volatile __bit RXB0IF @ (((unsigned) &PIR5)*8) + 0; #define RXB0IF_bit BANKMASK(PIR5), 0 extern volatile __bit RXB0IP @ (((unsigned) &IPR5)*8) + 0; #define RXB0IP_bit BANKMASK(IPR5), 0 extern volatile __bit RXB0M0 @ (((unsigned) &RXB0CON)*8) + 5; #define RXB0M0_bit BANKMASK(RXB0CON), 5 extern volatile __bit RXB0M1 @ (((unsigned) &RXB0CON)*8) + 6; #define RXB0M1_bit BANKMASK(RXB0CON), 6 extern volatile __bit RXB0OVFL @ (((unsigned) &COMSTAT)*8) + 7; #define RXB0OVFL_bit BANKMASK(COMSTAT), 7 extern volatile __bit RXB0RB0 @ (((unsigned) &RXB0DLC)*8) + 4; #define RXB0RB0_bit BANKMASK(RXB0DLC), 4 extern volatile __bit RXB0RB1 @ (((unsigned) &RXB0DLC)*8) + 5; #define RXB0RB1_bit BANKMASK(RXB0DLC), 5 extern volatile __bit RXB0RTR @ (((unsigned) &RXB0DLC)*8) + 6; #define RXB0RTR_bit BANKMASK(RXB0DLC), 6 extern volatile __bit RXB0RTRR0 @ (((unsigned) &RXB0CON)*8) + 3; #define RXB0RTRR0_bit BANKMASK(RXB0CON), 3 extern volatile __bit RXB0RTRRO @ (((unsigned) &RXB0CON)*8) + 5; #define RXB0RTRRO_bit BANKMASK(RXB0CON), 5 extern volatile __bit RXB0SID0 @ (((unsigned) &RXB0SIDL)*8) + 5; #define RXB0SID0_bit BANKMASK(RXB0SIDL), 5 extern volatile __bit RXB0SID1 @ (((unsigned) &RXB0SIDL)*8) + 6; #define RXB0SID1_bit BANKMASK(RXB0SIDL), 6 extern volatile __bit RXB0SID10 @ (((unsigned) &RXB0SIDH)*8) + 7; #define RXB0SID10_bit BANKMASK(RXB0SIDH), 7 extern volatile __bit RXB0SID2 @ (((unsigned) &RXB0SIDL)*8) + 7; #define RXB0SID2_bit BANKMASK(RXB0SIDL), 7 extern volatile __bit RXB0SID3 @ (((unsigned) &RXB0SIDH)*8) + 0; #define RXB0SID3_bit BANKMASK(RXB0SIDH), 0 extern volatile __bit RXB0SID4 @ (((unsigned) &RXB0SIDH)*8) + 1; #define RXB0SID4_bit BANKMASK(RXB0SIDH), 1 extern volatile __bit RXB0SID5 @ (((unsigned) &RXB0SIDH)*8) + 2; #define RXB0SID5_bit BANKMASK(RXB0SIDH), 2 extern volatile __bit RXB0SID6 @ (((unsigned) &RXB0SIDH)*8) + 3; #define RXB0SID6_bit BANKMASK(RXB0SIDH), 3 extern volatile __bit RXB0SID7 @ (((unsigned) &RXB0SIDH)*8) + 4; #define RXB0SID7_bit BANKMASK(RXB0SIDH), 4 extern volatile __bit RXB0SID8 @ (((unsigned) &RXB0SIDH)*8) + 5; #define RXB0SID8_bit BANKMASK(RXB0SIDH), 5 extern volatile __bit RXB0SID9 @ (((unsigned) &RXB0SIDH)*8) + 6; #define RXB0SID9_bit BANKMASK(RXB0SIDH), 6 extern volatile __bit RXB0SRR @ (((unsigned) &RXB0SIDL)*8) + 4; #define RXB0SRR_bit BANKMASK(RXB0SIDL), 4 extern volatile __bit RXB1D00 @ (((unsigned) &RXB1D0)*8) + 0; #define RXB1D00_bit BANKMASK(RXB1D0), 0 extern volatile __bit RXB1D01 @ (((unsigned) &RXB1D0)*8) + 1; #define RXB1D01_bit BANKMASK(RXB1D0), 1 extern volatile __bit RXB1D02 @ (((unsigned) &RXB1D0)*8) + 2; #define RXB1D02_bit BANKMASK(RXB1D0), 2 extern volatile __bit RXB1D03 @ (((unsigned) &RXB1D0)*8) + 3; #define RXB1D03_bit BANKMASK(RXB1D0), 3 extern volatile __bit RXB1D04 @ (((unsigned) &RXB1D0)*8) + 4; #define RXB1D04_bit BANKMASK(RXB1D0), 4 extern volatile __bit RXB1D05 @ (((unsigned) &RXB1D0)*8) + 5; #define RXB1D05_bit BANKMASK(RXB1D0), 5 extern volatile __bit RXB1D06 @ (((unsigned) &RXB1D0)*8) + 6; #define RXB1D06_bit BANKMASK(RXB1D0), 6 extern volatile __bit RXB1D07 @ (((unsigned) &RXB1D0)*8) + 7; #define RXB1D07_bit BANKMASK(RXB1D0), 7 extern volatile __bit RXB1D10 @ (((unsigned) &RXB1D1)*8) + 0; #define RXB1D10_bit BANKMASK(RXB1D1), 0 extern volatile __bit RXB1D11 @ (((unsigned) &RXB1D1)*8) + 1; #define RXB1D11_bit BANKMASK(RXB1D1), 1 extern volatile __bit RXB1D12 @ (((unsigned) &RXB1D1)*8) + 2; #define RXB1D12_bit BANKMASK(RXB1D1), 2 extern volatile __bit RXB1D13 @ (((unsigned) &RXB1D1)*8) + 3; #define RXB1D13_bit BANKMASK(RXB1D1), 3 extern volatile __bit RXB1D14 @ (((unsigned) &RXB1D1)*8) + 4; #define RXB1D14_bit BANKMASK(RXB1D1), 4 extern volatile __bit RXB1D15 @ (((unsigned) &RXB1D1)*8) + 5; #define RXB1D15_bit BANKMASK(RXB1D1), 5 extern volatile __bit RXB1D16 @ (((unsigned) &RXB1D1)*8) + 6; #define RXB1D16_bit BANKMASK(RXB1D1), 6 extern volatile __bit RXB1D17 @ (((unsigned) &RXB1D1)*8) + 7; #define RXB1D17_bit BANKMASK(RXB1D1), 7 extern volatile __bit RXB1D20 @ (((unsigned) &RXB1D2)*8) + 0; #define RXB1D20_bit BANKMASK(RXB1D2), 0 extern volatile __bit RXB1D21 @ (((unsigned) &RXB1D2)*8) + 1; #define RXB1D21_bit BANKMASK(RXB1D2), 1 extern volatile __bit RXB1D22 @ (((unsigned) &RXB1D2)*8) + 2; #define RXB1D22_bit BANKMASK(RXB1D2), 2 extern volatile __bit RXB1D23 @ (((unsigned) &RXB1D2)*8) + 3; #define RXB1D23_bit BANKMASK(RXB1D2), 3 extern volatile __bit RXB1D24 @ (((unsigned) &RXB1D2)*8) + 4; #define RXB1D24_bit BANKMASK(RXB1D2), 4 extern volatile __bit RXB1D25 @ (((unsigned) &RXB1D2)*8) + 5; #define RXB1D25_bit BANKMASK(RXB1D2), 5 extern volatile __bit RXB1D26 @ (((unsigned) &RXB1D2)*8) + 6; #define RXB1D26_bit BANKMASK(RXB1D2), 6 extern volatile __bit RXB1D27 @ (((unsigned) &RXB1D2)*8) + 7; #define RXB1D27_bit BANKMASK(RXB1D2), 7 extern volatile __bit RXB1D30 @ (((unsigned) &RXB1D3)*8) + 0; #define RXB1D30_bit BANKMASK(RXB1D3), 0 extern volatile __bit RXB1D31 @ (((unsigned) &RXB1D3)*8) + 1; #define RXB1D31_bit BANKMASK(RXB1D3), 1 extern volatile __bit RXB1D32 @ (((unsigned) &RXB1D3)*8) + 2; #define RXB1D32_bit BANKMASK(RXB1D3), 2 extern volatile __bit RXB1D33 @ (((unsigned) &RXB1D3)*8) + 3; #define RXB1D33_bit BANKMASK(RXB1D3), 3 extern volatile __bit RXB1D34 @ (((unsigned) &RXB1D3)*8) + 4; #define RXB1D34_bit BANKMASK(RXB1D3), 4 extern volatile __bit RXB1D35 @ (((unsigned) &RXB1D3)*8) + 5; #define RXB1D35_bit BANKMASK(RXB1D3), 5 extern volatile __bit RXB1D36 @ (((unsigned) &RXB1D3)*8) + 6; #define RXB1D36_bit BANKMASK(RXB1D3), 6 extern volatile __bit RXB1D37 @ (((unsigned) &RXB1D3)*8) + 7; #define RXB1D37_bit BANKMASK(RXB1D3), 7 extern volatile __bit RXB1D40 @ (((unsigned) &RXB1D4)*8) + 0; #define RXB1D40_bit BANKMASK(RXB1D4), 0 extern volatile __bit RXB1D41 @ (((unsigned) &RXB1D4)*8) + 1; #define RXB1D41_bit BANKMASK(RXB1D4), 1 extern volatile __bit RXB1D42 @ (((unsigned) &RXB1D4)*8) + 2; #define RXB1D42_bit BANKMASK(RXB1D4), 2 extern volatile __bit RXB1D43 @ (((unsigned) &RXB1D4)*8) + 3; #define RXB1D43_bit BANKMASK(RXB1D4), 3 extern volatile __bit RXB1D44 @ (((unsigned) &RXB1D4)*8) + 4; #define RXB1D44_bit BANKMASK(RXB1D4), 4 extern volatile __bit RXB1D45 @ (((unsigned) &RXB1D4)*8) + 5; #define RXB1D45_bit BANKMASK(RXB1D4), 5 extern volatile __bit RXB1D46 @ (((unsigned) &RXB1D4)*8) + 6; #define RXB1D46_bit BANKMASK(RXB1D4), 6 extern volatile __bit RXB1D47 @ (((unsigned) &RXB1D4)*8) + 7; #define RXB1D47_bit BANKMASK(RXB1D4), 7 extern volatile __bit RXB1D50 @ (((unsigned) &RXB1D5)*8) + 0; #define RXB1D50_bit BANKMASK(RXB1D5), 0 extern volatile __bit RXB1D51 @ (((unsigned) &RXB1D5)*8) + 1; #define RXB1D51_bit BANKMASK(RXB1D5), 1 extern volatile __bit RXB1D52 @ (((unsigned) &RXB1D5)*8) + 2; #define RXB1D52_bit BANKMASK(RXB1D5), 2 extern volatile __bit RXB1D53 @ (((unsigned) &RXB1D5)*8) + 3; #define RXB1D53_bit BANKMASK(RXB1D5), 3 extern volatile __bit RXB1D54 @ (((unsigned) &RXB1D5)*8) + 4; #define RXB1D54_bit BANKMASK(RXB1D5), 4 extern volatile __bit RXB1D55 @ (((unsigned) &RXB1D5)*8) + 5; #define RXB1D55_bit BANKMASK(RXB1D5), 5 extern volatile __bit RXB1D56 @ (((unsigned) &RXB1D5)*8) + 6; #define RXB1D56_bit BANKMASK(RXB1D5), 6 extern volatile __bit RXB1D57 @ (((unsigned) &RXB1D5)*8) + 7; #define RXB1D57_bit BANKMASK(RXB1D5), 7 extern volatile __bit RXB1D60 @ (((unsigned) &RXB1D6)*8) + 0; #define RXB1D60_bit BANKMASK(RXB1D6), 0 extern volatile __bit RXB1D61 @ (((unsigned) &RXB1D6)*8) + 1; #define RXB1D61_bit BANKMASK(RXB1D6), 1 extern volatile __bit RXB1D62 @ (((unsigned) &RXB1D6)*8) + 2; #define RXB1D62_bit BANKMASK(RXB1D6), 2 extern volatile __bit RXB1D63 @ (((unsigned) &RXB1D6)*8) + 3; #define RXB1D63_bit BANKMASK(RXB1D6), 3 extern volatile __bit RXB1D64 @ (((unsigned) &RXB1D6)*8) + 4; #define RXB1D64_bit BANKMASK(RXB1D6), 4 extern volatile __bit RXB1D65 @ (((unsigned) &RXB1D6)*8) + 5; #define RXB1D65_bit BANKMASK(RXB1D6), 5 extern volatile __bit RXB1D66 @ (((unsigned) &RXB1D6)*8) + 6; #define RXB1D66_bit BANKMASK(RXB1D6), 6 extern volatile __bit RXB1D67 @ (((unsigned) &RXB1D6)*8) + 7; #define RXB1D67_bit BANKMASK(RXB1D6), 7 extern volatile __bit RXB1D70 @ (((unsigned) &RXB1D7)*8) + 0; #define RXB1D70_bit BANKMASK(RXB1D7), 0 extern volatile __bit RXB1D71 @ (((unsigned) &RXB1D7)*8) + 1; #define RXB1D71_bit BANKMASK(RXB1D7), 1 extern volatile __bit RXB1D72 @ (((unsigned) &RXB1D7)*8) + 2; #define RXB1D72_bit BANKMASK(RXB1D7), 2 extern volatile __bit RXB1D73 @ (((unsigned) &RXB1D7)*8) + 3; #define RXB1D73_bit BANKMASK(RXB1D7), 3 extern volatile __bit RXB1D74 @ (((unsigned) &RXB1D7)*8) + 4; #define RXB1D74_bit BANKMASK(RXB1D7), 4 extern volatile __bit RXB1D75 @ (((unsigned) &RXB1D7)*8) + 5; #define RXB1D75_bit BANKMASK(RXB1D7), 5 extern volatile __bit RXB1D76 @ (((unsigned) &RXB1D7)*8) + 6; #define RXB1D76_bit BANKMASK(RXB1D7), 6 extern volatile __bit RXB1D77 @ (((unsigned) &RXB1D7)*8) + 7; #define RXB1D77_bit BANKMASK(RXB1D7), 7 extern volatile __bit RXB1DLC0 @ (((unsigned) &RXB1DLC)*8) + 0; #define RXB1DLC0_bit BANKMASK(RXB1DLC), 0 extern volatile __bit RXB1DLC1 @ (((unsigned) &RXB1DLC)*8) + 1; #define RXB1DLC1_bit BANKMASK(RXB1DLC), 1 extern volatile __bit RXB1DLC2 @ (((unsigned) &RXB1DLC)*8) + 2; #define RXB1DLC2_bit BANKMASK(RXB1DLC), 2 extern volatile __bit RXB1DLC3 @ (((unsigned) &RXB1DLC)*8) + 3; #define RXB1DLC3_bit BANKMASK(RXB1DLC), 3 extern volatile __bit RXB1EID0 @ (((unsigned) &RXB1EIDL)*8) + 0; #define RXB1EID0_bit BANKMASK(RXB1EIDL), 0 extern volatile __bit RXB1EID1 @ (((unsigned) &RXB1EIDL)*8) + 1; #define RXB1EID1_bit BANKMASK(RXB1EIDL), 1 extern volatile __bit RXB1EID10 @ (((unsigned) &RXB1EIDH)*8) + 2; #define RXB1EID10_bit BANKMASK(RXB1EIDH), 2 extern volatile __bit RXB1EID11 @ (((unsigned) &RXB1EIDH)*8) + 3; #define RXB1EID11_bit BANKMASK(RXB1EIDH), 3 extern volatile __bit RXB1EID12 @ (((unsigned) &RXB1EIDH)*8) + 4; #define RXB1EID12_bit BANKMASK(RXB1EIDH), 4 extern volatile __bit RXB1EID13 @ (((unsigned) &RXB1EIDH)*8) + 5; #define RXB1EID13_bit BANKMASK(RXB1EIDH), 5 extern volatile __bit RXB1EID14 @ (((unsigned) &RXB1EIDH)*8) + 6; #define RXB1EID14_bit BANKMASK(RXB1EIDH), 6 extern volatile __bit RXB1EID15 @ (((unsigned) &RXB1EIDH)*8) + 7; #define RXB1EID15_bit BANKMASK(RXB1EIDH), 7 extern volatile __bit RXB1EID16 @ (((unsigned) &RXB1SIDL)*8) + 0; #define RXB1EID16_bit BANKMASK(RXB1SIDL), 0 extern volatile __bit RXB1EID17 @ (((unsigned) &RXB1SIDL)*8) + 1; #define RXB1EID17_bit BANKMASK(RXB1SIDL), 1 extern volatile __bit RXB1EID2 @ (((unsigned) &RXB1EIDL)*8) + 2; #define RXB1EID2_bit BANKMASK(RXB1EIDL), 2 extern volatile __bit RXB1EID3 @ (((unsigned) &RXB1EIDL)*8) + 3; #define RXB1EID3_bit BANKMASK(RXB1EIDL), 3 extern volatile __bit RXB1EID4 @ (((unsigned) &RXB1EIDL)*8) + 4; #define RXB1EID4_bit BANKMASK(RXB1EIDL), 4 extern volatile __bit RXB1EID5 @ (((unsigned) &RXB1EIDL)*8) + 5; #define RXB1EID5_bit BANKMASK(RXB1EIDL), 5 extern volatile __bit RXB1EID6 @ (((unsigned) &RXB1EIDL)*8) + 6; #define RXB1EID6_bit BANKMASK(RXB1EIDL), 6 extern volatile __bit RXB1EID7 @ (((unsigned) &RXB1EIDL)*8) + 7; #define RXB1EID7_bit BANKMASK(RXB1EIDL), 7 extern volatile __bit RXB1EID8 @ (((unsigned) &RXB1EIDH)*8) + 0; #define RXB1EID8_bit BANKMASK(RXB1EIDH), 0 extern volatile __bit RXB1EID9 @ (((unsigned) &RXB1EIDH)*8) + 1; #define RXB1EID9_bit BANKMASK(RXB1EIDH), 1 extern volatile __bit RXB1EXID @ (((unsigned) &RXB1SIDL)*8) + 3; #define RXB1EXID_bit BANKMASK(RXB1SIDL), 3 extern volatile __bit RXB1FILHIT0 @ (((unsigned) &RXB1CON)*8) + 0; #define RXB1FILHIT0_bit BANKMASK(RXB1CON), 0 extern volatile __bit RXB1FILHIT1 @ (((unsigned) &RXB1CON)*8) + 1; #define RXB1FILHIT1_bit BANKMASK(RXB1CON), 1 extern volatile __bit RXB1FILHIT2 @ (((unsigned) &RXB1CON)*8) + 2; #define RXB1FILHIT2_bit BANKMASK(RXB1CON), 2 extern volatile __bit RXB1FILHIT3 @ (((unsigned) &RXB1CON)*8) + 3; #define RXB1FILHIT3_bit BANKMASK(RXB1CON), 3 extern volatile __bit RXB1FILHIT4 @ (((unsigned) &RXB1CON)*8) + 4; #define RXB1FILHIT4_bit BANKMASK(RXB1CON), 4 extern volatile __bit RXB1FUL @ (((unsigned) &RXB1CON)*8) + 7; #define RXB1FUL_bit BANKMASK(RXB1CON), 7 extern volatile __bit RXB1IF @ (((unsigned) &PIR5)*8) + 1; #define RXB1IF_bit BANKMASK(PIR5), 1 extern volatile __bit RXB1IP @ (((unsigned) &IPR5)*8) + 1; #define RXB1IP_bit BANKMASK(IPR5), 1 extern volatile __bit RXB1M0 @ (((unsigned) &RXB1CON)*8) + 5; #define RXB1M0_bit BANKMASK(RXB1CON), 5 extern volatile __bit RXB1M1 @ (((unsigned) &RXB1CON)*8) + 6; #define RXB1M1_bit BANKMASK(RXB1CON), 6 extern volatile __bit RXB1OVFL @ (((unsigned) &COMSTAT)*8) + 6; #define RXB1OVFL_bit BANKMASK(COMSTAT), 6 extern volatile __bit RXB1RB0 @ (((unsigned) &RXB1DLC)*8) + 4; #define RXB1RB0_bit BANKMASK(RXB1DLC), 4 extern volatile __bit RXB1RB1 @ (((unsigned) &RXB1DLC)*8) + 5; #define RXB1RB1_bit BANKMASK(RXB1DLC), 5 extern volatile __bit RXB1RTR @ (((unsigned) &RXB1DLC)*8) + 6; #define RXB1RTR_bit BANKMASK(RXB1DLC), 6 extern volatile __bit RXB1RTRR0 @ (((unsigned) &RXB1CON)*8) + 3; #define RXB1RTRR0_bit BANKMASK(RXB1CON), 3 extern volatile __bit RXB1RTRRO @ (((unsigned) &RXB1CON)*8) + 5; #define RXB1RTRRO_bit BANKMASK(RXB1CON), 5 extern volatile __bit RXB1SID0 @ (((unsigned) &RXB1SIDL)*8) + 5; #define RXB1SID0_bit BANKMASK(RXB1SIDL), 5 extern volatile __bit RXB1SID1 @ (((unsigned) &RXB1SIDL)*8) + 6; #define RXB1SID1_bit BANKMASK(RXB1SIDL), 6 extern volatile __bit RXB1SID10 @ (((unsigned) &RXB1SIDH)*8) + 7; #define RXB1SID10_bit BANKMASK(RXB1SIDH), 7 extern volatile __bit RXB1SID2 @ (((unsigned) &RXB1SIDL)*8) + 7; #define RXB1SID2_bit BANKMASK(RXB1SIDL), 7 extern volatile __bit RXB1SID3 @ (((unsigned) &RXB1SIDH)*8) + 0; #define RXB1SID3_bit BANKMASK(RXB1SIDH), 0 extern volatile __bit RXB1SID4 @ (((unsigned) &RXB1SIDH)*8) + 1; #define RXB1SID4_bit BANKMASK(RXB1SIDH), 1 extern volatile __bit RXB1SID5 @ (((unsigned) &RXB1SIDH)*8) + 2; #define RXB1SID5_bit BANKMASK(RXB1SIDH), 2 extern volatile __bit RXB1SID6 @ (((unsigned) &RXB1SIDH)*8) + 3; #define RXB1SID6_bit BANKMASK(RXB1SIDH), 3 extern volatile __bit RXB1SID7 @ (((unsigned) &RXB1SIDH)*8) + 4; #define RXB1SID7_bit BANKMASK(RXB1SIDH), 4 extern volatile __bit RXB1SID8 @ (((unsigned) &RXB1SIDH)*8) + 5; #define RXB1SID8_bit BANKMASK(RXB1SIDH), 5 extern volatile __bit RXB1SID9 @ (((unsigned) &RXB1SIDH)*8) + 6; #define RXB1SID9_bit BANKMASK(RXB1SIDH), 6 extern volatile __bit RXB1SRR @ (((unsigned) &RXB1SIDL)*8) + 4; #define RXB1SRR_bit BANKMASK(RXB1SIDL), 4 extern volatile __bit RXBNIE @ (((unsigned) &PIE3)*8) + 1; #define RXBNIE_bit BANKMASK(PIE3), 1 extern volatile __bit RXBNIF @ (((unsigned) &PIR3)*8) + 1; #define RXBNIF_bit BANKMASK(PIR3), 1 extern volatile __bit RXBNIP @ (((unsigned) &IPR3)*8) + 1; #define RXBNIP_bit BANKMASK(IPR3), 1 extern volatile __bit RXBNOVFL @ (((unsigned) &COMSTAT)*8) + 6; #define RXBNOVFL_bit BANKMASK(COMSTAT), 6 extern volatile __bit RXBP @ (((unsigned) &COMSTAT)*8) + 3; #define RXBP_bit BANKMASK(COMSTAT), 3 extern volatile __bit RXBnIE @ (((unsigned) &PIE5)*8) + 1; #define RXBnIE_bit BANKMASK(PIE5), 1 extern volatile __bit RXBnIF @ (((unsigned) &PIR5)*8) + 1; #define RXBnIF_bit BANKMASK(PIR5), 1 extern volatile __bit RXBnIP @ (((unsigned) &IPR5)*8) + 1; #define RXBnIP_bit BANKMASK(IPR5), 1 extern volatile __bit RXDTP1 @ (((unsigned) &BAUDCON1)*8) + 5; #define RXDTP1_bit BANKMASK(BAUDCON1), 5 extern volatile __bit RXDTP2 @ (((unsigned) &BAUDCON2)*8) + 5; #define RXDTP2_bit BANKMASK(BAUDCON2), 5 extern volatile __bit RXF0EID0 @ (((unsigned) &RXF0EIDL)*8) + 0; #define RXF0EID0_bit BANKMASK(RXF0EIDL), 0 extern volatile __bit RXF0EID1 @ (((unsigned) &RXF0EIDL)*8) + 1; #define RXF0EID1_bit BANKMASK(RXF0EIDL), 1 extern volatile __bit RXF0EID10 @ (((unsigned) &RXF0EIDH)*8) + 2; #define RXF0EID10_bit BANKMASK(RXF0EIDH), 2 extern volatile __bit RXF0EID11 @ (((unsigned) &RXF0EIDH)*8) + 3; #define RXF0EID11_bit BANKMASK(RXF0EIDH), 3 extern volatile __bit RXF0EID12 @ (((unsigned) &RXF0EIDH)*8) + 4; #define RXF0EID12_bit BANKMASK(RXF0EIDH), 4 extern volatile __bit RXF0EID13 @ (((unsigned) &RXF0EIDH)*8) + 5; #define RXF0EID13_bit BANKMASK(RXF0EIDH), 5 extern volatile __bit RXF0EID14 @ (((unsigned) &RXF0EIDH)*8) + 6; #define RXF0EID14_bit BANKMASK(RXF0EIDH), 6 extern volatile __bit RXF0EID15 @ (((unsigned) &RXF0EIDH)*8) + 7; #define RXF0EID15_bit BANKMASK(RXF0EIDH), 7 extern volatile __bit RXF0EID16 @ (((unsigned) &RXF0SIDL)*8) + 0; #define RXF0EID16_bit BANKMASK(RXF0SIDL), 0 extern volatile __bit RXF0EID17 @ (((unsigned) &RXF0SIDL)*8) + 1; #define RXF0EID17_bit BANKMASK(RXF0SIDL), 1 extern volatile __bit RXF0EID2 @ (((unsigned) &RXF0EIDL)*8) + 2; #define RXF0EID2_bit BANKMASK(RXF0EIDL), 2 extern volatile __bit RXF0EID3 @ (((unsigned) &RXF0EIDL)*8) + 3; #define RXF0EID3_bit BANKMASK(RXF0EIDL), 3 extern volatile __bit RXF0EID4 @ (((unsigned) &RXF0EIDL)*8) + 4; #define RXF0EID4_bit BANKMASK(RXF0EIDL), 4 extern volatile __bit RXF0EID5 @ (((unsigned) &RXF0EIDL)*8) + 5; #define RXF0EID5_bit BANKMASK(RXF0EIDL), 5 extern volatile __bit RXF0EID6 @ (((unsigned) &RXF0EIDL)*8) + 6; #define RXF0EID6_bit BANKMASK(RXF0EIDL), 6 extern volatile __bit RXF0EID7 @ (((unsigned) &RXF0EIDL)*8) + 7; #define RXF0EID7_bit BANKMASK(RXF0EIDL), 7 extern volatile __bit RXF0EID8 @ (((unsigned) &RXF0EIDH)*8) + 0; #define RXF0EID8_bit BANKMASK(RXF0EIDH), 0 extern volatile __bit RXF0EID9 @ (((unsigned) &RXF0EIDH)*8) + 1; #define RXF0EID9_bit BANKMASK(RXF0EIDH), 1 extern volatile __bit RXF0EN @ (((unsigned) &RXFCON0)*8) + 0; #define RXF0EN_bit BANKMASK(RXFCON0), 0 extern volatile __bit RXF0EXIDEN @ (((unsigned) &RXF0SIDL)*8) + 3; #define RXF0EXIDEN_bit BANKMASK(RXF0SIDL), 3 extern volatile __bit RXF0SID0 @ (((unsigned) &RXF0SIDL)*8) + 5; #define RXF0SID0_bit BANKMASK(RXF0SIDL), 5 extern volatile __bit RXF0SID1 @ (((unsigned) &RXF0SIDL)*8) + 6; #define RXF0SID1_bit BANKMASK(RXF0SIDL), 6 extern volatile __bit RXF0SID10 @ (((unsigned) &RXF0SIDH)*8) + 7; #define RXF0SID10_bit BANKMASK(RXF0SIDH), 7 extern volatile __bit RXF0SID2 @ (((unsigned) &RXF0SIDL)*8) + 7; #define RXF0SID2_bit BANKMASK(RXF0SIDL), 7 extern volatile __bit RXF0SID3 @ (((unsigned) &RXF0SIDH)*8) + 0; #define RXF0SID3_bit BANKMASK(RXF0SIDH), 0 extern volatile __bit RXF0SID4 @ (((unsigned) &RXF0SIDH)*8) + 1; #define RXF0SID4_bit BANKMASK(RXF0SIDH), 1 extern volatile __bit RXF0SID5 @ (((unsigned) &RXF0SIDH)*8) + 2; #define RXF0SID5_bit BANKMASK(RXF0SIDH), 2 extern volatile __bit RXF0SID6 @ (((unsigned) &RXF0SIDH)*8) + 3; #define RXF0SID6_bit BANKMASK(RXF0SIDH), 3 extern volatile __bit RXF0SID7 @ (((unsigned) &RXF0SIDH)*8) + 4; #define RXF0SID7_bit BANKMASK(RXF0SIDH), 4 extern volatile __bit RXF0SID8 @ (((unsigned) &RXF0SIDH)*8) + 5; #define RXF0SID8_bit BANKMASK(RXF0SIDH), 5 extern volatile __bit RXF0SID9 @ (((unsigned) &RXF0SIDH)*8) + 6; #define RXF0SID9_bit BANKMASK(RXF0SIDH), 6 extern volatile __bit RXF10EID0 @ (((unsigned) &RXF10EIDL)*8) + 0; #define RXF10EID0_bit BANKMASK(RXF10EIDL), 0 extern volatile __bit RXF10EID1 @ (((unsigned) &RXF10EIDL)*8) + 1; #define RXF10EID1_bit BANKMASK(RXF10EIDL), 1 extern volatile __bit RXF10EID10 @ (((unsigned) &RXF10EIDH)*8) + 2; #define RXF10EID10_bit BANKMASK(RXF10EIDH), 2 extern volatile __bit RXF10EID11 @ (((unsigned) &RXF10EIDH)*8) + 3; #define RXF10EID11_bit BANKMASK(RXF10EIDH), 3 extern volatile __bit RXF10EID12 @ (((unsigned) &RXF10EIDH)*8) + 4; #define RXF10EID12_bit BANKMASK(RXF10EIDH), 4 extern volatile __bit RXF10EID13 @ (((unsigned) &RXF10EIDH)*8) + 5; #define RXF10EID13_bit BANKMASK(RXF10EIDH), 5 extern volatile __bit RXF10EID14 @ (((unsigned) &RXF10EIDH)*8) + 6; #define RXF10EID14_bit BANKMASK(RXF10EIDH), 6 extern volatile __bit RXF10EID15 @ (((unsigned) &RXF10EIDH)*8) + 7; #define RXF10EID15_bit BANKMASK(RXF10EIDH), 7 extern volatile __bit RXF10EID16 @ (((unsigned) &RXF10SIDL)*8) + 0; #define RXF10EID16_bit BANKMASK(RXF10SIDL), 0 extern volatile __bit RXF10EID17 @ (((unsigned) &RXF10SIDL)*8) + 1; #define RXF10EID17_bit BANKMASK(RXF10SIDL), 1 extern volatile __bit RXF10EID2 @ (((unsigned) &RXF10EIDL)*8) + 2; #define RXF10EID2_bit BANKMASK(RXF10EIDL), 2 extern volatile __bit RXF10EID3 @ (((unsigned) &RXF10EIDL)*8) + 3; #define RXF10EID3_bit BANKMASK(RXF10EIDL), 3 extern volatile __bit RXF10EID4 @ (((unsigned) &RXF10EIDL)*8) + 4; #define RXF10EID4_bit BANKMASK(RXF10EIDL), 4 extern volatile __bit RXF10EID5 @ (((unsigned) &RXF10EIDL)*8) + 5; #define RXF10EID5_bit BANKMASK(RXF10EIDL), 5 extern volatile __bit RXF10EID6 @ (((unsigned) &RXF10EIDL)*8) + 6; #define RXF10EID6_bit BANKMASK(RXF10EIDL), 6 extern volatile __bit RXF10EID7 @ (((unsigned) &RXF10EIDL)*8) + 7; #define RXF10EID7_bit BANKMASK(RXF10EIDL), 7 extern volatile __bit RXF10EID8 @ (((unsigned) &RXF10EIDH)*8) + 0; #define RXF10EID8_bit BANKMASK(RXF10EIDH), 0 extern volatile __bit RXF10EID9 @ (((unsigned) &RXF10EIDH)*8) + 1; #define RXF10EID9_bit BANKMASK(RXF10EIDH), 1 extern volatile __bit RXF10EN @ (((unsigned) &RXFCON1)*8) + 2; #define RXF10EN_bit BANKMASK(RXFCON1), 2 extern volatile __bit RXF10EXIDEN @ (((unsigned) &RXF10SIDL)*8) + 3; #define RXF10EXIDEN_bit BANKMASK(RXF10SIDL), 3 extern volatile __bit RXF10SID0 @ (((unsigned) &RXF10SIDL)*8) + 5; #define RXF10SID0_bit BANKMASK(RXF10SIDL), 5 extern volatile __bit RXF10SID1 @ (((unsigned) &RXF10SIDL)*8) + 6; #define RXF10SID1_bit BANKMASK(RXF10SIDL), 6 extern volatile __bit RXF10SID10 @ (((unsigned) &RXF10SIDH)*8) + 7; #define RXF10SID10_bit BANKMASK(RXF10SIDH), 7 extern volatile __bit RXF10SID2 @ (((unsigned) &RXF10SIDL)*8) + 7; #define RXF10SID2_bit BANKMASK(RXF10SIDL), 7 extern volatile __bit RXF10SID3 @ (((unsigned) &RXF10SIDH)*8) + 0; #define RXF10SID3_bit BANKMASK(RXF10SIDH), 0 extern volatile __bit RXF10SID4 @ (((unsigned) &RXF10SIDH)*8) + 1; #define RXF10SID4_bit BANKMASK(RXF10SIDH), 1 extern volatile __bit RXF10SID5 @ (((unsigned) &RXF10SIDH)*8) + 2; #define RXF10SID5_bit BANKMASK(RXF10SIDH), 2 extern volatile __bit RXF10SID6 @ (((unsigned) &RXF10SIDH)*8) + 3; #define RXF10SID6_bit BANKMASK(RXF10SIDH), 3 extern volatile __bit RXF10SID7 @ (((unsigned) &RXF10SIDH)*8) + 4; #define RXF10SID7_bit BANKMASK(RXF10SIDH), 4 extern volatile __bit RXF10SID8 @ (((unsigned) &RXF10SIDH)*8) + 5; #define RXF10SID8_bit BANKMASK(RXF10SIDH), 5 extern volatile __bit RXF10SID9 @ (((unsigned) &RXF10SIDH)*8) + 6; #define RXF10SID9_bit BANKMASK(RXF10SIDH), 6 extern volatile __bit RXF11EID0 @ (((unsigned) &RXF11EIDL)*8) + 0; #define RXF11EID0_bit BANKMASK(RXF11EIDL), 0 extern volatile __bit RXF11EID1 @ (((unsigned) &RXF11EIDL)*8) + 1; #define RXF11EID1_bit BANKMASK(RXF11EIDL), 1 extern volatile __bit RXF11EID10 @ (((unsigned) &RXF11EIDH)*8) + 2; #define RXF11EID10_bit BANKMASK(RXF11EIDH), 2 extern volatile __bit RXF11EID11 @ (((unsigned) &RXF11EIDH)*8) + 3; #define RXF11EID11_bit BANKMASK(RXF11EIDH), 3 extern volatile __bit RXF11EID12 @ (((unsigned) &RXF11EIDH)*8) + 4; #define RXF11EID12_bit BANKMASK(RXF11EIDH), 4 extern volatile __bit RXF11EID13 @ (((unsigned) &RXF11EIDH)*8) + 5; #define RXF11EID13_bit BANKMASK(RXF11EIDH), 5 extern volatile __bit RXF11EID14 @ (((unsigned) &RXF11EIDH)*8) + 6; #define RXF11EID14_bit BANKMASK(RXF11EIDH), 6 extern volatile __bit RXF11EID15 @ (((unsigned) &RXF11EIDH)*8) + 7; #define RXF11EID15_bit BANKMASK(RXF11EIDH), 7 extern volatile __bit RXF11EID16 @ (((unsigned) &RXF11SIDL)*8) + 0; #define RXF11EID16_bit BANKMASK(RXF11SIDL), 0 extern volatile __bit RXF11EID17 @ (((unsigned) &RXF11SIDL)*8) + 1; #define RXF11EID17_bit BANKMASK(RXF11SIDL), 1 extern volatile __bit RXF11EID2 @ (((unsigned) &RXF11EIDL)*8) + 2; #define RXF11EID2_bit BANKMASK(RXF11EIDL), 2 extern volatile __bit RXF11EID3 @ (((unsigned) &RXF11EIDL)*8) + 3; #define RXF11EID3_bit BANKMASK(RXF11EIDL), 3 extern volatile __bit RXF11EID4 @ (((unsigned) &RXF11EIDL)*8) + 4; #define RXF11EID4_bit BANKMASK(RXF11EIDL), 4 extern volatile __bit RXF11EID5 @ (((unsigned) &RXF11EIDL)*8) + 5; #define RXF11EID5_bit BANKMASK(RXF11EIDL), 5 extern volatile __bit RXF11EID6 @ (((unsigned) &RXF11EIDL)*8) + 6; #define RXF11EID6_bit BANKMASK(RXF11EIDL), 6 extern volatile __bit RXF11EID7 @ (((unsigned) &RXF11EIDL)*8) + 7; #define RXF11EID7_bit BANKMASK(RXF11EIDL), 7 extern volatile __bit RXF11EID8 @ (((unsigned) &RXF11EIDH)*8) + 0; #define RXF11EID8_bit BANKMASK(RXF11EIDH), 0 extern volatile __bit RXF11EID9 @ (((unsigned) &RXF11EIDH)*8) + 1; #define RXF11EID9_bit BANKMASK(RXF11EIDH), 1 extern volatile __bit RXF11EN @ (((unsigned) &RXFCON1)*8) + 3; #define RXF11EN_bit BANKMASK(RXFCON1), 3 extern volatile __bit RXF11EXIDEN @ (((unsigned) &RXF11SIDL)*8) + 3; #define RXF11EXIDEN_bit BANKMASK(RXF11SIDL), 3 extern volatile __bit RXF11SID0 @ (((unsigned) &RXF11SIDL)*8) + 5; #define RXF11SID0_bit BANKMASK(RXF11SIDL), 5 extern volatile __bit RXF11SID1 @ (((unsigned) &RXF11SIDL)*8) + 6; #define RXF11SID1_bit BANKMASK(RXF11SIDL), 6 extern volatile __bit RXF11SID10 @ (((unsigned) &RXF11SIDH)*8) + 7; #define RXF11SID10_bit BANKMASK(RXF11SIDH), 7 extern volatile __bit RXF11SID2 @ (((unsigned) &RXF11SIDL)*8) + 7; #define RXF11SID2_bit BANKMASK(RXF11SIDL), 7 extern volatile __bit RXF11SID3 @ (((unsigned) &RXF11SIDH)*8) + 0; #define RXF11SID3_bit BANKMASK(RXF11SIDH), 0 extern volatile __bit RXF11SID4 @ (((unsigned) &RXF11SIDH)*8) + 1; #define RXF11SID4_bit BANKMASK(RXF11SIDH), 1 extern volatile __bit RXF11SID5 @ (((unsigned) &RXF11SIDH)*8) + 2; #define RXF11SID5_bit BANKMASK(RXF11SIDH), 2 extern volatile __bit RXF11SID6 @ (((unsigned) &RXF11SIDH)*8) + 3; #define RXF11SID6_bit BANKMASK(RXF11SIDH), 3 extern volatile __bit RXF11SID7 @ (((unsigned) &RXF11SIDH)*8) + 4; #define RXF11SID7_bit BANKMASK(RXF11SIDH), 4 extern volatile __bit RXF11SID8 @ (((unsigned) &RXF11SIDH)*8) + 5; #define RXF11SID8_bit BANKMASK(RXF11SIDH), 5 extern volatile __bit RXF11SID9 @ (((unsigned) &RXF11SIDH)*8) + 6; #define RXF11SID9_bit BANKMASK(RXF11SIDH), 6 extern volatile __bit RXF12EID0 @ (((unsigned) &RXF12EIDL)*8) + 0; #define RXF12EID0_bit BANKMASK(RXF12EIDL), 0 extern volatile __bit RXF12EID1 @ (((unsigned) &RXF12EIDL)*8) + 1; #define RXF12EID1_bit BANKMASK(RXF12EIDL), 1 extern volatile __bit RXF12EID10 @ (((unsigned) &RXF12EIDH)*8) + 2; #define RXF12EID10_bit BANKMASK(RXF12EIDH), 2 extern volatile __bit RXF12EID11 @ (((unsigned) &RXF12EIDH)*8) + 3; #define RXF12EID11_bit BANKMASK(RXF12EIDH), 3 extern volatile __bit RXF12EID12 @ (((unsigned) &RXF12EIDH)*8) + 4; #define RXF12EID12_bit BANKMASK(RXF12EIDH), 4 extern volatile __bit RXF12EID13 @ (((unsigned) &RXF12EIDH)*8) + 5; #define RXF12EID13_bit BANKMASK(RXF12EIDH), 5 extern volatile __bit RXF12EID14 @ (((unsigned) &RXF12EIDH)*8) + 6; #define RXF12EID14_bit BANKMASK(RXF12EIDH), 6 extern volatile __bit RXF12EID15 @ (((unsigned) &RXF12EIDH)*8) + 7; #define RXF12EID15_bit BANKMASK(RXF12EIDH), 7 extern volatile __bit RXF12EID16 @ (((unsigned) &RXF12SIDL)*8) + 0; #define RXF12EID16_bit BANKMASK(RXF12SIDL), 0 extern volatile __bit RXF12EID17 @ (((unsigned) &RXF12SIDL)*8) + 1; #define RXF12EID17_bit BANKMASK(RXF12SIDL), 1 extern volatile __bit RXF12EID2 @ (((unsigned) &RXF12EIDL)*8) + 2; #define RXF12EID2_bit BANKMASK(RXF12EIDL), 2 extern volatile __bit RXF12EID3 @ (((unsigned) &RXF12EIDL)*8) + 3; #define RXF12EID3_bit BANKMASK(RXF12EIDL), 3 extern volatile __bit RXF12EID4 @ (((unsigned) &RXF12EIDL)*8) + 4; #define RXF12EID4_bit BANKMASK(RXF12EIDL), 4 extern volatile __bit RXF12EID5 @ (((unsigned) &RXF12EIDL)*8) + 5; #define RXF12EID5_bit BANKMASK(RXF12EIDL), 5 extern volatile __bit RXF12EID6 @ (((unsigned) &RXF12EIDL)*8) + 6; #define RXF12EID6_bit BANKMASK(RXF12EIDL), 6 extern volatile __bit RXF12EID7 @ (((unsigned) &RXF12EIDL)*8) + 7; #define RXF12EID7_bit BANKMASK(RXF12EIDL), 7 extern volatile __bit RXF12EID8 @ (((unsigned) &RXF12EIDH)*8) + 0; #define RXF12EID8_bit BANKMASK(RXF12EIDH), 0 extern volatile __bit RXF12EID9 @ (((unsigned) &RXF12EIDH)*8) + 1; #define RXF12EID9_bit BANKMASK(RXF12EIDH), 1 extern volatile __bit RXF12EN @ (((unsigned) &RXFCON1)*8) + 4; #define RXF12EN_bit BANKMASK(RXFCON1), 4 extern volatile __bit RXF12EXIDEN @ (((unsigned) &RXF12SIDL)*8) + 3; #define RXF12EXIDEN_bit BANKMASK(RXF12SIDL), 3 extern volatile __bit RXF12SID0 @ (((unsigned) &RXF12SIDL)*8) + 5; #define RXF12SID0_bit BANKMASK(RXF12SIDL), 5 extern volatile __bit RXF12SID1 @ (((unsigned) &RXF12SIDL)*8) + 6; #define RXF12SID1_bit BANKMASK(RXF12SIDL), 6 extern volatile __bit RXF12SID10 @ (((unsigned) &RXF12SIDH)*8) + 7; #define RXF12SID10_bit BANKMASK(RXF12SIDH), 7 extern volatile __bit RXF12SID2 @ (((unsigned) &RXF12SIDL)*8) + 7; #define RXF12SID2_bit BANKMASK(RXF12SIDL), 7 extern volatile __bit RXF12SID3 @ (((unsigned) &RXF12SIDH)*8) + 0; #define RXF12SID3_bit BANKMASK(RXF12SIDH), 0 extern volatile __bit RXF12SID4 @ (((unsigned) &RXF12SIDH)*8) + 1; #define RXF12SID4_bit BANKMASK(RXF12SIDH), 1 extern volatile __bit RXF12SID5 @ (((unsigned) &RXF12SIDH)*8) + 2; #define RXF12SID5_bit BANKMASK(RXF12SIDH), 2 extern volatile __bit RXF12SID6 @ (((unsigned) &RXF12SIDH)*8) + 3; #define RXF12SID6_bit BANKMASK(RXF12SIDH), 3 extern volatile __bit RXF12SID7 @ (((unsigned) &RXF12SIDH)*8) + 4; #define RXF12SID7_bit BANKMASK(RXF12SIDH), 4 extern volatile __bit RXF12SID8 @ (((unsigned) &RXF12SIDH)*8) + 5; #define RXF12SID8_bit BANKMASK(RXF12SIDH), 5 extern volatile __bit RXF12SID9 @ (((unsigned) &RXF12SIDH)*8) + 6; #define RXF12SID9_bit BANKMASK(RXF12SIDH), 6 extern volatile __bit RXF13EID0 @ (((unsigned) &RXF13EIDL)*8) + 0; #define RXF13EID0_bit BANKMASK(RXF13EIDL), 0 extern volatile __bit RXF13EID1 @ (((unsigned) &RXF13EIDL)*8) + 1; #define RXF13EID1_bit BANKMASK(RXF13EIDL), 1 extern volatile __bit RXF13EID10 @ (((unsigned) &RXF13EIDH)*8) + 2; #define RXF13EID10_bit BANKMASK(RXF13EIDH), 2 extern volatile __bit RXF13EID11 @ (((unsigned) &RXF13EIDH)*8) + 3; #define RXF13EID11_bit BANKMASK(RXF13EIDH), 3 extern volatile __bit RXF13EID12 @ (((unsigned) &RXF13EIDH)*8) + 4; #define RXF13EID12_bit BANKMASK(RXF13EIDH), 4 extern volatile __bit RXF13EID13 @ (((unsigned) &RXF13EIDH)*8) + 5; #define RXF13EID13_bit BANKMASK(RXF13EIDH), 5 extern volatile __bit RXF13EID14 @ (((unsigned) &RXF13EIDH)*8) + 6; #define RXF13EID14_bit BANKMASK(RXF13EIDH), 6 extern volatile __bit RXF13EID15 @ (((unsigned) &RXF13EIDH)*8) + 7; #define RXF13EID15_bit BANKMASK(RXF13EIDH), 7 extern volatile __bit RXF13EID16 @ (((unsigned) &RXF13SIDL)*8) + 0; #define RXF13EID16_bit BANKMASK(RXF13SIDL), 0 extern volatile __bit RXF13EID17 @ (((unsigned) &RXF13SIDL)*8) + 1; #define RXF13EID17_bit BANKMASK(RXF13SIDL), 1 extern volatile __bit RXF13EID2 @ (((unsigned) &RXF13EIDL)*8) + 2; #define RXF13EID2_bit BANKMASK(RXF13EIDL), 2 extern volatile __bit RXF13EID3 @ (((unsigned) &RXF13EIDL)*8) + 3; #define RXF13EID3_bit BANKMASK(RXF13EIDL), 3 extern volatile __bit RXF13EID4 @ (((unsigned) &RXF13EIDL)*8) + 4; #define RXF13EID4_bit BANKMASK(RXF13EIDL), 4 extern volatile __bit RXF13EID5 @ (((unsigned) &RXF13EIDL)*8) + 5; #define RXF13EID5_bit BANKMASK(RXF13EIDL), 5 extern volatile __bit RXF13EID6 @ (((unsigned) &RXF13EIDL)*8) + 6; #define RXF13EID6_bit BANKMASK(RXF13EIDL), 6 extern volatile __bit RXF13EID7 @ (((unsigned) &RXF13EIDL)*8) + 7; #define RXF13EID7_bit BANKMASK(RXF13EIDL), 7 extern volatile __bit RXF13EID8 @ (((unsigned) &RXF13EIDH)*8) + 0; #define RXF13EID8_bit BANKMASK(RXF13EIDH), 0 extern volatile __bit RXF13EID9 @ (((unsigned) &RXF13EIDH)*8) + 1; #define RXF13EID9_bit BANKMASK(RXF13EIDH), 1 extern volatile __bit RXF13EN @ (((unsigned) &RXFCON1)*8) + 5; #define RXF13EN_bit BANKMASK(RXFCON1), 5 extern volatile __bit RXF13EXIDEN @ (((unsigned) &RXF13SIDL)*8) + 3; #define RXF13EXIDEN_bit BANKMASK(RXF13SIDL), 3 extern volatile __bit RXF13SID0 @ (((unsigned) &RXF13SIDL)*8) + 5; #define RXF13SID0_bit BANKMASK(RXF13SIDL), 5 extern volatile __bit RXF13SID1 @ (((unsigned) &RXF13SIDL)*8) + 6; #define RXF13SID1_bit BANKMASK(RXF13SIDL), 6 extern volatile __bit RXF13SID10 @ (((unsigned) &RXF13SIDH)*8) + 7; #define RXF13SID10_bit BANKMASK(RXF13SIDH), 7 extern volatile __bit RXF13SID2 @ (((unsigned) &RXF13SIDL)*8) + 7; #define RXF13SID2_bit BANKMASK(RXF13SIDL), 7 extern volatile __bit RXF13SID3 @ (((unsigned) &RXF13SIDH)*8) + 0; #define RXF13SID3_bit BANKMASK(RXF13SIDH), 0 extern volatile __bit RXF13SID4 @ (((unsigned) &RXF13SIDH)*8) + 1; #define RXF13SID4_bit BANKMASK(RXF13SIDH), 1 extern volatile __bit RXF13SID5 @ (((unsigned) &RXF13SIDH)*8) + 2; #define RXF13SID5_bit BANKMASK(RXF13SIDH), 2 extern volatile __bit RXF13SID6 @ (((unsigned) &RXF13SIDH)*8) + 3; #define RXF13SID6_bit BANKMASK(RXF13SIDH), 3 extern volatile __bit RXF13SID7 @ (((unsigned) &RXF13SIDH)*8) + 4; #define RXF13SID7_bit BANKMASK(RXF13SIDH), 4 extern volatile __bit RXF13SID8 @ (((unsigned) &RXF13SIDH)*8) + 5; #define RXF13SID8_bit BANKMASK(RXF13SIDH), 5 extern volatile __bit RXF13SID9 @ (((unsigned) &RXF13SIDH)*8) + 6; #define RXF13SID9_bit BANKMASK(RXF13SIDH), 6 extern volatile __bit RXF14EID0 @ (((unsigned) &RXF14EIDL)*8) + 0; #define RXF14EID0_bit BANKMASK(RXF14EIDL), 0 extern volatile __bit RXF14EID1 @ (((unsigned) &RXF14EIDL)*8) + 1; #define RXF14EID1_bit BANKMASK(RXF14EIDL), 1 extern volatile __bit RXF14EID10 @ (((unsigned) &RXF14EIDH)*8) + 2; #define RXF14EID10_bit BANKMASK(RXF14EIDH), 2 extern volatile __bit RXF14EID11 @ (((unsigned) &RXF14EIDH)*8) + 3; #define RXF14EID11_bit BANKMASK(RXF14EIDH), 3 extern volatile __bit RXF14EID12 @ (((unsigned) &RXF14EIDH)*8) + 4; #define RXF14EID12_bit BANKMASK(RXF14EIDH), 4 extern volatile __bit RXF14EID13 @ (((unsigned) &RXF14EIDH)*8) + 5; #define RXF14EID13_bit BANKMASK(RXF14EIDH), 5 extern volatile __bit RXF14EID14 @ (((unsigned) &RXF14EIDH)*8) + 6; #define RXF14EID14_bit BANKMASK(RXF14EIDH), 6 extern volatile __bit RXF14EID15 @ (((unsigned) &RXF14EIDH)*8) + 7; #define RXF14EID15_bit BANKMASK(RXF14EIDH), 7 extern volatile __bit RXF14EID16 @ (((unsigned) &RXF14SIDL)*8) + 0; #define RXF14EID16_bit BANKMASK(RXF14SIDL), 0 extern volatile __bit RXF14EID17 @ (((unsigned) &RXF14SIDL)*8) + 1; #define RXF14EID17_bit BANKMASK(RXF14SIDL), 1 extern volatile __bit RXF14EID2 @ (((unsigned) &RXF14EIDL)*8) + 2; #define RXF14EID2_bit BANKMASK(RXF14EIDL), 2 extern volatile __bit RXF14EID3 @ (((unsigned) &RXF14EIDL)*8) + 3; #define RXF14EID3_bit BANKMASK(RXF14EIDL), 3 extern volatile __bit RXF14EID4 @ (((unsigned) &RXF14EIDL)*8) + 4; #define RXF14EID4_bit BANKMASK(RXF14EIDL), 4 extern volatile __bit RXF14EID5 @ (((unsigned) &RXF14EIDL)*8) + 5; #define RXF14EID5_bit BANKMASK(RXF14EIDL), 5 extern volatile __bit RXF14EID6 @ (((unsigned) &RXF14EIDL)*8) + 6; #define RXF14EID6_bit BANKMASK(RXF14EIDL), 6 extern volatile __bit RXF14EID7 @ (((unsigned) &RXF14EIDL)*8) + 7; #define RXF14EID7_bit BANKMASK(RXF14EIDL), 7 extern volatile __bit RXF14EID8 @ (((unsigned) &RXF14EIDH)*8) + 0; #define RXF14EID8_bit BANKMASK(RXF14EIDH), 0 extern volatile __bit RXF14EID9 @ (((unsigned) &RXF14EIDH)*8) + 1; #define RXF14EID9_bit BANKMASK(RXF14EIDH), 1 extern volatile __bit RXF14EN @ (((unsigned) &RXFCON1)*8) + 6; #define RXF14EN_bit BANKMASK(RXFCON1), 6 extern volatile __bit RXF14EXIDEN @ (((unsigned) &RXF14SIDL)*8) + 3; #define RXF14EXIDEN_bit BANKMASK(RXF14SIDL), 3 extern volatile __bit RXF14SID0 @ (((unsigned) &RXF14SIDL)*8) + 5; #define RXF14SID0_bit BANKMASK(RXF14SIDL), 5 extern volatile __bit RXF14SID1 @ (((unsigned) &RXF14SIDL)*8) + 6; #define RXF14SID1_bit BANKMASK(RXF14SIDL), 6 extern volatile __bit RXF14SID10 @ (((unsigned) &RXF14SIDH)*8) + 7; #define RXF14SID10_bit BANKMASK(RXF14SIDH), 7 extern volatile __bit RXF14SID2 @ (((unsigned) &RXF14SIDL)*8) + 7; #define RXF14SID2_bit BANKMASK(RXF14SIDL), 7 extern volatile __bit RXF14SID3 @ (((unsigned) &RXF14SIDH)*8) + 0; #define RXF14SID3_bit BANKMASK(RXF14SIDH), 0 extern volatile __bit RXF14SID4 @ (((unsigned) &RXF14SIDH)*8) + 1; #define RXF14SID4_bit BANKMASK(RXF14SIDH), 1 extern volatile __bit RXF14SID5 @ (((unsigned) &RXF14SIDH)*8) + 2; #define RXF14SID5_bit BANKMASK(RXF14SIDH), 2 extern volatile __bit RXF14SID6 @ (((unsigned) &RXF14SIDH)*8) + 3; #define RXF14SID6_bit BANKMASK(RXF14SIDH), 3 extern volatile __bit RXF14SID7 @ (((unsigned) &RXF14SIDH)*8) + 4; #define RXF14SID7_bit BANKMASK(RXF14SIDH), 4 extern volatile __bit RXF14SID8 @ (((unsigned) &RXF14SIDH)*8) + 5; #define RXF14SID8_bit BANKMASK(RXF14SIDH), 5 extern volatile __bit RXF14SID9 @ (((unsigned) &RXF14SIDH)*8) + 6; #define RXF14SID9_bit BANKMASK(RXF14SIDH), 6 extern volatile __bit RXF15EID0 @ (((unsigned) &RXF15EIDL)*8) + 0; #define RXF15EID0_bit BANKMASK(RXF15EIDL), 0 extern volatile __bit RXF15EID1 @ (((unsigned) &RXF15EIDL)*8) + 1; #define RXF15EID1_bit BANKMASK(RXF15EIDL), 1 extern volatile __bit RXF15EID10 @ (((unsigned) &RXF15EIDH)*8) + 2; #define RXF15EID10_bit BANKMASK(RXF15EIDH), 2 extern volatile __bit RXF15EID11 @ (((unsigned) &RXF15EIDH)*8) + 3; #define RXF15EID11_bit BANKMASK(RXF15EIDH), 3 extern volatile __bit RXF15EID12 @ (((unsigned) &RXF15EIDH)*8) + 4; #define RXF15EID12_bit BANKMASK(RXF15EIDH), 4 extern volatile __bit RXF15EID13 @ (((unsigned) &RXF15EIDH)*8) + 5; #define RXF15EID13_bit BANKMASK(RXF15EIDH), 5 extern volatile __bit RXF15EID14 @ (((unsigned) &RXF15EIDH)*8) + 6; #define RXF15EID14_bit BANKMASK(RXF15EIDH), 6 extern volatile __bit RXF15EID15 @ (((unsigned) &RXF15EIDH)*8) + 7; #define RXF15EID15_bit BANKMASK(RXF15EIDH), 7 extern volatile __bit RXF15EID16 @ (((unsigned) &RXF15SIDL)*8) + 0; #define RXF15EID16_bit BANKMASK(RXF15SIDL), 0 extern volatile __bit RXF15EID17 @ (((unsigned) &RXF15SIDL)*8) + 1; #define RXF15EID17_bit BANKMASK(RXF15SIDL), 1 extern volatile __bit RXF15EID2 @ (((unsigned) &RXF15EIDL)*8) + 2; #define RXF15EID2_bit BANKMASK(RXF15EIDL), 2 extern volatile __bit RXF15EID3 @ (((unsigned) &RXF15EIDL)*8) + 3; #define RXF15EID3_bit BANKMASK(RXF15EIDL), 3 extern volatile __bit RXF15EID4 @ (((unsigned) &RXF15EIDL)*8) + 4; #define RXF15EID4_bit BANKMASK(RXF15EIDL), 4 extern volatile __bit RXF15EID5 @ (((unsigned) &RXF15EIDL)*8) + 5; #define RXF15EID5_bit BANKMASK(RXF15EIDL), 5 extern volatile __bit RXF15EID6 @ (((unsigned) &RXF15EIDL)*8) + 6; #define RXF15EID6_bit BANKMASK(RXF15EIDL), 6 extern volatile __bit RXF15EID7 @ (((unsigned) &RXF15EIDL)*8) + 7; #define RXF15EID7_bit BANKMASK(RXF15EIDL), 7 extern volatile __bit RXF15EID8 @ (((unsigned) &RXF15EIDH)*8) + 0; #define RXF15EID8_bit BANKMASK(RXF15EIDH), 0 extern volatile __bit RXF15EID9 @ (((unsigned) &RXF15EIDH)*8) + 1; #define RXF15EID9_bit BANKMASK(RXF15EIDH), 1 extern volatile __bit RXF15EN @ (((unsigned) &RXFCON1)*8) + 7; #define RXF15EN_bit BANKMASK(RXFCON1), 7 extern volatile __bit RXF15EXIDEN @ (((unsigned) &RXF15SIDL)*8) + 3; #define RXF15EXIDEN_bit BANKMASK(RXF15SIDL), 3 extern volatile __bit RXF15SID0 @ (((unsigned) &RXF15SIDL)*8) + 5; #define RXF15SID0_bit BANKMASK(RXF15SIDL), 5 extern volatile __bit RXF15SID1 @ (((unsigned) &RXF15SIDL)*8) + 6; #define RXF15SID1_bit BANKMASK(RXF15SIDL), 6 extern volatile __bit RXF15SID10 @ (((unsigned) &RXF15SIDH)*8) + 7; #define RXF15SID10_bit BANKMASK(RXF15SIDH), 7 extern volatile __bit RXF15SID2 @ (((unsigned) &RXF15SIDL)*8) + 7; #define RXF15SID2_bit BANKMASK(RXF15SIDL), 7 extern volatile __bit RXF15SID3 @ (((unsigned) &RXF15SIDH)*8) + 0; #define RXF15SID3_bit BANKMASK(RXF15SIDH), 0 extern volatile __bit RXF15SID4 @ (((unsigned) &RXF15SIDH)*8) + 1; #define RXF15SID4_bit BANKMASK(RXF15SIDH), 1 extern volatile __bit RXF15SID5 @ (((unsigned) &RXF15SIDH)*8) + 2; #define RXF15SID5_bit BANKMASK(RXF15SIDH), 2 extern volatile __bit RXF15SID6 @ (((unsigned) &RXF15SIDH)*8) + 3; #define RXF15SID6_bit BANKMASK(RXF15SIDH), 3 extern volatile __bit RXF15SID7 @ (((unsigned) &RXF15SIDH)*8) + 4; #define RXF15SID7_bit BANKMASK(RXF15SIDH), 4 extern volatile __bit RXF15SID8 @ (((unsigned) &RXF15SIDH)*8) + 5; #define RXF15SID8_bit BANKMASK(RXF15SIDH), 5 extern volatile __bit RXF15SID9 @ (((unsigned) &RXF15SIDH)*8) + 6; #define RXF15SID9_bit BANKMASK(RXF15SIDH), 6 extern volatile __bit RXF1EID0 @ (((unsigned) &RXF1EIDL)*8) + 0; #define RXF1EID0_bit BANKMASK(RXF1EIDL), 0 extern volatile __bit RXF1EID1 @ (((unsigned) &RXF1EIDL)*8) + 1; #define RXF1EID1_bit BANKMASK(RXF1EIDL), 1 extern volatile __bit RXF1EID10 @ (((unsigned) &RXF1EIDH)*8) + 2; #define RXF1EID10_bit BANKMASK(RXF1EIDH), 2 extern volatile __bit RXF1EID11 @ (((unsigned) &RXF1EIDH)*8) + 3; #define RXF1EID11_bit BANKMASK(RXF1EIDH), 3 extern volatile __bit RXF1EID12 @ (((unsigned) &RXF1EIDH)*8) + 4; #define RXF1EID12_bit BANKMASK(RXF1EIDH), 4 extern volatile __bit RXF1EID13 @ (((unsigned) &RXF1EIDH)*8) + 5; #define RXF1EID13_bit BANKMASK(RXF1EIDH), 5 extern volatile __bit RXF1EID14 @ (((unsigned) &RXF1EIDH)*8) + 6; #define RXF1EID14_bit BANKMASK(RXF1EIDH), 6 extern volatile __bit RXF1EID15 @ (((unsigned) &RXF1EIDH)*8) + 7; #define RXF1EID15_bit BANKMASK(RXF1EIDH), 7 extern volatile __bit RXF1EID16 @ (((unsigned) &RXF1SIDL)*8) + 0; #define RXF1EID16_bit BANKMASK(RXF1SIDL), 0 extern volatile __bit RXF1EID17 @ (((unsigned) &RXF1SIDL)*8) + 1; #define RXF1EID17_bit BANKMASK(RXF1SIDL), 1 extern volatile __bit RXF1EID2 @ (((unsigned) &RXF1EIDL)*8) + 2; #define RXF1EID2_bit BANKMASK(RXF1EIDL), 2 extern volatile __bit RXF1EID3 @ (((unsigned) &RXF1EIDL)*8) + 3; #define RXF1EID3_bit BANKMASK(RXF1EIDL), 3 extern volatile __bit RXF1EID4 @ (((unsigned) &RXF1EIDL)*8) + 4; #define RXF1EID4_bit BANKMASK(RXF1EIDL), 4 extern volatile __bit RXF1EID5 @ (((unsigned) &RXF1EIDL)*8) + 5; #define RXF1EID5_bit BANKMASK(RXF1EIDL), 5 extern volatile __bit RXF1EID6 @ (((unsigned) &RXF1EIDL)*8) + 6; #define RXF1EID6_bit BANKMASK(RXF1EIDL), 6 extern volatile __bit RXF1EID7 @ (((unsigned) &RXF1EIDL)*8) + 7; #define RXF1EID7_bit BANKMASK(RXF1EIDL), 7 extern volatile __bit RXF1EID8 @ (((unsigned) &RXF1EIDH)*8) + 0; #define RXF1EID8_bit BANKMASK(RXF1EIDH), 0 extern volatile __bit RXF1EID9 @ (((unsigned) &RXF1EIDH)*8) + 1; #define RXF1EID9_bit BANKMASK(RXF1EIDH), 1 extern volatile __bit RXF1EN @ (((unsigned) &RXFCON0)*8) + 1; #define RXF1EN_bit BANKMASK(RXFCON0), 1 extern volatile __bit RXF1EXIDEN @ (((unsigned) &RXF1SIDL)*8) + 3; #define RXF1EXIDEN_bit BANKMASK(RXF1SIDL), 3 extern volatile __bit RXF1SID0 @ (((unsigned) &RXF1SIDL)*8) + 5; #define RXF1SID0_bit BANKMASK(RXF1SIDL), 5 extern volatile __bit RXF1SID1 @ (((unsigned) &RXF1SIDL)*8) + 6; #define RXF1SID1_bit BANKMASK(RXF1SIDL), 6 extern volatile __bit RXF1SID10 @ (((unsigned) &RXF1SIDH)*8) + 7; #define RXF1SID10_bit BANKMASK(RXF1SIDH), 7 extern volatile __bit RXF1SID2 @ (((unsigned) &RXF1SIDL)*8) + 7; #define RXF1SID2_bit BANKMASK(RXF1SIDL), 7 extern volatile __bit RXF1SID3 @ (((unsigned) &RXF1SIDH)*8) + 0; #define RXF1SID3_bit BANKMASK(RXF1SIDH), 0 extern volatile __bit RXF1SID4 @ (((unsigned) &RXF1SIDH)*8) + 1; #define RXF1SID4_bit BANKMASK(RXF1SIDH), 1 extern volatile __bit RXF1SID5 @ (((unsigned) &RXF1SIDH)*8) + 2; #define RXF1SID5_bit BANKMASK(RXF1SIDH), 2 extern volatile __bit RXF1SID6 @ (((unsigned) &RXF1SIDH)*8) + 3; #define RXF1SID6_bit BANKMASK(RXF1SIDH), 3 extern volatile __bit RXF1SID7 @ (((unsigned) &RXF1SIDH)*8) + 4; #define RXF1SID7_bit BANKMASK(RXF1SIDH), 4 extern volatile __bit RXF1SID8 @ (((unsigned) &RXF1SIDH)*8) + 5; #define RXF1SID8_bit BANKMASK(RXF1SIDH), 5 extern volatile __bit RXF1SID9 @ (((unsigned) &RXF1SIDH)*8) + 6; #define RXF1SID9_bit BANKMASK(RXF1SIDH), 6 extern volatile __bit RXF2EID0 @ (((unsigned) &RXF2EIDL)*8) + 0; #define RXF2EID0_bit BANKMASK(RXF2EIDL), 0 extern volatile __bit RXF2EID1 @ (((unsigned) &RXF2EIDL)*8) + 1; #define RXF2EID1_bit BANKMASK(RXF2EIDL), 1 extern volatile __bit RXF2EID10 @ (((unsigned) &RXF2EIDH)*8) + 2; #define RXF2EID10_bit BANKMASK(RXF2EIDH), 2 extern volatile __bit RXF2EID11 @ (((unsigned) &RXF2EIDH)*8) + 3; #define RXF2EID11_bit BANKMASK(RXF2EIDH), 3 extern volatile __bit RXF2EID12 @ (((unsigned) &RXF2EIDH)*8) + 4; #define RXF2EID12_bit BANKMASK(RXF2EIDH), 4 extern volatile __bit RXF2EID13 @ (((unsigned) &RXF2EIDH)*8) + 5; #define RXF2EID13_bit BANKMASK(RXF2EIDH), 5 extern volatile __bit RXF2EID14 @ (((unsigned) &RXF2EIDH)*8) + 6; #define RXF2EID14_bit BANKMASK(RXF2EIDH), 6 extern volatile __bit RXF2EID15 @ (((unsigned) &RXF2EIDH)*8) + 7; #define RXF2EID15_bit BANKMASK(RXF2EIDH), 7 extern volatile __bit RXF2EID16 @ (((unsigned) &RXF2SIDL)*8) + 0; #define RXF2EID16_bit BANKMASK(RXF2SIDL), 0 extern volatile __bit RXF2EID17 @ (((unsigned) &RXF2SIDL)*8) + 1; #define RXF2EID17_bit BANKMASK(RXF2SIDL), 1 extern volatile __bit RXF2EID2 @ (((unsigned) &RXF2EIDL)*8) + 2; #define RXF2EID2_bit BANKMASK(RXF2EIDL), 2 extern volatile __bit RXF2EID3 @ (((unsigned) &RXF2EIDL)*8) + 3; #define RXF2EID3_bit BANKMASK(RXF2EIDL), 3 extern volatile __bit RXF2EID4 @ (((unsigned) &RXF2EIDL)*8) + 4; #define RXF2EID4_bit BANKMASK(RXF2EIDL), 4 extern volatile __bit RXF2EID5 @ (((unsigned) &RXF2EIDL)*8) + 5; #define RXF2EID5_bit BANKMASK(RXF2EIDL), 5 extern volatile __bit RXF2EID6 @ (((unsigned) &RXF2EIDL)*8) + 6; #define RXF2EID6_bit BANKMASK(RXF2EIDL), 6 extern volatile __bit RXF2EID7 @ (((unsigned) &RXF2EIDL)*8) + 7; #define RXF2EID7_bit BANKMASK(RXF2EIDL), 7 extern volatile __bit RXF2EID8 @ (((unsigned) &RXF2EIDH)*8) + 0; #define RXF2EID8_bit BANKMASK(RXF2EIDH), 0 extern volatile __bit RXF2EID9 @ (((unsigned) &RXF2EIDH)*8) + 1; #define RXF2EID9_bit BANKMASK(RXF2EIDH), 1 extern volatile __bit RXF2EN @ (((unsigned) &RXFCON0)*8) + 2; #define RXF2EN_bit BANKMASK(RXFCON0), 2 extern volatile __bit RXF2EXIDEN @ (((unsigned) &RXF2SIDL)*8) + 3; #define RXF2EXIDEN_bit BANKMASK(RXF2SIDL), 3 extern volatile __bit RXF2SID0 @ (((unsigned) &RXF2SIDL)*8) + 5; #define RXF2SID0_bit BANKMASK(RXF2SIDL), 5 extern volatile __bit RXF2SID1 @ (((unsigned) &RXF2SIDL)*8) + 6; #define RXF2SID1_bit BANKMASK(RXF2SIDL), 6 extern volatile __bit RXF2SID10 @ (((unsigned) &RXF2SIDH)*8) + 7; #define RXF2SID10_bit BANKMASK(RXF2SIDH), 7 extern volatile __bit RXF2SID2 @ (((unsigned) &RXF2SIDL)*8) + 7; #define RXF2SID2_bit BANKMASK(RXF2SIDL), 7 extern volatile __bit RXF2SID3 @ (((unsigned) &RXF2SIDH)*8) + 0; #define RXF2SID3_bit BANKMASK(RXF2SIDH), 0 extern volatile __bit RXF2SID4 @ (((unsigned) &RXF2SIDH)*8) + 1; #define RXF2SID4_bit BANKMASK(RXF2SIDH), 1 extern volatile __bit RXF2SID5 @ (((unsigned) &RXF2SIDH)*8) + 2; #define RXF2SID5_bit BANKMASK(RXF2SIDH), 2 extern volatile __bit RXF2SID6 @ (((unsigned) &RXF2SIDH)*8) + 3; #define RXF2SID6_bit BANKMASK(RXF2SIDH), 3 extern volatile __bit RXF2SID7 @ (((unsigned) &RXF2SIDH)*8) + 4; #define RXF2SID7_bit BANKMASK(RXF2SIDH), 4 extern volatile __bit RXF2SID8 @ (((unsigned) &RXF2SIDH)*8) + 5; #define RXF2SID8_bit BANKMASK(RXF2SIDH), 5 extern volatile __bit RXF2SID9 @ (((unsigned) &RXF2SIDH)*8) + 6; #define RXF2SID9_bit BANKMASK(RXF2SIDH), 6 extern volatile __bit RXF3EID0 @ (((unsigned) &RXF3EIDL)*8) + 0; #define RXF3EID0_bit BANKMASK(RXF3EIDL), 0 extern volatile __bit RXF3EID1 @ (((unsigned) &RXF3EIDL)*8) + 1; #define RXF3EID1_bit BANKMASK(RXF3EIDL), 1 extern volatile __bit RXF3EID10 @ (((unsigned) &RXF3EIDH)*8) + 2; #define RXF3EID10_bit BANKMASK(RXF3EIDH), 2 extern volatile __bit RXF3EID11 @ (((unsigned) &RXF3EIDH)*8) + 3; #define RXF3EID11_bit BANKMASK(RXF3EIDH), 3 extern volatile __bit RXF3EID12 @ (((unsigned) &RXF3EIDH)*8) + 4; #define RXF3EID12_bit BANKMASK(RXF3EIDH), 4 extern volatile __bit RXF3EID13 @ (((unsigned) &RXF3EIDH)*8) + 5; #define RXF3EID13_bit BANKMASK(RXF3EIDH), 5 extern volatile __bit RXF3EID14 @ (((unsigned) &RXF3EIDH)*8) + 6; #define RXF3EID14_bit BANKMASK(RXF3EIDH), 6 extern volatile __bit RXF3EID15 @ (((unsigned) &RXF3EIDH)*8) + 7; #define RXF3EID15_bit BANKMASK(RXF3EIDH), 7 extern volatile __bit RXF3EID16 @ (((unsigned) &RXF3SIDL)*8) + 0; #define RXF3EID16_bit BANKMASK(RXF3SIDL), 0 extern volatile __bit RXF3EID17 @ (((unsigned) &RXF3SIDL)*8) + 1; #define RXF3EID17_bit BANKMASK(RXF3SIDL), 1 extern volatile __bit RXF3EID2 @ (((unsigned) &RXF3EIDL)*8) + 2; #define RXF3EID2_bit BANKMASK(RXF3EIDL), 2 extern volatile __bit RXF3EID3 @ (((unsigned) &RXF3EIDL)*8) + 3; #define RXF3EID3_bit BANKMASK(RXF3EIDL), 3 extern volatile __bit RXF3EID4 @ (((unsigned) &RXF3EIDL)*8) + 4; #define RXF3EID4_bit BANKMASK(RXF3EIDL), 4 extern volatile __bit RXF3EID5 @ (((unsigned) &RXF3EIDL)*8) + 5; #define RXF3EID5_bit BANKMASK(RXF3EIDL), 5 extern volatile __bit RXF3EID6 @ (((unsigned) &RXF3EIDL)*8) + 6; #define RXF3EID6_bit BANKMASK(RXF3EIDL), 6 extern volatile __bit RXF3EID7 @ (((unsigned) &RXF3EIDL)*8) + 7; #define RXF3EID7_bit BANKMASK(RXF3EIDL), 7 extern volatile __bit RXF3EID8 @ (((unsigned) &RXF3EIDH)*8) + 0; #define RXF3EID8_bit BANKMASK(RXF3EIDH), 0 extern volatile __bit RXF3EID9 @ (((unsigned) &RXF3EIDH)*8) + 1; #define RXF3EID9_bit BANKMASK(RXF3EIDH), 1 extern volatile __bit RXF3EN @ (((unsigned) &RXFCON0)*8) + 3; #define RXF3EN_bit BANKMASK(RXFCON0), 3 extern volatile __bit RXF3EXIDEN @ (((unsigned) &RXF3SIDL)*8) + 3; #define RXF3EXIDEN_bit BANKMASK(RXF3SIDL), 3 extern volatile __bit RXF3SID0 @ (((unsigned) &RXF3SIDL)*8) + 5; #define RXF3SID0_bit BANKMASK(RXF3SIDL), 5 extern volatile __bit RXF3SID1 @ (((unsigned) &RXF3SIDL)*8) + 6; #define RXF3SID1_bit BANKMASK(RXF3SIDL), 6 extern volatile __bit RXF3SID10 @ (((unsigned) &RXF3SIDH)*8) + 7; #define RXF3SID10_bit BANKMASK(RXF3SIDH), 7 extern volatile __bit RXF3SID2 @ (((unsigned) &RXF3SIDL)*8) + 7; #define RXF3SID2_bit BANKMASK(RXF3SIDL), 7 extern volatile __bit RXF3SID3 @ (((unsigned) &RXF3SIDH)*8) + 0; #define RXF3SID3_bit BANKMASK(RXF3SIDH), 0 extern volatile __bit RXF3SID4 @ (((unsigned) &RXF3SIDH)*8) + 1; #define RXF3SID4_bit BANKMASK(RXF3SIDH), 1 extern volatile __bit RXF3SID5 @ (((unsigned) &RXF3SIDH)*8) + 2; #define RXF3SID5_bit BANKMASK(RXF3SIDH), 2 extern volatile __bit RXF3SID6 @ (((unsigned) &RXF3SIDH)*8) + 3; #define RXF3SID6_bit BANKMASK(RXF3SIDH), 3 extern volatile __bit RXF3SID7 @ (((unsigned) &RXF3SIDH)*8) + 4; #define RXF3SID7_bit BANKMASK(RXF3SIDH), 4 extern volatile __bit RXF3SID8 @ (((unsigned) &RXF3SIDH)*8) + 5; #define RXF3SID8_bit BANKMASK(RXF3SIDH), 5 extern volatile __bit RXF3SID9 @ (((unsigned) &RXF3SIDH)*8) + 6; #define RXF3SID9_bit BANKMASK(RXF3SIDH), 6 extern volatile __bit RXF4EID0 @ (((unsigned) &RXF4EIDL)*8) + 0; #define RXF4EID0_bit BANKMASK(RXF4EIDL), 0 extern volatile __bit RXF4EID1 @ (((unsigned) &RXF4EIDL)*8) + 1; #define RXF4EID1_bit BANKMASK(RXF4EIDL), 1 extern volatile __bit RXF4EID10 @ (((unsigned) &RXF4EIDH)*8) + 2; #define RXF4EID10_bit BANKMASK(RXF4EIDH), 2 extern volatile __bit RXF4EID11 @ (((unsigned) &RXF4EIDH)*8) + 3; #define RXF4EID11_bit BANKMASK(RXF4EIDH), 3 extern volatile __bit RXF4EID12 @ (((unsigned) &RXF4EIDH)*8) + 4; #define RXF4EID12_bit BANKMASK(RXF4EIDH), 4 extern volatile __bit RXF4EID13 @ (((unsigned) &RXF4EIDH)*8) + 5; #define RXF4EID13_bit BANKMASK(RXF4EIDH), 5 extern volatile __bit RXF4EID14 @ (((unsigned) &RXF4EIDH)*8) + 6; #define RXF4EID14_bit BANKMASK(RXF4EIDH), 6 extern volatile __bit RXF4EID15 @ (((unsigned) &RXF4EIDH)*8) + 7; #define RXF4EID15_bit BANKMASK(RXF4EIDH), 7 extern volatile __bit RXF4EID16 @ (((unsigned) &RXF4SIDL)*8) + 0; #define RXF4EID16_bit BANKMASK(RXF4SIDL), 0 extern volatile __bit RXF4EID17 @ (((unsigned) &RXF4SIDL)*8) + 1; #define RXF4EID17_bit BANKMASK(RXF4SIDL), 1 extern volatile __bit RXF4EID2 @ (((unsigned) &RXF4EIDL)*8) + 2; #define RXF4EID2_bit BANKMASK(RXF4EIDL), 2 extern volatile __bit RXF4EID3 @ (((unsigned) &RXF4EIDL)*8) + 3; #define RXF4EID3_bit BANKMASK(RXF4EIDL), 3 extern volatile __bit RXF4EID4 @ (((unsigned) &RXF4EIDL)*8) + 4; #define RXF4EID4_bit BANKMASK(RXF4EIDL), 4 extern volatile __bit RXF4EID5 @ (((unsigned) &RXF4EIDL)*8) + 5; #define RXF4EID5_bit BANKMASK(RXF4EIDL), 5 extern volatile __bit RXF4EID6 @ (((unsigned) &RXF4EIDL)*8) + 6; #define RXF4EID6_bit BANKMASK(RXF4EIDL), 6 extern volatile __bit RXF4EID7 @ (((unsigned) &RXF4EIDL)*8) + 7; #define RXF4EID7_bit BANKMASK(RXF4EIDL), 7 extern volatile __bit RXF4EID8 @ (((unsigned) &RXF4EIDH)*8) + 0; #define RXF4EID8_bit BANKMASK(RXF4EIDH), 0 extern volatile __bit RXF4EID9 @ (((unsigned) &RXF4EIDH)*8) + 1; #define RXF4EID9_bit BANKMASK(RXF4EIDH), 1 extern volatile __bit RXF4EN @ (((unsigned) &RXFCON0)*8) + 4; #define RXF4EN_bit BANKMASK(RXFCON0), 4 extern volatile __bit RXF4EXIDEN @ (((unsigned) &RXF4SIDL)*8) + 3; #define RXF4EXIDEN_bit BANKMASK(RXF4SIDL), 3 extern volatile __bit RXF4SID0 @ (((unsigned) &RXF4SIDL)*8) + 5; #define RXF4SID0_bit BANKMASK(RXF4SIDL), 5 extern volatile __bit RXF4SID1 @ (((unsigned) &RXF4SIDL)*8) + 6; #define RXF4SID1_bit BANKMASK(RXF4SIDL), 6 extern volatile __bit RXF4SID10 @ (((unsigned) &RXF4SIDH)*8) + 7; #define RXF4SID10_bit BANKMASK(RXF4SIDH), 7 extern volatile __bit RXF4SID2 @ (((unsigned) &RXF4SIDL)*8) + 7; #define RXF4SID2_bit BANKMASK(RXF4SIDL), 7 extern volatile __bit RXF4SID3 @ (((unsigned) &RXF4SIDH)*8) + 0; #define RXF4SID3_bit BANKMASK(RXF4SIDH), 0 extern volatile __bit RXF4SID4 @ (((unsigned) &RXF4SIDH)*8) + 1; #define RXF4SID4_bit BANKMASK(RXF4SIDH), 1 extern volatile __bit RXF4SID5 @ (((unsigned) &RXF4SIDH)*8) + 2; #define RXF4SID5_bit BANKMASK(RXF4SIDH), 2 extern volatile __bit RXF4SID6 @ (((unsigned) &RXF4SIDH)*8) + 3; #define RXF4SID6_bit BANKMASK(RXF4SIDH), 3 extern volatile __bit RXF4SID7 @ (((unsigned) &RXF4SIDH)*8) + 4; #define RXF4SID7_bit BANKMASK(RXF4SIDH), 4 extern volatile __bit RXF4SID8 @ (((unsigned) &RXF4SIDH)*8) + 5; #define RXF4SID8_bit BANKMASK(RXF4SIDH), 5 extern volatile __bit RXF4SID9 @ (((unsigned) &RXF4SIDH)*8) + 6; #define RXF4SID9_bit BANKMASK(RXF4SIDH), 6 extern volatile __bit RXF5EID0 @ (((unsigned) &RXF5EIDL)*8) + 0; #define RXF5EID0_bit BANKMASK(RXF5EIDL), 0 extern volatile __bit RXF5EID1 @ (((unsigned) &RXF5EIDL)*8) + 1; #define RXF5EID1_bit BANKMASK(RXF5EIDL), 1 extern volatile __bit RXF5EID10 @ (((unsigned) &RXF5EIDH)*8) + 2; #define RXF5EID10_bit BANKMASK(RXF5EIDH), 2 extern volatile __bit RXF5EID11 @ (((unsigned) &RXF5EIDH)*8) + 3; #define RXF5EID11_bit BANKMASK(RXF5EIDH), 3 extern volatile __bit RXF5EID12 @ (((unsigned) &RXF5EIDH)*8) + 4; #define RXF5EID12_bit BANKMASK(RXF5EIDH), 4 extern volatile __bit RXF5EID13 @ (((unsigned) &RXF5EIDH)*8) + 5; #define RXF5EID13_bit BANKMASK(RXF5EIDH), 5 extern volatile __bit RXF5EID14 @ (((unsigned) &RXF5EIDH)*8) + 6; #define RXF5EID14_bit BANKMASK(RXF5EIDH), 6 extern volatile __bit RXF5EID15 @ (((unsigned) &RXF5EIDH)*8) + 7; #define RXF5EID15_bit BANKMASK(RXF5EIDH), 7 extern volatile __bit RXF5EID16 @ (((unsigned) &RXF5SIDL)*8) + 0; #define RXF5EID16_bit BANKMASK(RXF5SIDL), 0 extern volatile __bit RXF5EID17 @ (((unsigned) &RXF5SIDL)*8) + 1; #define RXF5EID17_bit BANKMASK(RXF5SIDL), 1 extern volatile __bit RXF5EID2 @ (((unsigned) &RXF5EIDL)*8) + 2; #define RXF5EID2_bit BANKMASK(RXF5EIDL), 2 extern volatile __bit RXF5EID3 @ (((unsigned) &RXF5EIDL)*8) + 3; #define RXF5EID3_bit BANKMASK(RXF5EIDL), 3 extern volatile __bit RXF5EID4 @ (((unsigned) &RXF5EIDL)*8) + 4; #define RXF5EID4_bit BANKMASK(RXF5EIDL), 4 extern volatile __bit RXF5EID5 @ (((unsigned) &RXF5EIDL)*8) + 5; #define RXF5EID5_bit BANKMASK(RXF5EIDL), 5 extern volatile __bit RXF5EID6 @ (((unsigned) &RXF5EIDL)*8) + 6; #define RXF5EID6_bit BANKMASK(RXF5EIDL), 6 extern volatile __bit RXF5EID7 @ (((unsigned) &RXF5EIDL)*8) + 7; #define RXF5EID7_bit BANKMASK(RXF5EIDL), 7 extern volatile __bit RXF5EID8 @ (((unsigned) &RXF5EIDH)*8) + 0; #define RXF5EID8_bit BANKMASK(RXF5EIDH), 0 extern volatile __bit RXF5EID9 @ (((unsigned) &RXF5EIDH)*8) + 1; #define RXF5EID9_bit BANKMASK(RXF5EIDH), 1 extern volatile __bit RXF5EN @ (((unsigned) &RXFCON0)*8) + 5; #define RXF5EN_bit BANKMASK(RXFCON0), 5 extern volatile __bit RXF5EXIDEN @ (((unsigned) &RXF5SIDL)*8) + 3; #define RXF5EXIDEN_bit BANKMASK(RXF5SIDL), 3 extern volatile __bit RXF5SID0 @ (((unsigned) &RXF5SIDL)*8) + 5; #define RXF5SID0_bit BANKMASK(RXF5SIDL), 5 extern volatile __bit RXF5SID1 @ (((unsigned) &RXF5SIDL)*8) + 6; #define RXF5SID1_bit BANKMASK(RXF5SIDL), 6 extern volatile __bit RXF5SID10 @ (((unsigned) &RXF5SIDH)*8) + 7; #define RXF5SID10_bit BANKMASK(RXF5SIDH), 7 extern volatile __bit RXF5SID2 @ (((unsigned) &RXF5SIDL)*8) + 7; #define RXF5SID2_bit BANKMASK(RXF5SIDL), 7 extern volatile __bit RXF5SID3 @ (((unsigned) &RXF5SIDH)*8) + 0; #define RXF5SID3_bit BANKMASK(RXF5SIDH), 0 extern volatile __bit RXF5SID4 @ (((unsigned) &RXF5SIDH)*8) + 1; #define RXF5SID4_bit BANKMASK(RXF5SIDH), 1 extern volatile __bit RXF5SID5 @ (((unsigned) &RXF5SIDH)*8) + 2; #define RXF5SID5_bit BANKMASK(RXF5SIDH), 2 extern volatile __bit RXF5SID6 @ (((unsigned) &RXF5SIDH)*8) + 3; #define RXF5SID6_bit BANKMASK(RXF5SIDH), 3 extern volatile __bit RXF5SID7 @ (((unsigned) &RXF5SIDH)*8) + 4; #define RXF5SID7_bit BANKMASK(RXF5SIDH), 4 extern volatile __bit RXF5SID8 @ (((unsigned) &RXF5SIDH)*8) + 5; #define RXF5SID8_bit BANKMASK(RXF5SIDH), 5 extern volatile __bit RXF5SID9 @ (((unsigned) &RXF5SIDH)*8) + 6; #define RXF5SID9_bit BANKMASK(RXF5SIDH), 6 extern volatile __bit RXF6EID0 @ (((unsigned) &RXF6EIDL)*8) + 0; #define RXF6EID0_bit BANKMASK(RXF6EIDL), 0 extern volatile __bit RXF6EID1 @ (((unsigned) &RXF6EIDL)*8) + 1; #define RXF6EID1_bit BANKMASK(RXF6EIDL), 1 extern volatile __bit RXF6EID10 @ (((unsigned) &RXF6EIDH)*8) + 2; #define RXF6EID10_bit BANKMASK(RXF6EIDH), 2 extern volatile __bit RXF6EID11 @ (((unsigned) &RXF6EIDH)*8) + 3; #define RXF6EID11_bit BANKMASK(RXF6EIDH), 3 extern volatile __bit RXF6EID12 @ (((unsigned) &RXF6EIDH)*8) + 4; #define RXF6EID12_bit BANKMASK(RXF6EIDH), 4 extern volatile __bit RXF6EID13 @ (((unsigned) &RXF6EIDH)*8) + 5; #define RXF6EID13_bit BANKMASK(RXF6EIDH), 5 extern volatile __bit RXF6EID14 @ (((unsigned) &RXF6EIDH)*8) + 6; #define RXF6EID14_bit BANKMASK(RXF6EIDH), 6 extern volatile __bit RXF6EID15 @ (((unsigned) &RXF6EIDH)*8) + 7; #define RXF6EID15_bit BANKMASK(RXF6EIDH), 7 extern volatile __bit RXF6EID16 @ (((unsigned) &RXF6SIDL)*8) + 0; #define RXF6EID16_bit BANKMASK(RXF6SIDL), 0 extern volatile __bit RXF6EID17 @ (((unsigned) &RXF6SIDL)*8) + 1; #define RXF6EID17_bit BANKMASK(RXF6SIDL), 1 extern volatile __bit RXF6EID2 @ (((unsigned) &RXF6EIDL)*8) + 2; #define RXF6EID2_bit BANKMASK(RXF6EIDL), 2 extern volatile __bit RXF6EID3 @ (((unsigned) &RXF6EIDL)*8) + 3; #define RXF6EID3_bit BANKMASK(RXF6EIDL), 3 extern volatile __bit RXF6EID4 @ (((unsigned) &RXF6EIDL)*8) + 4; #define RXF6EID4_bit BANKMASK(RXF6EIDL), 4 extern volatile __bit RXF6EID5 @ (((unsigned) &RXF6EIDL)*8) + 5; #define RXF6EID5_bit BANKMASK(RXF6EIDL), 5 extern volatile __bit RXF6EID6 @ (((unsigned) &RXF6EIDL)*8) + 6; #define RXF6EID6_bit BANKMASK(RXF6EIDL), 6 extern volatile __bit RXF6EID7 @ (((unsigned) &RXF6EIDL)*8) + 7; #define RXF6EID7_bit BANKMASK(RXF6EIDL), 7 extern volatile __bit RXF6EID8 @ (((unsigned) &RXF6EIDH)*8) + 0; #define RXF6EID8_bit BANKMASK(RXF6EIDH), 0 extern volatile __bit RXF6EID9 @ (((unsigned) &RXF6EIDH)*8) + 1; #define RXF6EID9_bit BANKMASK(RXF6EIDH), 1 extern volatile __bit RXF6EN @ (((unsigned) &RXFCON0)*8) + 6; #define RXF6EN_bit BANKMASK(RXFCON0), 6 extern volatile __bit RXF6EXIDEN @ (((unsigned) &RXF6SIDL)*8) + 3; #define RXF6EXIDEN_bit BANKMASK(RXF6SIDL), 3 extern volatile __bit RXF6SID0 @ (((unsigned) &RXF6SIDL)*8) + 5; #define RXF6SID0_bit BANKMASK(RXF6SIDL), 5 extern volatile __bit RXF6SID1 @ (((unsigned) &RXF6SIDL)*8) + 6; #define RXF6SID1_bit BANKMASK(RXF6SIDL), 6 extern volatile __bit RXF6SID10 @ (((unsigned) &RXF6SIDH)*8) + 7; #define RXF6SID10_bit BANKMASK(RXF6SIDH), 7 extern volatile __bit RXF6SID2 @ (((unsigned) &RXF6SIDL)*8) + 7; #define RXF6SID2_bit BANKMASK(RXF6SIDL), 7 extern volatile __bit RXF6SID3 @ (((unsigned) &RXF6SIDH)*8) + 0; #define RXF6SID3_bit BANKMASK(RXF6SIDH), 0 extern volatile __bit RXF6SID4 @ (((unsigned) &RXF6SIDH)*8) + 1; #define RXF6SID4_bit BANKMASK(RXF6SIDH), 1 extern volatile __bit RXF6SID5 @ (((unsigned) &RXF6SIDH)*8) + 2; #define RXF6SID5_bit BANKMASK(RXF6SIDH), 2 extern volatile __bit RXF6SID6 @ (((unsigned) &RXF6SIDH)*8) + 3; #define RXF6SID6_bit BANKMASK(RXF6SIDH), 3 extern volatile __bit RXF6SID7 @ (((unsigned) &RXF6SIDH)*8) + 4; #define RXF6SID7_bit BANKMASK(RXF6SIDH), 4 extern volatile __bit RXF6SID8 @ (((unsigned) &RXF6SIDH)*8) + 5; #define RXF6SID8_bit BANKMASK(RXF6SIDH), 5 extern volatile __bit RXF6SID9 @ (((unsigned) &RXF6SIDH)*8) + 6; #define RXF6SID9_bit BANKMASK(RXF6SIDH), 6 extern volatile __bit RXF7EID0 @ (((unsigned) &RXF7EIDL)*8) + 0; #define RXF7EID0_bit BANKMASK(RXF7EIDL), 0 extern volatile __bit RXF7EID1 @ (((unsigned) &RXF7EIDL)*8) + 1; #define RXF7EID1_bit BANKMASK(RXF7EIDL), 1 extern volatile __bit RXF7EID10 @ (((unsigned) &RXF7EIDH)*8) + 2; #define RXF7EID10_bit BANKMASK(RXF7EIDH), 2 extern volatile __bit RXF7EID11 @ (((unsigned) &RXF7EIDH)*8) + 3; #define RXF7EID11_bit BANKMASK(RXF7EIDH), 3 extern volatile __bit RXF7EID12 @ (((unsigned) &RXF7EIDH)*8) + 4; #define RXF7EID12_bit BANKMASK(RXF7EIDH), 4 extern volatile __bit RXF7EID13 @ (((unsigned) &RXF7EIDH)*8) + 5; #define RXF7EID13_bit BANKMASK(RXF7EIDH), 5 extern volatile __bit RXF7EID14 @ (((unsigned) &RXF7EIDH)*8) + 6; #define RXF7EID14_bit BANKMASK(RXF7EIDH), 6 extern volatile __bit RXF7EID15 @ (((unsigned) &RXF7EIDH)*8) + 7; #define RXF7EID15_bit BANKMASK(RXF7EIDH), 7 extern volatile __bit RXF7EID16 @ (((unsigned) &RXF7SIDL)*8) + 0; #define RXF7EID16_bit BANKMASK(RXF7SIDL), 0 extern volatile __bit RXF7EID17 @ (((unsigned) &RXF7SIDL)*8) + 1; #define RXF7EID17_bit BANKMASK(RXF7SIDL), 1 extern volatile __bit RXF7EID2 @ (((unsigned) &RXF7EIDL)*8) + 2; #define RXF7EID2_bit BANKMASK(RXF7EIDL), 2 extern volatile __bit RXF7EID3 @ (((unsigned) &RXF7EIDL)*8) + 3; #define RXF7EID3_bit BANKMASK(RXF7EIDL), 3 extern volatile __bit RXF7EID4 @ (((unsigned) &RXF7EIDL)*8) + 4; #define RXF7EID4_bit BANKMASK(RXF7EIDL), 4 extern volatile __bit RXF7EID5 @ (((unsigned) &RXF7EIDL)*8) + 5; #define RXF7EID5_bit BANKMASK(RXF7EIDL), 5 extern volatile __bit RXF7EID6 @ (((unsigned) &RXF7EIDL)*8) + 6; #define RXF7EID6_bit BANKMASK(RXF7EIDL), 6 extern volatile __bit RXF7EID7 @ (((unsigned) &RXF7EIDL)*8) + 7; #define RXF7EID7_bit BANKMASK(RXF7EIDL), 7 extern volatile __bit RXF7EID8 @ (((unsigned) &RXF7EIDH)*8) + 0; #define RXF7EID8_bit BANKMASK(RXF7EIDH), 0 extern volatile __bit RXF7EID9 @ (((unsigned) &RXF7EIDH)*8) + 1; #define RXF7EID9_bit BANKMASK(RXF7EIDH), 1 extern volatile __bit RXF7EN @ (((unsigned) &RXFCON0)*8) + 7; #define RXF7EN_bit BANKMASK(RXFCON0), 7 extern volatile __bit RXF7EXIDEN @ (((unsigned) &RXF7SIDL)*8) + 3; #define RXF7EXIDEN_bit BANKMASK(RXF7SIDL), 3 extern volatile __bit RXF7SID0 @ (((unsigned) &RXF7SIDL)*8) + 5; #define RXF7SID0_bit BANKMASK(RXF7SIDL), 5 extern volatile __bit RXF7SID1 @ (((unsigned) &RXF7SIDL)*8) + 6; #define RXF7SID1_bit BANKMASK(RXF7SIDL), 6 extern volatile __bit RXF7SID10 @ (((unsigned) &RXF7SIDH)*8) + 7; #define RXF7SID10_bit BANKMASK(RXF7SIDH), 7 extern volatile __bit RXF7SID2 @ (((unsigned) &RXF7SIDL)*8) + 7; #define RXF7SID2_bit BANKMASK(RXF7SIDL), 7 extern volatile __bit RXF7SID3 @ (((unsigned) &RXF7SIDH)*8) + 0; #define RXF7SID3_bit BANKMASK(RXF7SIDH), 0 extern volatile __bit RXF7SID4 @ (((unsigned) &RXF7SIDH)*8) + 1; #define RXF7SID4_bit BANKMASK(RXF7SIDH), 1 extern volatile __bit RXF7SID5 @ (((unsigned) &RXF7SIDH)*8) + 2; #define RXF7SID5_bit BANKMASK(RXF7SIDH), 2 extern volatile __bit RXF7SID6 @ (((unsigned) &RXF7SIDH)*8) + 3; #define RXF7SID6_bit BANKMASK(RXF7SIDH), 3 extern volatile __bit RXF7SID7 @ (((unsigned) &RXF7SIDH)*8) + 4; #define RXF7SID7_bit BANKMASK(RXF7SIDH), 4 extern volatile __bit RXF7SID8 @ (((unsigned) &RXF7SIDH)*8) + 5; #define RXF7SID8_bit BANKMASK(RXF7SIDH), 5 extern volatile __bit RXF7SID9 @ (((unsigned) &RXF7SIDH)*8) + 6; #define RXF7SID9_bit BANKMASK(RXF7SIDH), 6 extern volatile __bit RXF8EID0 @ (((unsigned) &RXF8EIDL)*8) + 0; #define RXF8EID0_bit BANKMASK(RXF8EIDL), 0 extern volatile __bit RXF8EID1 @ (((unsigned) &RXF8EIDL)*8) + 1; #define RXF8EID1_bit BANKMASK(RXF8EIDL), 1 extern volatile __bit RXF8EID10 @ (((unsigned) &RXF8EIDH)*8) + 2; #define RXF8EID10_bit BANKMASK(RXF8EIDH), 2 extern volatile __bit RXF8EID11 @ (((unsigned) &RXF8EIDH)*8) + 3; #define RXF8EID11_bit BANKMASK(RXF8EIDH), 3 extern volatile __bit RXF8EID12 @ (((unsigned) &RXF8EIDH)*8) + 4; #define RXF8EID12_bit BANKMASK(RXF8EIDH), 4 extern volatile __bit RXF8EID13 @ (((unsigned) &RXF8EIDH)*8) + 5; #define RXF8EID13_bit BANKMASK(RXF8EIDH), 5 extern volatile __bit RXF8EID14 @ (((unsigned) &RXF8EIDH)*8) + 6; #define RXF8EID14_bit BANKMASK(RXF8EIDH), 6 extern volatile __bit RXF8EID15 @ (((unsigned) &RXF8EIDH)*8) + 7; #define RXF8EID15_bit BANKMASK(RXF8EIDH), 7 extern volatile __bit RXF8EID16 @ (((unsigned) &RXF8SIDL)*8) + 0; #define RXF8EID16_bit BANKMASK(RXF8SIDL), 0 extern volatile __bit RXF8EID17 @ (((unsigned) &RXF8SIDL)*8) + 1; #define RXF8EID17_bit BANKMASK(RXF8SIDL), 1 extern volatile __bit RXF8EID2 @ (((unsigned) &RXF8EIDL)*8) + 2; #define RXF8EID2_bit BANKMASK(RXF8EIDL), 2 extern volatile __bit RXF8EID3 @ (((unsigned) &RXF8EIDL)*8) + 3; #define RXF8EID3_bit BANKMASK(RXF8EIDL), 3 extern volatile __bit RXF8EID4 @ (((unsigned) &RXF8EIDL)*8) + 4; #define RXF8EID4_bit BANKMASK(RXF8EIDL), 4 extern volatile __bit RXF8EID5 @ (((unsigned) &RXF8EIDL)*8) + 5; #define RXF8EID5_bit BANKMASK(RXF8EIDL), 5 extern volatile __bit RXF8EID6 @ (((unsigned) &RXF8EIDL)*8) + 6; #define RXF8EID6_bit BANKMASK(RXF8EIDL), 6 extern volatile __bit RXF8EID7 @ (((unsigned) &RXF8EIDL)*8) + 7; #define RXF8EID7_bit BANKMASK(RXF8EIDL), 7 extern volatile __bit RXF8EID8 @ (((unsigned) &RXF8EIDH)*8) + 0; #define RXF8EID8_bit BANKMASK(RXF8EIDH), 0 extern volatile __bit RXF8EID9 @ (((unsigned) &RXF8EIDH)*8) + 1; #define RXF8EID9_bit BANKMASK(RXF8EIDH), 1 extern volatile __bit RXF8EN @ (((unsigned) &RXFCON1)*8) + 0; #define RXF8EN_bit BANKMASK(RXFCON1), 0 extern volatile __bit RXF8EXIDEN @ (((unsigned) &RXF8SIDL)*8) + 3; #define RXF8EXIDEN_bit BANKMASK(RXF8SIDL), 3 extern volatile __bit RXF8SID0 @ (((unsigned) &RXF8SIDL)*8) + 5; #define RXF8SID0_bit BANKMASK(RXF8SIDL), 5 extern volatile __bit RXF8SID1 @ (((unsigned) &RXF8SIDL)*8) + 6; #define RXF8SID1_bit BANKMASK(RXF8SIDL), 6 extern volatile __bit RXF8SID10 @ (((unsigned) &RXF8SIDH)*8) + 7; #define RXF8SID10_bit BANKMASK(RXF8SIDH), 7 extern volatile __bit RXF8SID2 @ (((unsigned) &RXF8SIDL)*8) + 7; #define RXF8SID2_bit BANKMASK(RXF8SIDL), 7 extern volatile __bit RXF8SID3 @ (((unsigned) &RXF8SIDH)*8) + 0; #define RXF8SID3_bit BANKMASK(RXF8SIDH), 0 extern volatile __bit RXF8SID4 @ (((unsigned) &RXF8SIDH)*8) + 1; #define RXF8SID4_bit BANKMASK(RXF8SIDH), 1 extern volatile __bit RXF8SID5 @ (((unsigned) &RXF8SIDH)*8) + 2; #define RXF8SID5_bit BANKMASK(RXF8SIDH), 2 extern volatile __bit RXF8SID6 @ (((unsigned) &RXF8SIDH)*8) + 3; #define RXF8SID6_bit BANKMASK(RXF8SIDH), 3 extern volatile __bit RXF8SID7 @ (((unsigned) &RXF8SIDH)*8) + 4; #define RXF8SID7_bit BANKMASK(RXF8SIDH), 4 extern volatile __bit RXF8SID8 @ (((unsigned) &RXF8SIDH)*8) + 5; #define RXF8SID8_bit BANKMASK(RXF8SIDH), 5 extern volatile __bit RXF8SID9 @ (((unsigned) &RXF8SIDH)*8) + 6; #define RXF8SID9_bit BANKMASK(RXF8SIDH), 6 extern volatile __bit RXF9EID0 @ (((unsigned) &RXF9EIDL)*8) + 0; #define RXF9EID0_bit BANKMASK(RXF9EIDL), 0 extern volatile __bit RXF9EID1 @ (((unsigned) &RXF9EIDL)*8) + 1; #define RXF9EID1_bit BANKMASK(RXF9EIDL), 1 extern volatile __bit RXF9EID10 @ (((unsigned) &RXF9EIDH)*8) + 2; #define RXF9EID10_bit BANKMASK(RXF9EIDH), 2 extern volatile __bit RXF9EID11 @ (((unsigned) &RXF9EIDH)*8) + 3; #define RXF9EID11_bit BANKMASK(RXF9EIDH), 3 extern volatile __bit RXF9EID12 @ (((unsigned) &RXF9EIDH)*8) + 4; #define RXF9EID12_bit BANKMASK(RXF9EIDH), 4 extern volatile __bit RXF9EID13 @ (((unsigned) &RXF9EIDH)*8) + 5; #define RXF9EID13_bit BANKMASK(RXF9EIDH), 5 extern volatile __bit RXF9EID14 @ (((unsigned) &RXF9EIDH)*8) + 6; #define RXF9EID14_bit BANKMASK(RXF9EIDH), 6 extern volatile __bit RXF9EID15 @ (((unsigned) &RXF9EIDH)*8) + 7; #define RXF9EID15_bit BANKMASK(RXF9EIDH), 7 extern volatile __bit RXF9EID16 @ (((unsigned) &RXF9SIDL)*8) + 0; #define RXF9EID16_bit BANKMASK(RXF9SIDL), 0 extern volatile __bit RXF9EID17 @ (((unsigned) &RXF9SIDL)*8) + 1; #define RXF9EID17_bit BANKMASK(RXF9SIDL), 1 extern volatile __bit RXF9EID2 @ (((unsigned) &RXF9EIDL)*8) + 2; #define RXF9EID2_bit BANKMASK(RXF9EIDL), 2 extern volatile __bit RXF9EID3 @ (((unsigned) &RXF9EIDL)*8) + 3; #define RXF9EID3_bit BANKMASK(RXF9EIDL), 3 extern volatile __bit RXF9EID4 @ (((unsigned) &RXF9EIDL)*8) + 4; #define RXF9EID4_bit BANKMASK(RXF9EIDL), 4 extern volatile __bit RXF9EID5 @ (((unsigned) &RXF9EIDL)*8) + 5; #define RXF9EID5_bit BANKMASK(RXF9EIDL), 5 extern volatile __bit RXF9EID6 @ (((unsigned) &RXF9EIDL)*8) + 6; #define RXF9EID6_bit BANKMASK(RXF9EIDL), 6 extern volatile __bit RXF9EID7 @ (((unsigned) &RXF9EIDL)*8) + 7; #define RXF9EID7_bit BANKMASK(RXF9EIDL), 7 extern volatile __bit RXF9EID8 @ (((unsigned) &RXF9EIDH)*8) + 0; #define RXF9EID8_bit BANKMASK(RXF9EIDH), 0 extern volatile __bit RXF9EID9 @ (((unsigned) &RXF9EIDH)*8) + 1; #define RXF9EID9_bit BANKMASK(RXF9EIDH), 1 extern volatile __bit RXF9EN @ (((unsigned) &RXFCON1)*8) + 1; #define RXF9EN_bit BANKMASK(RXFCON1), 1 extern volatile __bit RXF9EXIDEN @ (((unsigned) &RXF9SIDL)*8) + 3; #define RXF9EXIDEN_bit BANKMASK(RXF9SIDL), 3 extern volatile __bit RXF9SID0 @ (((unsigned) &RXF9SIDL)*8) + 5; #define RXF9SID0_bit BANKMASK(RXF9SIDL), 5 extern volatile __bit RXF9SID1 @ (((unsigned) &RXF9SIDL)*8) + 6; #define RXF9SID1_bit BANKMASK(RXF9SIDL), 6 extern volatile __bit RXF9SID10 @ (((unsigned) &RXF9SIDH)*8) + 7; #define RXF9SID10_bit BANKMASK(RXF9SIDH), 7 extern volatile __bit RXF9SID2 @ (((unsigned) &RXF9SIDL)*8) + 7; #define RXF9SID2_bit BANKMASK(RXF9SIDL), 7 extern volatile __bit RXF9SID3 @ (((unsigned) &RXF9SIDH)*8) + 0; #define RXF9SID3_bit BANKMASK(RXF9SIDH), 0 extern volatile __bit RXF9SID4 @ (((unsigned) &RXF9SIDH)*8) + 1; #define RXF9SID4_bit BANKMASK(RXF9SIDH), 1 extern volatile __bit RXF9SID5 @ (((unsigned) &RXF9SIDH)*8) + 2; #define RXF9SID5_bit BANKMASK(RXF9SIDH), 2 extern volatile __bit RXF9SID6 @ (((unsigned) &RXF9SIDH)*8) + 3; #define RXF9SID6_bit BANKMASK(RXF9SIDH), 3 extern volatile __bit RXF9SID7 @ (((unsigned) &RXF9SIDH)*8) + 4; #define RXF9SID7_bit BANKMASK(RXF9SIDH), 4 extern volatile __bit RXF9SID8 @ (((unsigned) &RXF9SIDH)*8) + 5; #define RXF9SID8_bit BANKMASK(RXF9SIDH), 5 extern volatile __bit RXF9SID9 @ (((unsigned) &RXF9SIDH)*8) + 6; #define RXF9SID9_bit BANKMASK(RXF9SIDH), 6 extern volatile __bit RXM0EID0 @ (((unsigned) &RXM0EIDL)*8) + 0; #define RXM0EID0_bit BANKMASK(RXM0EIDL), 0 extern volatile __bit RXM0EID1 @ (((unsigned) &RXM0EIDL)*8) + 1; #define RXM0EID1_bit BANKMASK(RXM0EIDL), 1 extern volatile __bit RXM0EID10 @ (((unsigned) &RXM0EIDH)*8) + 2; #define RXM0EID10_bit BANKMASK(RXM0EIDH), 2 extern volatile __bit RXM0EID11 @ (((unsigned) &RXM0EIDH)*8) + 3; #define RXM0EID11_bit BANKMASK(RXM0EIDH), 3 extern volatile __bit RXM0EID12 @ (((unsigned) &RXM0EIDH)*8) + 4; #define RXM0EID12_bit BANKMASK(RXM0EIDH), 4 extern volatile __bit RXM0EID13 @ (((unsigned) &RXM0EIDH)*8) + 5; #define RXM0EID13_bit BANKMASK(RXM0EIDH), 5 extern volatile __bit RXM0EID14 @ (((unsigned) &RXM0EIDH)*8) + 6; #define RXM0EID14_bit BANKMASK(RXM0EIDH), 6 extern volatile __bit RXM0EID15 @ (((unsigned) &RXM0EIDH)*8) + 7; #define RXM0EID15_bit BANKMASK(RXM0EIDH), 7 extern volatile __bit RXM0EID16 @ (((unsigned) &RXM0SIDL)*8) + 0; #define RXM0EID16_bit BANKMASK(RXM0SIDL), 0 extern volatile __bit RXM0EID17 @ (((unsigned) &RXM0SIDL)*8) + 1; #define RXM0EID17_bit BANKMASK(RXM0SIDL), 1 extern volatile __bit RXM0EID2 @ (((unsigned) &RXM0EIDL)*8) + 2; #define RXM0EID2_bit BANKMASK(RXM0EIDL), 2 extern volatile __bit RXM0EID3 @ (((unsigned) &RXM0EIDL)*8) + 3; #define RXM0EID3_bit BANKMASK(RXM0EIDL), 3 extern volatile __bit RXM0EID4 @ (((unsigned) &RXM0EIDL)*8) + 4; #define RXM0EID4_bit BANKMASK(RXM0EIDL), 4 extern volatile __bit RXM0EID5 @ (((unsigned) &RXM0EIDL)*8) + 5; #define RXM0EID5_bit BANKMASK(RXM0EIDL), 5 extern volatile __bit RXM0EID6 @ (((unsigned) &RXM0EIDL)*8) + 6; #define RXM0EID6_bit BANKMASK(RXM0EIDL), 6 extern volatile __bit RXM0EID7 @ (((unsigned) &RXM0EIDL)*8) + 7; #define RXM0EID7_bit BANKMASK(RXM0EIDL), 7 extern volatile __bit RXM0EID8 @ (((unsigned) &RXM0EIDH)*8) + 0; #define RXM0EID8_bit BANKMASK(RXM0EIDH), 0 extern volatile __bit RXM0EID9 @ (((unsigned) &RXM0EIDH)*8) + 1; #define RXM0EID9_bit BANKMASK(RXM0EIDH), 1 extern volatile __bit RXM0EXIDM @ (((unsigned) &RXM0SIDL)*8) + 3; #define RXM0EXIDM_bit BANKMASK(RXM0SIDL), 3 extern volatile __bit RXM0SID0 @ (((unsigned) &RXM0SIDL)*8) + 5; #define RXM0SID0_bit BANKMASK(RXM0SIDL), 5 extern volatile __bit RXM0SID1 @ (((unsigned) &RXM0SIDL)*8) + 6; #define RXM0SID1_bit BANKMASK(RXM0SIDL), 6 extern volatile __bit RXM0SID10 @ (((unsigned) &RXM0SIDH)*8) + 7; #define RXM0SID10_bit BANKMASK(RXM0SIDH), 7 extern volatile __bit RXM0SID2 @ (((unsigned) &RXM0SIDL)*8) + 7; #define RXM0SID2_bit BANKMASK(RXM0SIDL), 7 extern volatile __bit RXM0SID3 @ (((unsigned) &RXM0SIDH)*8) + 0; #define RXM0SID3_bit BANKMASK(RXM0SIDH), 0 extern volatile __bit RXM0SID4 @ (((unsigned) &RXM0SIDH)*8) + 1; #define RXM0SID4_bit BANKMASK(RXM0SIDH), 1 extern volatile __bit RXM0SID5 @ (((unsigned) &RXM0SIDH)*8) + 2; #define RXM0SID5_bit BANKMASK(RXM0SIDH), 2 extern volatile __bit RXM0SID6 @ (((unsigned) &RXM0SIDH)*8) + 3; #define RXM0SID6_bit BANKMASK(RXM0SIDH), 3 extern volatile __bit RXM0SID7 @ (((unsigned) &RXM0SIDH)*8) + 4; #define RXM0SID7_bit BANKMASK(RXM0SIDH), 4 extern volatile __bit RXM0SID8 @ (((unsigned) &RXM0SIDH)*8) + 5; #define RXM0SID8_bit BANKMASK(RXM0SIDH), 5 extern volatile __bit RXM0SID9 @ (((unsigned) &RXM0SIDH)*8) + 6; #define RXM0SID9_bit BANKMASK(RXM0SIDH), 6 extern volatile __bit RXM1EID0 @ (((unsigned) &RXM1EIDL)*8) + 0; #define RXM1EID0_bit BANKMASK(RXM1EIDL), 0 extern volatile __bit RXM1EID1 @ (((unsigned) &RXM1EIDL)*8) + 1; #define RXM1EID1_bit BANKMASK(RXM1EIDL), 1 extern volatile __bit RXM1EID10 @ (((unsigned) &RXM1EIDH)*8) + 2; #define RXM1EID10_bit BANKMASK(RXM1EIDH), 2 extern volatile __bit RXM1EID11 @ (((unsigned) &RXM1EIDH)*8) + 3; #define RXM1EID11_bit BANKMASK(RXM1EIDH), 3 extern volatile __bit RXM1EID12 @ (((unsigned) &RXM1EIDH)*8) + 4; #define RXM1EID12_bit BANKMASK(RXM1EIDH), 4 extern volatile __bit RXM1EID13 @ (((unsigned) &RXM1EIDH)*8) + 5; #define RXM1EID13_bit BANKMASK(RXM1EIDH), 5 extern volatile __bit RXM1EID14 @ (((unsigned) &RXM1EIDH)*8) + 6; #define RXM1EID14_bit BANKMASK(RXM1EIDH), 6 extern volatile __bit RXM1EID15 @ (((unsigned) &RXM1EIDH)*8) + 7; #define RXM1EID15_bit BANKMASK(RXM1EIDH), 7 extern volatile __bit RXM1EID16 @ (((unsigned) &RXM1SIDL)*8) + 0; #define RXM1EID16_bit BANKMASK(RXM1SIDL), 0 extern volatile __bit RXM1EID17 @ (((unsigned) &RXM1SIDL)*8) + 1; #define RXM1EID17_bit BANKMASK(RXM1SIDL), 1 extern volatile __bit RXM1EID2 @ (((unsigned) &RXM1EIDL)*8) + 2; #define RXM1EID2_bit BANKMASK(RXM1EIDL), 2 extern volatile __bit RXM1EID3 @ (((unsigned) &RXM1EIDL)*8) + 3; #define RXM1EID3_bit BANKMASK(RXM1EIDL), 3 extern volatile __bit RXM1EID4 @ (((unsigned) &RXM1EIDL)*8) + 4; #define RXM1EID4_bit BANKMASK(RXM1EIDL), 4 extern volatile __bit RXM1EID5 @ (((unsigned) &RXM1EIDL)*8) + 5; #define RXM1EID5_bit BANKMASK(RXM1EIDL), 5 extern volatile __bit RXM1EID6 @ (((unsigned) &RXM1EIDL)*8) + 6; #define RXM1EID6_bit BANKMASK(RXM1EIDL), 6 extern volatile __bit RXM1EID7 @ (((unsigned) &RXM1EIDL)*8) + 7; #define RXM1EID7_bit BANKMASK(RXM1EIDL), 7 extern volatile __bit RXM1EID8 @ (((unsigned) &RXM1EIDH)*8) + 0; #define RXM1EID8_bit BANKMASK(RXM1EIDH), 0 extern volatile __bit RXM1EID9 @ (((unsigned) &RXM1EIDH)*8) + 1; #define RXM1EID9_bit BANKMASK(RXM1EIDH), 1 extern volatile __bit RXM1EXIDEN @ (((unsigned) &RXM1SIDL)*8) + 3; #define RXM1EXIDEN_bit BANKMASK(RXM1SIDL), 3 extern volatile __bit RXM1SID0 @ (((unsigned) &RXM1SIDL)*8) + 5; #define RXM1SID0_bit BANKMASK(RXM1SIDL), 5 extern volatile __bit RXM1SID1 @ (((unsigned) &RXM1SIDL)*8) + 6; #define RXM1SID1_bit BANKMASK(RXM1SIDL), 6 extern volatile __bit RXM1SID10 @ (((unsigned) &RXM1SIDH)*8) + 7; #define RXM1SID10_bit BANKMASK(RXM1SIDH), 7 extern volatile __bit RXM1SID2 @ (((unsigned) &RXM1SIDL)*8) + 7; #define RXM1SID2_bit BANKMASK(RXM1SIDL), 7 extern volatile __bit RXM1SID3 @ (((unsigned) &RXM1SIDH)*8) + 0; #define RXM1SID3_bit BANKMASK(RXM1SIDH), 0 extern volatile __bit RXM1SID4 @ (((unsigned) &RXM1SIDH)*8) + 1; #define RXM1SID4_bit BANKMASK(RXM1SIDH), 1 extern volatile __bit RXM1SID5 @ (((unsigned) &RXM1SIDH)*8) + 2; #define RXM1SID5_bit BANKMASK(RXM1SIDH), 2 extern volatile __bit RXM1SID6 @ (((unsigned) &RXM1SIDH)*8) + 3; #define RXM1SID6_bit BANKMASK(RXM1SIDH), 3 extern volatile __bit RXM1SID7 @ (((unsigned) &RXM1SIDH)*8) + 4; #define RXM1SID7_bit BANKMASK(RXM1SIDH), 4 extern volatile __bit RXM1SID8 @ (((unsigned) &RXM1SIDH)*8) + 5; #define RXM1SID8_bit BANKMASK(RXM1SIDH), 5 extern volatile __bit RXM1SID9 @ (((unsigned) &RXM1SIDH)*8) + 6; #define RXM1SID9_bit BANKMASK(RXM1SIDH), 6 extern volatile __bit RXWARN @ (((unsigned) &COMSTAT)*8) + 1; #define RXWARN_bit BANKMASK(COMSTAT), 1 extern volatile __bit R_NOT_W @ (((unsigned) &SSPSTAT)*8) + 2; #define R_NOT_W_bit BANKMASK(SSPSTAT), 2 extern volatile __bit R_W @ (((unsigned) &SSPSTAT)*8) + 2; #define R_W_bit BANKMASK(SSPSTAT), 2 extern volatile __bit R_nW @ (((unsigned) &SSPSTAT)*8) + 2; #define R_nW_bit BANKMASK(SSPSTAT), 2 extern volatile __bit SAM @ (((unsigned) &BRGCON2)*8) + 6; #define SAM_bit BANKMASK(BRGCON2), 6 extern volatile __bit SBOREN @ (((unsigned) &RCON)*8) + 6; #define SBOREN_bit BANKMASK(RCON), 6 extern volatile __bit SCKP @ (((unsigned) &BAUDCON1)*8) + 4; #define SCKP_bit BANKMASK(BAUDCON1), 4 extern volatile __bit SCKP1 @ (((unsigned) &BAUDCON1)*8) + 4; #define SCKP1_bit BANKMASK(BAUDCON1), 4 extern volatile __bit SCKP2 @ (((unsigned) &BAUDCON2)*8) + 4; #define SCKP2_bit BANKMASK(BAUDCON2), 4 extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0; #define SCS0_bit BANKMASK(OSCCON), 0 extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1; #define SCS1_bit BANKMASK(OSCCON), 1 extern volatile __bit SEG1PH0 @ (((unsigned) &BRGCON2)*8) + 3; #define SEG1PH0_bit BANKMASK(BRGCON2), 3 extern volatile __bit SEG1PH1 @ (((unsigned) &BRGCON2)*8) + 4; #define SEG1PH1_bit BANKMASK(BRGCON2), 4 extern volatile __bit SEG1PH2 @ (((unsigned) &BRGCON2)*8) + 5; #define SEG1PH2_bit BANKMASK(BRGCON2), 5 extern volatile __bit SEG2PH0 @ (((unsigned) &BRGCON3)*8) + 0; #define SEG2PH0_bit BANKMASK(BRGCON3), 0 extern volatile __bit SEG2PH1 @ (((unsigned) &BRGCON3)*8) + 1; #define SEG2PH1_bit BANKMASK(BRGCON3), 1 extern volatile __bit SEG2PH2 @ (((unsigned) &BRGCON3)*8) + 2; #define SEG2PH2_bit BANKMASK(BRGCON3), 2 extern volatile __bit SEG2PHT @ (((unsigned) &BRGCON2)*8) + 7; #define SEG2PHT_bit BANKMASK(BRGCON2), 7 extern volatile __bit SEG2PHTS @ (((unsigned) &BRGCON2)*8) + 7; #define SEG2PHTS_bit BANKMASK(BRGCON2), 7 extern volatile __bit SEN @ (((unsigned) &SSPCON2)*8) + 0; #define SEN_bit BANKMASK(SSPCON2), 0 extern volatile __bit SENDB1 @ (((unsigned) &TXSTA1)*8) + 3; #define SENDB1_bit BANKMASK(TXSTA1), 3 extern volatile __bit SENDB2 @ (((unsigned) &TXSTA2)*8) + 3; #define SENDB2_bit BANKMASK(TXSTA2), 3 extern volatile __bit SJW0 @ (((unsigned) &BRGCON1)*8) + 6; #define SJW0_bit BANKMASK(BRGCON1), 6 extern volatile __bit SJW1 @ (((unsigned) &BRGCON1)*8) + 7; #define SJW1_bit BANKMASK(BRGCON1), 7 extern volatile __bit SLRA @ (((unsigned) &SLRCON)*8) + 0; #define SLRA_bit BANKMASK(SLRCON), 0 extern volatile __bit SLRB @ (((unsigned) &SLRCON)*8) + 1; #define SLRB_bit BANKMASK(SLRCON), 1 extern volatile __bit SLRC @ (((unsigned) &SLRCON)*8) + 2; #define SLRC_bit BANKMASK(SLRCON), 2 extern volatile __bit SMP @ (((unsigned) &SSPSTAT)*8) + 7; #define SMP_bit BANKMASK(SSPSTAT), 7 extern volatile __bit SOSCDRV @ (((unsigned) &OSCCON2)*8) + 4; #define SOSCDRV_bit BANKMASK(OSCCON2), 4 extern volatile __bit SOSCEN3 @ (((unsigned) &T3CON)*8) + 3; #define SOSCEN3_bit BANKMASK(T3CON), 3 extern volatile __bit SOSCGO @ (((unsigned) &OSCCON2)*8) + 3; #define SOSCGO_bit BANKMASK(OSCCON2), 3 extern volatile __bit SOSCRUN @ (((unsigned) &OSCCON2)*8) + 6; #define SOSCRUN_bit BANKMASK(OSCCON2), 6 extern volatile __bit SP0 @ (((unsigned) &STKPTR)*8) + 0; #define SP0_bit BANKMASK(STKPTR), 0 extern volatile __bit SP1 @ (((unsigned) &STKPTR)*8) + 1; #define SP1_bit BANKMASK(STKPTR), 1 extern volatile __bit SP2 @ (((unsigned) &STKPTR)*8) + 2; #define SP2_bit BANKMASK(STKPTR), 2 extern volatile __bit SP3 @ (((unsigned) &STKPTR)*8) + 3; #define SP3_bit BANKMASK(STKPTR), 3 extern volatile __bit SP4 @ (((unsigned) &STKPTR)*8) + 4; #define SP4_bit BANKMASK(STKPTR), 4 extern volatile __bit SPEN1 @ (((unsigned) &RCSTA1)*8) + 7; #define SPEN1_bit BANKMASK(RCSTA1), 7 extern volatile __bit SPEN2 @ (((unsigned) &RCSTA2)*8) + 7; #define SPEN2_bit BANKMASK(RCSTA2), 7 extern volatile __bit SPI1MD @ (((unsigned) &PMD0)*8) + 1; #define SPI1MD_bit BANKMASK(PMD0), 1 extern volatile __bit SPI2MD @ (((unsigned) &PMD0)*8) + 2; #define SPI2MD_bit BANKMASK(PMD0), 2 extern volatile __bit SREN1 @ (((unsigned) &RCSTA1)*8) + 5; #define SREN1_bit BANKMASK(RCSTA1), 5 extern volatile __bit SREN2 @ (((unsigned) &RCSTA2)*8) + 5; #define SREN2_bit BANKMASK(RCSTA2), 5 extern volatile __bit SRENA @ (((unsigned) &RCSTA1)*8) + 5; #define SRENA_bit BANKMASK(RCSTA1), 5 extern volatile __bit SRETEN @ (((unsigned) &WDTCON)*8) + 4; #define SRETEN_bit BANKMASK(WDTCON), 4 extern volatile __bit SSPEN @ (((unsigned) &SSPCON1)*8) + 5; #define SSPEN_bit BANKMASK(SSPCON1), 5 extern volatile __bit SSPIE @ (((unsigned) &PIE1)*8) + 3; #define SSPIE_bit BANKMASK(PIE1), 3 extern volatile __bit SSPIF @ (((unsigned) &PIR1)*8) + 3; #define SSPIF_bit BANKMASK(PIR1), 3 extern volatile __bit SSPIP @ (((unsigned) &IPR1)*8) + 3; #define SSPIP_bit BANKMASK(IPR1), 3 extern volatile __bit SSPM0 @ (((unsigned) &SSPCON1)*8) + 0; #define SSPM0_bit BANKMASK(SSPCON1), 0 extern volatile __bit SSPM1 @ (((unsigned) &SSPCON1)*8) + 1; #define SSPM1_bit BANKMASK(SSPCON1), 1 extern volatile __bit SSPM2 @ (((unsigned) &SSPCON1)*8) + 2; #define SSPM2_bit BANKMASK(SSPCON1), 2 extern volatile __bit SSPM3 @ (((unsigned) &SSPCON1)*8) + 3; #define SSPM3_bit BANKMASK(SSPCON1), 3 extern volatile __bit SSPMD @ (((unsigned) &PMD0)*8) + 0; #define SSPMD_bit BANKMASK(PMD0), 0 extern volatile __bit SSPOD @ (((unsigned) &ODCON)*8) + 7; #define SSPOD_bit BANKMASK(ODCON), 7 extern volatile __bit SSPOV @ (((unsigned) &SSPCON1)*8) + 6; #define SSPOV_bit BANKMASK(SSPCON1), 6 extern volatile __bit START @ (((unsigned) &SSPSTAT)*8) + 3; #define START_bit BANKMASK(SSPSTAT), 3 extern volatile __bit STKFUL @ (((unsigned) &STKPTR)*8) + 7; #define STKFUL_bit BANKMASK(STKPTR), 7 extern volatile __bit STKOVF @ (((unsigned) &STKPTR)*8) + 7; #define STKOVF_bit BANKMASK(STKPTR), 7 extern volatile __bit STKUNF @ (((unsigned) &STKPTR)*8) + 6; #define STKUNF_bit BANKMASK(STKPTR), 6 extern volatile __bit STOP @ (((unsigned) &SSPSTAT)*8) + 4; #define STOP_bit BANKMASK(SSPSTAT), 4 extern volatile __bit STRA @ (((unsigned) &PSTR1CON)*8) + 0; #define STRA_bit BANKMASK(PSTR1CON), 0 extern volatile __bit STRB @ (((unsigned) &PSTR1CON)*8) + 1; #define STRB_bit BANKMASK(PSTR1CON), 1 extern volatile __bit STRC @ (((unsigned) &PSTR1CON)*8) + 2; #define STRC_bit BANKMASK(PSTR1CON), 2 extern volatile __bit STRD @ (((unsigned) &PSTR1CON)*8) + 3; #define STRD_bit BANKMASK(PSTR1CON), 3 extern volatile __bit STRSYNC @ (((unsigned) &PSTR1CON)*8) + 4; #define STRSYNC_bit BANKMASK(PSTR1CON), 4 extern volatile __bit SWDTE @ (((unsigned) &WDTCON)*8) + 0; #define SWDTE_bit BANKMASK(WDTCON), 0 extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0; #define SWDTEN_bit BANKMASK(WDTCON), 0 extern volatile __bit SYNC1 @ (((unsigned) &TXSTA1)*8) + 4; #define SYNC1_bit BANKMASK(TXSTA1), 4 extern volatile __bit SYNC2 @ (((unsigned) &TXSTA2)*8) + 4; #define SYNC2_bit BANKMASK(TXSTA2), 4 extern volatile __bit T08BIT @ (((unsigned) &T0CON)*8) + 6; #define T08BIT_bit BANKMASK(T0CON), 6 extern volatile __bit T0CS @ (((unsigned) &T0CON)*8) + 5; #define T0CS_bit BANKMASK(T0CON), 5 extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5; #define T0IE_bit BANKMASK(INTCON), 5 extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2; #define T0IF_bit BANKMASK(INTCON), 2 extern volatile __bit T0IP @ (((unsigned) &INTCON2)*8) + 2; #define T0IP_bit BANKMASK(INTCON2), 2 extern volatile __bit T0PS0 @ (((unsigned) &T0CON)*8) + 0; #define T0PS0_bit BANKMASK(T0CON), 0 extern volatile __bit T0PS1 @ (((unsigned) &T0CON)*8) + 1; #define T0PS1_bit BANKMASK(T0CON), 1 extern volatile __bit T0PS2 @ (((unsigned) &T0CON)*8) + 2; #define T0PS2_bit BANKMASK(T0CON), 2 extern volatile __bit T0SE @ (((unsigned) &T0CON)*8) + 4; #define T0SE_bit BANKMASK(T0CON), 4 extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4; #define T1CKPS0_bit BANKMASK(T1CON), 4 extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5; #define T1CKPS1_bit BANKMASK(T1CON), 5 extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3; #define T1GGO_bit BANKMASK(T1GCON), 3 extern volatile __bit T1GGO_NOT_T1DONE @ (((unsigned) &T1GCON)*8) + 3; #define T1GGO_NOT_T1DONE_bit BANKMASK(T1GCON), 3 extern volatile __bit T1GGO_nT1DONE @ (((unsigned) &T1GCON)*8) + 3; #define T1GGO_nT1DONE_bit BANKMASK(T1GCON), 3 extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6; #define T1GPOL_bit BANKMASK(T1GCON), 6 extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4; #define T1GSPM_bit BANKMASK(T1GCON), 4 extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0; #define T1GSS0_bit BANKMASK(T1GCON), 0 extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1; #define T1GSS1_bit BANKMASK(T1GCON), 1 extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5; #define T1GTM_bit BANKMASK(T1GCON), 5 extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2; #define T1GVAL_bit BANKMASK(T1GCON), 2 extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3; #define T1OSCEN_bit BANKMASK(T1CON), 3 extern volatile __bit T1RD16 @ (((unsigned) &T1CON)*8) + 7; #define T1RD16_bit BANKMASK(T1CON), 7 extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0; #define T2CKPS0_bit BANKMASK(T2CON), 0 extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1; #define T2CKPS1_bit BANKMASK(T2CON), 1 extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3; #define T2OUTPS0_bit BANKMASK(T2CON), 3 extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4; #define T2OUTPS1_bit BANKMASK(T2CON), 4 extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5; #define T2OUTPS2_bit BANKMASK(T2CON), 5 extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6; #define T2OUTPS3_bit BANKMASK(T2CON), 6 extern volatile __bit T3CKPS0 @ (((unsigned) &T3CON)*8) + 4; #define T3CKPS0_bit BANKMASK(T3CON), 4 extern volatile __bit T3CKPS1 @ (((unsigned) &T3CON)*8) + 5; #define T3CKPS1_bit BANKMASK(T3CON), 5 extern volatile __bit T3GGO @ (((unsigned) &T3GCON)*8) + 3; #define T3GGO_bit BANKMASK(T3GCON), 3 extern volatile __bit T3GGO_NOT_T3DONE @ (((unsigned) &T3GCON)*8) + 3; #define T3GGO_NOT_T3DONE_bit BANKMASK(T3GCON), 3 extern volatile __bit T3GGO_nT3DONE @ (((unsigned) &T3GCON)*8) + 3; #define T3GGO_nT3DONE_bit BANKMASK(T3GCON), 3 extern volatile __bit T3GPOL @ (((unsigned) &T3GCON)*8) + 6; #define T3GPOL_bit BANKMASK(T3GCON), 6 extern volatile __bit T3GSPM @ (((unsigned) &T3GCON)*8) + 4; #define T3GSPM_bit BANKMASK(T3GCON), 4 extern volatile __bit T3GSS0 @ (((unsigned) &T3GCON)*8) + 0; #define T3GSS0_bit BANKMASK(T3GCON), 0 extern volatile __bit T3GSS1 @ (((unsigned) &T3GCON)*8) + 1; #define T3GSS1_bit BANKMASK(T3GCON), 1 extern volatile __bit T3GTM @ (((unsigned) &T3GCON)*8) + 5; #define T3GTM_bit BANKMASK(T3GCON), 5 extern volatile __bit T3GVAL @ (((unsigned) &T3GCON)*8) + 2; #define T3GVAL_bit BANKMASK(T3GCON), 2 extern volatile __bit T3RD16 @ (((unsigned) &T3CON)*8) + 7; #define T3RD16_bit BANKMASK(T3CON), 7 extern volatile __bit T4CKPS0 @ (((unsigned) &T4CON)*8) + 0; #define T4CKPS0_bit BANKMASK(T4CON), 0 extern volatile __bit T4CKPS1 @ (((unsigned) &T4CON)*8) + 1; #define T4CKPS1_bit BANKMASK(T4CON), 1 extern volatile __bit T4OUTPS0 @ (((unsigned) &T4CON)*8) + 3; #define T4OUTPS0_bit BANKMASK(T4CON), 3 extern volatile __bit T4OUTPS1 @ (((unsigned) &T4CON)*8) + 4; #define T4OUTPS1_bit BANKMASK(T4CON), 4 extern volatile __bit T4OUTPS2 @ (((unsigned) &T4CON)*8) + 5; #define T4OUTPS2_bit BANKMASK(T4CON), 5 extern volatile __bit T4OUTPS3 @ (((unsigned) &T4CON)*8) + 6; #define T4OUTPS3_bit BANKMASK(T4CON), 6 extern volatile __bit TEC0 @ (((unsigned) &TXERRCNT)*8) + 0; #define TEC0_bit BANKMASK(TXERRCNT), 0 extern volatile __bit TEC1 @ (((unsigned) &TXERRCNT)*8) + 1; #define TEC1_bit BANKMASK(TXERRCNT), 1 extern volatile __bit TEC2 @ (((unsigned) &TXERRCNT)*8) + 2; #define TEC2_bit BANKMASK(TXERRCNT), 2 extern volatile __bit TEC3 @ (((unsigned) &TXERRCNT)*8) + 3; #define TEC3_bit BANKMASK(TXERRCNT), 3 extern volatile __bit TEC4 @ (((unsigned) &TXERRCNT)*8) + 4; #define TEC4_bit BANKMASK(TXERRCNT), 4 extern volatile __bit TEC5 @ (((unsigned) &TXERRCNT)*8) + 5; #define TEC5_bit BANKMASK(TXERRCNT), 5 extern volatile __bit TEC6 @ (((unsigned) &TXERRCNT)*8) + 6; #define TEC6_bit BANKMASK(TXERRCNT), 6 extern volatile __bit TEC7 @ (((unsigned) &TXERRCNT)*8) + 7; #define TEC7_bit BANKMASK(TXERRCNT), 7 extern volatile __bit TGEN @ (((unsigned) &CTMUCONH)*8) + 4; #define TGEN_bit BANKMASK(CTMUCONH), 4 extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5; #define TMR0IE_bit BANKMASK(INTCON), 5 extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2; #define TMR0IF_bit BANKMASK(INTCON), 2 extern volatile __bit TMR0IP @ (((unsigned) &INTCON2)*8) + 2; #define TMR0IP_bit BANKMASK(INTCON2), 2 extern volatile __bit TMR0MD @ (((unsigned) &PMD1)*8) + 0; #define TMR0MD_bit BANKMASK(PMD1), 0 extern volatile __bit TMR0ON @ (((unsigned) &T0CON)*8) + 7; #define TMR0ON_bit BANKMASK(T0CON), 7 extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6; #define TMR1CS0_bit BANKMASK(T1CON), 6 extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7; #define TMR1CS1_bit BANKMASK(T1CON), 7 extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7; #define TMR1GE_bit BANKMASK(T1GCON), 7 extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 2; #define TMR1GIE_bit BANKMASK(PIE1), 2 extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 2; #define TMR1GIF_bit BANKMASK(PIR1), 2 extern volatile __bit TMR1GIP @ (((unsigned) &IPR1)*8) + 2; #define TMR1GIP_bit BANKMASK(IPR1), 2 extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0; #define TMR1IE_bit BANKMASK(PIE1), 0 extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0; #define TMR1IF_bit BANKMASK(PIR1), 0 extern volatile __bit TMR1IP @ (((unsigned) &IPR1)*8) + 0; #define TMR1IP_bit BANKMASK(IPR1), 0 extern volatile __bit TMR1MD @ (((unsigned) &PMD1)*8) + 1; #define TMR1MD_bit BANKMASK(PMD1), 1 extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0; #define TMR1ON_bit BANKMASK(T1CON), 0 extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1; #define TMR2IE_bit BANKMASK(PIE1), 1 extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1; #define TMR2IF_bit BANKMASK(PIR1), 1 extern volatile __bit TMR2IP @ (((unsigned) &IPR1)*8) + 1; #define TMR2IP_bit BANKMASK(IPR1), 1 extern volatile __bit TMR2MD @ (((unsigned) &PMD1)*8) + 2; #define TMR2MD_bit BANKMASK(PMD1), 2 extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2; #define TMR2ON_bit BANKMASK(T2CON), 2 extern volatile __bit TMR3CS0 @ (((unsigned) &T3CON)*8) + 6; #define TMR3CS0_bit BANKMASK(T3CON), 6 extern volatile __bit TMR3CS1 @ (((unsigned) &T3CON)*8) + 7; #define TMR3CS1_bit BANKMASK(T3CON), 7 extern volatile __bit TMR3GE @ (((unsigned) &T3GCON)*8) + 7; #define TMR3GE_bit BANKMASK(T3GCON), 7 extern volatile __bit TMR3GIE @ (((unsigned) &PIE2)*8) + 0; #define TMR3GIE_bit BANKMASK(PIE2), 0 extern volatile __bit TMR3GIF @ (((unsigned) &PIR2)*8) + 0; #define TMR3GIF_bit BANKMASK(PIR2), 0 extern volatile __bit TMR3GIP @ (((unsigned) &IPR2)*8) + 0; #define TMR3GIP_bit BANKMASK(IPR2), 0 extern volatile __bit TMR3IE @ (((unsigned) &PIE2)*8) + 1; #define TMR3IE_bit BANKMASK(PIE2), 1 extern volatile __bit TMR3IF @ (((unsigned) &PIR2)*8) + 1; #define TMR3IF_bit BANKMASK(PIR2), 1 extern volatile __bit TMR3IP @ (((unsigned) &IPR2)*8) + 1; #define TMR3IP_bit BANKMASK(IPR2), 1 extern volatile __bit TMR3MD @ (((unsigned) &PMD1)*8) + 3; #define TMR3MD_bit BANKMASK(PMD1), 3 extern volatile __bit TMR3ON @ (((unsigned) &T3CON)*8) + 0; #define TMR3ON_bit BANKMASK(T3CON), 0 extern volatile __bit TMR4IE @ (((unsigned) &PIE4)*8) + 7; #define TMR4IE_bit BANKMASK(PIE4), 7 extern volatile __bit TMR4IF @ (((unsigned) &PIR4)*8) + 7; #define TMR4IF_bit BANKMASK(PIR4), 7 extern volatile __bit TMR4IP @ (((unsigned) &IPR4)*8) + 7; #define TMR4IP_bit BANKMASK(IPR4), 7 extern volatile __bit TMR4MD @ (((unsigned) &PMD1)*8) + 4; #define TMR4MD_bit BANKMASK(PMD1), 4 extern volatile __bit TMR4ON @ (((unsigned) &T4CON)*8) + 2; #define TMR4ON_bit BANKMASK(T4CON), 2 extern volatile __bit TO @ (((unsigned) &RCON)*8) + 3; #define TO_bit BANKMASK(RCON), 3 extern volatile __bit TRIGSEL0 @ (((unsigned) &ADCON1)*8) + 6; #define TRIGSEL0_bit BANKMASK(ADCON1), 6 extern volatile __bit TRIGSEL1 @ (((unsigned) &ADCON1)*8) + 7; #define TRIGSEL1_bit BANKMASK(ADCON1), 7 extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0; #define TRISA0_bit BANKMASK(TRISA), 0 extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1; #define TRISA1_bit BANKMASK(TRISA), 1 extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2; #define TRISA2_bit BANKMASK(TRISA), 2 extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3; #define TRISA3_bit BANKMASK(TRISA), 3 extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5; #define TRISA5_bit BANKMASK(TRISA), 5 extern volatile __bit TRISA6 @ (((unsigned) &TRISA)*8) + 6; #define TRISA6_bit BANKMASK(TRISA), 6 extern volatile __bit TRISA7 @ (((unsigned) &TRISA)*8) + 7; #define TRISA7_bit BANKMASK(TRISA), 7 extern volatile __bit TRISB0 @ (((unsigned) &TRISB)*8) + 0; #define TRISB0_bit BANKMASK(TRISB), 0 extern volatile __bit TRISB1 @ (((unsigned) &TRISB)*8) + 1; #define TRISB1_bit BANKMASK(TRISB), 1 extern volatile __bit TRISB2 @ (((unsigned) &TRISB)*8) + 2; #define TRISB2_bit BANKMASK(TRISB), 2 extern volatile __bit TRISB3 @ (((unsigned) &TRISB)*8) + 3; #define TRISB3_bit BANKMASK(TRISB), 3 extern volatile __bit TRISB4 @ (((unsigned) &TRISB)*8) + 4; #define TRISB4_bit BANKMASK(TRISB), 4 extern volatile __bit TRISB5 @ (((unsigned) &TRISB)*8) + 5; #define TRISB5_bit BANKMASK(TRISB), 5 extern volatile __bit TRISB6 @ (((unsigned) &TRISB)*8) + 6; #define TRISB6_bit BANKMASK(TRISB), 6 extern volatile __bit TRISB7 @ (((unsigned) &TRISB)*8) + 7; #define TRISB7_bit BANKMASK(TRISB), 7 extern volatile __bit TRISC0 @ (((unsigned) &TRISC)*8) + 0; #define TRISC0_bit BANKMASK(TRISC), 0 extern volatile __bit TRISC1 @ (((unsigned) &TRISC)*8) + 1; #define TRISC1_bit BANKMASK(TRISC), 1 extern volatile __bit TRISC2 @ (((unsigned) &TRISC)*8) + 2; #define TRISC2_bit BANKMASK(TRISC), 2 extern volatile __bit TRISC3 @ (((unsigned) &TRISC)*8) + 3; #define TRISC3_bit BANKMASK(TRISC), 3 extern volatile __bit TRISC4 @ (((unsigned) &TRISC)*8) + 4; #define TRISC4_bit BANKMASK(TRISC), 4 extern volatile __bit TRISC5 @ (((unsigned) &TRISC)*8) + 5; #define TRISC5_bit BANKMASK(TRISC), 5 extern volatile __bit TRISC6 @ (((unsigned) &TRISC)*8) + 6; #define TRISC6_bit BANKMASK(TRISC), 6 extern volatile __bit TRISC7 @ (((unsigned) &TRISC)*8) + 7; #define TRISC7_bit BANKMASK(TRISC), 7 extern volatile __bit TRMT1 @ (((unsigned) &TXSTA1)*8) + 1; #define TRMT1_bit BANKMASK(TXSTA1), 1 extern volatile __bit TRMT2 @ (((unsigned) &TXSTA2)*8) + 1; #define TRMT2_bit BANKMASK(TXSTA2), 1 extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0; #define TUN0_bit BANKMASK(OSCTUNE), 0 extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1; #define TUN1_bit BANKMASK(OSCTUNE), 1 extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2; #define TUN2_bit BANKMASK(OSCTUNE), 2 extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3; #define TUN3_bit BANKMASK(OSCTUNE), 3 extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4; #define TUN4_bit BANKMASK(OSCTUNE), 4 extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5; #define TUN5_bit BANKMASK(OSCTUNE), 5 extern volatile __bit TX0IE @ (((unsigned) &TXBIE)*8) + 2; #define TX0IE_bit BANKMASK(TXBIE), 2 extern volatile __bit TX0IF @ (((unsigned) &TXB0CON)*8) + 7; #define TX0IF_bit BANKMASK(TXB0CON), 7 extern volatile __bit _DEPRECATED TX1IE @ (((unsigned) &PIE1)*8) + 4; #define TX1IE_bit BANKMASK(PIE1), 4 extern volatile __bit _DEPRECATED TX1IF @ (((unsigned) &PIR1)*8) + 4; #define TX1IF_bit BANKMASK(PIR1), 4 extern volatile __bit TX1IP @ (((unsigned) &IPR1)*8) + 4; #define TX1IP_bit BANKMASK(IPR1), 4 extern volatile __bit TX2EN @ (((unsigned) &CIOCON)*8) + 6; #define TX2EN_bit BANKMASK(CIOCON), 6 extern volatile __bit _DEPRECATED TX2IE @ (((unsigned) &PIE3)*8) + 4; #define TX2IE_bit BANKMASK(PIE3), 4 extern volatile __bit _DEPRECATED TX2IF @ (((unsigned) &PIR3)*8) + 4; #define TX2IF_bit BANKMASK(PIR3), 4 extern volatile __bit TX2IP @ (((unsigned) &IPR3)*8) + 4; #define TX2IP_bit BANKMASK(IPR3), 4 extern volatile __bit TX2SRC @ (((unsigned) &CIOCON)*8) + 7; #define TX2SRC_bit BANKMASK(CIOCON), 7 extern volatile __bit TX8_9 @ (((unsigned) &TXSTA1)*8) + 6; #define TX8_9_bit BANKMASK(TXSTA1), 6 extern volatile __bit TX8_92 @ (((unsigned) &TXSTA2)*8) + 6; #define TX8_92_bit BANKMASK(TXSTA2), 6 extern volatile __bit TX91 @ (((unsigned) &TXSTA1)*8) + 6; #define TX91_bit BANKMASK(TXSTA1), 6 extern volatile __bit TX92 @ (((unsigned) &TXSTA2)*8) + 6; #define TX92_bit BANKMASK(TXSTA2), 6 extern volatile __bit TX9D1 @ (((unsigned) &TXSTA1)*8) + 0; #define TX9D1_bit BANKMASK(TXSTA1), 0 extern volatile __bit TX9D2 @ (((unsigned) &TXSTA2)*8) + 0; #define TX9D2_bit BANKMASK(TXSTA2), 0 extern volatile __bit TXB0ABT @ (((unsigned) &TXB0CON)*8) + 6; #define TXB0ABT_bit BANKMASK(TXB0CON), 6 extern volatile __bit TXB0D00 @ (((unsigned) &TXB0D0)*8) + 0; #define TXB0D00_bit BANKMASK(TXB0D0), 0 extern volatile __bit TXB0D01 @ (((unsigned) &TXB0D0)*8) + 1; #define TXB0D01_bit BANKMASK(TXB0D0), 1 extern volatile __bit TXB0D02 @ (((unsigned) &TXB0D0)*8) + 2; #define TXB0D02_bit BANKMASK(TXB0D0), 2 extern volatile __bit TXB0D03 @ (((unsigned) &TXB0D0)*8) + 3; #define TXB0D03_bit BANKMASK(TXB0D0), 3 extern volatile __bit TXB0D04 @ (((unsigned) &TXB0D0)*8) + 4; #define TXB0D04_bit BANKMASK(TXB0D0), 4 extern volatile __bit TXB0D05 @ (((unsigned) &TXB0D0)*8) + 5; #define TXB0D05_bit BANKMASK(TXB0D0), 5 extern volatile __bit TXB0D06 @ (((unsigned) &TXB0D0)*8) + 6; #define TXB0D06_bit BANKMASK(TXB0D0), 6 extern volatile __bit TXB0D07 @ (((unsigned) &TXB0D0)*8) + 7; #define TXB0D07_bit BANKMASK(TXB0D0), 7 extern volatile __bit TXB0D10 @ (((unsigned) &TXB0D1)*8) + 0; #define TXB0D10_bit BANKMASK(TXB0D1), 0 extern volatile __bit TXB0D11 @ (((unsigned) &TXB0D1)*8) + 1; #define TXB0D11_bit BANKMASK(TXB0D1), 1 extern volatile __bit TXB0D12 @ (((unsigned) &TXB0D1)*8) + 2; #define TXB0D12_bit BANKMASK(TXB0D1), 2 extern volatile __bit TXB0D13 @ (((unsigned) &TXB0D1)*8) + 3; #define TXB0D13_bit BANKMASK(TXB0D1), 3 extern volatile __bit TXB0D14 @ (((unsigned) &TXB0D1)*8) + 4; #define TXB0D14_bit BANKMASK(TXB0D1), 4 extern volatile __bit TXB0D15 @ (((unsigned) &TXB0D1)*8) + 5; #define TXB0D15_bit BANKMASK(TXB0D1), 5 extern volatile __bit TXB0D16 @ (((unsigned) &TXB0D1)*8) + 6; #define TXB0D16_bit BANKMASK(TXB0D1), 6 extern volatile __bit TXB0D17 @ (((unsigned) &TXB0D1)*8) + 7; #define TXB0D17_bit BANKMASK(TXB0D1), 7 extern volatile __bit TXB0D20 @ (((unsigned) &TXB0D2)*8) + 0; #define TXB0D20_bit BANKMASK(TXB0D2), 0 extern volatile __bit TXB0D21 @ (((unsigned) &TXB0D2)*8) + 1; #define TXB0D21_bit BANKMASK(TXB0D2), 1 extern volatile __bit TXB0D22 @ (((unsigned) &TXB0D2)*8) + 2; #define TXB0D22_bit BANKMASK(TXB0D2), 2 extern volatile __bit TXB0D23 @ (((unsigned) &TXB0D2)*8) + 3; #define TXB0D23_bit BANKMASK(TXB0D2), 3 extern volatile __bit TXB0D24 @ (((unsigned) &TXB0D2)*8) + 4; #define TXB0D24_bit BANKMASK(TXB0D2), 4 extern volatile __bit TXB0D25 @ (((unsigned) &TXB0D2)*8) + 5; #define TXB0D25_bit BANKMASK(TXB0D2), 5 extern volatile __bit TXB0D26 @ (((unsigned) &TXB0D2)*8) + 6; #define TXB0D26_bit BANKMASK(TXB0D2), 6 extern volatile __bit TXB0D27 @ (((unsigned) &TXB0D2)*8) + 7; #define TXB0D27_bit BANKMASK(TXB0D2), 7 extern volatile __bit TXB0D30 @ (((unsigned) &TXB0D3)*8) + 0; #define TXB0D30_bit BANKMASK(TXB0D3), 0 extern volatile __bit TXB0D31 @ (((unsigned) &TXB0D3)*8) + 1; #define TXB0D31_bit BANKMASK(TXB0D3), 1 extern volatile __bit TXB0D32 @ (((unsigned) &TXB0D3)*8) + 2; #define TXB0D32_bit BANKMASK(TXB0D3), 2 extern volatile __bit TXB0D33 @ (((unsigned) &TXB0D3)*8) + 3; #define TXB0D33_bit BANKMASK(TXB0D3), 3 extern volatile __bit TXB0D34 @ (((unsigned) &TXB0D3)*8) + 4; #define TXB0D34_bit BANKMASK(TXB0D3), 4 extern volatile __bit TXB0D35 @ (((unsigned) &TXB0D3)*8) + 5; #define TXB0D35_bit BANKMASK(TXB0D3), 5 extern volatile __bit TXB0D36 @ (((unsigned) &TXB0D3)*8) + 6; #define TXB0D36_bit BANKMASK(TXB0D3), 6 extern volatile __bit TXB0D37 @ (((unsigned) &TXB0D3)*8) + 7; #define TXB0D37_bit BANKMASK(TXB0D3), 7 extern volatile __bit TXB0D40 @ (((unsigned) &TXB0D4)*8) + 0; #define TXB0D40_bit BANKMASK(TXB0D4), 0 extern volatile __bit TXB0D41 @ (((unsigned) &TXB0D4)*8) + 1; #define TXB0D41_bit BANKMASK(TXB0D4), 1 extern volatile __bit TXB0D42 @ (((unsigned) &TXB0D4)*8) + 2; #define TXB0D42_bit BANKMASK(TXB0D4), 2 extern volatile __bit TXB0D43 @ (((unsigned) &TXB0D4)*8) + 3; #define TXB0D43_bit BANKMASK(TXB0D4), 3 extern volatile __bit TXB0D44 @ (((unsigned) &TXB0D4)*8) + 4; #define TXB0D44_bit BANKMASK(TXB0D4), 4 extern volatile __bit TXB0D45 @ (((unsigned) &TXB0D4)*8) + 5; #define TXB0D45_bit BANKMASK(TXB0D4), 5 extern volatile __bit TXB0D46 @ (((unsigned) &TXB0D4)*8) + 6; #define TXB0D46_bit BANKMASK(TXB0D4), 6 extern volatile __bit TXB0D47 @ (((unsigned) &TXB0D4)*8) + 7; #define TXB0D47_bit BANKMASK(TXB0D4), 7 extern volatile __bit TXB0D50 @ (((unsigned) &TXB0D5)*8) + 0; #define TXB0D50_bit BANKMASK(TXB0D5), 0 extern volatile __bit TXB0D51 @ (((unsigned) &TXB0D5)*8) + 1; #define TXB0D51_bit BANKMASK(TXB0D5), 1 extern volatile __bit TXB0D52 @ (((unsigned) &TXB0D5)*8) + 2; #define TXB0D52_bit BANKMASK(TXB0D5), 2 extern volatile __bit TXB0D53 @ (((unsigned) &TXB0D5)*8) + 3; #define TXB0D53_bit BANKMASK(TXB0D5), 3 extern volatile __bit TXB0D54 @ (((unsigned) &TXB0D5)*8) + 4; #define TXB0D54_bit BANKMASK(TXB0D5), 4 extern volatile __bit TXB0D55 @ (((unsigned) &TXB0D5)*8) + 5; #define TXB0D55_bit BANKMASK(TXB0D5), 5 extern volatile __bit TXB0D56 @ (((unsigned) &TXB0D5)*8) + 6; #define TXB0D56_bit BANKMASK(TXB0D5), 6 extern volatile __bit TXB0D57 @ (((unsigned) &TXB0D5)*8) + 7; #define TXB0D57_bit BANKMASK(TXB0D5), 7 extern volatile __bit TXB0D60 @ (((unsigned) &TXB0D6)*8) + 0; #define TXB0D60_bit BANKMASK(TXB0D6), 0 extern volatile __bit TXB0D61 @ (((unsigned) &TXB0D6)*8) + 1; #define TXB0D61_bit BANKMASK(TXB0D6), 1 extern volatile __bit TXB0D62 @ (((unsigned) &TXB0D6)*8) + 2; #define TXB0D62_bit BANKMASK(TXB0D6), 2 extern volatile __bit TXB0D63 @ (((unsigned) &TXB0D6)*8) + 3; #define TXB0D63_bit BANKMASK(TXB0D6), 3 extern volatile __bit TXB0D64 @ (((unsigned) &TXB0D6)*8) + 4; #define TXB0D64_bit BANKMASK(TXB0D6), 4 extern volatile __bit TXB0D65 @ (((unsigned) &TXB0D6)*8) + 5; #define TXB0D65_bit BANKMASK(TXB0D6), 5 extern volatile __bit TXB0D66 @ (((unsigned) &TXB0D6)*8) + 6; #define TXB0D66_bit BANKMASK(TXB0D6), 6 extern volatile __bit TXB0D67 @ (((unsigned) &TXB0D6)*8) + 7; #define TXB0D67_bit BANKMASK(TXB0D6), 7 extern volatile __bit TXB0D70 @ (((unsigned) &TXB0D7)*8) + 0; #define TXB0D70_bit BANKMASK(TXB0D7), 0 extern volatile __bit TXB0D71 @ (((unsigned) &TXB0D7)*8) + 1; #define TXB0D71_bit BANKMASK(TXB0D7), 1 extern volatile __bit TXB0D72 @ (((unsigned) &TXB0D7)*8) + 2; #define TXB0D72_bit BANKMASK(TXB0D7), 2 extern volatile __bit TXB0D73 @ (((unsigned) &TXB0D7)*8) + 3; #define TXB0D73_bit BANKMASK(TXB0D7), 3 extern volatile __bit TXB0D74 @ (((unsigned) &TXB0D7)*8) + 4; #define TXB0D74_bit BANKMASK(TXB0D7), 4 extern volatile __bit TXB0D75 @ (((unsigned) &TXB0D7)*8) + 5; #define TXB0D75_bit BANKMASK(TXB0D7), 5 extern volatile __bit TXB0D76 @ (((unsigned) &TXB0D7)*8) + 6; #define TXB0D76_bit BANKMASK(TXB0D7), 6 extern volatile __bit TXB0D77 @ (((unsigned) &TXB0D7)*8) + 7; #define TXB0D77_bit BANKMASK(TXB0D7), 7 extern volatile __bit TXB0DLC0 @ (((unsigned) &TXB0DLC)*8) + 0; #define TXB0DLC0_bit BANKMASK(TXB0DLC), 0 extern volatile __bit TXB0DLC1 @ (((unsigned) &TXB0DLC)*8) + 1; #define TXB0DLC1_bit BANKMASK(TXB0DLC), 1 extern volatile __bit TXB0DLC2 @ (((unsigned) &TXB0DLC)*8) + 2; #define TXB0DLC2_bit BANKMASK(TXB0DLC), 2 extern volatile __bit TXB0DLC3 @ (((unsigned) &TXB0DLC)*8) + 3; #define TXB0DLC3_bit BANKMASK(TXB0DLC), 3 extern volatile __bit TXB0EID0 @ (((unsigned) &TXB0EIDL)*8) + 0; #define TXB0EID0_bit BANKMASK(TXB0EIDL), 0 extern volatile __bit TXB0EID1 @ (((unsigned) &TXB0EIDL)*8) + 1; #define TXB0EID1_bit BANKMASK(TXB0EIDL), 1 extern volatile __bit TXB0EID10 @ (((unsigned) &TXB0EIDH)*8) + 2; #define TXB0EID10_bit BANKMASK(TXB0EIDH), 2 extern volatile __bit TXB0EID11 @ (((unsigned) &TXB0EIDH)*8) + 3; #define TXB0EID11_bit BANKMASK(TXB0EIDH), 3 extern volatile __bit TXB0EID12 @ (((unsigned) &TXB0EIDH)*8) + 4; #define TXB0EID12_bit BANKMASK(TXB0EIDH), 4 extern volatile __bit TXB0EID13 @ (((unsigned) &TXB0EIDH)*8) + 5; #define TXB0EID13_bit BANKMASK(TXB0EIDH), 5 extern volatile __bit TXB0EID14 @ (((unsigned) &TXB0EIDH)*8) + 6; #define TXB0EID14_bit BANKMASK(TXB0EIDH), 6 extern volatile __bit TXB0EID15 @ (((unsigned) &TXB0EIDH)*8) + 7; #define TXB0EID15_bit BANKMASK(TXB0EIDH), 7 extern volatile __bit TXB0EID16 @ (((unsigned) &TXB0SIDL)*8) + 0; #define TXB0EID16_bit BANKMASK(TXB0SIDL), 0 extern volatile __bit TXB0EID17 @ (((unsigned) &TXB0SIDL)*8) + 1; #define TXB0EID17_bit BANKMASK(TXB0SIDL), 1 extern volatile __bit TXB0EID2 @ (((unsigned) &TXB0EIDL)*8) + 2; #define TXB0EID2_bit BANKMASK(TXB0EIDL), 2 extern volatile __bit TXB0EID3 @ (((unsigned) &TXB0EIDL)*8) + 3; #define TXB0EID3_bit BANKMASK(TXB0EIDL), 3 extern volatile __bit TXB0EID4 @ (((unsigned) &TXB0EIDL)*8) + 4; #define TXB0EID4_bit BANKMASK(TXB0EIDL), 4 extern volatile __bit TXB0EID5 @ (((unsigned) &TXB0EIDL)*8) + 5; #define TXB0EID5_bit BANKMASK(TXB0EIDL), 5 extern volatile __bit TXB0EID6 @ (((unsigned) &TXB0EIDL)*8) + 6; #define TXB0EID6_bit BANKMASK(TXB0EIDL), 6 extern volatile __bit TXB0EID7 @ (((unsigned) &TXB0EIDL)*8) + 7; #define TXB0EID7_bit BANKMASK(TXB0EIDL), 7 extern volatile __bit TXB0EID8 @ (((unsigned) &TXB0EIDH)*8) + 0; #define TXB0EID8_bit BANKMASK(TXB0EIDH), 0 extern volatile __bit TXB0EID9 @ (((unsigned) &TXB0EIDH)*8) + 1; #define TXB0EID9_bit BANKMASK(TXB0EIDH), 1 extern volatile __bit TXB0ERR @ (((unsigned) &TXB0CON)*8) + 4; #define TXB0ERR_bit BANKMASK(TXB0CON), 4 extern volatile __bit TXB0EXIDE @ (((unsigned) &TXB0SIDL)*8) + 3; #define TXB0EXIDE_bit BANKMASK(TXB0SIDL), 3 extern volatile __bit TXB0IF @ (((unsigned) &PIR5)*8) + 2; #define TXB0IF_bit BANKMASK(PIR5), 2 extern volatile __bit TXB0IP @ (((unsigned) &IPR5)*8) + 2; #define TXB0IP_bit BANKMASK(IPR5), 2 extern volatile __bit TXB0LARB @ (((unsigned) &TXB0CON)*8) + 5; #define TXB0LARB_bit BANKMASK(TXB0CON), 5 extern volatile __bit TXB0PRI0 @ (((unsigned) &TXB0CON)*8) + 0; #define TXB0PRI0_bit BANKMASK(TXB0CON), 0 extern volatile __bit TXB0PRI1 @ (((unsigned) &TXB0CON)*8) + 1; #define TXB0PRI1_bit BANKMASK(TXB0CON), 1 extern volatile __bit TXB0REQ @ (((unsigned) &TXB0CON)*8) + 3; #define TXB0REQ_bit BANKMASK(TXB0CON), 3 extern volatile __bit TXB0RTR @ (((unsigned) &TXB0DLC)*8) + 6; #define TXB0RTR_bit BANKMASK(TXB0DLC), 6 extern volatile __bit TXB0SID0 @ (((unsigned) &TXB0SIDL)*8) + 5; #define TXB0SID0_bit BANKMASK(TXB0SIDL), 5 extern volatile __bit TXB0SID1 @ (((unsigned) &TXB0SIDL)*8) + 6; #define TXB0SID1_bit BANKMASK(TXB0SIDL), 6 extern volatile __bit TXB0SID10 @ (((unsigned) &TXB0SIDH)*8) + 7; #define TXB0SID10_bit BANKMASK(TXB0SIDH), 7 extern volatile __bit TXB0SID2 @ (((unsigned) &TXB0SIDL)*8) + 7; #define TXB0SID2_bit BANKMASK(TXB0SIDL), 7 extern volatile __bit TXB0SID3 @ (((unsigned) &TXB0SIDH)*8) + 0; #define TXB0SID3_bit BANKMASK(TXB0SIDH), 0 extern volatile __bit TXB0SID4 @ (((unsigned) &TXB0SIDH)*8) + 1; #define TXB0SID4_bit BANKMASK(TXB0SIDH), 1 extern volatile __bit TXB0SID5 @ (((unsigned) &TXB0SIDH)*8) + 2; #define TXB0SID5_bit BANKMASK(TXB0SIDH), 2 extern volatile __bit TXB0SID6 @ (((unsigned) &TXB0SIDH)*8) + 3; #define TXB0SID6_bit BANKMASK(TXB0SIDH), 3 extern volatile __bit TXB0SID7 @ (((unsigned) &TXB0SIDH)*8) + 4; #define TXB0SID7_bit BANKMASK(TXB0SIDH), 4 extern volatile __bit TXB0SID8 @ (((unsigned) &TXB0SIDH)*8) + 5; #define TXB0SID8_bit BANKMASK(TXB0SIDH), 5 extern volatile __bit TXB0SID9 @ (((unsigned) &TXB0SIDH)*8) + 6; #define TXB0SID9_bit BANKMASK(TXB0SIDH), 6 extern volatile __bit TXB1ABT @ (((unsigned) &TXB1CON)*8) + 6; #define TXB1ABT_bit BANKMASK(TXB1CON), 6 extern volatile __bit TXB1D00 @ (((unsigned) &TXB1D0)*8) + 0; #define TXB1D00_bit BANKMASK(TXB1D0), 0 extern volatile __bit TXB1D01 @ (((unsigned) &TXB1D0)*8) + 1; #define TXB1D01_bit BANKMASK(TXB1D0), 1 extern volatile __bit TXB1D02 @ (((unsigned) &TXB1D0)*8) + 2; #define TXB1D02_bit BANKMASK(TXB1D0), 2 extern volatile __bit TXB1D03 @ (((unsigned) &TXB1D0)*8) + 3; #define TXB1D03_bit BANKMASK(TXB1D0), 3 extern volatile __bit TXB1D04 @ (((unsigned) &TXB1D0)*8) + 4; #define TXB1D04_bit BANKMASK(TXB1D0), 4 extern volatile __bit TXB1D05 @ (((unsigned) &TXB1D0)*8) + 5; #define TXB1D05_bit BANKMASK(TXB1D0), 5 extern volatile __bit TXB1D06 @ (((unsigned) &TXB1D0)*8) + 6; #define TXB1D06_bit BANKMASK(TXB1D0), 6 extern volatile __bit TXB1D07 @ (((unsigned) &TXB1D0)*8) + 7; #define TXB1D07_bit BANKMASK(TXB1D0), 7 extern volatile __bit TXB1D10 @ (((unsigned) &TXB1D1)*8) + 0; #define TXB1D10_bit BANKMASK(TXB1D1), 0 extern volatile __bit TXB1D11 @ (((unsigned) &TXB1D1)*8) + 1; #define TXB1D11_bit BANKMASK(TXB1D1), 1 extern volatile __bit TXB1D12 @ (((unsigned) &TXB1D1)*8) + 2; #define TXB1D12_bit BANKMASK(TXB1D1), 2 extern volatile __bit TXB1D13 @ (((unsigned) &TXB1D1)*8) + 3; #define TXB1D13_bit BANKMASK(TXB1D1), 3 extern volatile __bit TXB1D14 @ (((unsigned) &TXB1D1)*8) + 4; #define TXB1D14_bit BANKMASK(TXB1D1), 4 extern volatile __bit TXB1D15 @ (((unsigned) &TXB1D1)*8) + 5; #define TXB1D15_bit BANKMASK(TXB1D1), 5 extern volatile __bit TXB1D16 @ (((unsigned) &TXB1D1)*8) + 6; #define TXB1D16_bit BANKMASK(TXB1D1), 6 extern volatile __bit TXB1D17 @ (((unsigned) &TXB1D1)*8) + 7; #define TXB1D17_bit BANKMASK(TXB1D1), 7 extern volatile __bit TXB1D20 @ (((unsigned) &TXB1D2)*8) + 0; #define TXB1D20_bit BANKMASK(TXB1D2), 0 extern volatile __bit TXB1D21 @ (((unsigned) &TXB1D2)*8) + 1; #define TXB1D21_bit BANKMASK(TXB1D2), 1 extern volatile __bit TXB1D22 @ (((unsigned) &TXB1D2)*8) + 2; #define TXB1D22_bit BANKMASK(TXB1D2), 2 extern volatile __bit TXB1D23 @ (((unsigned) &TXB1D2)*8) + 3; #define TXB1D23_bit BANKMASK(TXB1D2), 3 extern volatile __bit TXB1D24 @ (((unsigned) &TXB1D2)*8) + 4; #define TXB1D24_bit BANKMASK(TXB1D2), 4 extern volatile __bit TXB1D25 @ (((unsigned) &TXB1D2)*8) + 5; #define TXB1D25_bit BANKMASK(TXB1D2), 5 extern volatile __bit TXB1D26 @ (((unsigned) &TXB1D2)*8) + 6; #define TXB1D26_bit BANKMASK(TXB1D2), 6 extern volatile __bit TXB1D27 @ (((unsigned) &TXB1D2)*8) + 7; #define TXB1D27_bit BANKMASK(TXB1D2), 7 extern volatile __bit TXB1D30 @ (((unsigned) &TXB1D3)*8) + 0; #define TXB1D30_bit BANKMASK(TXB1D3), 0 extern volatile __bit TXB1D31 @ (((unsigned) &TXB1D3)*8) + 1; #define TXB1D31_bit BANKMASK(TXB1D3), 1 extern volatile __bit TXB1D32 @ (((unsigned) &TXB1D3)*8) + 2; #define TXB1D32_bit BANKMASK(TXB1D3), 2 extern volatile __bit TXB1D33 @ (((unsigned) &TXB1D3)*8) + 3; #define TXB1D33_bit BANKMASK(TXB1D3), 3 extern volatile __bit TXB1D34 @ (((unsigned) &TXB1D3)*8) + 4; #define TXB1D34_bit BANKMASK(TXB1D3), 4 extern volatile __bit TXB1D35 @ (((unsigned) &TXB1D3)*8) + 5; #define TXB1D35_bit BANKMASK(TXB1D3), 5 extern volatile __bit TXB1D36 @ (((unsigned) &TXB1D3)*8) + 6; #define TXB1D36_bit BANKMASK(TXB1D3), 6 extern volatile __bit TXB1D37 @ (((unsigned) &TXB1D3)*8) + 7; #define TXB1D37_bit BANKMASK(TXB1D3), 7 extern volatile __bit TXB1D40 @ (((unsigned) &TXB1D4)*8) + 0; #define TXB1D40_bit BANKMASK(TXB1D4), 0 extern volatile __bit TXB1D41 @ (((unsigned) &TXB1D4)*8) + 1; #define TXB1D41_bit BANKMASK(TXB1D4), 1 extern volatile __bit TXB1D42 @ (((unsigned) &TXB1D4)*8) + 2; #define TXB1D42_bit BANKMASK(TXB1D4), 2 extern volatile __bit TXB1D43 @ (((unsigned) &TXB1D4)*8) + 3; #define TXB1D43_bit BANKMASK(TXB1D4), 3 extern volatile __bit TXB1D44 @ (((unsigned) &TXB1D4)*8) + 4; #define TXB1D44_bit BANKMASK(TXB1D4), 4 extern volatile __bit TXB1D45 @ (((unsigned) &TXB1D4)*8) + 5; #define TXB1D45_bit BANKMASK(TXB1D4), 5 extern volatile __bit TXB1D46 @ (((unsigned) &TXB1D4)*8) + 6; #define TXB1D46_bit BANKMASK(TXB1D4), 6 extern volatile __bit TXB1D47 @ (((unsigned) &TXB1D4)*8) + 7; #define TXB1D47_bit BANKMASK(TXB1D4), 7 extern volatile __bit TXB1D50 @ (((unsigned) &TXB1D5)*8) + 0; #define TXB1D50_bit BANKMASK(TXB1D5), 0 extern volatile __bit TXB1D51 @ (((unsigned) &TXB1D5)*8) + 1; #define TXB1D51_bit BANKMASK(TXB1D5), 1 extern volatile __bit TXB1D52 @ (((unsigned) &TXB1D5)*8) + 2; #define TXB1D52_bit BANKMASK(TXB1D5), 2 extern volatile __bit TXB1D53 @ (((unsigned) &TXB1D5)*8) + 3; #define TXB1D53_bit BANKMASK(TXB1D5), 3 extern volatile __bit TXB1D54 @ (((unsigned) &TXB1D5)*8) + 4; #define TXB1D54_bit BANKMASK(TXB1D5), 4 extern volatile __bit TXB1D55 @ (((unsigned) &TXB1D5)*8) + 5; #define TXB1D55_bit BANKMASK(TXB1D5), 5 extern volatile __bit TXB1D56 @ (((unsigned) &TXB1D5)*8) + 6; #define TXB1D56_bit BANKMASK(TXB1D5), 6 extern volatile __bit TXB1D57 @ (((unsigned) &TXB1D5)*8) + 7; #define TXB1D57_bit BANKMASK(TXB1D5), 7 extern volatile __bit TXB1D60 @ (((unsigned) &TXB1D6)*8) + 0; #define TXB1D60_bit BANKMASK(TXB1D6), 0 extern volatile __bit TXB1D61 @ (((unsigned) &TXB1D6)*8) + 1; #define TXB1D61_bit BANKMASK(TXB1D6), 1 extern volatile __bit TXB1D62 @ (((unsigned) &TXB1D6)*8) + 2; #define TXB1D62_bit BANKMASK(TXB1D6), 2 extern volatile __bit TXB1D63 @ (((unsigned) &TXB1D6)*8) + 3; #define TXB1D63_bit BANKMASK(TXB1D6), 3 extern volatile __bit TXB1D64 @ (((unsigned) &TXB1D6)*8) + 4; #define TXB1D64_bit BANKMASK(TXB1D6), 4 extern volatile __bit TXB1D65 @ (((unsigned) &TXB1D6)*8) + 5; #define TXB1D65_bit BANKMASK(TXB1D6), 5 extern volatile __bit TXB1D66 @ (((unsigned) &TXB1D6)*8) + 6; #define TXB1D66_bit BANKMASK(TXB1D6), 6 extern volatile __bit TXB1D67 @ (((unsigned) &TXB1D6)*8) + 7; #define TXB1D67_bit BANKMASK(TXB1D6), 7 extern volatile __bit TXB1D70 @ (((unsigned) &TXB1D7)*8) + 0; #define TXB1D70_bit BANKMASK(TXB1D7), 0 extern volatile __bit TXB1D71 @ (((unsigned) &TXB1D7)*8) + 1; #define TXB1D71_bit BANKMASK(TXB1D7), 1 extern volatile __bit TXB1D72 @ (((unsigned) &TXB1D7)*8) + 2; #define TXB1D72_bit BANKMASK(TXB1D7), 2 extern volatile __bit TXB1D73 @ (((unsigned) &TXB1D7)*8) + 3; #define TXB1D73_bit BANKMASK(TXB1D7), 3 extern volatile __bit TXB1D74 @ (((unsigned) &TXB1D7)*8) + 4; #define TXB1D74_bit BANKMASK(TXB1D7), 4 extern volatile __bit TXB1D75 @ (((unsigned) &TXB1D7)*8) + 5; #define TXB1D75_bit BANKMASK(TXB1D7), 5 extern volatile __bit TXB1D76 @ (((unsigned) &TXB1D7)*8) + 6; #define TXB1D76_bit BANKMASK(TXB1D7), 6 extern volatile __bit TXB1D77 @ (((unsigned) &TXB1D7)*8) + 7; #define TXB1D77_bit BANKMASK(TXB1D7), 7 extern volatile __bit TXB1DLC0 @ (((unsigned) &TXB1DLC)*8) + 0; #define TXB1DLC0_bit BANKMASK(TXB1DLC), 0 extern volatile __bit TXB1DLC1 @ (((unsigned) &TXB1DLC)*8) + 1; #define TXB1DLC1_bit BANKMASK(TXB1DLC), 1 extern volatile __bit TXB1DLC2 @ (((unsigned) &TXB1DLC)*8) + 2; #define TXB1DLC2_bit BANKMASK(TXB1DLC), 2 extern volatile __bit TXB1DLC3 @ (((unsigned) &TXB1DLC)*8) + 3; #define TXB1DLC3_bit BANKMASK(TXB1DLC), 3 extern volatile __bit TXB1EID0 @ (((unsigned) &TXB1EIDL)*8) + 0; #define TXB1EID0_bit BANKMASK(TXB1EIDL), 0 extern volatile __bit TXB1EID1 @ (((unsigned) &TXB1EIDL)*8) + 1; #define TXB1EID1_bit BANKMASK(TXB1EIDL), 1 extern volatile __bit TXB1EID10 @ (((unsigned) &TXB1EIDH)*8) + 2; #define TXB1EID10_bit BANKMASK(TXB1EIDH), 2 extern volatile __bit TXB1EID11 @ (((unsigned) &TXB1EIDH)*8) + 3; #define TXB1EID11_bit BANKMASK(TXB1EIDH), 3 extern volatile __bit TXB1EID12 @ (((unsigned) &TXB1EIDH)*8) + 4; #define TXB1EID12_bit BANKMASK(TXB1EIDH), 4 extern volatile __bit TXB1EID13 @ (((unsigned) &TXB1EIDH)*8) + 5; #define TXB1EID13_bit BANKMASK(TXB1EIDH), 5 extern volatile __bit TXB1EID14 @ (((unsigned) &TXB1EIDH)*8) + 6; #define TXB1EID14_bit BANKMASK(TXB1EIDH), 6 extern volatile __bit TXB1EID15 @ (((unsigned) &TXB1EIDH)*8) + 7; #define TXB1EID15_bit BANKMASK(TXB1EIDH), 7 extern volatile __bit TXB1EID16 @ (((unsigned) &TXB1SIDL)*8) + 0; #define TXB1EID16_bit BANKMASK(TXB1SIDL), 0 extern volatile __bit TXB1EID17 @ (((unsigned) &TXB1SIDL)*8) + 1; #define TXB1EID17_bit BANKMASK(TXB1SIDL), 1 extern volatile __bit TXB1EID2 @ (((unsigned) &TXB1EIDL)*8) + 2; #define TXB1EID2_bit BANKMASK(TXB1EIDL), 2 extern volatile __bit TXB1EID3 @ (((unsigned) &TXB1EIDL)*8) + 3; #define TXB1EID3_bit BANKMASK(TXB1EIDL), 3 extern volatile __bit TXB1EID4 @ (((unsigned) &TXB1EIDL)*8) + 4; #define TXB1EID4_bit BANKMASK(TXB1EIDL), 4 extern volatile __bit TXB1EID5 @ (((unsigned) &TXB1EIDL)*8) + 5; #define TXB1EID5_bit BANKMASK(TXB1EIDL), 5 extern volatile __bit TXB1EID6 @ (((unsigned) &TXB1EIDL)*8) + 6; #define TXB1EID6_bit BANKMASK(TXB1EIDL), 6 extern volatile __bit TXB1EID7 @ (((unsigned) &TXB1EIDL)*8) + 7; #define TXB1EID7_bit BANKMASK(TXB1EIDL), 7 extern volatile __bit TXB1EID8 @ (((unsigned) &TXB1EIDH)*8) + 0; #define TXB1EID8_bit BANKMASK(TXB1EIDH), 0 extern volatile __bit TXB1EID9 @ (((unsigned) &TXB1EIDH)*8) + 1; #define TXB1EID9_bit BANKMASK(TXB1EIDH), 1 extern volatile __bit TXB1ERR @ (((unsigned) &TXB1CON)*8) + 4; #define TXB1ERR_bit BANKMASK(TXB1CON), 4 extern volatile __bit TXB1EXIDE @ (((unsigned) &TXB1SIDL)*8) + 3; #define TXB1EXIDE_bit BANKMASK(TXB1SIDL), 3 extern volatile __bit TXB1IF @ (((unsigned) &PIR5)*8) + 3; #define TXB1IF_bit BANKMASK(PIR5), 3 extern volatile __bit TXB1IP @ (((unsigned) &IPR5)*8) + 3; #define TXB1IP_bit BANKMASK(IPR5), 3 extern volatile __bit TXB1LARB @ (((unsigned) &TXB1CON)*8) + 5; #define TXB1LARB_bit BANKMASK(TXB1CON), 5 extern volatile __bit TXB1PRI0 @ (((unsigned) &TXB1CON)*8) + 0; #define TXB1PRI0_bit BANKMASK(TXB1CON), 0 extern volatile __bit TXB1PRI1 @ (((unsigned) &TXB1CON)*8) + 1; #define TXB1PRI1_bit BANKMASK(TXB1CON), 1 extern volatile __bit TXB1REQ @ (((unsigned) &TXB1CON)*8) + 3; #define TXB1REQ_bit BANKMASK(TXB1CON), 3 extern volatile __bit TXB1RTR @ (((unsigned) &TXB1DLC)*8) + 6; #define TXB1RTR_bit BANKMASK(TXB1DLC), 6 extern volatile __bit TXB1SID0 @ (((unsigned) &TXB1SIDL)*8) + 5; #define TXB1SID0_bit BANKMASK(TXB1SIDL), 5 extern volatile __bit TXB1SID1 @ (((unsigned) &TXB1SIDL)*8) + 6; #define TXB1SID1_bit BANKMASK(TXB1SIDL), 6 extern volatile __bit TXB1SID10 @ (((unsigned) &TXB1SIDH)*8) + 7; #define TXB1SID10_bit BANKMASK(TXB1SIDH), 7 extern volatile __bit TXB1SID2 @ (((unsigned) &TXB1SIDL)*8) + 7; #define TXB1SID2_bit BANKMASK(TXB1SIDL), 7 extern volatile __bit TXB1SID3 @ (((unsigned) &TXB1SIDH)*8) + 0; #define TXB1SID3_bit BANKMASK(TXB1SIDH), 0 extern volatile __bit TXB1SID4 @ (((unsigned) &TXB1SIDH)*8) + 1; #define TXB1SID4_bit BANKMASK(TXB1SIDH), 1 extern volatile __bit TXB1SID5 @ (((unsigned) &TXB1SIDH)*8) + 2; #define TXB1SID5_bit BANKMASK(TXB1SIDH), 2 extern volatile __bit TXB1SID6 @ (((unsigned) &TXB1SIDH)*8) + 3; #define TXB1SID6_bit BANKMASK(TXB1SIDH), 3 extern volatile __bit TXB1SID7 @ (((unsigned) &TXB1SIDH)*8) + 4; #define TXB1SID7_bit BANKMASK(TXB1SIDH), 4 extern volatile __bit TXB1SID8 @ (((unsigned) &TXB1SIDH)*8) + 5; #define TXB1SID8_bit BANKMASK(TXB1SIDH), 5 extern volatile __bit TXB1SID9 @ (((unsigned) &TXB1SIDH)*8) + 6; #define TXB1SID9_bit BANKMASK(TXB1SIDH), 6 extern volatile __bit TXB2ABT @ (((unsigned) &TXB2CON)*8) + 6; #define TXB2ABT_bit BANKMASK(TXB2CON), 6 extern volatile __bit TXB2D00 @ (((unsigned) &TXB2D0)*8) + 0; #define TXB2D00_bit BANKMASK(TXB2D0), 0 extern volatile __bit TXB2D01 @ (((unsigned) &TXB2D0)*8) + 1; #define TXB2D01_bit BANKMASK(TXB2D0), 1 extern volatile __bit TXB2D02 @ (((unsigned) &TXB2D0)*8) + 2; #define TXB2D02_bit BANKMASK(TXB2D0), 2 extern volatile __bit TXB2D03 @ (((unsigned) &TXB2D0)*8) + 3; #define TXB2D03_bit BANKMASK(TXB2D0), 3 extern volatile __bit TXB2D04 @ (((unsigned) &TXB2D0)*8) + 4; #define TXB2D04_bit BANKMASK(TXB2D0), 4 extern volatile __bit TXB2D05 @ (((unsigned) &TXB2D0)*8) + 5; #define TXB2D05_bit BANKMASK(TXB2D0), 5 extern volatile __bit TXB2D06 @ (((unsigned) &TXB2D0)*8) + 6; #define TXB2D06_bit BANKMASK(TXB2D0), 6 extern volatile __bit TXB2D07 @ (((unsigned) &TXB2D0)*8) + 7; #define TXB2D07_bit BANKMASK(TXB2D0), 7 extern volatile __bit TXB2D10 @ (((unsigned) &TXB2D1)*8) + 0; #define TXB2D10_bit BANKMASK(TXB2D1), 0 extern volatile __bit TXB2D11 @ (((unsigned) &TXB2D1)*8) + 1; #define TXB2D11_bit BANKMASK(TXB2D1), 1 extern volatile __bit TXB2D12 @ (((unsigned) &TXB2D1)*8) + 2; #define TXB2D12_bit BANKMASK(TXB2D1), 2 extern volatile __bit TXB2D13 @ (((unsigned) &TXB2D1)*8) + 3; #define TXB2D13_bit BANKMASK(TXB2D1), 3 extern volatile __bit TXB2D14 @ (((unsigned) &TXB2D1)*8) + 4; #define TXB2D14_bit BANKMASK(TXB2D1), 4 extern volatile __bit TXB2D15 @ (((unsigned) &TXB2D1)*8) + 5; #define TXB2D15_bit BANKMASK(TXB2D1), 5 extern volatile __bit TXB2D16 @ (((unsigned) &TXB2D1)*8) + 6; #define TXB2D16_bit BANKMASK(TXB2D1), 6 extern volatile __bit TXB2D17 @ (((unsigned) &TXB2D1)*8) + 7; #define TXB2D17_bit BANKMASK(TXB2D1), 7 extern volatile __bit TXB2D20 @ (((unsigned) &TXB2D2)*8) + 0; #define TXB2D20_bit BANKMASK(TXB2D2), 0 extern volatile __bit TXB2D21 @ (((unsigned) &TXB2D2)*8) + 1; #define TXB2D21_bit BANKMASK(TXB2D2), 1 extern volatile __bit TXB2D22 @ (((unsigned) &TXB2D2)*8) + 2; #define TXB2D22_bit BANKMASK(TXB2D2), 2 extern volatile __bit TXB2D23 @ (((unsigned) &TXB2D2)*8) + 3; #define TXB2D23_bit BANKMASK(TXB2D2), 3 extern volatile __bit TXB2D24 @ (((unsigned) &TXB2D2)*8) + 4; #define TXB2D24_bit BANKMASK(TXB2D2), 4 extern volatile __bit TXB2D25 @ (((unsigned) &TXB2D2)*8) + 5; #define TXB2D25_bit BANKMASK(TXB2D2), 5 extern volatile __bit TXB2D26 @ (((unsigned) &TXB2D2)*8) + 6; #define TXB2D26_bit BANKMASK(TXB2D2), 6 extern volatile __bit TXB2D27 @ (((unsigned) &TXB2D2)*8) + 7; #define TXB2D27_bit BANKMASK(TXB2D2), 7 extern volatile __bit TXB2D30 @ (((unsigned) &TXB2D3)*8) + 0; #define TXB2D30_bit BANKMASK(TXB2D3), 0 extern volatile __bit TXB2D31 @ (((unsigned) &TXB2D3)*8) + 1; #define TXB2D31_bit BANKMASK(TXB2D3), 1 extern volatile __bit TXB2D32 @ (((unsigned) &TXB2D3)*8) + 2; #define TXB2D32_bit BANKMASK(TXB2D3), 2 extern volatile __bit TXB2D33 @ (((unsigned) &TXB2D3)*8) + 3; #define TXB2D33_bit BANKMASK(TXB2D3), 3 extern volatile __bit TXB2D34 @ (((unsigned) &TXB2D3)*8) + 4; #define TXB2D34_bit BANKMASK(TXB2D3), 4 extern volatile __bit TXB2D35 @ (((unsigned) &TXB2D3)*8) + 5; #define TXB2D35_bit BANKMASK(TXB2D3), 5 extern volatile __bit TXB2D36 @ (((unsigned) &TXB2D3)*8) + 6; #define TXB2D36_bit BANKMASK(TXB2D3), 6 extern volatile __bit TXB2D37 @ (((unsigned) &TXB2D3)*8) + 7; #define TXB2D37_bit BANKMASK(TXB2D3), 7 extern volatile __bit TXB2D40 @ (((unsigned) &TXB2D4)*8) + 0; #define TXB2D40_bit BANKMASK(TXB2D4), 0 extern volatile __bit TXB2D41 @ (((unsigned) &TXB2D4)*8) + 1; #define TXB2D41_bit BANKMASK(TXB2D4), 1 extern volatile __bit TXB2D42 @ (((unsigned) &TXB2D4)*8) + 2; #define TXB2D42_bit BANKMASK(TXB2D4), 2 extern volatile __bit TXB2D43 @ (((unsigned) &TXB2D4)*8) + 3; #define TXB2D43_bit BANKMASK(TXB2D4), 3 extern volatile __bit TXB2D44 @ (((unsigned) &TXB2D4)*8) + 4; #define TXB2D44_bit BANKMASK(TXB2D4), 4 extern volatile __bit TXB2D45 @ (((unsigned) &TXB2D4)*8) + 5; #define TXB2D45_bit BANKMASK(TXB2D4), 5 extern volatile __bit TXB2D46 @ (((unsigned) &TXB2D4)*8) + 6; #define TXB2D46_bit BANKMASK(TXB2D4), 6 extern volatile __bit TXB2D47 @ (((unsigned) &TXB2D4)*8) + 7; #define TXB2D47_bit BANKMASK(TXB2D4), 7 extern volatile __bit TXB2D50 @ (((unsigned) &TXB2D5)*8) + 0; #define TXB2D50_bit BANKMASK(TXB2D5), 0 extern volatile __bit TXB2D51 @ (((unsigned) &TXB2D5)*8) + 1; #define TXB2D51_bit BANKMASK(TXB2D5), 1 extern volatile __bit TXB2D52 @ (((unsigned) &TXB2D5)*8) + 2; #define TXB2D52_bit BANKMASK(TXB2D5), 2 extern volatile __bit TXB2D53 @ (((unsigned) &TXB2D5)*8) + 3; #define TXB2D53_bit BANKMASK(TXB2D5), 3 extern volatile __bit TXB2D54 @ (((unsigned) &TXB2D5)*8) + 4; #define TXB2D54_bit BANKMASK(TXB2D5), 4 extern volatile __bit TXB2D55 @ (((unsigned) &TXB2D5)*8) + 5; #define TXB2D55_bit BANKMASK(TXB2D5), 5 extern volatile __bit TXB2D56 @ (((unsigned) &TXB2D5)*8) + 6; #define TXB2D56_bit BANKMASK(TXB2D5), 6 extern volatile __bit TXB2D57 @ (((unsigned) &TXB2D5)*8) + 7; #define TXB2D57_bit BANKMASK(TXB2D5), 7 extern volatile __bit TXB2D60 @ (((unsigned) &TXB2D6)*8) + 0; #define TXB2D60_bit BANKMASK(TXB2D6), 0 extern volatile __bit TXB2D61 @ (((unsigned) &TXB2D6)*8) + 1; #define TXB2D61_bit BANKMASK(TXB2D6), 1 extern volatile __bit TXB2D62 @ (((unsigned) &TXB2D6)*8) + 2; #define TXB2D62_bit BANKMASK(TXB2D6), 2 extern volatile __bit TXB2D63 @ (((unsigned) &TXB2D6)*8) + 3; #define TXB2D63_bit BANKMASK(TXB2D6), 3 extern volatile __bit TXB2D64 @ (((unsigned) &TXB2D6)*8) + 4; #define TXB2D64_bit BANKMASK(TXB2D6), 4 extern volatile __bit TXB2D65 @ (((unsigned) &TXB2D6)*8) + 5; #define TXB2D65_bit BANKMASK(TXB2D6), 5 extern volatile __bit TXB2D66 @ (((unsigned) &TXB2D6)*8) + 6; #define TXB2D66_bit BANKMASK(TXB2D6), 6 extern volatile __bit TXB2D67 @ (((unsigned) &TXB2D6)*8) + 7; #define TXB2D67_bit BANKMASK(TXB2D6), 7 extern volatile __bit TXB2D70 @ (((unsigned) &TXB2D7)*8) + 0; #define TXB2D70_bit BANKMASK(TXB2D7), 0 extern volatile __bit TXB2D71 @ (((unsigned) &TXB2D7)*8) + 1; #define TXB2D71_bit BANKMASK(TXB2D7), 1 extern volatile __bit TXB2D72 @ (((unsigned) &TXB2D7)*8) + 2; #define TXB2D72_bit BANKMASK(TXB2D7), 2 extern volatile __bit TXB2D73 @ (((unsigned) &TXB2D7)*8) + 3; #define TXB2D73_bit BANKMASK(TXB2D7), 3 extern volatile __bit TXB2D74 @ (((unsigned) &TXB2D7)*8) + 4; #define TXB2D74_bit BANKMASK(TXB2D7), 4 extern volatile __bit TXB2D75 @ (((unsigned) &TXB2D7)*8) + 5; #define TXB2D75_bit BANKMASK(TXB2D7), 5 extern volatile __bit TXB2D76 @ (((unsigned) &TXB2D7)*8) + 6; #define TXB2D76_bit BANKMASK(TXB2D7), 6 extern volatile __bit TXB2D77 @ (((unsigned) &TXB2D7)*8) + 7; #define TXB2D77_bit BANKMASK(TXB2D7), 7 extern volatile __bit TXB2DLC0 @ (((unsigned) &TXB2DLC)*8) + 0; #define TXB2DLC0_bit BANKMASK(TXB2DLC), 0 extern volatile __bit TXB2DLC1 @ (((unsigned) &TXB2DLC)*8) + 1; #define TXB2DLC1_bit BANKMASK(TXB2DLC), 1 extern volatile __bit TXB2DLC2 @ (((unsigned) &TXB2DLC)*8) + 2; #define TXB2DLC2_bit BANKMASK(TXB2DLC), 2 extern volatile __bit TXB2DLC3 @ (((unsigned) &TXB2DLC)*8) + 3; #define TXB2DLC3_bit BANKMASK(TXB2DLC), 3 extern volatile __bit TXB2EID0 @ (((unsigned) &TXB2EIDL)*8) + 0; #define TXB2EID0_bit BANKMASK(TXB2EIDL), 0 extern volatile __bit TXB2EID1 @ (((unsigned) &TXB2EIDL)*8) + 1; #define TXB2EID1_bit BANKMASK(TXB2EIDL), 1 extern volatile __bit TXB2EID10 @ (((unsigned) &TXB2EIDH)*8) + 2; #define TXB2EID10_bit BANKMASK(TXB2EIDH), 2 extern volatile __bit TXB2EID11 @ (((unsigned) &TXB2EIDH)*8) + 3; #define TXB2EID11_bit BANKMASK(TXB2EIDH), 3 extern volatile __bit TXB2EID12 @ (((unsigned) &TXB2EIDH)*8) + 4; #define TXB2EID12_bit BANKMASK(TXB2EIDH), 4 extern volatile __bit TXB2EID13 @ (((unsigned) &TXB2EIDH)*8) + 5; #define TXB2EID13_bit BANKMASK(TXB2EIDH), 5 extern volatile __bit TXB2EID14 @ (((unsigned) &TXB2EIDH)*8) + 6; #define TXB2EID14_bit BANKMASK(TXB2EIDH), 6 extern volatile __bit TXB2EID15 @ (((unsigned) &TXB2EIDH)*8) + 7; #define TXB2EID15_bit BANKMASK(TXB2EIDH), 7 extern volatile __bit TXB2EID16 @ (((unsigned) &TXB2SIDL)*8) + 0; #define TXB2EID16_bit BANKMASK(TXB2SIDL), 0 extern volatile __bit TXB2EID17 @ (((unsigned) &TXB2SIDL)*8) + 1; #define TXB2EID17_bit BANKMASK(TXB2SIDL), 1 extern volatile __bit TXB2EID2 @ (((unsigned) &TXB2EIDL)*8) + 2; #define TXB2EID2_bit BANKMASK(TXB2EIDL), 2 extern volatile __bit TXB2EID3 @ (((unsigned) &TXB2EIDL)*8) + 3; #define TXB2EID3_bit BANKMASK(TXB2EIDL), 3 extern volatile __bit TXB2EID4 @ (((unsigned) &TXB2EIDL)*8) + 4; #define TXB2EID4_bit BANKMASK(TXB2EIDL), 4 extern volatile __bit TXB2EID5 @ (((unsigned) &TXB2EIDL)*8) + 5; #define TXB2EID5_bit BANKMASK(TXB2EIDL), 5 extern volatile __bit TXB2EID6 @ (((unsigned) &TXB2EIDL)*8) + 6; #define TXB2EID6_bit BANKMASK(TXB2EIDL), 6 extern volatile __bit TXB2EID7 @ (((unsigned) &TXB2EIDL)*8) + 7; #define TXB2EID7_bit BANKMASK(TXB2EIDL), 7 extern volatile __bit TXB2EID8 @ (((unsigned) &TXB2EIDH)*8) + 0; #define TXB2EID8_bit BANKMASK(TXB2EIDH), 0 extern volatile __bit TXB2EID9 @ (((unsigned) &TXB2EIDH)*8) + 1; #define TXB2EID9_bit BANKMASK(TXB2EIDH), 1 extern volatile __bit TXB2ERR @ (((unsigned) &TXB2CON)*8) + 4; #define TXB2ERR_bit BANKMASK(TXB2CON), 4 extern volatile __bit TXB2EXIDE @ (((unsigned) &TXB2SIDL)*8) + 3; #define TXB2EXIDE_bit BANKMASK(TXB2SIDL), 3 extern volatile __bit TXB2IF @ (((unsigned) &PIR5)*8) + 4; #define TXB2IF_bit BANKMASK(PIR5), 4 extern volatile __bit TXB2IP @ (((unsigned) &IPR5)*8) + 4; #define TXB2IP_bit BANKMASK(IPR5), 4 extern volatile __bit TXB2LARB @ (((unsigned) &TXB2CON)*8) + 5; #define TXB2LARB_bit BANKMASK(TXB2CON), 5 extern volatile __bit TXB2PRI0 @ (((unsigned) &TXB2CON)*8) + 0; #define TXB2PRI0_bit BANKMASK(TXB2CON), 0 extern volatile __bit TXB2PRI1 @ (((unsigned) &TXB2CON)*8) + 1; #define TXB2PRI1_bit BANKMASK(TXB2CON), 1 extern volatile __bit TXB2REQ @ (((unsigned) &TXB2CON)*8) + 3; #define TXB2REQ_bit BANKMASK(TXB2CON), 3 extern volatile __bit TXB2RTR @ (((unsigned) &TXB2DLC)*8) + 6; #define TXB2RTR_bit BANKMASK(TXB2DLC), 6 extern volatile __bit TXB2SID0 @ (((unsigned) &TXB2SIDL)*8) + 5; #define TXB2SID0_bit BANKMASK(TXB2SIDL), 5 extern volatile __bit TXB2SID1 @ (((unsigned) &TXB2SIDL)*8) + 6; #define TXB2SID1_bit BANKMASK(TXB2SIDL), 6 extern volatile __bit TXB2SID10 @ (((unsigned) &TXB2SIDH)*8) + 7; #define TXB2SID10_bit BANKMASK(TXB2SIDH), 7 extern volatile __bit TXB2SID2 @ (((unsigned) &TXB2SIDL)*8) + 7; #define TXB2SID2_bit BANKMASK(TXB2SIDL), 7 extern volatile __bit TXB2SID3 @ (((unsigned) &TXB2SIDH)*8) + 0; #define TXB2SID3_bit BANKMASK(TXB2SIDH), 0 extern volatile __bit TXB2SID4 @ (((unsigned) &TXB2SIDH)*8) + 1; #define TXB2SID4_bit BANKMASK(TXB2SIDH), 1 extern volatile __bit TXB2SID5 @ (((unsigned) &TXB2SIDH)*8) + 2; #define TXB2SID5_bit BANKMASK(TXB2SIDH), 2 extern volatile __bit TXB2SID6 @ (((unsigned) &TXB2SIDH)*8) + 3; #define TXB2SID6_bit BANKMASK(TXB2SIDH), 3 extern volatile __bit TXB2SID7 @ (((unsigned) &TXB2SIDH)*8) + 4; #define TXB2SID7_bit BANKMASK(TXB2SIDH), 4 extern volatile __bit TXB2SID8 @ (((unsigned) &TXB2SIDH)*8) + 5; #define TXB2SID8_bit BANKMASK(TXB2SIDH), 5 extern volatile __bit TXB2SID9 @ (((unsigned) &TXB2SIDH)*8) + 6; #define TXB2SID9_bit BANKMASK(TXB2SIDH), 6 extern volatile __bit TXBNIE @ (((unsigned) &PIE3)*8) + 4; #define TXBNIE_bit BANKMASK(PIE3), 4 extern volatile __bit TXBNIF @ (((unsigned) &PIR3)*8) + 4; #define TXBNIF_bit BANKMASK(PIR3), 4 extern volatile __bit TXBNIP @ (((unsigned) &IPR3)*8) + 4; #define TXBNIP_bit BANKMASK(IPR3), 4 extern volatile __bit TXBO @ (((unsigned) &COMSTAT)*8) + 5; #define TXBO_bit BANKMASK(COMSTAT), 5 extern volatile __bit TXBP @ (((unsigned) &COMSTAT)*8) + 4; #define TXBP_bit BANKMASK(COMSTAT), 4 extern volatile __bit TXBnIE @ (((unsigned) &PIE5)*8) + 4; #define TXBnIE_bit BANKMASK(PIE5), 4 extern volatile __bit TXBnIF @ (((unsigned) &PIR5)*8) + 4; #define TXBnIF_bit BANKMASK(PIR5), 4 extern volatile __bit TXBnIP @ (((unsigned) &IPR5)*8) + 4; #define TXBnIP_bit BANKMASK(IPR5), 4 extern volatile __bit TXCKP1 @ (((unsigned) &BAUDCON1)*8) + 4; #define TXCKP1_bit BANKMASK(BAUDCON1), 4 extern volatile __bit TXCKP2 @ (((unsigned) &BAUDCON2)*8) + 4; #define TXCKP2_bit BANKMASK(BAUDCON2), 4 extern volatile __bit TXD8 @ (((unsigned) &TXSTA1)*8) + 0; #define TXD8_bit BANKMASK(TXSTA1), 0 extern volatile __bit TXD82 @ (((unsigned) &TXSTA2)*8) + 0; #define TXD82_bit BANKMASK(TXSTA2), 0 extern volatile __bit TXEN1 @ (((unsigned) &TXSTA1)*8) + 5; #define TXEN1_bit BANKMASK(TXSTA1), 5 extern volatile __bit TXEN2 @ (((unsigned) &TXSTA2)*8) + 5; #define TXEN2_bit BANKMASK(TXSTA2), 5 extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4; #define TXIE_bit BANKMASK(PIE1), 4 extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4; #define TXIF_bit BANKMASK(PIR1), 4 extern volatile __bit TXIP @ (((unsigned) &IPR1)*8) + 4; #define TXIP_bit BANKMASK(IPR1), 4 extern volatile __bit TXWARN @ (((unsigned) &COMSTAT)*8) + 2; #define TXWARN_bit BANKMASK(COMSTAT), 2 extern volatile __bit U1OD @ (((unsigned) &ODCON)*8) + 0; #define U1OD_bit BANKMASK(ODCON), 0 extern volatile __bit U2OD @ (((unsigned) &ODCON)*8) + 1; #define U2OD_bit BANKMASK(ODCON), 1 extern volatile __bit UA @ (((unsigned) &SSPSTAT)*8) + 1; #define UA_bit BANKMASK(SSPSTAT), 1 extern volatile __bit UART1MD @ (((unsigned) &PMD0)*8) + 1; #define UART1MD_bit BANKMASK(PMD0), 1 extern volatile __bit UART2MD @ (((unsigned) &PMD0)*8) + 2; #define UART2MD_bit BANKMASK(PMD0), 2 extern volatile __bit ULPEN @ (((unsigned) &WDTCON)*8) + 2; #define ULPEN_bit BANKMASK(WDTCON), 2 extern volatile __bit ULPLVL @ (((unsigned) &WDTCON)*8) + 5; #define ULPLVL_bit BANKMASK(WDTCON), 5 extern volatile __bit ULPSINK @ (((unsigned) &WDTCON)*8) + 1; #define ULPSINK_bit BANKMASK(WDTCON), 1 extern volatile __bit ULPWUIN @ (((unsigned) &PORTA)*8) + 0; #define ULPWUIN_bit BANKMASK(PORTA), 0 extern volatile __bit VCFG0 @ (((unsigned) &ADCON1)*8) + 4; #define VCFG0_bit BANKMASK(ADCON1), 4 extern volatile __bit VCFG01 @ (((unsigned) &ADCON1)*8) + 4; #define VCFG01_bit BANKMASK(ADCON1), 4 extern volatile __bit VCFG1 @ (((unsigned) &ADCON1)*8) + 5; #define VCFG1_bit BANKMASK(ADCON1), 5 extern volatile __bit VCFG11 @ (((unsigned) &ADCON1)*8) + 5; #define VCFG11_bit BANKMASK(ADCON1), 5 extern volatile __bit VDIRMAG @ (((unsigned) &HLVDCON)*8) + 7; #define VDIRMAG_bit BANKMASK(HLVDCON), 7 extern volatile __bit VNCFG @ (((unsigned) &ADCON1)*8) + 3; #define VNCFG_bit BANKMASK(ADCON1), 3 extern volatile __bit WAIT0 @ (((unsigned) &PR2)*8) + 4; #define WAIT0_bit BANKMASK(PR2), 4 extern volatile __bit WAIT1 @ (((unsigned) &PR2)*8) + 5; #define WAIT1_bit BANKMASK(PR2), 5 extern volatile __bit WAKDIS @ (((unsigned) &BRGCON3)*8) + 7; #define WAKDIS_bit BANKMASK(BRGCON3), 7 extern volatile __bit WAKFIL @ (((unsigned) &BRGCON3)*8) + 6; #define WAKFIL_bit BANKMASK(BRGCON3), 6 extern volatile __bit WAKIE @ (((unsigned) &PIE5)*8) + 6; #define WAKIE_bit BANKMASK(PIE5), 6 extern volatile __bit WAKIF @ (((unsigned) &PIR5)*8) + 6; #define WAKIF_bit BANKMASK(PIR5), 6 extern volatile __bit WAKIP @ (((unsigned) &IPR5)*8) + 6; #define WAKIP_bit BANKMASK(IPR5), 6 extern volatile __bit WCOL @ (((unsigned) &SSPCON1)*8) + 7; #define WCOL_bit BANKMASK(SSPCON1), 7 extern volatile __bit WM0 @ (((unsigned) &PR2)*8) + 0; #define WM0_bit BANKMASK(PR2), 0 extern volatile __bit WM1 @ (((unsigned) &PR2)*8) + 1; #define WM1_bit BANKMASK(PR2), 1 extern volatile __bit WPUB0 @ (((unsigned) &WPUB)*8) + 0; #define WPUB0_bit BANKMASK(WPUB), 0 extern volatile __bit WPUB1 @ (((unsigned) &WPUB)*8) + 1; #define WPUB1_bit BANKMASK(WPUB), 1 extern volatile __bit WPUB2 @ (((unsigned) &WPUB)*8) + 2; #define WPUB2_bit BANKMASK(WPUB), 2 extern volatile __bit WPUB3 @ (((unsigned) &WPUB)*8) + 3; #define WPUB3_bit BANKMASK(WPUB), 3 extern volatile __bit WPUB4 @ (((unsigned) &WPUB)*8) + 4; #define WPUB4_bit BANKMASK(WPUB), 4 extern volatile __bit WPUB5 @ (((unsigned) &WPUB)*8) + 5; #define WPUB5_bit BANKMASK(WPUB), 5 extern volatile __bit WPUB6 @ (((unsigned) &WPUB)*8) + 6; #define WPUB6_bit BANKMASK(WPUB), 6 extern volatile __bit WPUB7 @ (((unsigned) &WPUB)*8) + 7; #define WPUB7_bit BANKMASK(WPUB), 7 extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1; #define WR_bit BANKMASK(EECON1), 1 extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2; #define WREN_bit BANKMASK(EECON1), 2 extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3; #define WRERR_bit BANKMASK(EECON1), 3 extern volatile __bit WUE1 @ (((unsigned) &BAUDCON1)*8) + 1; #define WUE1_bit BANKMASK(BAUDCON1), 1 extern volatile __bit WUE2 @ (((unsigned) &BAUDCON2)*8) + 1; #define WUE2_bit BANKMASK(BAUDCON2), 1 extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2; #define ZERO_bit BANKMASK(STATUS), 2 extern volatile __bit nA @ (((unsigned) &SSPSTAT)*8) + 5; #define nA_bit BANKMASK(SSPSTAT), 5 extern volatile __bit nADDRESS @ (((unsigned) &SSPSTAT)*8) + 5; #define nADDRESS_bit BANKMASK(SSPSTAT), 5 extern volatile __bit nBOR @ (((unsigned) &RCON)*8) + 0; #define nBOR_bit BANKMASK(RCON), 0 extern volatile __bit nCM @ (((unsigned) &RCON)*8) + 5; #define nCM_bit BANKMASK(RCON), 5 extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1; #define nDONE_bit BANKMASK(ADCON0), 1 extern volatile __bit nFIFOEMPTY @ (((unsigned) &COMSTAT)*8) + 7; #define nFIFOEMPTY_bit BANKMASK(COMSTAT), 7 extern volatile __bit nPD @ (((unsigned) &RCON)*8) + 2; #define nPD_bit BANKMASK(RCON), 2 extern volatile __bit nPOR @ (((unsigned) &RCON)*8) + 1; #define nPOR_bit BANKMASK(RCON), 1 extern volatile __bit nRBPU @ (((unsigned) &INTCON2)*8) + 7; #define nRBPU_bit BANKMASK(INTCON2), 7 extern volatile __bit nRC8 @ (((unsigned) &RCSTA1)*8) + 6; #define nRC8_bit BANKMASK(RCSTA1), 6 extern volatile __bit nRI @ (((unsigned) &RCON)*8) + 4; #define nRI_bit BANKMASK(RCON), 4 extern volatile __bit nT1DONE @ (((unsigned) &T1GCON)*8) + 3; #define nT1DONE_bit BANKMASK(T1GCON), 3 extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2; #define nT1SYNC_bit BANKMASK(T1CON), 2 extern volatile __bit nT3DONE @ (((unsigned) &T3GCON)*8) + 3; #define nT3DONE_bit BANKMASK(T3GCON), 3 extern volatile __bit nT3SYNC @ (((unsigned) &T3CON)*8) + 2; #define nT3SYNC_bit BANKMASK(T3CON), 2 extern volatile __bit nTO @ (((unsigned) &RCON)*8) + 3; #define nTO_bit BANKMASK(RCON), 3 extern volatile __bit nTX8 @ (((unsigned) &TXSTA1)*8) + 6; #define nTX8_bit BANKMASK(TXSTA1), 6 extern volatile __bit nW @ (((unsigned) &SSPSTAT)*8) + 2; #define nW_bit BANKMASK(SSPSTAT), 2 extern volatile __bit nWRITE @ (((unsigned) &SSPSTAT)*8) + 2; #define nWRITE_bit BANKMASK(SSPSTAT), 2 #endif // _PIC18F26K80_H_