//************************************************************************************ //** //** File name: E:\RF EB063-00-1\Telefon_oskar\30F2011\telfon_sender.c //** Generated by: Flowcode v4.4.13.69 //** Date: Thursday, March 17, 2011 17:57:21 //** Licence: Professional //** Registered to: wolfgang sachs //** //** //** http://www.matrixmultimedia.com //************************************************************************************ #define MX_PIC_16BIT //Defines for microcontroller #define P30F2011 #define MX_CLKS_PER_INST 4 #define MX_SPI1 #define MX_SPI1_PORT_B #define MX_SPI1_SDI 5 #define MX_SPI1_SDO 4 #define MX_SPI1_SCK 6 #define MX_UART1 #define MX_UART1_PORT_B #define MX_MI2C1 #define MX_I2C1_PORT_B #define MX_I2C1_SDA 5 #define MX_I2C1_SCL 4 #define MX_PWM #define MX_PWM_PORT_D #define MX_PWM_CNT 2 #define MX_PWM_1 0 #define MX_PWM_2 7 //Functions #define MX_Fosc 29480000 #include "../support/dsPIC30F/h/p30fxxxx.h" #include #include #define _RESERVED1(x) int temp1 = (x); #define _RESERVED2(x) int temp2 = (x); #define _ICD(x) _FICD(x); //Configuration data _FOSC(0x8701) //addr = 0xf80000 _FWDT(0x3f) //addr = 0xf80002 _FBORPOR(0x8733) //addr = 0xf80004 _RESERVED1(0x310f) //addr = 0xf80006 _RESERVED2(0x330f) //addr = 0xf80008 _FGS(0x7) //addr = 0xf8000a _ICD(0xc003) //addr = 0xf8000c //Internal functions #include "C:\Program Files\Matrix Multimedia\Flowcode PIC24&dsPIC V4\FCD\internals.h" //Macro function declarations void FCM_tm1_int(); //Variable declarations volatile char FCV_RETURN_VALUE; //Defines: /**** Macro Substitutions **** 0 = SPI Bus HW / SW mode 0-SW / 1-HW SPI1 / 2-HW SPI2 / 3-HW SPI3 B = SPI Port Letter 0 = FSEL Pin 2 = SPI MOSI Pin 3 = SPI MISO Pin 6 = SPI Clock Pin 1 = SPI Chip Select Pin 1 = Frequency Selection 1-433MHz 2-868MHz 3-915MHz 97 = Centre Frequency Channel selection - 96-3903 See Calculation p28 71 = Baud Rate See Calculation p37 0 = Receiver Bandwidth 0 = Receiver Gain 0 = Receiver Threshold 0 = Transmitter Deviation 0 = Transmitter Power Output 100 = Transmitter Duty Cycle Setting 1 = Data Mode 85 = Preamble Sync ID Value 0 = Extended Preamble Sync ID Enable ******************************/ //Duty cycle limit when using the 868MHz band in Europe //common defines #define MX_RF_SPI_HW 0 //SPI Hardware or Bitbanged Port Control #define MX_RF_PORT PORTB //Port Connection #define MX_RF_TRIS TRISB //DDR Connection #define MX_RF_FSEL 0 //RFmodule - FSEL #define MX_RF_SDO 2 //SPI - Data Out #define MX_RF_SDI 3 //SPI - Data In #define MX_RF_SCK 6 //SPI - Clock #define MX_RF_SCS 1 //SPI - Chip Select #define MX_RF_FREQ 1 //Module Frequency #define MX_RF_CFREQ 97 //Central Frequency 96 <-> 3903 #define MX_RF_BAUD 71 //Data Baud Rate #define MX_RF_BWIDTH 0 //Bandwithd 0= / 6= #define MX_RF_GAIN 0 //Gain 0= / 3= #define MX_RF_THRESH 0 //Threshold 0= / 5= #define MX_RF_DVN 0 //Deviation 0=15KHz / 15=240KHz #define MX_RF_PWR 0 //Power 0=0dB / 7=-17.5dB #define MX_RF_DATAMODE 1 //Data mode - I/O or Data #define MX_RF_ID 85 //Sync ID #define MX_RF_EXTID 0 //Extended Sync 0x00=Off / 0x08=On #define MX_RF_DUTY 100 //-------------------------------------------------------------------- // MRF49XA Static Defines: //-------------------------------------------------------------------- #define NODATA 0 #define DATA_RECEIVED 1 #define PACKET_RECEIVED 2 #define PAYLOAD_MAX 20 //-------------------------------------------------------------------- // MRF49XA SPI commands: //-------------------------------------------------------------------- // General commands #define GENCREG (0x8008 | (MX_RF_FREQ << 4)) //RF_Frequency does not change.... #define PMCREG 0x8208 #define CFSREG 0xA000 // Data commands #define DATARATE 0xC600 #define SYNCHRON 0xCE00 // RX commands #define RXCREG 0x9000 #define FIFORSTREG 0xCA81 #define BBFCREG 0xC22C #define AFCCREG 0xC4D7 // TX commands #define TXCREG 0x9800 #define TXBREG 0xB800 // Preloaded commands with data #define TXCREGPRE ((TXCREG | (MX_RF_DVN << 4)) | MX_RF_PWR) #define CFSREGPRE (CFSREG | MX_RF_CFREQ) #define SYNCHPRE (SYNCHRON | MX_RF_ID) #define FIFORSPRE (FIFORSTREG | MX_RF_EXTID) #define PDOWN 0x8201 char RX_Mode = 0; //RF(0): //Macro function declarations static char FCD_RF0_SPI_Byte(char Data); static void FCD_RF0_SPI_Byte16(short spicmd); static short FCD_RF0_SPI_Command(short spicmd); static void FCD_RF0_Wait_For_SDI(); static short FCD_RF0_Init_RF_Module(); static void FCD_RF0_Uninit_RF_Module(); static void FCD_RF0_Send_Byte(char Data); static void FCD_RF0_Send_String(char* Data, char MSZ_Data, char Length); static char FCD_RF0_Receive_Byte(char Timeout); static void FCD_RF0_Receive_String(char* FCR_RETVAL, char FCR_RETVAL_SIZE, char Length, char Timeout); static void FCD_RF0_Activate_RX_Mode(); static void FCD_RF0_Activate_TX_Mode(); static void FCD_RF0_Update_Centre_Frequency(short Frequency); static void FCD_RF0_Set_Sync_Pattern(char Mode, char Pattern); static void FCD_RF0_RX_Tune(char Bandwidth, char Gain, char Threshold); static void FCD_RF0_TX_Tune(char Deviation, char Power); static void FCD_RF0_Set_Data_Rate(char Rate); static char FCD_RF0_Read_RX_Signal_Strength(); //RF(0): //Macro implementations static char FCD_RF0_SPI_Byte(char Data) { char retVal = 0; #if (MX_RF_SPI_HW == 0) char idx; for (idx = 0; idx < 8; idx++) { if (test_bit(Data, 7)) set_bit(MX_RF_PORT, MX_RF_SDO); // Set SDO bit else clear_bit(MX_RF_PORT, MX_RF_SDO); // Clear SDO bit Data = Data << 1; set_bit(MX_RF_PORT, MX_RF_SCK); // SCK Output 1 delay_us(1); //Added BR 06/10 if(test_bit(MX_RF_PORT, MX_RF_SDI)) retVal = retVal | 0x01; else retVal = retVal & 0xFE; clear_bit(MX_RF_PORT, MX_RF_SCK); // SCK Output 0 } #endif #if (MX_RF_SPI_HW == 1) SPI1BUF = Data; //send a dummy byte while (SPI1STATbits.SPIRBF == 0); //wait until data has been sent retVal = SPI1BUF; //receive the byte #endif #if (MX_RF_SPI_HW == 2) SPI2BUF = Data; //send a dummy byte while (SPI2STATbits.SPIRBF == 0); //wait until data has been sent retVal = SPI2BUF; //receive the byte #endif #if (MX_RF_SPI_HW == 3) SPI3BUF = Data; //send a dummy byte while (SPI3STATbits.SPIRBF == 0); //wait until data has been sent retVal = SPI3BUF; //receive the byte #endif return(retVal); } static void FCD_RF0_SPI_Byte16(short spicmd) { FCD_RF0_SPI_Byte ((spicmd & 0xFF00) >> 8); // Send Upper Command Byte FCD_RF0_SPI_Byte ((spicmd & 0x00FF)); // Send Lower Command Byte } static short FCD_RF0_SPI_Command(short spicmd) { unsigned int retval; clear_bit(MX_RF_PORT,MX_RF_SCS); // Clear Chip Select bit delay_us(1); retval = ( FCD_RF0_SPI_Byte ((spicmd & 0xFF00) >> 8) << 8); // Send Upper Command Byte retval = retval | FCD_RF0_SPI_Byte ((spicmd & 0x00FF)); // Send Lower Command Byte delay_us(1); set_bit(MX_RF_PORT,MX_RF_SCS); // Set Chip Select bit delay_us(1); return retval; } static void FCD_RF0_Wait_For_SDI() { while(test_bit(MX_RF_PORT, MX_RF_SDI) == 0); //Wait for SDI Input } static short FCD_RF0_Init_RF_Module() { unsigned int Retval; #if (MX_RF_SPI_HW == 0) // Configure the I/O Pins set_bit(MX_RF_PORT, MX_RF_SCS); clear_bit(MX_RF_TRIS, MX_RF_SCS); clear_bit(MX_RF_TRIS, MX_RF_SDO); clear_bit(MX_RF_PORT, MX_RF_SDO); clear_bit(MX_RF_TRIS, MX_RF_SCK); clear_bit(MX_RF_PORT, MX_RF_SCK); set_bit(MX_RF_TRIS, MX_RF_SDI); #endif #if (MX_RF_SPI_HW == 1) #ifndef MX_SPI1 #error Chip does not have SPI port 1 capability #endif #ifdef MX_SPI1_PORT_FREEALLOC #ifdef MX_SPI1_ALT //configure remapping RPINR20 = (RPINR20 & 0xFF00) | 0x0E; //Assign SDI - RP14 / PORTB14 RPOR4 = (RPOR4 & 0x00FF) | 0x0800; //Assign SCK - RP9 / PORTB9 RPOR7 = (RPOR7 & 0x00FF) | 0x0700; //Assign SDO - RP15 / PORTB15 #else //configure remapping RPINR20 = (RPINR20 & 0xFF00) | 0x04; //Assign SDI - RP4 / PORTB4 RPOR1 = (RPOR1 & 0x00FF) | 0x0800; //Assign SCK - RP3 / PORTB3 RPOR2 = (RPOR2 & 0x00FF) | 0x0700; //Assign SDO - RP5 / PORTB5 #endif #else #ifdef MX_SPI1_PORT_E16ALLOC //configure remapping RPINR20 = (RPINR20 & 0xFF00) | 0x11; //Assign SDI - RP17 / PORTC1 RPOR7 = (RPOR7 & 0x00FF) | 0x0800; //Assign SCK - RP15 / PORTB15 RPOR8 = (RPOR8 & 0xFF00) | 0x0007; //Assign SDO - RP16 / PORTC0 #else #ifdef dsPIC30 #define SPI1CON1 SPI1CON #define SPI1CON1bits SPI1CONbits #endif #endif #endif SPI1CON1 = 0x011F; SPI1CON1bits.MSTEN = 1; //master mode SPI1STATbits.SPIROV = 0; //clear unread data flag SPI1STATbits.SPIEN = 1; //enable SPI peripheral #endif #if (MX_RF_SPI_HW == 2) #ifndef MX_SPI2 #error Chip does not have SPI port 2 capability #endif #ifdef MX_SPI2_PORT_FREEALLOC //configure remapping RPINR22 = (RPINR22 & 0xFF00) | 0x0E; //Assign SDI - RP14 / PORTB14 RPOR6 = (RPOR6 & 0x00FF) | 0x0B00; //Assign SCK - RP13 / PORTB13 RPOR7 = (RPOR7 & 0x00FF) | 0x0A00; //Assign SDO - RP15 / PORTB15 #else #ifdef MX_SPI2_PORT_E16ALLOC //configure remapping RPINR22 = (RPINR22 & 0xFF00) | 0x14; //Assign SDI - RP20 / PORTC4 RPOR12 = (RPOR12 & 0xFF00) | 0x000B; //Assign SCK - RP24 / PORTC8 RPOR10 = (RPOR10 & 0x00FF) | 0x0A00; //Assign SDO - RP21 / PORTC5 #else #ifdef dsPIC30 #define SPI2CON1 SPI2CON #define SPI2CON1bits SPI2CONbits #endif #endif #endif SPI2CON1 = 0x011F; SPI2CON1bits.MSTEN = 1; //master mode SPI2STATbits.SPIROV = 0; //clear unread data flag SPI2STATbits.SPIEN = 1; //enable SPI peripheral #endif #if (MX_RF_SPI_HW == 3) #ifndef MX_SPI3 #error Chip does not have SPI port 3 capability #endif #ifdef MX_SPI3_PORT_FREEALLOC //configure remapping RPINR28 = (RPINR28 & 0xFF00) | 0x19; //Assign SDI - RP25 / PORTD4 RPOR11 = (RPOR11 & 0xFF00) | 0x21; //Assign SCK - RP22 / PORTD5 RPOR10 = (RPOR10 & 0xFF00) | 0x20; //Assign SDO - RP20 / PORTD3 #endif SPI3CON1 = 0x011F; SPI3CON1bits.MSTEN = 1; //master mode SPI3STATbits.SPIROV = 0; //clear unread data flag SPI3STATbits.SPIEN = 1; //enable SPI peripheral #endif delay_ms(100); //100ms Delay to ensure transceiver has powered up // Configuring the RF link FCD_RF0_SPI_Command(FIFORSPRE); //Disable (Sensitive) Reset Mode FCD_RF0_SPI_Command(FIFORSPRE | 0x02); //Restart Synchronous character pattern recognition FCD_RF0_SPI_Command(GENCREG); //Assign frequency band and set load capacitance //SPI_Command(AFCCREG); //Enable AFC function FCD_RF0_SPI_Command(CFSREG | MX_RF_CFREQ); //Set Channel Center Frequency FCD_RF0_SPI_Command(DATARATE | MX_RF_BAUD); //Set Data Rate FCD_RF0_SPI_Command(PMCREG); //Turn Off TX and RX controller chains Retval = RXCREG; //Enable Data RX Output / Set signal strengths and gain Retval = Retval | (MX_RF_BWIDTH << 5); Retval = Retval | (MX_RF_GAIN << 3); Retval = Retval | MX_RF_THRESH; FCD_RF0_SPI_Command(Retval); FCD_RF0_SPI_Command(SYNCHPRE); FCD_RF0_SPI_Command(TXCREG | 0x0030); //Set TX modulation to 60khz // Antenna Tuning FCD_RF0_SPI_Command( PMCREG | 0x0020); //Turn on TX baseband circuit delay_ms(5); //Wait for oscillatr to stabilise // Set Up The Receiver FCD_RF0_SPI_Command(PMCREG | 0x0080); //Turn off Tx, turn on receiver FCD_RF0_SPI_Command(GENCREG | 0x0040); //Enable the FIFO FCD_RF0_SPI_Command(FIFORSPRE); FCD_RF0_SPI_Command(FIFORSPRE | 0x02); //Restart Synchronous character pattern recognition set_bit(MX_RF_PORT, MX_RF_FSEL); clear_bit(MX_RF_TRIS, MX_RF_FSEL); //Need a better way of confirming initialisation Retval = FCD_RF0_SPI_Command(0); //Read back and return STSREG return (Retval); } static void FCD_RF0_Uninit_RF_Module() { FCD_RF0_SPI_Command(PDOWN); } static void FCD_RF0_Send_Byte(char Data) { if (RX_Mode == 0) //If we are in receive mode FCD_RF0_Activate_TX_Mode(); //Switch to transmit mode FCD_RF0_Send_String (&Data, 1, 1); } static void FCD_RF0_Send_String(char* Data, char MSZ_Data, char Length) { unsigned int idx = 0; if (RX_Mode == 0) //If we are in receive mode FCD_RF0_Activate_TX_Mode(); //Switch to transmit mode clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit //delay_us(1); FCD_RF0_SPI_Byte16(TXBREG | 0xAA); // preamble FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte(0x2D); // sync pattern 1st byte FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte(0xD4); // sync pattern 2nd byte FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte(Length); for (idx=0; idx= PacketLen) // end of packet? { FCD_RF0_SPI_Command(FIFORSPRE); // reset FIFO set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 Length = nrbytes; nrbytes = 0; PacketLen = 0; return; } } else // First byte already received { bl = FCD_RF0_SPI_Byte(0); if((bl > 0) && (bl < PAYLOAD_MAX)) // Check if correct number of bytes in payload { PacketLen = bl; nrbytes = 0; } else { set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 FCD_RF0_SPI_Command(PMCREG); // turn off tx and rx FCD_RF0_SPI_Command(FIFORSPRE); // reset FIFO FCD_RF0_SPI_Command(GENCREG); // disable FIFO , Tx_latch FCD_RF0_SPI_Command(GENCREG | 0x0040); // enable the FIFO FCD_RF0_SPI_Command(PMCREG | 0x0080); // turn on receiver FCD_RF0_SPI_Command(FIFORSPRE | 0x02); // FIFO syncron latch re-enable Length = 0; return; } } set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 return; } else { set_bit(MX_RF_PORT, MX_RF_SCS); // Set Chip Select bit Length = 0; return; } } static void FCD_RF0_Activate_RX_Mode() { FCD_RF0_SPI_Command(PMCREG | 0x0080); // turn off Tx, turn on the receiver FCD_RF0_SPI_Command(GENCREG | 0x0040); // disable the Tx register, Enable the FIFO RX_Mode = 0; //Clear software mode flag } static void FCD_RF0_Activate_TX_Mode() { FCD_RF0_SPI_Command(PMCREG); // Turn off the transmitter and receiver FCD_RF0_SPI_Command(GENCREG | 0x0080); // Enable the Tx register FCD_RF0_SPI_Command(PMCREG | 0x0020); // Turn on tx RX_Mode = 1; //Set software mode flag } static void FCD_RF0_Update_Centre_Frequency(short Frequency) { if (Frequency < 96) Frequency = 96; if (Frequency > 3903) Frequency = 3903; FCD_RF0_SPI_Command(CFSREG | Frequency); } static void FCD_RF0_Set_Sync_Pattern(char Mode, char Pattern) { if (Mode) Mode = 0x08; #undef FIFORSPRE #define FIFORSPRE (FIFORSTREG | Mode) if (Mode) { //Word type synchronisation FCD_RF0_SPI_Command(FIFORSPRE); FCD_RF0_SPI_Command(SYNCHRON | Pattern); } else { //Byte type synchronisation FCD_RF0_SPI_Command(FIFORSPRE); FCD_RF0_SPI_Command(SYNCHRON | Pattern); } } static void FCD_RF0_RX_Tune(char Bandwidth, char Gain, char Threshold) { unsigned int TuneVals; if (Bandwidth > 6) Bandwidth = 6; if (Bandwidth < 1) Bandwidth = 1; if (Gain > 3) Gain = 3; if (Threshold > 5) Threshold = 5; TuneVals = RXCREG; TuneVals = TuneVals | (Bandwidth << 5); TuneVals = TuneVals | (Gain << 3); TuneVals = TuneVals | Threshold; FCD_RF0_SPI_Command(TuneVals); } static void FCD_RF0_TX_Tune(char Deviation, char Power) { unsigned int TuneVals; if (Deviation > 15) Deviation = 15; if (Power > 7) Power = 7; TuneVals = TXCREG; TuneVals = TuneVals | (Deviation << 4); TuneVals = TuneVals | Power; FCD_RF0_SPI_Command(TuneVals); } static void FCD_RF0_Set_Data_Rate(char Rate) { char cs = 0; unsigned long r; r = 100000 / (29 * Rate); //10 x data rate value r = r + 5; //round up r = r / 10; //divide by 10 if (r > 0x80) //result too large { cs = 0x80; //set cs bit r >>= 2; //divide by 4 if (r & 0x01) r += 1; //round up r >>= 1; //divide by 2 } r = r - 1; FCD_RF0_SPI_Command(DATARATE | cs | (char)r); } static char FCD_RF0_Read_RX_Signal_Strength() { unsigned int test = 0; test = FCD_RF0_SPI_Command(0); //Read back and return STSREG test = test >> 7; //Rotate so that data we want is one bits 0 and 1 test = test & 0x03; //Mask off any unwanted values return (test); } //Macro implementations void FCM_tm1_int() { } int main() { //Initialisation ADPCFG = 0xffff; //Interrupt initialisation code //Call Component Macro //Call Component Macro: return_value=RF(0)::Init_RF_Module FCV_RETURN_VALUE = FCD_RF0_Init_RF_Module(); //Connection Point //Connection Point: [A]: A FCC_Main_A: ; //Output //Output: 0 -> D0 TRISD = TRISD & 0xfffe; if (0) PORTD = (LATD & 0xfffe) | 0x0001; else PORTD = LATD & 0xfffe; //Delay //Delay: 500 ms delay_ms(255); delay_ms(245); //Output //Output: 1 -> D0 TRISD = TRISD & 0xfffe; if (1) PORTD = (LATD & 0xfffe) | 0x0001; else PORTD = LATD & 0xfffe; //Delay //Delay: 500 ms delay_ms(255); delay_ms(245); //Goto Connection Point //Goto Connection Point: [A]: A goto FCC_Main_A; mainendloop: goto mainendloop; return 0; }