//************************************************************************************ //** //** File name: J:\04 Matrix\16f877a.c //** Generated by: Flowcode v4.5.18.74 //** Date: Wednesday, October 12, 2011 19:35:09 //** Licence: Professional //** Registered to: james beaton //** //** //** http://www.matrixmultimedia.com //************************************************************************************ #define MX_PIC //Defines for microcontroller #define P16F877A #define MX_EE #define MX_EE_TYPE2 #define MX_EE_SIZE 256 #define MX_SPI #define MX_SPI_C #define MX_SPI_SDI 4 #define MX_SPI_SDO 5 #define MX_SPI_SCK 3 #define MX_UART #define MX_UART_C #define MX_UART_TX 6 #define MX_UART_RX 7 #define MX_I2C #define MX_MI2C #define MX_I2C_C #define MX_I2C_SDA 4 #define MX_I2C_SCL 3 #define MX_PWM #define MX_PWM_CNT 2 #define MX_PWM_TRIS1 trisc #define MX_PWM_1 2 #define MX_PWM_TRIS2 trisc #define MX_PWM_2 1 //Functions #define MX_CLK_SPEED 19660800 #ifdef _BOOSTC #include #endif #ifdef HI_TECH_C #include #endif //Configuration data #ifdef _BOOSTC #pragma DATA 0x2007, 0x3fbe #endif #ifdef HI_TECH_C __CONFIG(0x3fbe); #endif //Internal functions #include "C:\Program Files\Matrix Multimedia\Flowcode V4\FCD\internals.h" //Macro function declarations //Variable declarations char FCV_RET2; char FCV_RET; //RF(0): //Defines: /**** Macro Substitutions **** 0 = SPI Bus HW / SW mode 0-SW / 1-HW SPI1 / 2-HW SPI2 / 3-HW SPI3 c = SPI Port Letter 1 = FSEL Pin 5 = SPI MOSI Pin 4 = SPI MISO Pin 3 = SPI Clock Pin 0 = SPI Chip Select Pin 1 = Frequency Selection 1-433MHz 2-868MHz 3-915MHz 2000 = Centre Frequency Channel selection - 96-3903 See Calculation p28 71 = Baud Rate See Calculation p37 0 = Receiver Bandwidth 0 = Receiver Gain 0 = Receiver Threshold 7 = Transmitter Deviation 0 = Transmitter Power Output 100 = Transmitter Duty Cycle Setting 0 = Data Mode 109 = Preamble Sync ID Value 0 = Extended Preamble Sync ID Enable ******************************/ //Duty cycle limit when using the 868MHz band in Europe //common defines #define MX_RF_SPI_HW 0 //SPI Hardware or Bitbanged Port Control #define MX_RF_PORT portc //Port Connection //#define MX_RF_PIN latc //Port Connection #define MX_RF_TRIS trisc //DDR Connection #define MX_RF_FSEL 1 //RFmodule - FSEL #define MX_RF_SDO 5 //SPI - Data Out #define MX_RF_SDI 4 //SPI - Data In #define MX_RF_SCK 3 //SPI - Clock #define MX_RF_SCS 0 //SPI - Chip Select #define MX_RF_FREQ 1 //Module Frequency #define MX_RF_CFREQ 2000 //Central Frequency 96 <-> 3903 (0x7D0) #define MX_RF_BAUD 71 //Data Baud Rate (0x23) #define MX_RF_BWIDTH (0 + 1) //Bandwithd 0= / 6= #define MX_RF_GAIN 0 //Gain 0= / 3= #define MX_RF_THRESH 0 //Threshold 0= / 5= #define MX_RF_DVN 7 //Deviation 0=15KHz / 15=240KHz #define MX_RF_PWR 0 //Power 0=0dB / 7=-17.5dB #define MX_RF_DATAMODE 0 //Data mode - I/O or Data #define MX_RF_ID 109 //Sync ID #define MX_RF_EXTID ((1 - 0) * 8) //Extended Sync 0=Off / 1=On #define MX_RF_DUTY 100 #define MX_RF_TXPROP ((MX_RF_DVN << 4) | MX_RF_PWR) #define MX_RF_BUFFER_MAX 8 // General commands #define GENCREG (0x8008 | (MX_RF_FREQ << 4)) //RF_Frequency does not change.... #define PMCREG 0x8200 #define CFSREG 0xA000 // Data commands #define DATARATE 0xC600 #define SYNCHRON 0xCE00 // RX commands #define RXCREG 0x9000 #define RXBREG 0xB000 #define FIFORSTREG 0xCA81 //0xCA85 #define BBFCREG 0xC22C #define AFCCREG 0xC4D7 // TX commands #define TXCREG 0x9800 #define TXBREG 0xB800 // Preloaded commands with data #define PDOWN 0x8201 char MX_RF_Mode; char MX_RF_Sync = MX_RF_ID; char MX_RF_RX_Buffer[MX_RF_BUFFER_MAX + 2]; char MX_RF_RX_Buff1[MX_RF_BUFFER_MAX + 2]; char MX_RF_TX_Buffer[MX_RF_BUFFER_MAX + 2]; //RF(0): //Macro function declarations char FCD_RF0_SPI_Byte(char Data); void FCD_RF0_SPI_Byte16(short spicmd); short FCD_RF0_SPI_Command(short spicmd); void FCD_RF0_Wait_For_SDI(); short FCD_RF0_Init_RF_Module(); void FCD_RF0_Uninit_RF_Module(); void FCD_RF0_Send_Byte(char Data); void FCD_RF0_Send_String(char* String, char MSZ_String); char FCD_RF0_Receive_Byte(char Timeout); void FCD_RF0_Receive_String(char* FCR_RETVAL, char FCR_RETVAL_SIZE, char Length, char Timeout); void FCD_RF0_Activate_RX_Mode(); void FCD_RF0_Activate_TX_Mode(); void FCD_RF0_Update_Centre_Frequency(short Frequency); void FCD_RF0_Set_Sync_Pattern(char Mode, char Pattern); void FCD_RF0_RX_Tune(char Bandwidth, char Gain, char Threshold); void FCD_RF0_TX_Tune(char Deviation, char Power); void FCD_RF0_Set_Data_Rate(char Rate); char FCD_RF0_Read_RX_Signal_Strength(); void FCD_RF0_FSK_Write(char State); char FCD_RF0_FSK_Read(); void FCD_RF0_Set_Buffer_Data(char Index, char Data); void FCD_RF0_Send_Buffer(char Count); char FCD_RF0_Check_Buffer(char Timeout); char FCD_RF0_Get_Data_Count(); char FCD_RF0_Get_Buffer_Data(char Index); //RF(0): //Macro implementations char FCD_RF0_SPI_Byte(char Data) { char retVal = 0; #if (MX_RF_SPI_HW == 0) char idx; for (idx = 0; idx < 8; idx++) { if (test_bit(Data, 7)) set_bit(MX_RF_PORT, MX_RF_SDO); // Set SDO bit else clear_bit(MX_RF_PORT, MX_RF_SDO); // Clear SDO bit Data = Data << 1; set_bit(MX_RF_PORT, MX_RF_SCK); // SCK Output 1 delay_us(1); retVal = retVal << 1; if(test_bit(MX_RF_PORT, MX_RF_SDI)) retVal = retVal | 0x01; clear_bit(MX_RF_PORT, MX_RF_SCK); // SCK Output 0 delay_us(1); } #endif #if (MX_RF_SPI_HW == 1) #ifndef MX_SPI #error Chip does not have SPI capability #endif MX_RF_SPIBUF = Data; //send a dummy byte while (MX_RF_SPISTATbits.SPIRBF == 0); //wait until data has been sent retVal = MX_RF_SPIBUF; //receive the byte #endif return(retVal); } void FCD_RF0_SPI_Byte16(short spicmd) { FCD_RF0_SPI_Byte ((spicmd & 0xFF00) >> 8); // Send Upper Command Byte FCD_RF0_SPI_Byte ((spicmd & 0x00FF)); // Send Lower Command Byte } short FCD_RF0_SPI_Command(short spicmd) { unsigned int retval; clear_bit(MX_RF_PORT,MX_RF_SCS); // Clear Chip Select bit delay_us(1); retval = ( FCD_RF0_SPI_Byte ((spicmd & 0xFF00) >> 8) << 8); // Send Upper Command Byte retval = retval | FCD_RF0_SPI_Byte ((spicmd & 0x00FF)); // Send Lower Command Byte delay_us(1); set_bit(MX_RF_PORT,MX_RF_SCS); // Set Chip Select bit delay_us(1); return retval; } void FCD_RF0_Wait_For_SDI() { #if (MX_RF_SPI_HW == 0) while(test_bit(MX_RF_PORT, MX_RF_SDI) == 0); //Wait for SDI Input #else while(test_bit(MX_RF_SDI_PORT, MX_RF_SDI_PIN) == 0); #endif } short FCD_RF0_Init_RF_Module() { unsigned int Retval; set_bit(MX_RF_PORT, MX_RF_SCS); clear_bit(MX_RF_TRIS, MX_RF_SCS); #if (MX_RF_SPI_HW == 0) // Configure the I/O Pins clear_bit(MX_RF_TRIS, MX_RF_SDO); clear_bit(MX_RF_TRIS, MX_RF_SCK); set_bit(MX_RF_TRIS, MX_RF_SDI); clear_bit(MX_RF_PORT, MX_RF_SDO); clear_bit(MX_RF_PORT, MX_RF_SCK); #else // Configure the I/O Pins clear_bit(MX_RF_SDO_TRIS, MX_RF_SDO_PIN); clear_bit(MX_RF_SCK_TRIS, MX_RF_SCK_PIN); set_bit(MX_RF_SDI_TRIS, MX_RF_SDI_PIN); //configure SPI sspstat = 64; // Configure SPI Peripheral #ifdef _BOOSTC #ifdef SSPCON // SPI Low Speed for Initialise sspcon = 2; st_bit(sspcon, SSPEN); #endif #ifdef SSPCON1 sspcon1 = 2; st_bit(sspcon1, SSPEN); #endif #endif #ifdef HI_TECH_C #ifdef sspcon // SPI Low Speed for Initialise SSPCON = 2; st_bit(SSPCON, SSPEN); #endif #ifdef sspcon1 SSPCON1 = 2; st_bit(SSPCON1, SSPEN); #endif #endif #endif delay_ms(100); //100ms Delay to ensure transceiver has powered up // Configuring the RF link FCD_RF0_SPI_Command(FIFORSTREG); //Disable (Sensitive) Reset Mode FCD_RF0_SPI_Command(FIFORSTREG | MX_RF_EXTID | 0x02); //Restart Synchronous character pattern recognition FCD_RF0_SPI_Command(GENCREG); //Assign frequency band and set load capacitance FCD_RF0_SPI_Command(CFSREG | MX_RF_CFREQ); //Set Channel Center Frequency FCD_RF0_SPI_Command(DATARATE | MX_RF_BAUD); //Set Data Rate FCD_RF0_SPI_Command(PMCREG); //Turn Off TX and RX controller chains Retval = (MX_RF_BWIDTH << 5) | (MX_RF_GAIN << 3) | MX_RF_THRESH; FCD_RF0_SPI_Command(RXCREG | Retval); //Enable Data RX Output / Set signal strengths and gain FCD_RF0_SPI_Command(SYNCHRON | MX_RF_Sync); FCD_RF0_SPI_Command(TXCREG | MX_RF_TXPROP); //Set TX frequency deviation // Antenna Tuning FCD_RF0_SPI_Command( PMCREG | 0x0020); //Turn on TX baseband circuit delay_ms(5); //Wait for oscillatr to stabilise // Set Up The Receiver FCD_RF0_SPI_Command(PMCREG | 0x0080); //Turn off Tx, turn on receiver #if (MX_RF_DATAMODE == 1) FCD_RF0_SPI_Command(GENCREG | 0x0040); //Enable the FIFO FCD_RF0_SPI_Command(FIFORSTREG); FCD_RF0_SPI_Command(FIFORSTREG | MX_RF_EXTID | 0x02); //Restart Synchronous character pattern recognition set_bit(MX_RF_PORT, MX_RF_FSEL); clear_bit(MX_RF_TRIS, MX_RF_FSEL); MX_RF_Mode = 0; #else set_bit(MX_RF_TRIS, MX_RF_FSEL); FCD_RF0_SPI_Command(GENCREG); //Leave the FIFO disabled MX_RF_Mode = 2; #endif Retval = FCD_RF0_SPI_Command(0); //Read back and return STSREG return (Retval); } void FCD_RF0_Uninit_RF_Module() { FCD_RF0_SPI_Command(PDOWN); } void FCD_RF0_Send_Byte(char Data) { FCD_RF0_Send_String (&Data, 1); } void FCD_RF0_Send_String(char* String, char MSZ_String) { char ch; char Ptr = 0; char NextByte = 1; if (MX_RF_Mode != 1) //If we are in receive mode { MX_RF_Mode = 1; //Set mode to data transmit FCD_RF0_Activate_TX_Mode(); //Activate selected mode } if(MSZ_String) { set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit delay_us(1); FCD_RF0_SPI_Byte16(TXBREG | 0xAA); // preamble #if (MX_RF_EXTID == 0) FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | 0x2D); // sync pattern 1st byte (optional) #endif FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | MX_RF_Sync); // sync pattern 2nd byte ch = String[Ptr++]; if(ch) //Atleast 1 character to send? { while(NextByte) { FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | ch); ch = String[Ptr]; if(ch == 0) NextByte = 0; if((Ptr == 0) || (Ptr > MSZ_String)) NextByte = 0; Ptr = Ptr + 1; } FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | 0x00); FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | 0x00); FCD_RF0_Wait_For_SDI(); //Wait for SDI Input } set_bit(MX_RF_PORT, MX_RF_SCS); // Chip select high, end transmission } MX_RF_Mode = 0; FCD_RF0_Activate_RX_Mode(); //Switch to receive mode } char FCD_RF0_Receive_Byte(char Timeout) { char retVal; FCD_RF0_Receive_String(&retVal, 1, 1, Timeout); return retVal; } void FCD_RF0_Receive_String(char* FCR_RETVAL, char FCR_RETVAL_SIZE, char Length, char Timeout) { char ByteRx, ch; char LoopCount; char Ptr = 0; char NextByte = 1; if (MX_RF_Mode != 0) //If we are in transmit mode { MX_RF_Mode = 0; //Set data receive mode FCD_RF0_Activate_RX_Mode(); //Activate selected mode } if (Length > FCR_RETVAL_SIZE) Length = FCR_RETVAL_SIZE; while(NextByte) { LoopCount = 0; ByteRx = 0; while((LoopCount < Timeout) && (ByteRx == 0)) { clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit delay_us(1); #if (MX_RF_SPI_HW == 0) ByteRx = (test_bit(MX_RF_PORT, MX_RF_SDI)); #else ByteRx = (test_bit(MX_RF_SDI_PORT, MX_RF_SDI_PIN)); #endif set_bit(MX_RF_PORT, MX_RF_SCS); // Set Chip Select bit if (ByteRx == 0) { delay_us(100); } LoopCount++; } if(ByteRx) { clear_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 0 delay_us(1); ch = FCD_RF0_SPI_Byte(0); if (ch) { FCR_RETVAL[Ptr] = ch; Ptr = Ptr + 1; } else { NextByte = 0; } set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 } else { NextByte = 0; } if(Ptr == Length) NextByte = 0; } if(Ptr < FCR_RETVAL_SIZE) FCR_RETVAL[Ptr] = 0; if(Ptr) { FCD_RF0_SPI_Command(FIFORSTREG); FCD_RF0_SPI_Command(FIFORSTREG | MX_RF_EXTID | 0x0002);// reset FIFO } set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 set_bit(MX_RF_PORT, MX_RF_SCS); // Chip select high, end transmission } void FCD_RF0_Activate_RX_Mode() { FCD_RF0_SPI_Command(PMCREG | 0x0080); // turn off Tx, turn on the receiver if (MX_RF_Mode == 0) //Set system mode value { FCD_RF0_SPI_Command(GENCREG | 0x0040); // disable the Tx register, Enable the FIFO FCD_RF0_SPI_Command(FIFORSTREG); FCD_RF0_SPI_Command(FIFORSTREG | MX_RF_EXTID | 0x0002); // reset FIFO set_bit(MX_RF_PORT, MX_RF_FSEL); clear_bit(MX_RF_TRIS, MX_RF_FSEL); //FSEL pin as output } else { set_bit(MX_RF_TRIS, MX_RF_FSEL); //FSEL pin as input FCD_RF0_SPI_Command(GENCREG); //Leave the FIFO disabled } } void FCD_RF0_Activate_TX_Mode() { FCD_RF0_SPI_Command(PMCREG); // Turn off the transmitter and receiver if (MX_RF_Mode == 1) { FCD_RF0_SPI_Command(GENCREG | 0x0080); // Enable the Tx register } else { FCD_RF0_SPI_Command(GENCREG); // disable the Tx register and the FIFO } FCD_RF0_SPI_Command(PMCREG | 0x0020); // Turn on tx set_bit(MX_RF_PORT, MX_RF_FSEL); clear_bit(MX_RF_TRIS, MX_RF_FSEL); //FSEL pin as output } void FCD_RF0_Update_Centre_Frequency(short Frequency) { if (Frequency < 96) Frequency = 96; if (Frequency > 3903) Frequency = 3903; FCD_RF0_SPI_Command(CFSREG | Frequency); } void FCD_RF0_Set_Sync_Pattern(char Mode, char Pattern) { MX_RF_Sync = Pattern; FCD_RF0_SPI_Command(FIFORSTREG); if (Mode) { //Word type synchronisation FCD_RF0_SPI_Command(FIFORSTREG | 0x02); } else { //Byte type synchronisation FCD_RF0_SPI_Command(FIFORSTREG | 0x0a); } FCD_RF0_SPI_Command(SYNCHRON | MX_RF_Sync); } void FCD_RF0_RX_Tune(char Bandwidth, char Gain, char Threshold) { unsigned int TuneVals; if (Bandwidth > 6) Bandwidth = 6; if (Bandwidth < 1) Bandwidth = 1; if (Gain > 3) Gain = 3; if (Threshold > 5) Threshold = 5; TuneVals = RXCREG; TuneVals = TuneVals | (Bandwidth << 5); TuneVals = TuneVals | (Gain << 3); TuneVals = TuneVals | Threshold; FCD_RF0_SPI_Command(TuneVals); } void FCD_RF0_TX_Tune(char Deviation, char Power) { char MX_RF_TxProps; if (Deviation > 15) Deviation = 15; if (Power > 7) Power = 7; MX_RF_TxProps = Deviation << 4; MX_RF_TxProps = MX_RF_TxProps | Power; FCD_RF0_SPI_Command(TXCREG | MX_RF_TxProps); } void FCD_RF0_Set_Data_Rate(char Rate) { char cs = 0; unsigned long r; r = 100000 / (29 * Rate); //10 x data rate value r = r + 5; //round up r = r / 10; //divide by 10 if (r > 0x80) //result too large { cs = 0x80; //set cs bit r >>= 2; //divide by 4 if (r & 0x01) r = r + 1; //round up r >>= 1; //divide by 2 } r = r - 1; FCD_RF0_SPI_Command(DATARATE | cs | (char)r); } char FCD_RF0_Read_RX_Signal_Strength() { unsigned int test = 0; test = FCD_RF0_SPI_Command(0); //Read back and return STSREG test = test >> 6; //Rotate so that data we want is one bits 0 and 1 test = test & 0x07; //Mask off any unwanted values return (test); } void FCD_RF0_FSK_Write(char State) { if(MX_RF_Mode != 3) { MX_RF_Mode = 3; //Set system mode value FCD_RF0_Activate_TX_Mode(); } if(State) set_bit(MX_RF_PORT, MX_RF_FSEL); else clear_bit(MX_RF_PORT, MX_RF_FSEL); } char FCD_RF0_FSK_Read() { if (MX_RF_Mode != 2) { MX_RF_Mode = 2; FCD_RF0_Activate_RX_Mode(); } return(test_bit(MX_RF_PORT, MX_RF_FSEL)); } void FCD_RF0_Set_Buffer_Data(char Index, char Data) { if (Index < MX_RF_BUFFER_MAX) MX_RF_TX_Buffer[Index + 1] = Data; } void FCD_RF0_Send_Buffer(char Count) { char Data; char Ptr; char NextByte = 1; char Csum = 0; if (Count < MX_RF_BUFFER_MAX) { MX_RF_TX_Buffer[0] = Count; //Calculate checksum for(Ptr = 0; Ptr <= Count; Ptr++) Csum = Csum ^ MX_RF_TX_Buffer[Ptr]; MX_RF_TX_Buffer[Ptr] = Csum; //Include count and checksum Count = Count + 2; //Set Tx mode if (MX_RF_Mode != 1) //If we are in receive mode { MX_RF_Mode = 1; FCD_RF0_Activate_TX_Mode(); //Switch to transmit mode } set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit delay_us(1); // FCD_RF0_Wait_For_SDI(); FCD_RF0_SPI_Byte16(TXBREG | 0xAA); // preamble #if (MX_RF_EXTID == 0) FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | 0x2D); // sync pattern 1st byte (optional) #endif FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | MX_RF_Sync); // sync pattern 2nd byte Ptr = 0; Data = MX_RF_TX_Buffer[Ptr]; Ptr = Ptr + 1; while(NextByte) { FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | Data); // write byte to tx register Data = MX_RF_TX_Buffer[Ptr]; Ptr = Ptr + 1; if(Ptr == Count) NextByte = 0; } FCD_RF0_Wait_For_SDI(); //Wait for SDI Input FCD_RF0_SPI_Byte16(TXBREG | 0x00); // write a dummy byte since the previous byte is still in buffer FCD_RF0_Wait_For_SDI(); //Wait for SDI Input set_bit(MX_RF_PORT, MX_RF_SCS); // Chip select high, end transmission MX_RF_Mode = 0; FCD_RF0_Activate_RX_Mode(); //Switch to receive mode } } char FCD_RF0_Check_Buffer(char Timeout) { char ByteRx, Data; char LoopCount; char Ptr = 0; char NextByte = 1; char Count; char retVal = 255; /* Return values 255 = No data 254 = Count error (data count > buffer) 253 = Insufficient data/timeout during reception 252 = Checksum error (TODO) */ if (MX_RF_Mode != 0) //If we are in transmit mode { MX_RF_Mode = 0; FCD_RF0_Activate_RX_Mode(); //Switch to receive mode } //Get data count LoopCount = 0; ByteRx = 0; while((LoopCount < Timeout) && (ByteRx == 0)) { clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit delay_us(1); #if (MX_RF_SPI_HW == 0) ByteRx = (test_bit(MX_RF_PORT, MX_RF_SDI)); #else ByteRx = (test_bit(MX_RF_PORT, MX_SPI_SDI)); #endif set_bit(MX_RF_PORT, MX_RF_SCS); // Set Chip Select bit if (ByteRx == 0) delay_us(100); LoopCount++; } if(ByteRx) { retVal = 254; //Count received: default = count error clear_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 0 delay_us(1); Count = FCD_RF0_SPI_Byte(0); set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 if (Count <= MX_RF_BUFFER_MAX) { retVal = 253; //Receiving data: default = count match error MX_RF_RX_Buff1[Ptr] = Count; Ptr = Ptr + 1; Count = Count + 2; //Include count and checksum while(NextByte) { LoopCount = 0; ByteRx = 0; while((LoopCount < Timeout) && (ByteRx == 0)) { clear_bit(MX_RF_PORT, MX_RF_SCS); // Clear Chip Select bit delay_us(1); #if (MX_RF_SPI_HW == 0) ByteRx = (test_bit(MX_RF_PORT, MX_RF_SDI)); #else ByteRx = (test_bit(MX_RF_PORT, MX_SPI_SDI)); #endif set_bit(MX_RF_PORT, MX_RF_SCS); // Set Chip Select bit if (ByteRx == 0) { delay_us(100); } LoopCount = LoopCount + 1; } if(ByteRx) { clear_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 0 delay_us(1); MX_RF_RX_Buff1[Ptr] = FCD_RF0_SPI_Byte(0); Ptr = Ptr + 1; set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 } else { NextByte = 0; } if(Ptr == Count) { NextByte = 0; for(Ptr = 0; Ptr < Count; Ptr++) MX_RF_RX_Buffer[Ptr] = MX_RF_RX_Buff1[Ptr]; retVal = Count - 2; } } } // set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 // FCD_RF0_SPI_Command(PMCREG); // FCD_RF0_SPI_Command(GENCREG); // FCD_RF0_SPI_Command(GENCREG | 0x0040); // FCD_RF0_SPI_Command(PMCREG | 0x0080); FCD_RF0_SPI_Command(FIFORSTREG); FCD_RF0_SPI_Command(FIFORSTREG | MX_RF_EXTID | 0x0002); // reset FIFO } set_bit(MX_RF_PORT, MX_RF_FSEL); // FSEL Output 1 set_bit(MX_RF_PORT, MX_RF_SCS); // Chip select high, end transmission return (retVal); } char FCD_RF0_Get_Data_Count() { return(MX_RF_RX_Buffer[0]); } char FCD_RF0_Get_Buffer_Data(char Index) { if (Index < MX_RF_BUFFER_MAX) return(MX_RF_RX_Buffer[Index + 1]); else return(0); } //Macro implementations void main() { //Initialisation adcon1 = 0x07; //Interrupt initialisation code option_reg = 0xC0; //Call Component Macro //Call Component Macro: ret2=RF(0)::Init_RF_Module FCV_RET2 = FCD_RF0_Init_RF_Module(); //Loop //Loop: While 1 while (1) { //Calculation //Calculation: // ret = ret+1 FCV_RET = FCV_RET+1; //Call Component Macro //Call Component Macro: RF(0)::Send_Byte(ret) FCD_RF0_Send_Byte(FCV_RET); //Comment: //program does not get past this point, why ? //Output //Output: ret -> PORTD trisd = 0x00; portd = FCV_RET; //Delay //Delay: 1 s delay_s(1); } mainendloop: goto mainendloop; } void MX_INTERRUPT_MACRO(void) { }