//************************************************************************************ //** //** File name: C:\Documents and Settings\Administrator\Desktop\CAN_Example_04_Receive.c //** Generated by: Flowcode v4.5.17.73 //** Date: Tuesday, July 17, 2012 16:12:27 //** Licence: Professional //** Registered to: Ben Rowland //** //** //** http://www.matrixmultimedia.com //************************************************************************************ #define MX_PIC //Defines for microcontroller #define P18F2580 #define MX_EE #define MX_EE_TYPE3 #define MX_EE_SIZE 256 #define MX_SPI #define MX_SPI_C #define MX_SPI_SDI 4 #define MX_SPI_SDO 5 #define MX_SPI_SCK 3 #define MX_UART #define MX_UART_C #define MX_UART_TX 6 #define MX_UART_RX 7 #define MX_I2C #define MX_MI2C #define MX_I2C_C #define MX_I2C_SDA 4 #define MX_I2C_SCL 3 #define MX_PWM #define MX_PWM_CNT 1 #define MX_PWM_TRIS1 trisc #define MX_PWM_1 2 #define MX_ECAN //Functions #define MX_CLK_SPEED 20000000 #ifdef _BOOSTC #include #endif #ifdef HI_TECH_C #include #endif //Configuration data #ifdef _BOOSTC #pragma DATA 0x300000, 0xff #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300001, 0x42 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300002, 0x1f #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300003, 0x1e #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300004, 0xff #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300005, 0x86 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300006, 0x91 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300007, 0xff #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300008, 0xf #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x300009, 0xc0 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x30000a, 0xf #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x30000b, 0xe0 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x30000c, 0xf #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif #ifdef _BOOSTC #pragma DATA 0x30000d, 0x40 #endif #ifdef _HI_TECH_C %C__CONFIG(%A, %V); #endif //Internal functions #include "C:\Program Files\Matrix Multimedia\Flowcode V4\FCD\internals.h" //Macro function declarations void FCM_INTERRUPT_TMR0(); void FCM_INTERRUPT_RB0INT(); void FCM_INTERRUPT_PORTB(); void FCM_CAN_MONITOR(); void FCM_NODE_FROM_ID(); //Variable declarations char FCV_ID_LO; char FCV_NODE; char FCV_TO_MENU; char FCV_DATA_COUNT; char FCV_MENU_CHOICE; char FCV_ID_VAL; char FCV_MESSAGE; char FCV_DATA_VAL; char FCV_ID_HI; //CAN(0): //Defines: /**** Macro Substitutions **** 6 = Chip Select Pin 0 = Interrupt Pin 1 = Interrupt Pin Mask 7 = Filter 1 Configuration 209 = Filter 2 Configuration 3 = Filter 3 Configuration 12 = Buffer Control 0 = TXRTS Control //Transmission message (TXB0): #define TXB0CTRL_VAL 3 #define TXB0SIDH_VAL 0 #define TXB0SIDL_VAL 32 #define TXB0DLC_VAL 0 #define TXB0DB0_VAL 255 #define TXB0DB1_VAL 170 #define TXB0DB2_VAL 0 #define TXB0DB3_VAL 0 #define TXB0DB4_VAL 0 #define TXB0DB5_VAL 0 #define TXB0DB6_VAL 0 #define TXB0DB7_VAL 0 = Transmit Buffer 0 Messages //Transmission message (TXB1): #define TXB1CTRL_VAL 2 #define TXB1SIDH_VAL 0 #define TXB1SIDL_VAL 64 #define TXB1DLC_VAL 0 #define TXB1DB0_VAL 255 #define TXB1DB1_VAL 255 #define TXB1DB2_VAL 255 #define TXB1DB3_VAL 6 #define TXB1DB4_VAL 5 #define TXB1DB5_VAL 4 #define TXB1DB6_VAL 3 #define TXB1DB7_VAL 2 = Transmit Buffer 1 Messages //Transmission message (TXB2): #define TXB2CTRL_VAL 1 #define TXB2SIDH_VAL 0 #define TXB2SIDL_VAL 96 #define TXB2DLC_VAL 0 #define TXB2DB0_VAL 255 #define TXB2DB1_VAL 0 #define TXB2DB2_VAL 0 #define TXB2DB3_VAL 0 #define TXB2DB4_VAL 0 #define TXB2DB5_VAL 0 #define TXB2DB6_VAL 0 #define TXB2DB7_VAL 0 = Transmit Buffer 2 Messages //Reception (RXB0) #define RXB0CTRL_VAL 96 #define RXF0SIDH_VAL 12 #define RXF0SIDL_VAL 128 #define RXF1SIDH_VAL 12 #define RXF1SIDL_VAL 160 #define RXM0SIDH_VAL 255 #define RXM0SIDL_VAL 224 = Receive Buffer 0 Messages //Reception (RXB1) #define RXB1CTRL_VAL 32 #define RXF2SIDH_VAL 12 #define RXF2SIDL_VAL 200 #define RXF3SIDH_VAL 255 #define RXF3SIDL_VAL 232 #define RXF4SIDH_VAL 255 #define RXF4SIDL_VAL 232 #define RXF5SIDH_VAL 255 #define RXF5SIDL_VAL 232 #define RXM1SIDH_VAL 255 #define RXM1SIDL_VAL 224 = Receive Buffer 1 Messages 1 = Internal CAN enable %o = Internal Bit Rate0 %p = Internal Bit Rate1 %q = Internal Bit Rate2 ******************************/ //common defines #define CAN_CHIPSEL 6 #define CAN_INTERRUPT 0 #define CAN_INT_MASK 1 #define CNF1_VAL 7 #define CNF2_VAL 209 #define CNF3_VAL 3 #define BFPCTRL_VAL 12 #define TXRTSCTRL_VAL 0 #define CAN_MAX_TX_BUF (3) #define CAN_MAX_RX_BUF (2) //One shot mode, CLKOUT enable, CLKOUT prescaler #define CANCTRL_VAL 0x80 #define MX_CANSTAT_VAL 0x80 //Extended ID Dummy Values #define TXB0EID8_VAL 0x00 #define TXB0EID0_VAL 0x00 #define TXB1EID8_VAL 0x00 #define TXB1EID0_VAL 0x00 #define TXB2EID8_VAL 0x00 #define TXB2EID0_VAL 0x00 #define RXF0EID8_VAL 0x00 #define RXF0EID0_VAL 0x00 #define RXF1EID8_VAL 0x00 #define RXF1EID0_VAL 0x00 #define RXF2EID8_VAL 0x00 #define RXF2EID0_VAL 0x00 #define RXF3EID8_VAL 0x00 #define RXF3EID0_VAL 0x00 #define RXF4EID8_VAL 0x00 #define RXF4EID0_VAL 0x00 #define RXF5EID8_VAL 0x00 #define RXF5EID0_VAL 0x00 #define RXM0EID8_VAL 0xFF #define RXM0EID0_VAL 0xFF #define RXM1EID8_VAL 0xFF #define RXM1EID0_VAL 0xFF //CANCTRL #define REQOP_CONFIG 0x80 #define REQOP_LISTEN 0x60 #define REQOP_LOOPBACK 0x40 #define REQOP_SLEEP 0x20 #define REQOP_NORMAL 0x00 //Transmission messages (TXB0-2): //Transmission message (TXB0): #define TXB0CTRL_VAL 3 #define TXB0SIDH_VAL 0 #define TXB0SIDL_VAL 32 #define TXB0DLC_VAL 0 #define TXB0DB0_VAL 255 #define TXB0DB1_VAL 170 #define TXB0DB2_VAL 0 #define TXB0DB3_VAL 0 #define TXB0DB4_VAL 0 #define TXB0DB5_VAL 0 #define TXB0DB6_VAL 0 #define TXB0DB7_VAL 0 //Transmission message (TXB1): #define TXB1CTRL_VAL 2 #define TXB1SIDH_VAL 0 #define TXB1SIDL_VAL 64 #define TXB1DLC_VAL 0 #define TXB1DB0_VAL 255 #define TXB1DB1_VAL 255 #define TXB1DB2_VAL 255 #define TXB1DB3_VAL 6 #define TXB1DB4_VAL 5 #define TXB1DB5_VAL 4 #define TXB1DB6_VAL 3 #define TXB1DB7_VAL 2 //Transmission message (TXB2): #define TXB2CTRL_VAL 1 #define TXB2SIDH_VAL 0 #define TXB2SIDL_VAL 96 #define TXB2DLC_VAL 0 #define TXB2DB0_VAL 255 #define TXB2DB1_VAL 0 #define TXB2DB2_VAL 0 #define TXB2DB3_VAL 0 #define TXB2DB4_VAL 0 #define TXB2DB5_VAL 0 #define TXB2DB6_VAL 0 #define TXB2DB7_VAL 0 //Reception (TXB0-1) //Reception (RXB0) #define RXB0CTRL_VAL 96 #define RXF0SIDH_VAL 12 #define RXF0SIDL_VAL 128 #define RXF1SIDH_VAL 12 #define RXF1SIDL_VAL 160 #define RXM0SIDH_VAL 255 #define RXM0SIDL_VAL 224 //Reception (RXB1) #define RXB1CTRL_VAL 32 #define RXF2SIDH_VAL 12 #define RXF2SIDL_VAL 200 #define RXF3SIDH_VAL 255 #define RXF3SIDL_VAL 232 #define RXF4SIDH_VAL 255 #define RXF4SIDL_VAL 232 #define RXF5SIDH_VAL 255 #define RXF5SIDL_VAL 232 #define RXM1SIDH_VAL 255 #define RXM1SIDL_VAL 224 #define INTERNAL_CAN_ENABLE 1 char CAN_MSG_DLC; char CAN_MSG_DATA[8]; char MsgFlags = 0; #ifdef CAN_USE_EXID char CAN_MSG_ID[4]; #else char CAN_MSG_ID[2]; #endif #if INTERNAL_CAN_ENABLE == 1 #define USE_INT_CAN #define CAN_OP_MODE_BITS 0xE0 #else ////////////////////////////////////////////////////////// //THESE SHOULD *NOT* BE MODIFIED BY THE USER: ///////////////////////////////////////////////////////// #ifndef MX_SPI #error "Chip does not have SPI capability" #endif #ifdef MX_SPI_B #define MX_CAN_PORT portb #define MX_CAN_TRIS trisb #define MX_CAN_SDO_TRIS trisb #define MX_CAN_CS_PORT portb #define MX_CAN_CS_TRIS trisb #define MX_CAN_INT_PORT portb #define MX_CAN_INT_TRIS trisb #endif #ifdef MX_SPI_C #define MX_CAN_PORT portc #define MX_CAN_TRIS trisc #define MX_CAN_SDO_TRIS trisc #define MX_CAN_CS_PORT portc #define MX_CAN_CS_TRIS trisc #define MX_CAN_INT_PORT portc #define MX_CAN_INT_TRIS trisc #endif #ifdef MX_SPI_BCB #define MX_CAN_PORT portb #define MX_CAN_TRIS trisb #define MX_CAN_SDO_TRIS trisc #define MX_CAN_CS_PORT portb #define MX_CAN_CS_TRIS trisb #define MX_CAN_INT_PORT portb #define MX_CAN_INT_TRIS trisb #endif #ifdef MX_MIAC #undef MX_CAN_CS_PORT #undef MX_CAN_CS_TRIS #undef MX_CAN_INT_PORT #undef MX_CAN_INT_TRIS #undef CAN_CHIPSEL #undef CAN_INTERRUPT #undef CAN_INT_MASK #define MX_CAN_CS_PORT portd #define MX_CAN_CS_TRIS trisd #define MX_CAN_INT_PORT porta #define MX_CAN_INT_TRIS trisa #define CAN_CHIPSEL 7 #define CAN_INTERRUPT 4 #define CAN_INT_MASK 16 #endif #ifndef MX_CAN_PORT #error "MX_CAN_PORT has not been assigned" #endif //This is the interrupt enable register (set to flag on message received - RX0 and RX1 - and on an error) //#define CANINTE_VAL 0x23 //TODO: should we turn interrupts off, like this: //#define CANINTE_VAL 0x00 //TODO: of just turn on RX interrupts, like this: #define CANINTE_VAL 0x03 // ********************************************************************** // * MCP2510 Register Definitions * // ********************************************************************** //Configuration Registers #define MX_CANSTAT 0x0E #define CANCTRL 0x0F #define BFPCTRL 0x0C #define TEC 0x1C #define REC 0x1D #define CNF3 0x28 #define CNF2 0x29 #define CNF1 0x2A #define CANINTE 0x2B #define CANINTF 0x2C #define EFLG 0x2D #define TXRTSCTRL 0x0D //Receive Filters //NOTE: Use "a" for i={0,1,2} and "b" for i={3,4,5} #define RXFxaSIDH(i) ((i*4)+0) #define RXFxaSIDL(i) ((i*4)+1) #define RXFxaEID8(i) ((i*4)+2) #define RXFxaEID0(i) ((i*4)+3) #define RXFxbSIDH(i) ((i*4)+4) #define RXFxbSIDL(i) ((i*4)+5) #define RXFxbEID8(i) ((i*4)+6) #define RXFxbEID0(i) ((i*4)+7) /* #define RXF0SIDH 0x00 #define RXF0SIDL 0x01 #define RXF0EID8 0x02 #define RXF0EID0 0x03 #define RXF1SIDH 0x04 #define RXF1SIDL 0x05 #define RXF1EID8 0x06 #define RXF1EID0 0x07 #define RXF2SIDH 0x08 #define RXF2SIDL 0x09 #define RXF2EID8 0x0A #define RXF2EID0 0x0B #define RXF3SIDH 0x10 #define RXF3SIDL 0x11 #define RXF3EID8 0x12 #define RXF3EID0 0x13 #define RXF4SIDH 0x14 #define RXF4SIDL 0x15 #define RXF4EID8 0x16 #define RXF4EID0 0x17 #define RXF5SIDH 0x18 #define RXF5SIDL 0x19 #define RXF5EID8 0x1A #define RXF5EID0 0x1B */ //Receive Masks #define RXMxSIDH(i) ((i*4)+0x20) #define RXMxSIDL(i) ((i*4)+0x21) #define RXMxEID8(i) ((i*4)+0x22) #define RXMxEID0(i) ((i*4)+0x23) //Tx Buffers #define TXBxCTRL(i) ((i*0x10)+0x30) #define TXBxSIDH(i) ((i*0x10)+0x31) #define TXBxSIDL(i) ((i*0x10)+0x32) #define TXBxEID8(i) ((i*0x10)+0x33) #define TXBxEID0(i) ((i*0x10)+0x34) #define TXBxDLC(i) ((i*0x10)+0x35) #define TXBxD0(i) ((i*0x10)+0x36) #define TXBxDy(i,j) ((i*0x10)+0x36+j) //Rx Buffers #define RXBxCTRL(i) ((i*0x10)+0x60) #define RXBxSIDH(i) ((i*0x10)+0x61) #define RXBxSIDL(i) ((i*0x10)+0x62) #define RXBxEID8(i) ((i*0x10)+0x63) #define RXBxEID0(i) ((i*0x10)+0x64) #define RXBxDLC(i) ((i*0x10)+0x65) #define RXBxD0(i) ((i*0x10)+0x66) #define RXBxDy(i,j) ((i*0x10)+0x66+j) // ******************************************************************* // * Bit register masks * // ******************************************************************* //TXBnCTRL #define MX_TXREQ 0x08 #define TXP 0x03 //RXBnCTRL #define RXM 0x60 #define BUKT 0x04 //CANCTRL #define REQOP 0xE0 #define MX_ABAT 0x10 #define CLKEN 0x04 #define CLKPRE 0x03 #define OSM 0x08 // (ST) new for the 2515 //MX_CANSTAT #define REQOP 0xE0 #define ICOD 0x0E //CANINTE #define RX0IE 0x01 #define RX1IE 0x02 #define TX0IE 0x04 #define TX1IE 0x80 #define TX2IE 0x10 #define MX_ERRIE 0x20 #define MX_WAKIE 0x40 #define IVMIE 0x80 //CANINTF #define RX0IF 0x01 #define RX1IF 0x02 #define TX0IF 0x04 #define TX1IF 0x80 #define TX2IF 0x10 #define MX_ERRIF 0x20 #define MX_WAKIF 0x40 #define IVMIF 0x80 //BFPCTRL #define B1BFS 0x20 #define B0BFS 0x10 #define B1BFE 0x08 #define B0BFE 0x04 #define B1BFM 0x02 #define B0BFM 0x01 //CNF1 Masks #define SJW 0xC0 #define BRP 0x3F //CNF2 Masks #define BTLMODE 0x80 #define MX_SAM 0x40 #define PHSEG1 0x38 #define PRSEG 0x07 //CNF3 Masks #define MX_WAKFIL 0x40 #define PHSEG2 0x07 #define SOF 0x80 // (ST) new for the 2515 //TXRTSCTRL Masks #define TXB2RTS 0x04 #define TXB1RTS 0x02 #define TXB0RTS 0x01 // ******************************************************************* // * Bit Timing Configuration * // ******************************************************************* //CNF1 #define SJW_1TQ 0x40 #define SJW_2TQ 0x80 #define SJW_3TQ 0x90 #define SJW_4TQ 0xC0 //CNF2 #define BTLMODE_CNF3 0x80 #define BTLMODE_PH1_IPT 0x00 #define SMPL_3X 0x40 #define SMPL_1X 0x00 #define PHSEG1_8TQ 0x38 #define PHSEG1_7TQ 0x30 #define PHSEG1_6TQ 0x28 #define PHSEG1_5TQ 0x20 #define PHSEG1_4TQ 0x18 #define PHSEG1_3TQ 0x10 #define PHSEG1_2TQ 0x08 #define PHSEG1_1TQ 0x00 #define PRSEG_8TQ 0x07 #define PRSEG_7TQ 0x06 #define PRSEG_6TQ 0x05 #define PRSEG_5TQ 0x04 #define PRSEG_4TQ 0x03 #define PRSEG_3TQ 0x02 #define PRSEG_2TQ 0x01 #define PRSEG_1TQ 0x00 //CNF3 #define PHSEG2_8TQ 0x07 #define PHSEG2_7TQ 0x06 #define PHSEG2_6TQ 0x05 #define PHSEG2_5TQ 0x04 #define PHSEG2_4TQ 0x03 #define PHSEG2_3TQ 0x02 #define PHSEG2_2TQ 0x01 #define PHSEG2_1TQ 0x00 #define MX_WAKFIL_ENABLED 0x40 #define MX_WAKFIL_DISABLED 0x00 // ******************************************************************* // * Control/Configuration Registers * // ******************************************************************* //CANINTE #define RX0IE_ENABLED 0x01 #define RX0IE_DISABLED 0x00 #define RX1IE_ENABLED 0x02 #define RX1IE_DISABLED 0x00 #define G_RXIE_ENABLED 0x03 #define G_RXIE_DISABLED 0x00 #define TX0IE_ENABLED 0x04 #define TX0IE_DISABLED 0x00 #define TX1IE_ENABLED 0x08 #define TX2IE_DISABLED 0x00 #define TX2IE_ENABLED 0x10 #define TX2IE_DISABLED 0x00 #define G_TXIE_ENABLED 0x1C #define G_TXIE_DISABLED 0x00 #define MX_ERRIE_ENABLED 0x20 #define MX_ERRIE_DISABLED 0x00 #define MX_WAKIE_ENABLED 0x40 #define MX_WAKIE_DISABLED 0x00 #define IVRE_ENABLED 0x80 #define IVRE_DISABLED 0x00 //CANINTF #define RX0IF_SET 0x01 #define RX0IF_RESET 0x00 #define RX1IF_SET 0x02 #define RX1IF_RESET 0x00 #define TX0IF_SET 0x04 #define TX0IF_RESET 0x00 #define TX1IF_SET 0x08 #define TX2IF_RESET 0x00 #define TX2IF_SET 0x10 #define TX2IF_RESET 0x00 #define MX_ERRIF_SET 0x20 #define MX_ERRIF_RESET 0x00 #define MX_WAKIF_SET 0x40 #define MX_WAKIF_RESET 0x00 #define IVRF_SET 0x80 #define IVRF_RESET 0x00 #define ABORT 0x10 #define CLKOUT_ENABLED 0x04 #define CLKOUT_DISABLED 0x00 #define CLKOUT_PRE_8 0x03 #define CLKOUT_PRE_4 0x02 #define CLKOUT_PRE_2 0x01 #define CLKOUT_PRE_1 0x00 //MX_CANSTAT #define OPMODE_CONFIG 0x80 #define OPMODE_LISTEN 0x60 #define OPMODE_LOOPBACK 0x40 #define OPMODE_SLEEP 0x20 #define OPMODE_NORMAL 0x00 //RXBnCTRL #define RXM_RCV_ALL 0x60 #define RXM_VALID_EXT 0x40 #define RXM_VALID_STD 0x20 #define RXM_VALID_ALL 0x00 #define RXRTR_REMOTE 0x08 #define RXRTR_NO_REMOTE 0x00 #define BUKT_ROLLOVER 0x04 #define BUKT_NO_ROLLOVER 0x00 #define FILHIT0_FLTR_1 0x01 #define FILHIT0_FLTR_0 0x00 #define FILHIT1_FLTR_5 0x05 #define FILHIT1_FLTR_4 0x04 #define FILHIT1_FLTR_3 0x03 #define FILHIT1_FLTR_2 0x02 #define FILHIT1_FLTR_1 0x01 #define FILHIT1_FLTR_0 0x00 //TXBnCTRL #define MX_TXREQ_SEND 0x08 #define MX_TXREQ_ABORT 0x00 #define TXP_HIGHEST 0x03 #define TXP_INTER_HIGH 0x02 #define TXP_INTER_LOW 0x01 #define TXP_LOWEST 0x00 // ******************************************************************* // * Register Bit Masks * // ******************************************************************* #define DLC_0 0x00 #define DLC_1 0x01 #define DLC_2 0x02 #define DLC_3 0x03 #define DLC_4 0x04 #define DLC_5 0x05 #define DLC_6 0x06 #define DLC_7 0x07 #define DLC_8 0x08 // ******************************************************************* // * CAN SPI commands * // ******************************************************************* #define CAN_RESET 0xC0 #define CAN_READ 0x03 #define CAN_WRITE 0x02 #define CAN_RD_STATUS 0xA0 #define CAN_BIT_MODIFY 0x05 #define CAN_RTS 0x80 #define CAN_RTS_TXB0 0x81 #define CAN_RTS_TXB1 0x82 //#define CAN_RTS_TXB2 0x83 // (ST) I think this is wrong..so I changed it to this: #define CAN_RTS_TXB2 0x84 //#define CAN_RTS_TXB(i) (0x80 + (0x01 << i)) //NOTE: the above line does not work because the RHS of a shift cannot be a variable // (ST) I also added these for multiple requests... #define CAN_RTS_TXB01 0x83 #define CAN_RTS_TXB02 0x85 #define CAN_RTS_TXB12 0x86 #define CAN_RTS_TXB012 0x87 #define CAN_RX_STATUS 0xB0 #define CAN_RD_RXBUF_ID(i) (0x90 + (i*4)) #define CAN_RD_RXBUF_DT(i) (0x92 + (i*4)) #define CAN_LD_TXBUF_ID(i) (0x40 + (i*2)) #define CAN_LD_TXBUF_DT(i) (0x41 + (i*2)) #endif // ******************************************************************* // * Miscellaneous * // ******************************************************************* //uncomment this if supporting extended identifiers: //#define CAN_USE_EXID char BF_MASK; //CAN(0): //Macro function declarations void FCD_CAN0_SPI_Init(); char FCD_CAN0_SPI_SendByte(char byte); char FCD_CAN0_CAN_MaskFromBit(char which_bit); void FCD_CAN0_CAN_Reset(); void FCD_CAN0_CAN_Write(char addr, char data); char FCD_CAN0_CAN_Read(char addr); void FCD_CAN0_CAN_Config(char cfg); char FCD_CAN0_CAN_ReadStatus(); char FCD_CAN0_CAN_ReadRXStatus(); void FCD_CAN0_CAN_BitModify(char addr, char mask, char data); char FCD_CAN0_CAN_ReadRX_ID_and_Data(char buffer); void FCD_CAN0_Init(); void FCD_CAN0_SendBuffer(char buffer); char FCD_CAN0_CheckRx(char buffer); void FCD_CAN0_ShowLEDs(char led1, char led2); char FCD_CAN0_ReadSwitches(); char FCD_CAN0_GetRxDataCount(char buffer); char FCD_CAN0_GetRxData(char buffer, char index); void FCD_CAN0_SetTxData(char buffer, char data_cnt, char d0, char d1, char d2, char d3, char d4, char d5, char d6, char d7); void FCD_CAN0_SetTxID(char buffer, char hi, char lo); char FCD_CAN0_GetRxIDLo(char buffer); char FCD_CAN0_GetRxIDHi(char buffer); //LCDDisplay(0): //Defines: /**** Macro Substitutions **** portc = D1 Port trisc = D1 Data Direction portc = D2 Port trisc = D2 Data Direction portc = D3 Port trisc = D3 Data Direction portc = D4 Port trisc = D4 Data Direction portc = RS Port trisc = RS Data Direction portc = E Port trisc = E Data Direction 0 = Data 1_Pin 1 = Data 2 Pin 2 = Data 3 Pin 3 = Data 4 Pin 4 = RS Pin 5 = Enable Pin LCD_1246738 = Unique Component Reference Number 2 = Row Count 16 = Column Count ******************************/ //component connections #define LCD_1246738_PORT0 portc #define LCD_1246738_TRIS0 trisc #define LCD_1246738_PORT1 portc #define LCD_1246738_TRIS1 trisc #define LCD_1246738_PORT2 portc #define LCD_1246738_TRIS2 trisc #define LCD_1246738_PORT3 portc #define LCD_1246738_TRIS3 trisc #define LCD_1246738_PORT4 portc #define LCD_1246738_TRIS4 trisc #define LCD_1246738_PORT5 portc #define LCD_1246738_TRIS5 trisc #define LCD_1246738_BIT0 0 #define LCD_1246738_BIT1 1 #define LCD_1246738_BIT2 2 #define LCD_1246738_BIT3 3 #define LCD_1246738_RS 4 #define LCD_1246738_E 5 #define LCD_1246738_ROWCNT 2 #define LCD_1246738_COLCNT 16 #ifdef _BOOSTC #define LCD_1246738_DELAY delay_10us(10) #endif #ifdef _C2C_ #define LCD_1246738_DELAY delay_us(100) #endif #ifdef HI_TECH_C #define LCD_1246738_DELAY __delay_us(120) #endif #ifndef LCD_1246738_DELAY #define LCD_1246738_DELAY delay_us(100) #endif #define ModIDLCD_1246738LCD_1246738 (((trisc << 5) + portc) << 9) //LCDDisplay(0): //Macro function declarations void FCD_LCDDisplay0_RawSend(char in, char mask); void FCD_LCDDisplay0_Start(); void FCD_LCDDisplay0_Clear(); void FCD_LCDDisplay0_PrintASCII(char Character); void FCD_LCDDisplay0_Command(char in); void FCD_LCDDisplay0_Cursor(char x, char y); void FCD_LCDDisplay0_PrintNumber(short Number); void FCD_LCDDisplay0_PrintString(char* String, char MSZ_String); void FCD_LCDDisplay0_ScrollDisplay(char Direction, char Num_Positions); void FCD_LCDDisplay0_ClearLine(char Line); void FCD_LCDDisplay0_RAM_Write(char nIdx, char d0, char d1, char d2, char d3, char d4, char d5, char d6, char d7); //CAN(0): //Macro implementations void FCD_CAN0_SPI_Init() { #ifndef USE_INT_CAN #ifndef MX_SPI #error "Chip does not have SPI capability" #endif //initialise spi set_bit(MX_CAN_TRIS,MX_SPI_SDI); clear_bit(MX_CAN_SDO_TRIS,MX_SPI_SDO); clear_bit(MX_CAN_TRIS,MX_SPI_SCK); clear_bit(MX_CAN_CS_TRIS,CAN_CHIPSEL); set_bit(MX_CAN_INT_TRIS,CAN_INTERRUPT); //disable the CAN chip select line set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); sspstat = 0; st_bit(sspstat, CKE); //SMP = 0, CKE = 1 #ifdef _BOOSTC #ifdef SSPCON // SPI Low Speed for Initialise sspcon = 0; st_bit(sspcon, SSPEN); #endif #ifdef SSPCON1 sspcon1 = 0; st_bit(sspcon1, SSPEN); #endif #endif #ifdef HI_TECH_C #ifdef sspcon // SPI Low Speed for Initialise sspcon = 0; st_bit(sspcon, SSPEN); #endif #ifdef sspcon1 sspcon1 = 0; st_bit(sspcon1, SSPEN); #endif #endif //get the mask for the BF bit for later use BF_MASK = FCD_CAN0_CAN_MaskFromBit(BF); #endif } char FCD_CAN0_SPI_SendByte(char byte) { char retval = 0; #ifndef USE_INT_CAN //send the byte sspbuf = byte; //wait until data has been received (transmit complete) while ((sspstat & BF_MASK) == 0); //get received byte retval = sspbuf; #endif return retval; } char FCD_CAN0_CAN_MaskFromBit(char which_bit) { char retVal = 0; switch (which_bit) { case 0: retVal = 0x01; break; case 1: retVal = 0x02; break; case 2: retVal = 0x04; break; case 3: retVal = 0x08; break; case 4: retVal = 0x10; break; case 5: retVal = 0x20; break; case 6: retVal = 0x40; break; case 7: retVal = 0x80; break; } return (retVal); } void FCD_CAN0_CAN_Reset() { #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_RESET); //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); //wait for the CAN device to complete its OST delay_us(20); #endif } void FCD_CAN0_CAN_Write(char addr, char data) { #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_WRITE); //send a byte FCD_CAN0_SPI_SendByte(addr); //send the address FCD_CAN0_SPI_SendByte(data); //send the data //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif } char FCD_CAN0_CAN_Read(char addr) { char data; #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_READ); //read a byte FCD_CAN0_SPI_SendByte(addr); //send the address data = FCD_CAN0_SPI_SendByte(0x5A); //send a don't care byte //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif return (data); } void FCD_CAN0_CAN_Config(char cfg) { #ifndef USE_INT_CAN char mode; char done = 0; while (done == 0) { FCD_CAN0_CAN_Write(CANCTRL, cfg); Wdt_Delay_Ms(1); //not sure if this is needed //read the config mode back mode = FCD_CAN0_CAN_Read(MX_CANSTAT); //mask off the config bits mode = mode & 0xE0; if (mode == cfg) { //it has been set correctly done = 1; } } Wdt_Delay_Ms(1); //not sure if this is needed #endif } char FCD_CAN0_CAN_ReadStatus() { char retval = 0; #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_RD_STATUS); //read the status retval = FCD_CAN0_SPI_SendByte(0x5A); //send a don't care byte //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif return (retval); } char FCD_CAN0_CAN_ReadRXStatus() { char retval = 0; #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_RX_STATUS); //read the status retval = FCD_CAN0_SPI_SendByte(0x5A); //send a don't care byte //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif return (retval); } void FCD_CAN0_CAN_BitModify(char addr, char mask, char data) { #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_BIT_MODIFY); //bit modify FCD_CAN0_SPI_SendByte(addr); //send the address FCD_CAN0_SPI_SendByte(mask); //send the mask FCD_CAN0_SPI_SendByte(data); //send the data //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif } char FCD_CAN0_CAN_ReadRX_ID_and_Data(char buffer) { //populates CAN_MSG_ID[], CAN_MSG_DLC, and CAN_MSG_DATA[], and returns CAN_MSG_DLC char idx = 0; if (buffer > CAN_MAX_RX_BUF) { return (0); } #ifndef USE_INT_CAN //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_RD_RXBUF_ID(buffer)); //read the RX ID CAN_MSG_ID[idx++] = FCD_CAN0_SPI_SendByte(0x5A); //read back SIDH CAN_MSG_ID[idx++] = FCD_CAN0_SPI_SendByte(0x5A); //read back SIDL sspbuf = 0x5A; //send a don't care byte while ((sspstat & BF_MASK) == 0); //wait until data has been received (transmit complete) #ifdef CAN_USE_EXID CAN_MSG_ID[idx++] = sspbuf; //read back EXID8 #endif sspbuf = 0x5A; //send a don't care byte while ((sspstat & BF_MASK) == 0); //wait until data has been received (transmit complete) #ifdef CAN_USE_EXID CAN_MSG_ID[idx++] = sspbuf; //read back EXID0 #endif CAN_MSG_DLC = FCD_CAN0_SPI_SendByte(0x5A); //read back DLC //now read the data (if there is any) if (CAN_MSG_DLC > 0) { CAN_MSG_DATA[0] = FCD_CAN0_SPI_SendByte(0x5A); //read back D0 if (CAN_MSG_DLC > 1) { CAN_MSG_DATA[1] = FCD_CAN0_SPI_SendByte(0x5A); //read back D1 if (CAN_MSG_DLC > 2) { CAN_MSG_DATA[2] = FCD_CAN0_SPI_SendByte(0x5A); //read back D2 if (CAN_MSG_DLC > 3) { CAN_MSG_DATA[3] = FCD_CAN0_SPI_SendByte(0x5A); //read back D3 if (CAN_MSG_DLC > 4) { CAN_MSG_DATA[4] = FCD_CAN0_SPI_SendByte(0x5A); //read back D4 if (CAN_MSG_DLC > 5) { CAN_MSG_DATA[5] = FCD_CAN0_SPI_SendByte(0x5A); //read back D5 if (CAN_MSG_DLC > 6) { CAN_MSG_DATA[6] = FCD_CAN0_SPI_SendByte(0x5A); //read back D6 if (CAN_MSG_DLC > 7) { CAN_MSG_DATA[7] = FCD_CAN0_SPI_SendByte(0x5A); //read back D7 } } } } } } } } //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif return (CAN_MSG_DLC); } void FCD_CAN0_Init() { #ifdef USE_INT_CAN //configure CAN I/O ciocon = 0x30; // In order to setup necessary config parameters of CAN module, // it must be in CONFIG mode. // Request desired mode. cancon = REQOP_CONFIG; // Wait till desired mode is set. while( (canstat & CAN_OP_MODE_BITS) != REQOP_CONFIG ); // ************************************ // Now set the baud rate. // 20MHz XTAL Required for correct baud // ************************************ brgcon3 = CNF3_VAL; brgcon2 = CNF2_VAL; brgcon1 = CNF1_VAL; rxf0sidh = RXF0SIDH_VAL; // ID Filter 0 - Buffer 0 rxf0sidl = RXF0SIDL_VAL; rxf0eidh = RXF0EID8_VAL; rxf0eidl = RXF0EID0_VAL; rxf1sidh = RXF1SIDH_VAL; // ID Filter 1 - Buffer 0 rxf1sidl = RXF1SIDL_VAL; rxf1eidh = RXF1EID8_VAL; rxf1eidl = RXF1EID0_VAL; rxf2sidh = RXF2SIDH_VAL; // ID Filter 2 - Buffer 1 rxf2sidl = RXF2SIDL_VAL; rxf2eidh = RXF2EID8_VAL; rxf2eidl = RXF2EID0_VAL; rxf3sidh = RXF3SIDH_VAL; // ID Filter 3 - Buffer 1 rxf3sidl = RXF3SIDL_VAL; rxf3eidh = RXF3EID8_VAL; rxf3eidl = RXF3EID0_VAL; rxf4sidh = RXF4SIDH_VAL; // ID Filter 4 - Buffer 1 rxf4sidl = RXF4SIDL_VAL; rxf4eidh = RXF4EID8_VAL; rxf4eidl = RXF4EID0_VAL; rxf5sidh = RXF5SIDH_VAL; // ID Filter 5 - Buffer 1 rxf5sidl = RXF5SIDL_VAL; rxf5eidh = RXF5EID8_VAL; rxf5eidl = RXF5EID0_VAL; rxm0sidh = RXM0SIDH_VAL; // ID Mask 0 - Buffer 0 rxm0sidl = RXM0SIDL_VAL; rxm0eidh = RXM0EID8_VAL; rxm0eidl = RXM0EID0_VAL; rxm1sidh = RXM1SIDH_VAL; // ID Mask 1 - Buffer 1 rxm1sidl = RXM1SIDL_VAL; rxm1eidh = RXM1EID8_VAL; rxm1eidl = RXM1EID0_VAL; cancon = cancon & 0xE0; //cancon = cancon | 0x0C; rxb0con = RXB0CTRL_VAL; // Receive Buffer 0 Control cancon = cancon & 0xE0; cancon = cancon | 0x0A; rxb0con = RXB1CTRL_VAL; // Receive Buffer 1 Control cancon = cancon & 0xE0; cancon = cancon | 0x08; rxb0con = TXB0CTRL_VAL; // Transmit Buffer 0 Control rxb0sidh = TXB0SIDH_VAL; // Transmit ID 0 rxb0sidl = TXB0SIDL_VAL; rxb0eidh = TXB0EID8_VAL; rxb0eidl = TXB0EID0_VAL; rxb0dlc = TXB0DLC_VAL; rxb0d0 = TXB0DB0_VAL; // Transmit Data Bytes rxb0d1 = TXB0DB1_VAL; rxb0d2 = TXB0DB2_VAL; rxb0d3 = TXB0DB3_VAL; rxb0d4 = TXB0DB4_VAL; rxb0d5 = TXB0DB5_VAL; rxb0d6 = TXB0DB6_VAL; rxb0d7 = TXB0DB7_VAL; cancon = cancon & 0xE0; cancon = cancon | 0x06; rxb0con = TXB1CTRL_VAL; // Transmit Buffer 1 Control rxb0sidh = TXB1SIDH_VAL; // Transmit ID 1 rxb0sidl = TXB1SIDL_VAL; rxb0eidh = TXB1EID8_VAL; rxb0eidl = TXB1EID0_VAL; rxb0dlc = TXB1DLC_VAL; rxb0d1 = TXB1DB0_VAL; // Transmit Data Bytes rxb0d1 = TXB1DB1_VAL; rxb0d2 = TXB1DB2_VAL; rxb0d3 = TXB1DB3_VAL; rxb0d4 = TXB1DB4_VAL; rxb0d5 = TXB1DB5_VAL; rxb0d6 = TXB1DB6_VAL; rxb0d7 = TXB1DB7_VAL; cancon = cancon & 0xE0; cancon = cancon | 0x04; rxb0con = TXB2CTRL_VAL; // Transmit Buffer 2 Control rxb0sidh = TXB2SIDH_VAL; // Transmit ID 2 rxb0sidl = TXB2SIDL_VAL; rxb0eidh = TXB2EID8_VAL; rxb0eidl = TXB2EID0_VAL; rxb0dlc = TXB2DLC_VAL; rxb0d0 = TXB2DB0_VAL; // Transmit Data Bytes rxb0d1 = TXB2DB1_VAL; rxb0d2 = TXB2DB2_VAL; rxb0d3 = TXB2DB3_VAL; rxb0d4 = TXB2DB4_VAL; rxb0d5 = TXB2DB5_VAL; rxb0d6 = TXB2DB6_VAL; rxb0d7 = TXB2DB7_VAL; // Request desired mode. cancon = REQOP_NORMAL; // Wait till desired mode is set. while( (canstat & CAN_OP_MODE_BITS) != REQOP_NORMAL ); #else //Init SPI FCD_CAN0_SPI_Init(); //brief pause here Wdt_Delay_Ms(50); //Reset the CAN device FCD_CAN0_CAN_Reset(); //Put the CAN device into config mode FCD_CAN0_CAN_Config(REQOP_CONFIG); //Initialise all the CAN device registers //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_WRITE); //CAN write mode FCD_CAN0_SPI_SendByte(0x00); //start writting at address 0x00 FCD_CAN0_SPI_SendByte(RXF0SIDH_VAL); // RXF0SIDH 0x00 FCD_CAN0_SPI_SendByte(RXF0SIDL_VAL); // RXF0SIDL 0x01 FCD_CAN0_SPI_SendByte(RXF0EID8_VAL); // RXF0EID8 0x02 FCD_CAN0_SPI_SendByte(RXF0EID0_VAL); // RXF0EID0 0x03 FCD_CAN0_SPI_SendByte(RXF1SIDH_VAL); // RXF1SIDH 0x04 FCD_CAN0_SPI_SendByte(RXF1SIDL_VAL); // RXF1SIDL 0x05 FCD_CAN0_SPI_SendByte(RXF1EID8_VAL); // RXF1EID8 0x06 FCD_CAN0_SPI_SendByte(RXF1EID0_VAL); // RXF1EID0 0x07 FCD_CAN0_SPI_SendByte(RXF2SIDH_VAL); // RXF2SIDH 0x08 FCD_CAN0_SPI_SendByte(RXF2SIDL_VAL); // RXF2SIDL 0x09 FCD_CAN0_SPI_SendByte(RXF2EID8_VAL); // RXF2EID8 0x0A FCD_CAN0_SPI_SendByte(RXF2EID0_VAL); // RXF2EID0 0x0B FCD_CAN0_SPI_SendByte(BFPCTRL_VAL); // BFPCTRL 0x0C FCD_CAN0_SPI_SendByte(TXRTSCTRL_VAL); // TXRTSCTRL 0x0D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x0E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x0F FCD_CAN0_SPI_SendByte(RXF3SIDH_VAL); // RXF3SIDH 0x10 FCD_CAN0_SPI_SendByte(RXF3SIDL_VAL); // RXF3SIDL 0x11 FCD_CAN0_SPI_SendByte(RXF3EID8_VAL); // RXF3EID8 0x12 FCD_CAN0_SPI_SendByte(RXF3EID0_VAL); // RXF3EID0 0x13 FCD_CAN0_SPI_SendByte(RXF4SIDH_VAL); // RXF4SIDH 0x14 FCD_CAN0_SPI_SendByte(RXF4SIDL_VAL); // RXF4SIDL 0x15 FCD_CAN0_SPI_SendByte(RXF4EID8_VAL); // RXF4EID8 0x16 FCD_CAN0_SPI_SendByte(RXF4EID0_VAL); // RXF4EID0 0x17 FCD_CAN0_SPI_SendByte(RXF5SIDH_VAL); // RXF5SIDH 0x18 FCD_CAN0_SPI_SendByte(RXF5SIDL_VAL); // RXF5SIDL 0x19 FCD_CAN0_SPI_SendByte(RXF5EID8_VAL); // RXF5EID8 0x1A FCD_CAN0_SPI_SendByte(RXF5EID0_VAL); // RXF5EID0 0x1B FCD_CAN0_SPI_SendByte(0x00); // TEC 0x1C FCD_CAN0_SPI_SendByte(0x00); // REC 0x1D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x1E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x1F FCD_CAN0_SPI_SendByte(RXM0SIDH_VAL); // RXM0SIDH 0x20 FCD_CAN0_SPI_SendByte(RXM0SIDL_VAL); // RXM0SIDL 0x21 FCD_CAN0_SPI_SendByte(RXM0EID8_VAL); // RXM0EID8 0x22 FCD_CAN0_SPI_SendByte(RXM0EID0_VAL); // RXM0EID0 0x23 FCD_CAN0_SPI_SendByte(RXM1SIDH_VAL); // RXM1SIDH 0x20 FCD_CAN0_SPI_SendByte(RXM1SIDL_VAL); // RXM1SIDL 0x21 FCD_CAN0_SPI_SendByte(RXM1EID8_VAL); // RXM1EID8 0x26 FCD_CAN0_SPI_SendByte(RXM1EID0_VAL); // RXM1EID0 0x27 FCD_CAN0_SPI_SendByte(CNF3_VAL); // CNF3 0x28 FCD_CAN0_SPI_SendByte(CNF2_VAL); // CNF2 0x29 FCD_CAN0_SPI_SendByte(CNF1_VAL); // CNF1 0x2A FCD_CAN0_SPI_SendByte(CANINTE_VAL); // CANINTE 0x2B FCD_CAN0_SPI_SendByte(0x00); // CANINTF 0x2C FCD_CAN0_SPI_SendByte(0x00); // EFLG 0x2D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x2E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x2F FCD_CAN0_SPI_SendByte(TXB0CTRL_VAL); // TXB0CTRL 0x30 FCD_CAN0_SPI_SendByte(TXB0SIDH_VAL); // TXB0SIDH 0x31 FCD_CAN0_SPI_SendByte(TXB0SIDL_VAL); // TXB0SIDL 0x32 FCD_CAN0_SPI_SendByte(TXB0EID8_VAL); // TXB0EID8 0x33 FCD_CAN0_SPI_SendByte(TXB0EID0_VAL); // TXB0EID0 0x34 FCD_CAN0_SPI_SendByte(TXB0DLC_VAL); // TXB0DLC 0x35 FCD_CAN0_SPI_SendByte(TXB0DB0_VAL); // TXB0DB0 0x36 FCD_CAN0_SPI_SendByte(TXB0DB1_VAL); // TXB0DB1 0x37 FCD_CAN0_SPI_SendByte(TXB0DB2_VAL); // TXB0DB2 0x38 FCD_CAN0_SPI_SendByte(TXB0DB3_VAL); // TXB0DB3 0x39 FCD_CAN0_SPI_SendByte(TXB0DB4_VAL); // TXB0DB4 0x3A FCD_CAN0_SPI_SendByte(TXB0DB5_VAL); // TXB0DB5 0x3B FCD_CAN0_SPI_SendByte(TXB0DB6_VAL); // TXB0DB6 0x3C FCD_CAN0_SPI_SendByte(TXB0DB7_VAL); // TXB0DB7 0x3D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x3E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x3F FCD_CAN0_SPI_SendByte(TXB1CTRL_VAL); // TXB1CTRL 0x40 Highest priority FCD_CAN0_SPI_SendByte(TXB1SIDH_VAL); // TXB1SIDH 0x41 FCD_CAN0_SPI_SendByte(TXB1SIDL_VAL); // TXB1SIDL 0x42 FCD_CAN0_SPI_SendByte(TXB1EID8_VAL); // TXB1EID8 0x43 FCD_CAN0_SPI_SendByte(TXB1EID0_VAL); // TXB1EID0 0x44 FCD_CAN0_SPI_SendByte(TXB1DLC_VAL); // TXB1DLC 0x45 FCD_CAN0_SPI_SendByte(TXB1DB0_VAL); // TXB1DB0 0x46 FCD_CAN0_SPI_SendByte(TXB1DB1_VAL); // TXB1DB1 0x47 FCD_CAN0_SPI_SendByte(TXB1DB2_VAL); // TXB1DB2 0x48 FCD_CAN0_SPI_SendByte(TXB1DB3_VAL); // TXB1DB3 0x49 FCD_CAN0_SPI_SendByte(TXB1DB4_VAL); // TXB1DB4 0x4A FCD_CAN0_SPI_SendByte(TXB1DB5_VAL); // TXB1DB5 0x4B FCD_CAN0_SPI_SendByte(TXB1DB6_VAL); // TXB1DB6 0x4C FCD_CAN0_SPI_SendByte(TXB1DB7_VAL); // TXB1DB7 0x4D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x4E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x4F FCD_CAN0_SPI_SendByte(TXB2CTRL_VAL); // TXB2CTRL 0x50 FCD_CAN0_SPI_SendByte(TXB2SIDH_VAL); // TXB2SIDH 0x51 FCD_CAN0_SPI_SendByte(TXB2SIDL_VAL); // TXB2SIDL 0x52 FCD_CAN0_SPI_SendByte(TXB2EID8_VAL); // TXB2EID8 0x53 FCD_CAN0_SPI_SendByte(TXB2EID0_VAL); // TXB2EID0 0x54 FCD_CAN0_SPI_SendByte(TXB2DLC_VAL); // TXB2DLC 0x55 FCD_CAN0_SPI_SendByte(TXB2DB0_VAL); // TXB2DB0 0x56 FCD_CAN0_SPI_SendByte(TXB2DB1_VAL); // TXB2DB1 0x57 FCD_CAN0_SPI_SendByte(TXB2DB2_VAL); // TXB2DB2 0x58 FCD_CAN0_SPI_SendByte(TXB2DB3_VAL); // TXB2DB3 0x59 FCD_CAN0_SPI_SendByte(TXB2DB4_VAL); // TXB2DB4 0x5A FCD_CAN0_SPI_SendByte(TXB2DB5_VAL); // TXB2DB5 0x5B FCD_CAN0_SPI_SendByte(TXB2DB6_VAL); // TXB2DB6 0x5C FCD_CAN0_SPI_SendByte(TXB2DB7_VAL); // TXB2DB7 0x5D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x5E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x5F FCD_CAN0_SPI_SendByte(RXB0CTRL_VAL); // RXB0CTRL 0x60 FCD_CAN0_SPI_SendByte(0x00); // RXB0SIDH 0x61 FCD_CAN0_SPI_SendByte(0x00); // RXB0SIDL 0x62 FCD_CAN0_SPI_SendByte(0x00); // RXB0EID8 0x63 FCD_CAN0_SPI_SendByte(0x00); // RXB0EID0 0x64 FCD_CAN0_SPI_SendByte(0x00); // RXB0DLC 0x65 FCD_CAN0_SPI_SendByte(0x00); // RXB0DB0 0x66 FCD_CAN0_SPI_SendByte(0x00); // RXB0DB1 0x67 FCD_CAN0_SPI_SendByte(0x00); // RXB0DB2 0x68 FCD_CAN0_SPI_SendByte(0x00); // RXB0DB3 0x69 FCD_CAN0_SPI_SendByte(0x00); // RXB0DB4 0x6A FCD_CAN0_SPI_SendByte(0x00); // RXB0DB5 0x6B FCD_CAN0_SPI_SendByte(0x00); // RXB0DB6 0x6C FCD_CAN0_SPI_SendByte(0x00); // RXB0DB7 0x6D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x6E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x6F FCD_CAN0_SPI_SendByte(RXB1CTRL_VAL); // RXB1CTRL 0x70 FCD_CAN0_SPI_SendByte(0x00); // RXB1SIDH 0x71 FCD_CAN0_SPI_SendByte(0x00); // RXB1SIDL 0x72 FCD_CAN0_SPI_SendByte(0x00); // RXB1EID8 0x73 FCD_CAN0_SPI_SendByte(0x00); // RXB1EID0 0x74 FCD_CAN0_SPI_SendByte(0x00); // RXB1DLC 0x75 FCD_CAN0_SPI_SendByte(0x00); // RXB1DB0 0x76 FCD_CAN0_SPI_SendByte(0x00); // RXB1DB1 0x77 FCD_CAN0_SPI_SendByte(0x00); // RXB1DB2 0x78 FCD_CAN0_SPI_SendByte(0x00); // RXB1DB3 0x79 FCD_CAN0_SPI_SendByte(0x00); // RXB1DB4 0x7A FCD_CAN0_SPI_SendByte(0x00); // RXB1DB5 0x7B FCD_CAN0_SPI_SendByte(0x00); // RXB1DB6 0x7C FCD_CAN0_SPI_SendByte(0x00); // RXB1DB7 0x7D FCD_CAN0_SPI_SendByte(MX_CANSTAT_VAL); // MX_CANSTAT 0x7E FCD_CAN0_SPI_SendByte(CANCTRL_VAL); // CANCTRL 0x7F //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); //Put the CAN device into normal mode FCD_CAN0_CAN_Config(REQOP_NORMAL); #endif } void FCD_CAN0_SendBuffer(char buffer) { if (buffer > CAN_MAX_TX_BUF) { return; } #ifdef USE_INT_CAN unsigned int timeout = 0xFFFF; switch (buffer) { case 0: cancon = cancon & 0xE0; cancon = cancon | 0x08; st_bit(rxb0con, TXREQ); //Set Message Transmission Flag while (ts_bit(rxb0con, TXREQ) && timeout) //Wait for message to send timeout = timeout - 1; break; case 1: cancon = cancon & 0xE0; cancon = cancon | 0x06; st_bit(rxb0con, TXREQ); while (ts_bit(rxb0con, TXREQ) && timeout) timeout = timeout - 1; break; case 2: cancon = cancon & 0xE0; cancon = cancon | 0x04; st_bit(rxb0con, TXREQ); while (ts_bit(rxb0con, TXREQ) && timeout) timeout = timeout - 1; break; } #else char cmd = CAN_RTS; //default value switch (buffer) { case 0: cmd = CAN_RTS_TXB0; break; case 1: cmd = CAN_RTS_TXB1; break; case 2: cmd = CAN_RTS_TXB2; break; } //NOTE: this following didn't work: //cmd = CAN_RTS_TXB(buffer); //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(cmd); //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif } char FCD_CAN0_CheckRx(char buffer) { //returns 1 if the buffer is full, 0 otherwise char rx_status; char status_mask; char retval = 0; if (buffer > CAN_MAX_RX_BUF) { return (0); } #ifdef USE_INT_CAN if (buffer == 0) { cancon = cancon & 0xE0; cancon = cancon | 0x0C; //Rx Buffer 0 } else { cancon = cancon & 0xE0; cancon = cancon | 0x0A; //Rx Buffer 1 } if (ts_bit(rxb0con, RXFUL)) { CAN_MSG_DLC = rxb0dlc & 0b00001111; // Retrieve message length. CAN_MSG_ID[0] = rxb0sidh; CAN_MSG_ID[1] = rxb0sidl; if(CAN_MSG_DLC > 0) { CAN_MSG_DATA[0] = rxb0d0; if(CAN_MSG_DLC > 1) { CAN_MSG_DATA[1] = rxb0d1; if(CAN_MSG_DLC > 2) { CAN_MSG_DATA[2] = rxb0d2; if(CAN_MSG_DLC > 3) { CAN_MSG_DATA[3] = rxb0d3; if(CAN_MSG_DLC > 4) { CAN_MSG_DATA[4] = rxb0d4; if(CAN_MSG_DLC > 5) { CAN_MSG_DATA[5] = rxb0d5; if(CAN_MSG_DLC > 6) { CAN_MSG_DATA[6] = rxb0d6; if(CAN_MSG_DLC > 7) { CAN_MSG_DATA[7] = rxb0d7; } } } } } } } } cr_bit(rxb0con, RXFUL); } else return 0; retval = 1; #else if (buffer == 1) { //status_mask = 0x02; //if using FCD_CAN0_CAN_ReadStatus status_mask = 0x80; //if using FCD_CAN0_CAN_ReadRXStatus } else { //status_mask = 0x01; //if using FCD_CAN0_CAN_ReadStatus status_mask = 0x40; //if using FCD_CAN0_CAN_ReadRXStatus } //rx_status = FCD_CAN0_CAN_ReadStatus(); //if using FCD_CAN0_CAN_ReadStatus rx_status = FCD_CAN0_CAN_ReadRXStatus(); //if using FCD_CAN0_CAN_ReadRXStatus if ((rx_status & status_mask) != 0) { retval = 1; //now read in the id and data info FCD_CAN0_CAN_ReadRX_ID_and_Data(buffer); } #endif return (retval); } void FCD_CAN0_ShowLEDs(char led1, char led2) { #ifdef USE_INT_CAN #else // Code_CAN_ShowLEDs char data = 0; if (led1 != 0) { data = data | 0x10; } if (led2 != 0) { data = data | 0x20; } FCD_CAN0_CAN_BitModify(BFPCTRL, 0x30, data); #endif } char FCD_CAN0_ReadSwitches() { char retval = 0; #ifdef USE_INT_CAN #else // Code_CAN_ReadSwitches retval = FCD_CAN0_CAN_Read(TXRTSCTRL); retval = retval & 0x38; // mask off the state retval = retval / 8; // divide by 8 to leave switch data in bottom 3 bits #endif return (retval); } char FCD_CAN0_GetRxDataCount(char buffer) { return (CAN_MSG_DLC); } char FCD_CAN0_GetRxData(char buffer, char index) { if (index > 7) { return (0); } return (CAN_MSG_DATA[index]); } void FCD_CAN0_SetTxData(char buffer, char data_cnt, char d0, char d1, char d2, char d3, char d4, char d5, char d6, char d7) { // Code_CAN_SetTxData if (buffer > CAN_MAX_TX_BUF) { return; } if (data_cnt > 8) { return; } #ifdef USE_INT_CAN switch(buffer) { case 0: cancon = cancon & 0xE0; cancon = cancon | 0x08; //Tx Buffer 0 break; case 1: cancon = cancon & 0xE0; cancon = cancon | 0x06; //Tx Buffer 1 break; case 2: cancon = cancon & 0xE0; cancon = cancon | 0x04; //Tx Buffer 2 break; } rxb0dlc = data_cnt; // Set data count if (data_cnt > 0) { rxb0d0 = d0; if (data_cnt > 1) { rxb0d1 = d1; if (data_cnt > 2) { rxb0d2 = d2; if (data_cnt > 3) { rxb0d3 = d3; if (data_cnt > 4) { rxb0d4 = d4; if (data_cnt > 5) { rxb0d5 = d5; if (data_cnt > 6) { rxb0d6 = d6; if (data_cnt > 7) { rxb0d7 = d7; } } } } } } } } #else char i; char dlc_addr = TXBxDLC(buffer); //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_WRITE); //CAN write mode FCD_CAN0_SPI_SendByte(dlc_addr); //start writting at address 0x00 FCD_CAN0_SPI_SendByte(data_cnt); //send the DLC value //now fill the data bytes... //if (data_cnt > 0) //{ // for (i=0; i 0) { FCD_CAN0_SPI_SendByte(d0); if (data_cnt > 1) { FCD_CAN0_SPI_SendByte(d1); if (data_cnt > 2) { FCD_CAN0_SPI_SendByte(d2); if (data_cnt > 3) { FCD_CAN0_SPI_SendByte(d3); if (data_cnt > 4) { FCD_CAN0_SPI_SendByte(d4); if (data_cnt > 5) { FCD_CAN0_SPI_SendByte(d5); if (data_cnt > 6) { FCD_CAN0_SPI_SendByte(d6); if (data_cnt > 7) { FCD_CAN0_SPI_SendByte(d7); } } } } } } } } //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif } void FCD_CAN0_SetTxID(char buffer, char hi, char lo) { // Code_SetTxID if (buffer > CAN_MAX_TX_BUF) { return; } #ifdef USE_INT_CAN switch(buffer) { case 0: cancon = cancon & 0xE0; cancon = cancon | 0x08; txb0sidh = hi; //set the Hi ID value txb0sidl = lo; //set the Lo ID value break; case 1: cancon = cancon & 0xE0; cancon = cancon | 0x06; txb1sidh = hi; //set the Hi ID value txb1sidl = lo; //set the Lo ID value break; case 2: cancon = cancon & 0xE0; cancon = cancon | 0x04; txb2sidh = hi; //set the Hi ID value txb2sidl = lo; //set the Lo ID value break; } #else char i; char id_addr = TXBxSIDH(buffer); //enable SPI clear_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); FCD_CAN0_SPI_SendByte(CAN_WRITE); //CAN write mode FCD_CAN0_SPI_SendByte(id_addr); //start writting at hi id address FCD_CAN0_SPI_SendByte(hi); //send the Hi ID value FCD_CAN0_SPI_SendByte(lo); //send the Lo ID value //disable SPI set_bit(MX_CAN_CS_PORT, CAN_CHIPSEL); #endif } char FCD_CAN0_GetRxIDLo(char buffer) { return (CAN_MSG_ID[1]); } char FCD_CAN0_GetRxIDHi(char buffer) { return (CAN_MSG_ID[0]); } //LCDDisplay(0): //Macro implementations void FCD_LCDDisplay0_RawSend(char in, char mask) { #ifndef MX_MIAC_SYSTEM unsigned char pt; clear_bit(LCD_1246738_PORT0, LCD_1246738_BIT0); clear_bit(LCD_1246738_PORT1, LCD_1246738_BIT1); clear_bit(LCD_1246738_PORT2, LCD_1246738_BIT2); clear_bit(LCD_1246738_PORT3, LCD_1246738_BIT3); clear_bit(LCD_1246738_PORT4, LCD_1246738_RS); clear_bit(LCD_1246738_PORT5, LCD_1246738_E); pt = ((in >> 4) & 0x0f); if (pt & 0x01) set_bit(LCD_1246738_PORT0, LCD_1246738_BIT0); if (pt & 0x02) set_bit(LCD_1246738_PORT1, LCD_1246738_BIT1); if (pt & 0x04) set_bit(LCD_1246738_PORT2, LCD_1246738_BIT2); if (pt & 0x08) set_bit(LCD_1246738_PORT3, LCD_1246738_BIT3); if (mask) set_bit(LCD_1246738_PORT4, LCD_1246738_RS); LCD_1246738_DELAY; set_bit (LCD_1246738_PORT5, LCD_1246738_E); LCD_1246738_DELAY; clear_bit (LCD_1246738_PORT5, LCD_1246738_E); pt = (in & 0x0f); LCD_1246738_DELAY; clear_bit(LCD_1246738_PORT0, LCD_1246738_BIT0); clear_bit(LCD_1246738_PORT1, LCD_1246738_BIT1); clear_bit(LCD_1246738_PORT2, LCD_1246738_BIT2); clear_bit(LCD_1246738_PORT3, LCD_1246738_BIT3); clear_bit(LCD_1246738_PORT4, LCD_1246738_RS); clear_bit(LCD_1246738_PORT5, LCD_1246738_E); if (pt & 0x01) set_bit(LCD_1246738_PORT0, LCD_1246738_BIT0); if (pt & 0x02) set_bit(LCD_1246738_PORT1, LCD_1246738_BIT1); if (pt & 0x04) set_bit(LCD_1246738_PORT2, LCD_1246738_BIT2); if (pt & 0x08) set_bit(LCD_1246738_PORT3, LCD_1246738_BIT3); if (mask) set_bit(LCD_1246738_PORT4, LCD_1246738_RS); LCD_1246738_DELAY; set_bit (LCD_1246738_PORT5, LCD_1246738_E); LCD_1246738_DELAY; clear_bit (LCD_1246738_PORT5, LCD_1246738_E); LCD_1246738_DELAY; #endif } void FCD_LCDDisplay0_Start() { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_CAN_TX[0] = 0; MIAC_CAN_TX[1] = 1; MIAC_CAN_TX[2] = 2; MIAC_CAN_TX[3] = 3; MIAC_CAN_TX[4] = 4; MIAC_CAN_TX[5] = 5; MIAC_Module_WR(ModIDLCD_1246738, 608, 6,1,1); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 608, 20); MIAC_CAN_TX[0] = 2; MIAC_CAN_TX[1] = 16; MIAC_Module_WR(ModIDLCD_1246738, 608, 2,0,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 608, 255); #endif #else clear_bit(LCD_1246738_TRIS0, LCD_1246738_BIT0); clear_bit(LCD_1246738_TRIS1, LCD_1246738_BIT1); clear_bit(LCD_1246738_TRIS2, LCD_1246738_BIT2); clear_bit(LCD_1246738_TRIS3, LCD_1246738_BIT3); clear_bit(LCD_1246738_TRIS4, LCD_1246738_RS); clear_bit(LCD_1246738_TRIS5, LCD_1246738_E); Wdt_Delay_Ms(12); FCD_LCDDisplay0_RawSend(0x33, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x33, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x32, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x2c, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x06, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x0c, 0); Wdt_Delay_Ms(2); //clear the display FCD_LCDDisplay0_RawSend(0x01, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x02, 0); Wdt_Delay_Ms(2); #endif } void FCD_LCDDisplay0_Clear() { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_Module_WR(ModIDLCD_1246738, 609, 0,1,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 609, 200); #endif #else FCD_LCDDisplay0_RawSend(0x01, 0); Wdt_Delay_Ms(2); FCD_LCDDisplay0_RawSend(0x02, 0); Wdt_Delay_Ms(2); #endif } void FCD_LCDDisplay0_PrintASCII(char Character) { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_CAN_TX[0] = Character; MIAC_Module_WR(ModIDLCD_1246738, 610, 1,1,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 610, 20); #endif #else FCD_LCDDisplay0_RawSend(Character, 0x10); #endif } void FCD_LCDDisplay0_Command(char in) { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_CAN_TX[0] = in; MIAC_Module_WR(ModIDLCD_1246738, 611, 1,1,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 611, 200); #endif #else FCD_LCDDisplay0_RawSend(in, 0); Wdt_Delay_Ms(2); #endif } void FCD_LCDDisplay0_Cursor(char x, char y) { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_CAN_TX[0] = x; MIAC_CAN_TX[1] = y; MIAC_Module_WR(ModIDLCD_1246738, 612, 2,1,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 612, 20); #endif #else #if (LCD_1246738_ROWCNT == 1) y=0x80; #endif #if (LCD_1246738_ROWCNT == 2) if (y==0) y=0x80; else y=0xc0; #endif #if (LCD_1246738_ROWCNT == 4) if (y==0) y=0x80; else if (y==1) y=0xc0; #if (LCD_1246738_COLCNT == 16) else if (y==2) y=0x90; else y=0xd0; #endif #if (LCD_1246738_COLCNT == 20) else if (y==2) y=0x94; else y=0xd4; #endif #endif FCD_LCDDisplay0_RawSend(y+x, 0); Wdt_Delay_Ms(2); #endif } void FCD_LCDDisplay0_PrintNumber(short Number) { #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) MIAC_CAN_TX[1] = Number; MIAC_CAN_TX[0] = Number >> 8; MIAC_Module_WR(ModIDLCD_1246738, 613, 4,1,0); MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 613, 200); #endif #else short tmp_int; char tmp_byte; if (Number < 0) { FCD_LCDDisplay0_RawSend('-', 0x10); Number = 0 - Number; } tmp_int = Number; if (Number >= 10000) { tmp_byte = tmp_int / 10000; FCD_LCDDisplay0_RawSend('0' + tmp_byte, 0x10); while (tmp_byte > 0) { tmp_int = tmp_int - 10000; tmp_byte--; } } if (Number >= 1000) { tmp_byte = tmp_int / 1000; FCD_LCDDisplay0_RawSend('0' + tmp_byte, 0x10); while (tmp_byte > 0) { tmp_int = tmp_int - 1000; tmp_byte--; } } if (Number >= 100) { tmp_byte = tmp_int / 100; FCD_LCDDisplay0_RawSend('0' + tmp_byte, 0x10); while (tmp_byte > 0) { tmp_int = tmp_int - 100; tmp_byte--; } } if (Number >= 10) { tmp_byte = tmp_int / 10; FCD_LCDDisplay0_RawSend('0' + tmp_byte, 0x10); while (tmp_byte > 0) { tmp_int = tmp_int - 10; tmp_byte--; } } FCD_LCDDisplay0_RawSend('0' + tmp_int, 0x10); #endif } void FCD_LCDDisplay0_PrintString(char* String, char MSZ_String) { char idx = 0; #ifdef MX_MIAC_SYSTEM #if (portc != MX_MIAC_MM_MIAC_BASE) char msg_count, ch; char cmd_start = 1; char more_data = 1; // Split string into 6-byte packets do { msg_count = 0; do { ch = String[idx]; if (ch) { MIAC_CAN_TX[msg_count] = ch; idx = idx + 1; msg_count = msg_count + 1; } } while (ch && (msg_count < 6) && (idx < MSZ_String)); // check for 2 x End Of String conditions and packet full if (idx == MSZ_String) // end of string { more_data = 0; }else{ if (String[idx] == 0) more_data = 0; // next ch = null } MIAC_Module_WR(ModIDLCD_1246738, 614, msg_count,cmd_start,more_data); // TX data MIAC_Module_GetAck(ModIDLCD_1246738 + 32, 614, 200); cmd_start = 0; } while (more_data); #endif #else for (idx=0; idx0? if (FCV_MESSAGE>0) { //Call Macro //Call Component Macro: LCDDisplay(0)::Clear FCD_LCDDisplay0_Clear(); //Call Macro //Call Component Macro: ID_HI=CAN(0)::GetRxIDHi(0) FCV_ID_HI = FCD_CAN0_GetRxIDHi(0); //Comment: //We are using the //Hi byte only for this example //Assume all Lo bytes are the same //Call Macro //Call Macro: NODE_FROM_ID FCM_NODE_FROM_ID(); //Call Macro //Call Component Macro: LCDDisplay(0)::Cursor(0, 1) FCD_LCDDisplay0_Cursor(0, 1); //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("Data: ") FCD_LCDDisplay0_PrintASCII('D'); FCD_LCDDisplay0_PrintASCII('a'); FCD_LCDDisplay0_PrintASCII('t'); FCD_LCDDisplay0_PrintASCII('a'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); //Call Macro //Call Component Macro: DATA_COUNT=CAN(0)::GetRxDataCount(0) FCV_DATA_COUNT = FCD_CAN0_GetRxDataCount(0); //Decision //Decision: DATA_COUNT>0? if (FCV_DATA_COUNT>0) { //Call Macro //Call Component Macro: DATA_VAL=CAN(0)::GetRxData(0, 1) FCV_DATA_VAL = FCD_CAN0_GetRxData(0, 1); //Call Macro //Call Component Macro: LCDDisplay(0)::PrintNumber(DATA_VAL) FCD_LCDDisplay0_PrintNumber(FCV_DATA_VAL); } else { //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("None") FCD_LCDDisplay0_PrintASCII('N'); FCD_LCDDisplay0_PrintASCII('o'); FCD_LCDDisplay0_PrintASCII('n'); FCD_LCDDisplay0_PrintASCII('e'); } } } } void FCM_NODE_FROM_ID() { //Get the Node name from the ID Hi param //Calculation //Calculation: // NODE = 0 FCV_NODE = 0; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("N") FCD_LCDDisplay0_PrintASCII('N'); //Decision //Decision: ID_HI = 100? if (FCV_ID_HI == 100) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Brakes") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('B'); FCD_LCDDisplay0_PrintASCII('r'); FCD_LCDDisplay0_PrintASCII('a'); FCD_LCDDisplay0_PrintASCII('k'); FCD_LCDDisplay0_PrintASCII('e'); FCD_LCDDisplay0_PrintASCII('s'); } //Decision //Decision: ID_HI = 101? if (FCV_ID_HI == 101) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Lights") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('L'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); FCD_LCDDisplay0_PrintASCII('s'); } //Decision //Decision: ID_HI = 102? if (FCV_ID_HI == 102) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Left light") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('L'); FCD_LCDDisplay0_PrintASCII('e'); FCD_LCDDisplay0_PrintASCII('f'); FCD_LCDDisplay0_PrintASCII('t'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('l'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); } //Decision //Decision: ID_HI = 103? if (FCV_ID_HI == 103) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Right light") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('R'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('l'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); } //Decision //Decision: ID_HI = 104? if (FCV_ID_HI == 104) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Fog light") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('F'); FCD_LCDDisplay0_PrintASCII('o'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('l'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); } //Decision //Decision: ID_HI = 105? if (FCV_ID_HI == 105) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2:Wipers") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII('W'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('p'); FCD_LCDDisplay0_PrintASCII('e'); FCD_LCDDisplay0_PrintASCII('r'); FCD_LCDDisplay0_PrintASCII('s'); } //Decision //Decision: ID_HI = 106? if (FCV_ID_HI == 106) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Passing Light") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('P'); FCD_LCDDisplay0_PrintASCII('a'); FCD_LCDDisplay0_PrintASCII('s'); FCD_LCDDisplay0_PrintASCII('s'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('n'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('L'); FCD_LCDDisplay0_PrintASCII('i'); FCD_LCDDisplay0_PrintASCII('g'); FCD_LCDDisplay0_PrintASCII('h'); FCD_LCDDisplay0_PrintASCII('t'); } //Decision //Decision: ID_HI = 107? if (FCV_ID_HI == 107) { //Calculation //Calculation: // NODE = 2 FCV_NODE = 2; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("2: Horn") FCD_LCDDisplay0_PrintASCII('2'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('H'); FCD_LCDDisplay0_PrintASCII('o'); FCD_LCDDisplay0_PrintASCII('r'); FCD_LCDDisplay0_PrintASCII('n'); } //Decision //Decision: ID_HI = 200? if (FCV_ID_HI == 200) { //Calculation //Calculation: // NODE = 3 FCV_NODE = 3; //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("4: Fuel ") FCD_LCDDisplay0_PrintASCII('4'); FCD_LCDDisplay0_PrintASCII(':'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('F'); FCD_LCDDisplay0_PrintASCII('u'); FCD_LCDDisplay0_PrintASCII('e'); FCD_LCDDisplay0_PrintASCII('l'); FCD_LCDDisplay0_PrintASCII(' '); } //Decision //Decision: NODE=0? if (FCV_NODE==0) { //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("X - Unknown") FCD_LCDDisplay0_PrintASCII('X'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('-'); FCD_LCDDisplay0_PrintASCII(' '); FCD_LCDDisplay0_PrintASCII('U'); FCD_LCDDisplay0_PrintASCII('n'); FCD_LCDDisplay0_PrintASCII('k'); FCD_LCDDisplay0_PrintASCII('n'); FCD_LCDDisplay0_PrintASCII('o'); FCD_LCDDisplay0_PrintASCII('w'); FCD_LCDDisplay0_PrintASCII('n'); } //Call Macro //Call Component Macro: LCDDisplay(0)::Cursor(0, 1) FCD_LCDDisplay0_Cursor(0, 1); //Call Macro //Call Component Macro: LCDDisplay(0)::PrintASCII("ID:") FCD_LCDDisplay0_PrintASCII('I'); FCD_LCDDisplay0_PrintASCII('D'); FCD_LCDDisplay0_PrintASCII(':'); //Call Macro //Call Component Macro: LCDDisplay(0)::PrintNumber(ID_HI) FCD_LCDDisplay0_PrintNumber(FCV_ID_HI); } void main() { //Initialisation adcon1 = 0x0F; //Interrupt initialisation code //Call Macro //Call Component Macro: CAN(0)::Init FCD_CAN0_Init(); //Loop //Loop: While 1 while (1) { //Call Component Macro //Call Component Macro: CAN(0)::SetTxID(0, 0x10, 0) FCD_CAN0_SetTxID(0, 0x10, 0); //Call Component Macro //Call Component Macro: CAN(0)::SetTxData(0, 1, MESSAGE, 0, 0, 0, 0, 0, 0, 0) FCD_CAN0_SetTxData(0, 1, FCV_MESSAGE, 0, 0, 0, 0, 0, 0, 0); //Calculation //Calculation: // MESSAGE = MESSAGE + 1 FCV_MESSAGE = FCV_MESSAGE + 1; //Delay //Delay: 1 s delay_s(1); } //Loop forever //Loop: While 1 while (1) { //Call Macro //Call Component Macro: MESSAGE=CAN(0)::CheckRx(0) FCV_MESSAGE = FCD_CAN0_CheckRx(0); //Decision //Decision: MESSAGE>0? if (FCV_MESSAGE>0) { //Output //Output: 255 -> PORTB trisb = 0x00; portb = 255; } else { //Output //Output: 0 -> PORTB trisb = 0x00; portb = 0; } } mainendloop: goto mainendloop; } void MX_INTERRUPT_MACRO(void) { }