/********************************************************************* * Flowcode CAL SPI File * * File: PIC_CAL_SPI.c * * (c) 2011 Matrix Multimedia Ltd. * http://www.matrixmultimedia.com * * Software License Agreement * * The software supplied herewith by Matrix Multimedia Ltd (the * “Company”) for its Flowcode graphical programming language is * intended and supplied to you, the Company’s customer, for use * solely and exclusively on the Company's products. The software * is owned by the Company, and is protected under applicable * copyright laws. All rights are reserved. Any use in violation * of the foregoing restrictions may subject the user to criminal * sanctions under applicable laws, as well as to civil liability * for the breach of the terms and conditions of this licence. * * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * * Changelog: * * date | by | description * -------+----+----------------------------------------------------- * 010911 | BR | Created * 150911 | BR | Updated variables with typedef alternatives * 050312 | BR | Updated to v5.1 CAL Schema * 200712 | BR | Added new macro to configure prescaler on the fly */ //When using hardware SPI channels override port and pin conns with FCD conn definitions //Only overwrite CS pin defines when using SPI in slave mode on a hardware channel //Also sort out postscale and prescale options for hardware channels #define MX_SPI_REF_X CAL_APPEND(MX_SPI_REF, MX_SPI_NUM) #define MX_SPI_CHANNEL_X CAL_APPEND(MX_SPI_CHANNEL_, MX_SPI_NUM) #define MX_SPI_MOSI_PIN_X CAL_APPEND(MX_SPI_MOSI_PIN_, MX_SPI_NUM) #define MX_SPI_MOSI_PORT_X CAL_APPEND(MX_SPI_MOSI_PORT_, MX_SPI_NUM) #define MX_SPI_MOSI_TRIS_X CAL_APPEND(MX_SPI_MOSI_TRIS_, MX_SPI_NUM) #define MX_SPI_MISO_PIN_X CAL_APPEND(MX_SPI_MISO_PIN_, MX_SPI_NUM) #define MX_SPI_MISO_PORT_X CAL_APPEND(MX_SPI_MISO_PORT_, MX_SPI_NUM) #define MX_SPI_MISO_TRIS_X CAL_APPEND(MX_SPI_MISO_TRIS_, MX_SPI_NUM) #define MX_SPI_SCK_PIN_X CAL_APPEND(MX_SPI_SCK_PIN_, MX_SPI_NUM) #define MX_SPI_SCK_PORT_X CAL_APPEND(MX_SPI_SCK_PORT_, MX_SPI_NUM) #define MX_SPI_SCK_TRIS_X CAL_APPEND(MX_SPI_SCK_TRIS_, MX_SPI_NUM) #define MX_SPI_CS_PIN_X CAL_APPEND(MX_SPI_CS_PIN_, MX_SPI_NUM) #define MX_SPI_CS_PORT_X CAL_APPEND(MX_SPI_CS_PORT_, MX_SPI_NUM) #define MX_SPI_CS_TRIS_X CAL_APPEND(MX_SPI_CS_TRIS_, MX_SPI_NUM) #define MX_SPI_BMODE_X CAL_APPEND(MX_SPI_BMODE_, MX_SPI_NUM) #define MX_SPI_PR_SCALE_X CAL_APPEND(MX_SPI_PR_SCALE_, MX_SPI_NUM) #define MX_SPI_PO_SCALE_X CAL_APPEND(MX_SPI_PO_SCALE_, MX_SPI_NUM) #define MX_SPI_INT_X CAL_APPEND(MX_SPI_INT_, MX_SPI_NUM) #define MX_PRESCALE_VAR_X CAL_APPEND(prescale_, MX_SPI_NUM) //Setup Definitions #ifdef MX_SPI_REF_X #if MX_SPI_CHANNEL_X > 0 #undef MX_SPI_MOSI_PIN_X #undef MX_SPI_MOSI_PORT_X #undef MX_SPI_MOSI_TRIS_X #undef MX_SPI_MISO_PIN_X #undef MX_SPI_MISO_PORT_X #undef MX_SPI_MISO_TRIS_X #undef MX_SPI_SCK_PIN_X #undef MX_SPI_SCK_PORT_X #undef MX_SPI_SCK_TRIS_X #undef MX_SPI_CS_PIN_X #undef MX_SPI_CS_PORT_X #undef MX_SPI_CS_TRIS_X //Compatible Setting #if MX_SPI_PR_SCALE_X == 4 #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0x30 #endif #if MX_SPI_PR_SCALE_X == 6 #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0x0C #endif #if MX_SPI_PR_SCALE_X == 12 #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0x18 #endif #if MX_SPI_PR_SCALE_X == 24 #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0x30 #endif #if MX_SPI_PR_SCALE_X == 48 #undef MX_SPI_PR_SCALE_X #define MX_SPI_PR_SCALE_X 0x60 #endif #endif #if MX_SPI_CHANNEL_X == 1 #define MX_SPI_MOSI_PIN_X MX_SPI_1_MOSI_PIN #define MX_SPI_MOSI_PORT_X MX_SPI_1_MOSI_PORT #define MX_SPI_MOSI_TRIS_X MX_SPI_1_MOSI_TRIS #define MX_SPI_MISO_PIN_X MX_SPI_1_MISO_PIN #define MX_SPI_MISO_PORT_X MX_SPI_1_MISO_PORT #define MX_SPI_MISO_TRIS_X MX_SPI_1_MISO_TRIS #define MX_SPI_SCK_PIN_X MX_SPI_1_CLK_PIN #define MX_SPI_SCK_PORT_X MX_SPI_1_CLK_PORT #define MX_SPI_SCK_TRIS_X MX_SPI_1_CLK_TRIS #define MX_SPI_CS_PIN_X MX_SPI_1_SS_PIN #define MX_SPI_CS_PORT_X MX_SPI_1_SS_PORT #define MX_SPI_CS_TRIS_X MX_SPI_1_SS_TRIS #endif #if MX_SPI_CHANNEL_X == 2 #define MX_SPI_MOSI_PIN_X MX_SPI_2_MOSI_PIN #define MX_SPI_MOSI_PORT_X MX_SPI_2_MOSI_PORT #define MX_SPI_MOSI_TRIS_X MX_SPI_2_MOSI_TRIS #define MX_SPI_MISO_PIN_X MX_SPI_2_MISO_PIN #define MX_SPI_MISO_PORT_X MX_SPI_2_MISO_PORT #define MX_SPI_MISO_TRIS_X MX_SPI_2_MISO_TRIS #define MX_SPI_SCK_PIN_X MX_SPI_2_CLK_PIN #define MX_SPI_SCK_PORT_X MX_SPI_2_CLK_PORT #define MX_SPI_SCK_TRIS_X MX_SPI_2_CLK_TRIS #define MX_SPI_CS_PIN_X MX_SPI_2_SS_PIN #define MX_SPI_CS_PORT_X MX_SPI_2_SS_PORT #define MX_SPI_CS_TRIS_X MX_SPI_2_SS_TRIS #endif #if MX_SPI_CHANNEL_X == 3 #define MX_SPI_MOSI_PIN_X MX_SPI_3_MOSI_PIN #define MX_SPI_MOSI_PORT_X MX_SPI_3_MOSI_PORT #define MX_SPI_MOSI_TRIS_X MX_SPI_3_MOSI_TRIS #define MX_SPI_MISO_PIN_X MX_SPI_3_MISO_PIN #define MX_SPI_MISO_PORT_X MX_SPI_3_MISO_PORT #define MX_SPI_MISO_TRIS_X MX_SPI_3_MISO_TRIS #define MX_SPI_SCK_PIN_X MX_SPI_3_CLK_PIN #define MX_SPI_SCK_PORT_X MX_SPI_3_CLK_PORT #define MX_SPI_SCK_TRIS_X MX_SPI_3_CLK_TRIS #define MX_SPI_CS_PIN_X MX_SPI_3_SS_PIN #define MX_SPI_CS_PORT_X MX_SPI_3_SS_PORT #define MX_SPI_CS_TRIS_X MX_SPI_3_SS_TRIS #endif #if MX_SPI_CHANNEL_X == 4 #define MX_SPI_MOSI_PIN_X MX_SPI_4_MOSI_PIN #define MX_SPI_MOSI_PORT_X MX_SPI_4_MOSI_PORT #define MX_SPI_MOSI_TRIS_X MX_SPI_4_MOSI_TRIS #define MX_SPI_MISO_PIN_X MX_SPI_4_MISO_PIN #define MX_SPI_MISO_PORT_X MX_SPI_4_MISO_PORT #define MX_SPI_MISO_TRIS_X MX_SPI_4_MISO_TRIS #define MX_SPI_SCK_PIN_X MX_SPI_4_CLK_PIN #define MX_SPI_SCK_PORT_X MX_SPI_4_CLK_PORT #define MX_SPI_SCK_TRIS_X MX_SPI_4_CLK_TRIS #define MX_SPI_CS_PIN_X MX_SPI_4_SS_PIN #define MX_SPI_CS_PORT_X MX_SPI_4_SS_PORT #define MX_SPI_CS_TRIS_X MX_SPI_4_SS_TRIS #endif #else #error "SPI CAL reference not defined!" #endif MX_UINT8 MX_PRESCALE_VAR_X = MX_SPI_PR_SCALE_X; //Function Prototypes CALFUNCTION(void, FC_CAL_SPI_Master_Init_, (void)); CALFUNCTION(void, FC_CAL_SPI_Master_Uninit_, (void)); CALFUNCTION(MX_UINT8, FC_CAL_SPI_Master_Byte_, (MX_UINT8 DataOut)); CALFUNCTION(void, FC_CAL_SPI_Set_Prescaler_, (MX_UINT8 Prescaler)); CALFUNCTION(void, FC_CAL_SPI_Slave_Init_, (void)); CALFUNCTION(void, FC_CAL_SPI_Slave_Uninit_, (void)); CALFUNCTION(void, FC_CAL_SPI_Slave_SetTxData_, (MX_UINT8 Data)); CALFUNCTION(MX_UINT8, FC_CAL_SPI_Slave_GetRxData_, (void)); //Bus Mode - Bit0=CPOL, Bit1=CPHA, Bit2=CSMP //CPOL - Clock Polarity - Idle State of the clock 0=0, 1=1 //CPHA - Clock Phase - Clock Edge 0=leading edge, 1=trailing edge //CSMP - Input Data Bit Sample Phase //CRAT - SPI Clock Rate 0=1/4, 1=1/16, 2=1/64 CALFUNCTION(void, FC_CAL_SPI_Master_Init_, (void)) { FC_CAL_Bit_High_DDR (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_TRIS_X, MX_SPI_MOSI_PIN_X); // MOSI pin is default high FC_CAL_Bit_In_DDR (MX_SPI_MISO_PORT_X, MX_SPI_MISO_TRIS_X, MX_SPI_MISO_PIN_X); // MISO pin is a input #if (MX_SPI_BMODE_X & 0x02) FC_CAL_Bit_Low_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); // Clock pin is default low #else FC_CAL_Bit_High_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); // Clock pin is default high #endif #if (MX_SPI_CHANNEL_X == 1) #ifndef MX_SPI_1 #error "SPI channel 1 not available on this device" #else AT91F_SPI_CfgPMC(); AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, (unsigned int)AT91C_PA12_MISO | (unsigned int)AT91C_PA13_MOSI | (unsigned int)AT91C_PA14_SPCK, 0); AT91F_SPI_Reset(AT91C_BASE_SPI); AT91F_SPI_Enable(AT91C_BASE_SPI); AT91F_SPI_CfgMode(AT91C_BASE_SPI, 0xc0000013); AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, (MX_PRESCALE_VAR_X << 8) | (MX_SPI_BMODE_X & 0x01) | (MX_SPI_BMODE_X & 0x02)); #endif #endif #if (MX_SPI_CHANNEL_X == 2) #ifndef MX_SPI_2 #error "SPI channel 2 not available on this device" #else //ARM only has 1 SPI channel #endif #endif } CALFUNCTION(void, FC_CAL_SPI_Master_Uninit_, (void)) { #if (MX_SPI_CHANNEL_X == 1) AT91F_SPI_Disable(AT91C_BASE_SPI); AT91F_PIO_CfgInput( AT91C_BASE_PIOA, (unsigned int)AT91C_PA12_MISO | (unsigned int)AT91C_PA13_MOSI | (unsigned int)AT91C_PA14_SPCK); #endif #if (MX_SPI_CHANNEL_X == 2) //ARM only has 1 SPI channel #endif //Reset Pins to Inputs FC_CAL_Bit_In_DDR (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_TRIS_X, MX_SPI_MOSI_PIN_X); FC_CAL_Bit_In_DDR (MX_SPI_MISO_PORT_X, MX_SPI_MISO_TRIS_X, MX_SPI_MISO_PIN_X); FC_CAL_Bit_In_DDR (MX_SPI_SCK_PORT_X, MX_SPI_SCK_TRIS_X, MX_SPI_SCK_PIN_X); } CALFUNCTION(MX_UINT8, FC_CAL_SPI_Master_Byte_, (MX_UINT8 DataOut)) { MX_UINT8 retVal = 0; #if (MX_SPI_CHANNEL_X == 0) MX_UINT8 idx, i; for (idx = 0; idx < 8; idx++) { retVal = retVal << 1; #if ((MX_SPI_BMODE_X & 0x02) == 0x00) //CKE = 0; Set SCK active before data #if ((MX_SPI_BMODE_X & 0x01) == 0x00) //CKP = 0 FC_CAL_Bit_High(MX_SPI_SCK_PORT_X, MX_SPI_SCK_PIN_X); #else FC_CAL_Bit_Low(MX_SPI_SCK_PORT_X, MX_SPI_SCK_PIN_X); #endif #endif if (DataOut & 0x80) //Test Data bit FC_CAL_Bit_High(MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_PIN_X); //Set SDO bit else FC_CAL_Bit_Low (MX_SPI_MOSI_PORT_X, MX_SPI_MOSI_PIN_X); //Clear SDO bit for (i=0; iSPI_SR & AT91C_SPI_TXEMPTY) == 0); // Wait for the transmit buffer to empty retVal = AT91F_SPI_GetChar(AT91C_BASE_SPI); // Read the data #endif #if (MX_SPI_CHANNEL_X == 2) //ARM only has 1 SPI channel #endif return (retVal); } CALFUNCTION(void, FC_CAL_SPI_Set_Prescaler_, (MX_UINT8 Prescaler)) { MX_PRESCALE_VAR_X = Prescaler; #if (MX_SPI_CHANNEL_X == 1) AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, (MX_PRESCALE_VAR_X << 8) | (MX_SPI_BMODE_X & 0x01) | (MX_SPI_BMODE_X & 0x02)); #endif } CALFUNCTION(void, FC_CAL_SPI_Slave_Init_, (void)) { } CALFUNCTION(void, FC_CAL_SPI_Slave_Uninit_, (void)) { } CALFUNCTION(void, FC_CAL_SPI_Slave_SetTxData_, (MX_UINT8 Data)) { } CALFUNCTION(MX_UINT8, FC_CAL_SPI_Slave_GetRxData_, (void)) { }