[General] CfgVersion=4 [PIC24HJ128GP202] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x6650000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP204] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x6670000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP206] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x5d3000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP206A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x5d3000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP210] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x5f3000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP210A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x5f3000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP302] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x650000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP304] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x660000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP306] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x653000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP306A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x653000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP310] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x673000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP310A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x673000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP502] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x67d0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP504] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x67f0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP506] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x613000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP506A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x613000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP510] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x633000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP510A] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x633000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ128GP802] pgmmem=0x0 ~pgmmem=0x157ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x6d0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ12GP201] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x80a0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ12GP202] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x80b0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ12MC201] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x8080000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ12MC202] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x8090000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ16GP304] pgmmem=0x0 ~pgmmem=0x2bff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf170000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ16MC302] pgmmem=0x0 ~pgmmem=0x2bff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf110000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=LPOL,0x20,Low-side PWM Output Polarity FPOR~4=HPOL,0x40,High-side PWM Output Polarity FPOR~5=PWMPIN,0x80,PWM Output Pin Reset FPOR~6=RES,0xff00,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0x20,0x20,Active High FPOR~3~2=0x20,0x0,Active Low FPOR~4~1=0x40,0x40,Active High FPOR~4~2=0x40,0x0,Active Low FPOR~5~1=0x80,0x80,Control with PORT/TRIS regs FPOR~5~2=0x80,0x0,Control with HPOL/LPOL bits FPOR~6~1=0xff00,0xff00,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ16MC304] pgmmem=0x0 ~pgmmem=0x2bff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf120000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=LPOL,0x20,Low-side PWM Output Polarity FPOR~4=HPOL,0x40,High-side PWM Output Polarity FPOR~5=PWMPIN,0x80,PWM Output Pin Reset FPOR~6=RES,0xff00,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0x20,0x20,Active High FPOR~3~2=0x20,0x0,Active Low FPOR~4~1=0x40,0x40,Active High FPOR~4~2=0x40,0x0,Active Low FPOR~5~1=0x80,0x80,Control with PORT/TRIS regs FPOR~5~2=0x80,0x0,Control with HPOL/LPOL bits FPOR~6~1=0xff00,0xff00,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP206] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x713000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP206A] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x7710000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=PLLKEN,0x20,PLL Lock Enable FWDT~4=WINDIS,0x40,Watchdog Timer Window FWDT~5=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enable FWDT~3~2=0x20,0x0,Disable FWDT~4~1=0x40,0x40,Non-Window mode FWDT~4~2=0x40,0x0,Window mode FWDT~5~1=0x80,0x80,Enable FWDT~5~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP210] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x733000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP210A] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x7730000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=PLLKEN,0x20,PLL Lock Enable FWDT~4=WINDIS,0x40,Watchdog Timer Window FWDT~5=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enable FWDT~3~2=0x20,0x0,Disable FWDT~4~1=0x40,0x40,Non-Window mode FWDT~4~2=0x40,0x0,Window mode FWDT~5~1=0x80,0x80,Enable FWDT~5~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP610] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x7b3000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ256GP610A] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x77b0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002=FSS 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~3=RBS,0xc0,Boot Segment RAM Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FBS~3~1=0xc0,0xc0,No Boot RAM FBS~3~2=0xc0,0x80,Small-sized Boot RAM FBS~3~3=0xc0,0x40,Medium-sized Boot RAM FBS~3~4=0xc0,0x0,Large-sized Boot RAM FSS_unused=0x0 FSS~1=SWRP,0x1,Secure Segment Program Write Protect FSS~2=SSS,0xe,Secure Segment Program Flash Memory Code Protection FSS~3=RSS,0xc0,Secure Segment Data RAM Protection FSS~1~1=0x1,0x1,Disabled FSS~1~2=0x1,0x0,Enabled FSS~2~1=0xe,0xe,No Secure Segment FSS~2~2=0xe,0xc,Standard Security, Small-sized Secure Flash FSS~2~3=0xe,0xa,Standard Security, Medium-sized Secure Flash FSS~2~4=0xe,0x8,Standard Security, Large-sized Secure Flash FSS~2~5=0xe,0x6,No Secure Segment FSS~2~6=0xe,0x4,High Security, Small-sized Secure Flash FSS~2~7=0xe,0x2,High Security, Medium-sized Secure Flash FSS~2~8=0xe,0x0,High Security, Large-sized Secure Flash FSS~3~1=0xc0,0xc0,No Secure RAM FSS~3~2=0xc0,0x80,Small-sized Secure RAM FSS~3~3=0xc0,0x40,Medium-sized Secure RAM FSS~3~4=0xc0,0x0,Large-sized Secure RAM FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=TEMP,0x20,Temperature Protection Enable FOSCSEL~3=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x20,0x20,Temperature protection disabled FOSCSEL~2~2=0x20,0x0,Temperature protection enabled FOSCSEL~3~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~3~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~3~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~3~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=PLLKEN,0x20,PLL Lock Enable FWDT~4=WINDIS,0x40,Watchdog Timer Window FWDT~5=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enable FWDT~3~2=0x20,0x0,Disable FWDT~4~1=0x40,0x40,Non-Window mode FWDT~4~2=0x40,0x0,Window mode FWDT~5~1=0x80,0x80,Enable FWDT~5~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32GP202] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf1d0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32GP204] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf1f0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32GP302] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x6450000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC)with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32GP304] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x6470000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPS,0xf,Watchdog Timer Postscaler FWDT~2=FWPSA0,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=RES0,0xe0,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 pins FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 pins FPOR~3~1=0xe0,0xe0,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32MC202] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf190000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=LPOL,0x20,Low-side PWM Output Polarity FPOR~4=HPOL,0x40,High-side PWM Output Polarity FPOR~5=PWMPIN,0x80,PWM Output Pin Reset FPOR~6=RES,0xff00,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0x20,0x20,Active High FPOR~3~2=0x20,0x0,Active Low FPOR~4~1=0x40,0x40,Active High FPOR~4~2=0x40,0x0,Active Low FPOR~5~1=0x80,0x80,Control with PORT/TRIS regs FPOR~5~2=0x80,0x0,Control with HPOL/LPOL bits FPOR~6~1=0xff00,0xff00,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24HJ32MC204] pgmmem=0x0 ~pgmmem=0x57ff cfgmem=0xf80000 ~cfgmem=0xf8000f userid=0xf80010 ~userid=0xf80017 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0xf1b0000 configslots=16 0xf80000=FBS 0xf80001= 0xf80002= 0xf80003= 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= FBS_unused=0x0 FBS~1=BWRP,0x1,Boot Segment Write Protect FBS~2=BSS,0xe,Boot Segment Program Flash Code Protection FBS~1~1=0x1,0x1,Boot Segment may be written FBS~1~2=0x1,0x0,Boot Segment is write protected FBS~2~1=0xe,0xe,No Boot Segment FBS~2~2=0xe,0xc,Standard Security, Small-sized Boot Flash FBS~2~3=0xe,0xa,Standard Security, Medium-sized Boot Flash FBS~2~4=0xe,0x8,Standard Security, Large-sized Boot Flash FBS~2~5=0xe,0x6,No Boot Segment FBS~2~6=0xe,0x4,High Security, Small-sized Boot Flash FBS~2~7=0xe,0x2,High Security, Medium-sized Boot Flash FBS~2~8=0xe,0x0,High Security, Large-sized Boot Flash FGS_unused=0x0 FGS~1=GWRP,0x1,General Code Segment Write Protect FGS~2=GSS,0x6,General Segment Code Protection FGS~1~1=0x1,0x1,General Segment may be written FGS~1~2=0x1,0x0,General Segment is write protected FGS~2~1=0x6,0x6,Disabled FGS~2~2=0x6,0x4,Enabled FGS~2~3=0x6,0x2,High Security Code Protection Enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Mode FOSCSEL~2=IESO,0x80,Internal External Switch Over Mode FOSCSEL~1~1=0x7,0x7,(FRC/16) divided by N FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) divide by 16 FOSCSEL~1~3=0x7,0x5,Low Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) w/ PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC (FRC) w/ PLL FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Start up with FRC, then switch FOSCSEL~2~2=0x80,0x0,Start up with user-selected oscillator FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Source FOSC~2=OSCIOFNC,0x4,OSCO/OSC2 Pin Function FOSC~3=IOL1WAY,0x20,Peripheral Pin Select Configuration FOSC~4=FCKSM,0xc0,Clock Switching and Monitor FOSC~1~1=0x3,0x3,Primary Oscillator Disabled FOSC~1~2=0x3,0x2,HS Oscillator Mode FOSC~1~3=0x3,0x1,XT Oscillator Mode FOSC~1~4=0x3,0x0,EC Oscillator Mode FOSC~2~1=0x4,0x4,OSCO pin has clock out function FOSC~2~2=0x4,0x0,OSCO pin has digital I/O function FOSC~3~1=0x20,0x20,Allow Only One Re-configuration FOSC~3~2=0x20,0x0,Allow Multiple Re-configurations FOSC~4~1=0x80,0x80,Sw Disabled, Mon Disabled FOSC~4~2=0xc0,0x40,Sw Enabled, Mon Disabled FOSC~4~3=0xc0,0x0,Sw Enabled, Mon Enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler FWDT~2=WDTPRE,0x10,WDT Prescaler FWDT~3=WINDIS,0x40,Watchdog Timer Window FWDT~4=FWDTEN,0x80,Watchdog Timer Enable FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x40,0x40,Non-Window mode FWDT~3~2=0x40,0x0,Window mode FWDT~4~1=0x80,0x80,Enable FWDT~4~2=0x80,0x0,Disable FPOR_unused=0x0 FPOR~1=FPWRT,0x7,POR Timer Value FPOR~2=ALTI2C,0x10,Alternate I2C pins FPOR~3=LPOL,0x20,Low-side PWM Output Polarity FPOR~4=HPOL,0x40,High-side PWM Output Polarity FPOR~5=PWMPIN,0x80,PWM Output Pin Reset FPOR~6=RES,0xff00,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Off FPOR~2~1=0x10,0x10,I2C mapped to SDA1/SCL1 FPOR~2~2=0x10,0x0,I2C mapped to ASDA1/ASCL1 FPOR~3~1=0x20,0x20,Active High FPOR~3~2=0x20,0x0,Active Low FPOR~4~1=0x40,0x40,Active High FPOR~4~2=0x40,0x0,Active Low FPOR~5~1=0x80,0x80,Control with PORT/TRIS regs FPOR~5~2=0x80,0x0,Control with HPOL/LPOL bits FPOR~6~1=0xff00,0xff00,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,Comm Channel Select FICD~2=JTAGEN,0x20,JTAG Port Enable FICD~3=COE,0x40,Set Clip On Emulation Mode FICD~4=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Use PGC1/EMUC1 and PGD1/EMUD1 FICD~1~2=0x3,0x2,Use PGC2/EMUC2 and PGD2/EMUD2 FICD~1~3=0x3,0x1,Use PGC3/EMUC3 and PGD3/EMUD3 FICD~2~1=0x20,0x20,Enabled FICD~2~2=0x20,0x0,Disabled FICD~3~1=0x40,0x40,Reset Into Operational Mode FICD~3~2=0x40,0x0,Reset Into Clip On Emulation Mode FICD~4~1=0x80,0x80,Disabled FICD~4~2=0x80,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128GP202] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e594000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128GP204] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e584000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128GP206] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e5b4000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128MC202] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e514000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128MC204] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e504000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP128MC206] pgmmem=0x0 ~pgmmem=0x157eb cfgmem=0x157f0 ~cfgmem=0x157ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1e534000 configslots=12 0x157f0=FICD 0x157f1= 0x157f2=FPOR 0x157f3= 0x157f4=FWDT 0x157f5= 0x157f6=FOSC 0x157f7= 0x157f8=FOSCSEL 0x157f9= 0x157fa=FGS 0x157fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256GP202] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f794000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256GP204] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f784000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256GP206] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f7b4000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256GU810] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80004 ~cfgmem=0xf80011 userid=0xf80012 ~userid=0xf80013 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x18264000 configslots=14 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= 0xf80010=FAS 0xf80011= FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GSS,0x2,General Segment Code-Protect bit FGS~3=GSSK,0x30,General Segment Key bits FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled FGS~3~1=0x30,0x30,Enabled FGS~3~2=0x30,0x0,Disabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Initial Oscillator Source Selection bits FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) Oscillator with divide-by-16 FOSCSEL~1~3=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) with PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC with PLL (FRCPLL) FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Wait Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FPOR_unused=0x0 FPOR~1=FPWRT,0x7,Power-on Reset Timer Value Select bits FPOR~2=BOREN,0x8,Brown-out Reset (BOR) Detection Enable bit FPOR~3=ALTI2C1,0x10,Alternate I2C pins for I2C1 FPOR~4=ALTI2C2,0x20,Alternate I2C pins for I2C2 FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Disabled FPOR~2~1=0x8,0x8,Enabled FPOR~2~2=0x8,0x0,Disabled FPOR~3~1=0x10,0x10,Disabled FPOR~3~2=0x10,0x0,Enabled FPOR~4~1=0x20,0x20,Disabled FPOR~4~2=0x20,0x0,Enabled FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=RSTPRI,0x4,Reset Target Vector Select bit FICD~3=ATMOD8,0x10,Reserved FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=COE,0x40,Debugger/Emulation Enable Bit FICD~6=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x4,0x4,Device will obtain reset instruction from Primary flash FICD~2~2=0x4,0x0,Device will obtain reset instruction from Aux flash FICD~3~1=0x10,0x10,Disabled FICD~3~2=0x10,0x0,Enabled FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x40,0x40,Enabled FICD~5~2=0x40,0x0,Disabled FICD~6~1=0x80,0x80,Disabled FICD~6~2=0x80,0x0,Enabled FAS_unused=0x0 FAS~1=AWRP,0x1,Auxiliary Segment Write-protect bit FAS~2=APL,0x2,Auxiliary Segment Code-protect bit FAS~3=APLK,0x30,Auxiliary Segment Key bits FAS~1~1=0x1,0x1,Disabled FAS~1~2=0x1,0x0,Enabled FAS~2~1=0x2,0x2,Disabled FAS~2~2=0x2,0x0,Enabled FAS~3~1=0x30,0x30,Enabled FAS~3~2=0x30,0x0,Disabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256GU814] pgmmem=0x0 ~pgmmem=0x2abff cfgmem=0xf80004 ~cfgmem=0xf80011 userid=0xf80012 ~userid=0xf80013 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x18274000 configslots=14 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= 0xf80010=FAS 0xf80011= FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GSS,0x2,General Segment Code-Protect bit FGS~3=GSSK,0x30,General Segment Key bits FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled FGS~3~1=0x30,0x30,Enabled FGS~3~2=0x30,0x0,Disabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Initial Oscillator Source Selection bits FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) Oscillator with divide-by-16 FOSCSEL~1~3=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) with PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC with PLL (FRCPLL) FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Wait Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FPOR_unused=0x0 FPOR~1=FPWRT,0x7,Power-on Reset Timer Value Select bits FPOR~2=BOREN,0x8,Brown-out Reset (BOR) Detection Enable bit FPOR~3=ALTI2C1,0x10,Alternate I2C pins for I2C1 FPOR~4=ALTI2C2,0x20,Alternate I2C pins for I2C2 FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Disabled FPOR~2~1=0x8,0x8,Enabled FPOR~2~2=0x8,0x0,Disabled FPOR~3~1=0x10,0x10,Disabled FPOR~3~2=0x10,0x0,Enabled FPOR~4~1=0x20,0x20,Disabled FPOR~4~2=0x20,0x0,Enabled FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=RSTPRI,0x4,Reset Target Vector Select bit FICD~3=ATMOD8,0x10,Reserved FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=COE,0x40,Debugger/Emulation Enable Bit FICD~6=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x4,0x4,Device will obtain reset instruction from Primary flash FICD~2~2=0x4,0x0,Device will obtain reset instruction from Aux flash FICD~3~1=0x10,0x10,Disabled FICD~3~2=0x10,0x0,Enabled FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x40,0x40,Enabled FICD~5~2=0x40,0x0,Disabled FICD~6~1=0x80,0x80,Disabled FICD~6~2=0x80,0x0,Enabled FAS_unused=0x0 FAS~1=AWRP,0x1,Auxiliary Segment Write-protect bit FAS~2=APL,0x2,Auxiliary Segment Code-protect bit FAS~3=APLK,0x30,Auxiliary Segment Key bits FAS~1~1=0x1,0x1,Disabled FAS~1~2=0x1,0x0,Enabled FAS~2~1=0x2,0x2,Disabled FAS~2~2=0x2,0x0,Enabled FAS~3~1=0x30,0x30,Enabled FAS~3~2=0x30,0x0,Disabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256MC202] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f714000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256MC204] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f704000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP256MC206] pgmmem=0x0 ~pgmmem=0x2afeb cfgmem=0x2aff0 ~cfgmem=0x2afff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1f734000 configslots=12 0x2aff0=FICD 0x2aff1= 0x2aff2=FPOR 0x2aff3= 0x2aff4=FWDT 0x2aff5= 0x2aff6=FOSC 0x2aff7= 0x2aff8=FOSCSEL 0x2aff9= 0x2affa=FGS 0x2affb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32GP202] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c194000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32GP203] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c1a4000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32GP204] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c184000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32MC202] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c114000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32MC203] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c124000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP32MC204] pgmmem=0x0 ~pgmmem=0x57eb cfgmem=0x57f0 ~cfgmem=0x57ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1c104000 configslots=12 0x57f0=FICD 0x57f1= 0x57f2=FPOR 0x57f3= 0x57f4=FWDT 0x57f5= 0x57f6=FOSC 0x57f7= 0x57f8=FOSCSEL 0x57f9= 0x57fa=FGS 0x57fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GP202] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x17994003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GP204] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x17984003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GP206] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x179b4003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GP806] pgmmem=0x0 ~pgmmem=0x557ff cfgmem=0xf80004 ~cfgmem=0xf80011 userid=0xf80012 ~userid=0xf80013 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x183d4000 configslots=14 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= 0xf80010=FAS 0xf80011= FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GSS,0x2,General Segment Code-Protect bit FGS~3=GSSK,0x30,General Segment Key bits FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled FGS~3~1=0x30,0x30,Enabled FGS~3~2=0x30,0x0,Disabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Initial Oscillator Source Selection bits FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) Oscillator with divide-by-16 FOSCSEL~1~3=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) with PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC with PLL (FRCPLL) FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Wait Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FPOR_unused=0x0 FPOR~1=FPWRT,0x7,Power-on Reset Timer Value Select bits FPOR~2=BOREN,0x8,Brown-out Reset (BOR) Detection Enable bit FPOR~3=ALTI2C1,0x10,Alternate I2C pins for I2C1 FPOR~4=RES,0x20,Reserved FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Disabled FPOR~2~1=0x8,0x8,Enabled FPOR~2~2=0x8,0x0,Disabled FPOR~3~1=0x10,0x10,Disabled FPOR~3~2=0x10,0x0,Enabled FPOR~4~1=0x20,0x20,Reserved FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=RSTPRI,0x4,Reset Target Vector Select bit FICD~3=ATMOD8,0x10,Reserved FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=COE,0x40,Debugger/Emulation Enable Bit FICD~6=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x4,0x4,Device will obtain reset instruction from Primary flash FICD~2~2=0x4,0x0,Device will obtain reset instruction from Aux flash FICD~3~1=0x10,0x10,Disabled FICD~3~2=0x10,0x0,Enabled FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x40,0x40,Enabled FICD~5~2=0x40,0x0,Disabled FICD~6~1=0x80,0x80,Disabled FICD~6~2=0x80,0x0,Enabled FAS_unused=0x0 FAS~1=AWRP,0x1,Auxiliary Segment Write-protect bit FAS~2=APL,0x2,Auxiliary Segment Code-protect bit FAS~3=APLK,0x30,Auxiliary Segment Key bits FAS~1~1=0x1,0x1,Disabled FAS~1~2=0x1,0x0,Enabled FAS~2~1=0x2,0x2,Disabled FAS~2~2=0x2,0x0,Enabled FAS~3~1=0x30,0x30,Enabled FAS~3~2=0x30,0x0,Disabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GU810] pgmmem=0x0 ~pgmmem=0x557ff cfgmem=0xf80004 ~cfgmem=0xf80011 userid=0xf80012 ~userid=0xf80013 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x18364000 configslots=14 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= 0xf80010=FAS 0xf80011= FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GSS,0x2,General Segment Code-Protect bit FGS~3=GSSK,0x30,General Segment Key bits FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled FGS~3~1=0x30,0x30,Enabled FGS~3~2=0x30,0x0,Disabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Initial Oscillator Source Selection bits FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) Oscillator with divide-by-16 FOSCSEL~1~3=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) with PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC with PLL (FRCPLL) FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Wait Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FPOR_unused=0x0 FPOR~1=FPWRT,0x7,Power-on Reset Timer Value Select bits FPOR~2=BOREN,0x8,Brown-out Reset (BOR) Detection Enable bit FPOR~3=ALTI2C1,0x10,Alternate I2C pins for I2C1 FPOR~4=ALTI2C2,0x20,Alternate I2C pins for I2C2 FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Disabled FPOR~2~1=0x8,0x8,Enabled FPOR~2~2=0x8,0x0,Disabled FPOR~3~1=0x10,0x10,Disabled FPOR~3~2=0x10,0x0,Enabled FPOR~4~1=0x20,0x20,Disabled FPOR~4~2=0x20,0x0,Enabled FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=RSTPRI,0x4,Reset Target Vector Select bit FICD~3=ATMOD8,0x10,Reserved FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=COE,0x40,Debugger/Emulation Enable Bit FICD~6=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGC3/EMUC3 and PGD3/EMUD3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x4,0x4,Device will obtain reset instruction from Primary flash FICD~2~2=0x4,0x0,Device will obtain reset instruction from Aux flash FICD~3~1=0x10,0x10,Disabled FICD~3~2=0x10,0x0,Enabled FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x40,0x40,Enabled FICD~5~2=0x40,0x0,Disabled FICD~6~1=0x80,0x80,Disabled FICD~6~2=0x80,0x0,Enabled FAS_unused=0x0 FAS~1=AWRP,0x1,Auxiliary Segment Write-protect bit FAS~2=APL,0x2,Auxiliary Segment Code-protect bit FAS~3=APLK,0x30,Auxiliary Segment Key bits FAS~1~1=0x1,0x1,Disabled FAS~1~2=0x1,0x0,Enabled FAS~2~1=0x2,0x2,Disabled FAS~2~2=0x2,0x0,Enabled FAS~3~1=0x30,0x30,Enabled FAS~3~2=0x30,0x0,Disabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512GU814] pgmmem=0x0 ~pgmmem=0x557ff cfgmem=0xf80004 ~cfgmem=0xf80011 userid=0xf80012 ~userid=0xf80013 eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x18374000 configslots=14 0xf80004=FGS 0xf80005= 0xf80006=FOSCSEL 0xf80007= 0xf80008=FOSC 0xf80009= 0xf8000a=FWDT 0xf8000b= 0xf8000c=FPOR 0xf8000d= 0xf8000e=FICD 0xf8000f= 0xf80010=FAS 0xf80011= FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GSS,0x2,General Segment Code-Protect bit FGS~3=GSSK,0x30,General Segment Key bits FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled FGS~3~1=0x30,0x30,Enabled FGS~3~2=0x30,0x0,Disabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Initial Oscillator Source Selection bits FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x6,Internal Fast RC (FRC) Oscillator with divide-by-16 FOSCSEL~1~3=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~4=0x7,0x4,Secondary Oscillator (SOSC) FOSCSEL~1~5=0x7,0x3,Primary Oscillator (XT, HS, EC) with PLL FOSCSEL~1~6=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~7=0x7,0x1,Internal Fast RC with PLL (FRCPLL) FOSCSEL~1~8=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Wait Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FPOR_unused=0x0 FPOR~1=FPWRT,0x7,Power-on Reset Timer Value Select bits FPOR~2=BOREN,0x8,Brown-out Reset (BOR) Detection Enable bit FPOR~3=ALTI2C1,0x10,Alternate I2C pins for I2C1 FPOR~4=ALTI2C2,0x20,Alternate I2C pins for I2C2 FPOR~1~1=0x7,0x7,128ms FPOR~1~2=0x7,0x6,64ms FPOR~1~3=0x7,0x5,32ms FPOR~1~4=0x7,0x4,16ms FPOR~1~5=0x7,0x3,8ms FPOR~1~6=0x7,0x2,4ms FPOR~1~7=0x7,0x1,2ms FPOR~1~8=0x7,0x0,Disabled FPOR~2~1=0x8,0x8,Enabled FPOR~2~2=0x8,0x0,Disabled FPOR~3~1=0x10,0x10,Disabled FPOR~3~2=0x10,0x0,Enabled FPOR~4~1=0x20,0x20,Disabled FPOR~4~2=0x20,0x0,Enabled FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=RSTPRI,0x4,Reset Target Vector Select bit FICD~3=ATMOD8,0x10,Reserved FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=COE,0x40,Debugger/Emulation Enable Bit FICD~6=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x4,0x4,Device will obtain reset instruction from Primary flash FICD~2~2=0x4,0x0,Device will obtain reset instruction from Aux flash FICD~3~1=0x10,0x10,Disabled FICD~3~2=0x10,0x0,Enabled FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x40,0x40,Enabled FICD~5~2=0x40,0x0,Disabled FICD~6~1=0x80,0x80,Disabled FICD~6~2=0x80,0x0,Enabled FAS_unused=0x0 FAS~1=AWRP,0x1,Auxiliary Segment Write-protect bit FAS~2=APL,0x2,Auxiliary Segment Code-protect bit FAS~3=APLK,0x30,Auxiliary Segment Key bits FAS~1~1=0x1,0x1,Disabled FAS~1~2=0x1,0x0,Enabled FAS~2~1=0x2,0x2,Disabled FAS~2~2=0x2,0x0,Enabled FAS~3~1=0x30,0x30,Enabled FAS~3~2=0x30,0x0,Disabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512MC202] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x17914003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512MC204] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x17904003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP512MC206] pgmmem=0x0 ~pgmmem=0x557eb cfgmem=0x557f0 ~cfgmem=0x557ff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x17934003 configslots=12 0x557f0=FICD 0x557f1= 0x557f2=FPOR 0x557f3= 0x557f4=FWDT 0x557f5= 0x557f6=FOSC 0x557f7= 0x557f8=FOSCSEL 0x557f9= 0x557fa=FGS 0x557fb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64GP202] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d394001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64GP203] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d3a4001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64GP204] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d384001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64GP206] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d3b4001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x80,0x80,Enabled FOSCSEL~2~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64MC202] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d314001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64MC203] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d324001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64MC204] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d304001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC24EP64MC206] pgmmem=0x0 ~pgmmem=0xafeb cfgmem=0xaff0 ~cfgmem=0xafff userid=0x800ff8 ~userid=0x800fff eedata= ~eedata= devid=0xff0000 ~devid=0xff0003 idmask=0xffff0000 id=0x1d334001 configslots=12 0xaff0=FICD 0xaff1= 0xaff2=FPOR 0xaff3= 0xaff4=FWDT 0xaff5= 0xaff6=FOSC 0xaff7= 0xaff8=FOSCSEL 0xaff9= 0xaffa=FGS 0xaffb= FICD_unused=0x0 FICD~1=ICS,0x3,ICD Communication Channel Select bits FICD~2=ATMOD8,0x8,Reserved FICD~3=SIGN,0x10,Signature Bit FICD~4=JTAGEN,0x20,JTAG Enable bit FICD~5=BACKBUG,0x80,Background Debug FICD~1~1=0x3,0x3,Communicate on PGEC1 and PGED1 FICD~1~2=0x3,0x2,Communicate on PGEC2 and PGED2 FICD~1~3=0x3,0x1,Communicate on PGEC3 and PGED3 FICD~1~4=0x3,0x0,Reserved, do not use FICD~2~1=0x8,0x8,Disabled FICD~2~2=0x8,0x0,Enabled FICD~3~1=0x10,0x0,Correct FICD~4~1=0x20,0x20,Enabled FICD~4~2=0x20,0x0,Disabled FICD~5~1=0x80,0x80,Disabled FICD~5~2=0x80,0x0,Enabled FPOR_unused=0x0 FPOR~1=ALTI2C1,0x10,Alternate I2C1 pins FPOR~2=ALTI2C2,0x20,Alternate I2C2 pins FPOR~3=WDTWIN,0xc0,Watchdog Window Select bits FPOR~1~1=0x10,0x10,Disabled FPOR~1~2=0x10,0x0,Enabled FPOR~2~1=0x20,0x20,Disabled FPOR~2~2=0x20,0x0,Enabled FPOR~3~1=0xc0,0xc0,WDT Window is 25% of WDT period FPOR~3~2=0xc0,0x80,WDT Window is 37.5% of WDT period FPOR~3~3=0xc0,0x40,WDT Window is 50% of WDT period FPOR~3~4=0xc0,0x0,WDT Window is 75% of WDT period FWDT_unused=0x0 FWDT~1=WDTPOST,0xf,Watchdog Timer Postscaler bits FWDT~2=WDTPRE,0x10,Watchdog Timer Prescaler bit FWDT~3=PLLKEN,0x20,PLL Lock Enable bit FWDT~4=WINDIS,0x40,Watchdog Timer Window Enable bit FWDT~5=FWDTEN,0x80,Watchdog Timer Enable bit FWDT~1~1=0xf,0xf,1:32,768 FWDT~1~2=0xf,0xe,1:16,384 FWDT~1~3=0xf,0xd,1:8,192 FWDT~1~4=0xf,0xc,1:4,096 FWDT~1~5=0xf,0xb,1:2,048 FWDT~1~6=0xf,0xa,1:1,024 FWDT~1~7=0xf,0x9,1:512 FWDT~1~8=0xf,0x8,1:256 FWDT~1~9=0xf,0x7,1:128 FWDT~1~10=0xf,0x6,1:64 FWDT~1~11=0xf,0x5,1:32 FWDT~1~12=0xf,0x4,1:16 FWDT~1~13=0xf,0x3,1:8 FWDT~1~14=0xf,0x2,1:4 FWDT~1~15=0xf,0x1,1:2 FWDT~1~16=0xf,0x0,1:1 FWDT~2~1=0x10,0x10,1:128 FWDT~2~2=0x10,0x0,1:32 FWDT~3~1=0x20,0x20,Enabled FWDT~3~2=0x20,0x0,Disabled FWDT~4~1=0x40,0x40,Disabled FWDT~4~2=0x40,0x0,Enabled FWDT~5~1=0x80,0x80,Enabled FWDT~5~2=0x80,0x0,Disabled FOSC_unused=0x0 FOSC~1=POSCMD,0x3,Primary Oscillator Mode Select bits FOSC~2=OSCIOFNC,0x4,OSC2 Pin Function bit FOSC~3=IOL1WAY,0x20,Peripheral pin select configuration FOSC~4=FCKSM,0xc0,Clock Switching Mode bits FOSC~1~1=0x3,0x3,Primary Oscillator disabled FOSC~1~2=0x3,0x2,HS Crystal Oscillator Mode FOSC~1~3=0x3,0x1,XT Crystal Oscillator Mode FOSC~1~4=0x3,0x0,EC (External Clock) Mode FOSC~2~1=0x4,0x4,ClockOut Enabled I/O Disabled FOSC~2~2=0x4,0x0,ClockOut Disabled I/O Enabled FOSC~3~1=0x20,0x20,Allow one reconfiguration FOSC~3~2=0x20,0x0,Allow Multiple Reconfigurations FOSC~4~1=0xc0,0xc0,Both Clock switching and Fail-safe Clock Monitor are disabled FOSC~4~2=0xc0,0x40,Clock switching is enabled,Fail-safe Clock Monitor is disabled FOSC~4~3=0xc0,0x0,Both Clock switching and Fail-safe Clock Monitor are enabled FOSCSEL_unused=0x0 FOSCSEL~1=FNOSC,0x7,Oscillator Source Selection FOSCSEL~2=PWMLOCK,0x40,PWM Lock Enable bit FOSCSEL~3=IESO,0x80,Two-speed Oscillator Start-up Enable bit FOSCSEL~1~1=0x7,0x7,Internal Fast RC (FRC) Oscillator with postscaler FOSCSEL~1~2=0x7,0x5,Low-Power RC Oscillator (LPRC) FOSCSEL~1~3=0x7,0x3,Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) FOSCSEL~1~4=0x7,0x2,Primary Oscillator (XT, HS, EC) FOSCSEL~1~5=0x7,0x1,Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) FOSCSEL~1~6=0x7,0x0,Internal Fast RC (FRC) FOSCSEL~2~1=0x40,0x40,Enabled FOSCSEL~2~2=0x40,0x0,Disabled FOSCSEL~3~1=0x80,0x80,Enabled FOSCSEL~3~2=0x80,0x0,Disabled FGS_unused=0x0 FGS~1=GWRP,0x1,General Segment Write-Protect bit FGS~2=GCP,0x2,General Segment Code-Protect bit FGS~1~1=0x1,0x1,Disabled FGS~1~2=0x1,0x0,Enabled FGS~2~1=0x2,0x2,Disabled FGS~2~2=0x2,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA