enable I/O Pins on 12F635 ?

[goingo]

using flowcode 4.5
eblocks eb 006-00-6
12f635

how is it possible to enable ra3,ra4,ra5 as I/O pins ? (ra3 input)
only ra0,ra1,ra2 can be selected in flowcode - changing fuses causes the same result

many thanx and a happy new year from austria
ingo

[medelec35]

Hi ingo,
Happy new year to you as well from the UK.

I have corrected the fcd file so you can select all available ports.
If you place this attachment, in Flowcode V4/FCD directory, then start up Flowcode (close 1st if already running)
Then If you delete and re-add LED array (Or just alter connections )then array will also show RA0 to RA5.

Martin

[goingo]

many thany for your fast answer medelec35

it is now possible to check ra3,ra4,ra5
then i write a little programm in flowcode witch turns on a led on ra0,ra1,ra2,ra4,ra5
then all leds should be off
in simulation all works fine but then in the hardware ra0 and ra1 dont work like i expected
ra0 and ra1 switch on and dont hold the state as in the simulation - only ra0 and ra1 immediatly switch to low the other ra2,ra4,ra5 work fine
i can not realize this
how is this possible?

ingo

[medelec35]

Your welcome ingo,
Without testing on hardware, the only thing I can see is the configuration is wrong on the file you posted.
I have set the flowchart to run hardware with internal oscillator set at 8MHz
Program works on a different simulator using hex file generated from Flowcode, but that's not 100% guaranteed attached file will work.

Also If using EB006 programmer Eblock, then if you look at the data sheet:
http://www.matrixmultimedia.com/datashe ... 6-30-7.pdf
Then you can see that GP0 is mapped to RB7 and GP1 is mapped to RB6 of and GP2 is mapped to RB2 programmer. Could that be your issue?

Martin

[jgu1]

Hi Martin!

I've noticed recently that there have been some bugs in some different FCD files for different Pic. A friendly inquiry, my suggestion and idea, every time there's an updated FCD file, place the updates in "Temporary fixes for V4.5 PICmicro release".

It is sometimes coincidences that we find the corrections.

Best regard an happy newyear!

Jgu1

[medelec35]

I've noticed recently that there have been some bugs in some different FCD files for different Pic. A friendly inquiry, my suggestion and idea, every time there's an updated FCD file, place the updates in "Temporary fixes for V4.5 PICmicro release".

It is sometimes coincidences that we find the corrections.

Best regard an happy newyear!

Jgu1

Hi Jgu1,
Happy New year to you too.
I do agree with you 100%. But when I post fixes, since I don't work for Matrix Multimedia, they are all unofficial &they may not even work.
For that reason I believe it should only be down to MM staff to post the fixes in 'Temporary fixes for V4.5 PICmicro release' thread.
I did answer a simular question here:
http://www.matrixmultimedia.com/mmforum ... 81&#p26632

The only other thing I can think of is either MM staff give permission for unofficial updates to be posted there, or another sticky could be created. E.g Unofficial Temporary fixes for V4.5 PICmicro release.

What does any forum members believe is best way to go?

Martin

[goingo]

Also If using EB006 programmer Eblock, then if you look at the data sheet:
http://www.matrixmultimedia.com/datashe ... 6-30-7.pdf
Then you can see that GP0 is mapped to RB7 and GP1 is mapped to RB6 of and GP2 is mapped to RB2 programmer. Could that be your issue?

Martin

testing your file for 12f635 doesnt help
i only use the EB006 for programming
programm was also tested on external hardware with 12f675 -- this pic works well in simulation and on hardware
ingo

[medelec35]

Hi ingo, Since I'm not an expert with decoding ASM and I do not have the chip in question then sorry I unable to help any further.


In looking at the generated assembly to a non expert as myself looks correct starting from when only bit 0 is set high to gpio

has a value of 1:
MOVLW 0xFD //Value used for Masking off all bits except bit 1
BCF STATUS, RP0 //Selct Bank 0
ANDWF gbl_gpio, W // AND PortA with 0xFD then store result in Working reg
MOVWF CompTempVar2202 // Store value of working reg (0xFD AND 0x1 = 1)
MOVLW 0x02 //Store literal value of 0x2 in Wreg
IORWF CompTempVar2202, W // IOR Wreg & value in CompTempVar220 (0x1 IOR 0x2 =0x3)
MOVWF gbl_gpio //Move result of Wreg into Port A i.e PortA = 0x3

So its odd how hardware is not working.

Or I could just have read ASM wrong?

I think I will leave this for Matrix team to solve as it's more their field then mime.

Martin

[goingo]

hello martin

all that i can say is thank you for spendig your time for trying to solve my problem
for me this is not a matter of course
so ill try to solve on my own or perhaps anyone can guide me to an result

best regards and a happy new year especially to you and your family

ingo

p.s the problem never gets out of my mind so i took my old icd2 with mplab and the ccs compiler
writing the same programm in c then generating a hex file and burn it down with ppp ---> result it work´s
so for me it is definitiv a compiler bug in flowcode v4.5
to matrix: please correct it in v5