Although this is old tec now, I have had a couple of pms asking if I could post a flowchart driving 74HC595, so here it is
I will create a circuit diagram if the interest is there os just let me know.
Hopefully all required information has been added to flowchart.
I have tested this on hardware and 7seg display was incrementing by 1 every second as expected.
In simplified terms Referring to the diagram the serial to parallel chip works as follows: 1st bit of serial data sets or clears at pin 14
then Clock (pin 11) is toggled
2nd bit of serial data sets or clears at pin 14
Clock (pin 11) is toggled again.
The above is repeated until all 8 bits of serial data have controlled pin 14
Now the serial data has to be is transferred to pins the parallel pins :
15(Q0 which will be the same state as 1st bit of serial data connected to seg a of 7seg)
1 (Q1 which will be the same state as 2nd bit of serial data connected to seg b of 7seg)
2 (Q2 which will be the same state as 3rd bit of serial data seg c of 7seg) etc.
To transfer the store serial data to all the parallel pins (Latch data to the pins)
just involves toggling (or clocking is another word) pin 12 just once!
Now all the serial data is latched to the parallel pins, andwill remain there until power is removed or the whole process is started all over again with another lot of serial data to be converted into parallel.
Martin
