Does Flowcode support LAT?
Posted: Sat Mar 03, 2012 11:52 am
Hello,
does Flowcode support LAT Variable?
12.2.3 LAT Registers
The LATx register associated with an I/O pin eliminates the problems that could occur with read-modify-write instructions. A read of the LATx register returns the values held in the port output latches instead of the values on the I/O pins. A read-modify-write operation on the LATx register, associated with an I/O port, avoids the possibility of writing the input pin values into the port latches. A write to the LATx register has the same effect as a write to the PORTx register.
The differences between the PORTx and LATx registers can be summarized as follows:
" A write to the PORTx register writes the data value to the port latch. A write to the LATx register writes the data value to the port latch. A read of the PORTx register reads the data value on the I/O pin. A read of the LATx register reads the data value held in the port latch.
Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read as zeros.
Regards
Dirk
does Flowcode support LAT Variable?
12.2.3 LAT Registers
The LATx register associated with an I/O pin eliminates the problems that could occur with read-modify-write instructions. A read of the LATx register returns the values held in the port output latches instead of the values on the I/O pins. A read-modify-write operation on the LATx register, associated with an I/O port, avoids the possibility of writing the input pin values into the port latches. A write to the LATx register has the same effect as a write to the PORTx register.
The differences between the PORTx and LATx registers can be summarized as follows:
" A write to the PORTx register writes the data value to the port latch. A write to the LATx register writes the data value to the port latch. A read of the PORTx register reads the data value on the I/O pin. A read of the LATx register reads the data value held in the port latch.
Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read as zeros.
Regards
Dirk