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Hi all

Trying to communicate with MRF24J40MA I'm not getting the response I was looking for.
I would read from a register (which is accessed by value 34 on the logic analyzer) that has a POR-value not zero (28 to be precise).

So I took my spade & started digging to find out where things go wrong,
I found that, given the SPI-module settings (image 2) the data-signal was sometimes erroneous. On image 0 you can see that address 34 is being sent over the MOSI, but not always. In the middle you see that address 2 pops-up on the MOSI-line.
Taking a zoom on the error in image 1, I see the data-signal is set way to close to the active clock and even sometimes later than the active clock-signal!

Bug report: I tried to do it on FC7, but channel 2 is not working/supported for the chip (there are debug-leds on channel 1 & they are flashing, meaning that even selecting channel 2, SPI is still configured on channel 1 --> bug )

The story goes on... (sorry for the flood, I need to post other images).

So perhaps I had poor PCB-lines, so I took a look to the MOSI with a scope (image 3...). It looks fine to me getting back to the fact that the MOSI-line is getting the wright value way to close/late in relation to the CLK in my opinion.
PS : The length of MOSI & CLK are 2mm different (on about 8cm length), but on these frequency this should not even matter.

So next step was : bit-banging. I wrote a little code (image 4...) to do the same thing as the component-macro's Sendchar & GetChar.
HalleluJah ! Not only you can see the MOSI-line coming up before the active clock (logic because of the delay in instruction execution) but the MRF responds correctly with a good reply (28). This confirms that the MRF is not getting the wright input!

So... Mr Leigh or Ben (or Microchip ?), what can be done about it?

I thank everyone in advance for the time taken by reading this.

Solution found !

SPI-setting / Clock phase should have been : trailing edge
(it was set on leading edge)

Can I delete my own posts ? (no I can't)