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Chinese version SSD1306 working perfectly in software mode.
Vdd is 3V3
In Channel mode, both data and clock remain near VDD, Never drops to 0V
Using Internal osc set to 48MHz, I2C 100KHz and MCLR as port.

Hi Martin,

Thanks for the spot, I'll get this fix pushed to the update system as soon as possible.

For now here you go.

Perfect thank you.
Confirmed working with channels 1 & 2 (Remapping ok) and software mode.