Good research, that sure looks like the issue then

Hi Ben.
The signal looks inverted, but if you analyse the data it looks correct for "Test"
So I think it is in break mode in the inter data gaps.
There is a bit in UxCON1 that controls break, I wondered if that is causing it, perhaps it is getting inadvertently set?

Looks like the TX output is being forced into a non-Idle (break) state
One for Ben and the UART CAL I think
(UxCON1 issue with this device?)

Could you provide a sample picture and what data it represents that you are sending

You must include the quotes e.g. "color"

Hi,
I've just had chance to look at your projects and their settings.
You have PLL selected as system clock, but PLL source is set to OFF
Please change PLL source to HSI
With these settings your system clock and timer clocks will be 48MHz
You have correctly set the Flowcode project clock speed to ...

Could it be the e-blocks2 port remapping that is causing confusion?

This sounds like wrong project or component settings. Clock speeds for example. Because delays and PWM definitely do work.
I'm not in a position to check your settings at the moment.
It looks like you have posted your HAL code version?
Perhaps if you post your Flowcode native version someone may be ...

Interesting about the Orange Pi, I've been using these for some time, although they are not as dirt cheap as they used to be.
I have one running my NAS, running on Armbian Linux, which I would recommend, as I've found it to be the most stable and supported ARM distro,
apart from Raspberry PI OS of ...

Could you try adding a property
file = "ATTINY4313_dev_board"
after the name =
(I can't remember if we need the .fcdx suffix)
And delete everything above <root>
Such that it's the first line.