Jump to content

Component: Linear Feedback Shift Register (Calculation): Difference between revisions

From Flowcode Help
m Text replacement - "width="10%" align="center" style="background-color:#D8C9D8;" align="center"" to "width="10%" align="center" class="mtx-class-macrohead""
m Text replacement - "width="90%" style="background-color:#D8C9D8; color:#4B008D;"" to "width="90%" class="mtx-class-macrohead""
 
(One intermediate revision by the same user not shown)
Line 29: Line 29:
|-
|-
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="90%" style="background-color:#D8C9D8; color:#4B008D;" | '''Generate'''
| width="90%" class="mtx-class-macrohead" | '''Generate'''
|-
|-
| colspan="2" | Generate the next itteration 
| colspan="2" | Generate the next itteration 
Line 43: Line 43:
|-
|-
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="90%" style="background-color:#D8C9D8; color:#4B008D;" | '''Seed'''
| width="90%" class="mtx-class-macrohead" | '''Seed'''
|-
|-
| colspan="2" | Write a seed value into the shift register. Any 16-bit value is allowed except zero. 
| colspan="2" | Write a seed value into the shift register. Any 16-bit value is allowed except zero. 
Line 62: Line 62:
|-
|-
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-comp-macro.png]]
| width="90%" style="background-color:#D8C9D8; color:#4B008D;" | '''Set_Mask'''
| width="90%" class="mtx-class-macrohead" | '''Set_Mask'''
|-
|-
| colspan="2" | Set the 16-bit mask to describe the feedback polynomial. 1=bit is fed back 0=bit is not fed back The number of taps must be even and setwise co-prime (no common divisor except 1) 
| colspan="2" | Set the 16-bit mask to describe the feedback polynomial. 1=bit is fed back 0=bit is not fed back The number of taps must be even and setwise co-prime (no common divisor except 1) 
Line 81: Line 81:
{| class="mtx-class-macrotable wikitable"
{| class="mtx-class-macrotable wikitable"
|-
|-
| width="10%" align="center" style="background-color:#D8C9D8;" | [[File:Fc9-prop-icon.png]]
| width="10%" align="center" class="mtx-class-macrohead" | [[File:Fc9-prop-icon.png]]
| width="90%" style="background-color:#D8C9D8; color:#4B008D;" | '''Properties'''  
| width="90%" class="mtx-class-macrohead" | '''Properties'''  
|-
|-
|}
|}

Latest revision as of 14:23, 13 July 2026

Author PC
Version 1.0
Category Calculation


Linear Feedback Shift Register component

Implements a linear feedback shift register to produce a pseudo-random bit sequence.

Detailed description

No detailed description exists yet for this component

Examples

No additional examples

Macro reference

Generate

Generate
Generate the next itteration 
- BOOL Return


Seed

Seed
Write a seed value into the shift register. Any 16-bit value is allowed except zero. 
- UINT Seed
 
- VOID Return


Set_Mask

Set_Mask
Set the 16-bit mask to describe the feedback polynomial. 1=bit is fed back 0=bit is not fed back The number of taps must be even and setwise co-prime (no common divisor except 1) 
- UINT Mask
16-bit polynomial 
- VOID Return


Property reference

Properties

Component Source Code

Please click here to download the component source project: FC_Comp_Source_Linear_Feedback_Shift_Register.fcfx

Please click here to view the component source code (Beta): FC_Comp_Source_Linear_Feedback_Shift_Register.fcfx